sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
add missing weird dyn_pm display code 22397370c173dd1763b703f2b9144fd0994bbe5c Sylvain BERTRAND 2014-09-04 17:13:08
order matters 0102f69355f70737fcebc74f8e94d39486a1ce83 Sylvain BERTRAND 2014-09-03 19:16:04
add the I2C algo acd92dd9affcc7902a444084b7dc101820c3cd83 Sylvain BERTRAND 2014-09-03 18:47:20
typo ccb7d6e12b38adecd8a77bfce7bcc67c4bd361f4 Sylvain BERTRAND 2014-09-01 10:29:10
new PCI IDS ea4bc021abcfc66e48f6565ce02e719b1cf4db97 Sylvain BERTRAND 2014-09-01 09:03:12
mc fw2 issues are actually dpm issues eecf2acffb1798e42f4a77b1d351e62dc297fb17 Sylvain BERTRAND 2014-09-01 08:53:26
add no_dpm option because radeon dpm is a shame 003cb84f01f60e99b138d0694ddf58bebf724fd6 Sylvain BERTRAND 2014-09-01 08:41:24
page flip fix e51d9d4b1788c17633b0cdffd7a50309d51f8d0f Sylvain BERTRAND 2014-08-30 14:08:35
ack-ing the DCE irqs at the right time a12ec7f4781872de8d155e4e1d90b07df3e44c34 Sylvain BERTRAND 2014-08-28 15:23:29
normal programs use normal syscalls then ioctl 37589b6856d941efdc763eed41b237f4f62cb960 Sylvain BERTRAND 2014-07-08 19:01:52
new firware breaks the 3D pipeline 13db71ba4522d7266d68a21f43f25ee3781d0b92 Sylvain BERTRAND 2014-07-03 22:54:30
closed src or gnu gpl *not* v2 drivers are illegal dc1de426b639ffee863b0a211e9cf0e349f855f0 Sylvain BERTRAND 2014-07-03 17:59:46
compiling with 3.16 rc2 new mc fw code e00afdaeef8513da35c82cc82dcfee0745aa9129 Sylvain BERTRAND 2014-06-29 01:54:40
untested handling of new mc fw eb89a71b0af7781d1fc9ee226c1269b6d5183749 Sylvain BERTRAND 2014-06-29 01:26:15
become legal ef922b67f25aaf0c4f8cff5be572e53fb53bdfe5 Sylvain BERTRAND 2014-06-28 23:33:40
use usleep_range and fix a dp 1.1 time out d4183ce73e6ec7d7f3baf9d710dd2ba015b4a6a9 Sylvain BERTRAND 2014-02-19 20:09:44
fix dac a864ba601253674b679b07e4b1ddc00fb83a8cb6 Sylvain BERTRAND 2014-02-19 19:17:08
clear atombias dpm state and warn for instability 28b598d81f6a873f90d1a9325e3e1002743487a5 Sylvain BERTRAND 2014-02-19 19:10:43
CFG_MEM_SZ upper 16bits may have garbage f08f2e3471989e448d6d76ba02565fd9efc3293f Sylvain BERTRAND 2014-02-19 17:55:38
fix ena rbs mask performance critical bug 289497449dd0f2acb09e03f65988e22e45948fb6 Sylvain BERTRAND 2014-02-19 17:15:18
Commit 22397370c173dd1763b703f2b9144fd0994bbe5c - add missing weird dyn_pm display code
Author: Sylvain BERTRAND
Author date (UTC): 2014-09-04 17:13
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-09-04 17:13
Parent(s): 0102f69355f70737fcebc74f8e94d39486a1ce83
Signing key:
Tree: 930971c1c197ce61375a2ff684828f9b49bb6721
File Lines added Lines deleted
drivers/gpu/alga/amd/dce6/dce6.h 2 0
drivers/gpu/alga/amd/dce6/mod.c 47 0
drivers/gpu/alga/amd/si/drv.c 1 0
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c 58 8
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.h 2 0
drivers/gpu/alga/amd/si/regs.h 10 2
include/alga/amd/dce6/dce6_dev.h 2 0
File drivers/gpu/alga/amd/dce6/dce6.h changed (mode: 100644) (index 17e1dd2..5d58bed)
... ... struct dp {
42 42 struct dce6 *dce; /* to navigate back to dce */ struct dce6 *dce; /* to navigate back to dce */
43 43 u8 i; u8 i;
44 44
45 u8 active;
46
45 47 u8 edp; u8 edp;
46 48 u8 atb_dfp; u8 atb_dfp;
47 49
File drivers/gpu/alga/amd/dce6/mod.c changed (mode: 100644) (index 48604d2..3f37b67)
... ... static long dps_connected_dpcd_info(struct dce6 *dce)
314 314 return 0; return 0;
315 315 } }
316 316
317 static void dps_used_active_info(struct dce6 *dce, u8 *active_cnt,
318 u8 *active_first)
319 {
320 u8 i;
321
322 *active_cnt = 0;
323 *active_first = 0;
324
325 for (i = 0; i < dce->ddev.crtcs_n; ++i) {
326 if ((dce->dps_used & BIT(i)) == 0)
327 continue;
328
329 if (dce->dps[i].active)
330 ++(*active_cnt);
331 }
332
333 if (!*active_cnt)
334 return;
335
336 for (i = 0; i < dce->ddev.crtcs_n; ++i) {
337 if ((dce->dps_used & BIT(i)) == 0)
338 continue;
339
340 if (dce->dps[i].active) {
341 *active_first = i;
342 return;
343 }
344 }
345 }
346
317 347 long dce6_sink_mode_set(struct dce6 *dce, u8 i, struct dce_db_fb *db_fb) long dce6_sink_mode_set(struct dce6 *dce, u8 i, struct dce_db_fb *db_fb)
318 348 { {
319 349 long r; long r;
320 350 struct sink_db_fb sink_db_fb; struct sink_db_fb sink_db_fb;
321 351 struct alga_timing ts[ALGA_TIMINGS_MAX]; struct alga_timing ts[ALGA_TIMINGS_MAX];
322 352 u8 pixel_fmt; u8 pixel_fmt;
353 u8 active_cnt;
354 u8 active_first;
323 355
324 356 lock(dce); lock(dce);
325 357
 
... ... long dce6_sink_mode_set(struct dce6 *dce, u8 i, struct dce_db_fb *db_fb)
376 408 } }
377 409
378 410 r = sink_mode_set(dce, i, &sink_db_fb); r = sink_mode_set(dce, i, &sink_db_fb);
411 if (r == -DCE6_ERR)
412 goto unlock;
413
414 dce->dps[i].active = 1;
415
416 dps_used_active_info(dce, &active_cnt, &active_first);
417
418 /* this is some dynamic power management related notification */
419 dce->ddev.dyn_pm_new_display_notify(dce->ddev.dev, active_cnt,
420 active_first);
379 421 unlock: unlock:
380 422 unlock(dce); unlock(dce);
381 423 return r; return r;
 
... ... long dce6_dp_dpm(struct dce6 *dce, u8 i)
398 440 goto unlock; goto unlock;
399 441 } }
400 442 r = dp_dpm_off(dce, i); r = dp_dpm_off(dce, i);
443 if (r == -DCE6_ERR)
444 goto unlock;
445
446 dce->dps[i].active = 0;
447
401 448 unlock: unlock:
402 449 unlock(dce); unlock(dce);
403 450 return r; return r;
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index 6a676e9..cd199b9)
... ... static int probe(struct pci_dev *dev, const struct pci_device_id *id)
569 569 ddev.crtcs_n = dd->cfg.dce_crtcs_n; ddev.crtcs_n = dd->cfg.dce_crtcs_n;
570 570 ddev.rr32 = extern_rr32; ddev.rr32 = extern_rr32;
571 571 ddev.wr32 = extern_wr32; ddev.wr32 = extern_wr32;
572 ddev.dyn_pm_new_display_notify = dyn_pm_new_display_notify;
572 573
573 574 dd->dce = dce6_alloc(&ddev); dd->dce = dce6_alloc(&ddev);
574 575
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c changed (mode: 100644) (index 56ea94e..2f10e4a)
... ... static void sstp_program(struct pci_dev *dev)
424 424 | set(CS_SST, SSTP_SST_DEFAULT), CG_SSP); | set(CS_SST, SSTP_SST_DEFAULT), CG_SSP);
425 425 } }
426 426
427 #define DISP_GAP_VBLANK_OR_WM 0
428 #define DISP_GAP_VBLANK 1
429 #define DISP_GAP_WATERMARK 2
430 #define DISP_GAP_IGNORE 3
431 427 static void display_gap_ena(struct pci_dev *dev) static void display_gap_ena(struct pci_dev *dev)
432 428 { {
433 429 u32 cg_disp_gap_ctl; u32 cg_disp_gap_ctl;
 
... ... static void display_gap_ena(struct pci_dev *dev)
435 431 cg_disp_gap_ctl = rr32(dev, CG_DISP_GAP_CTL); cg_disp_gap_ctl = rr32(dev, CG_DISP_GAP_CTL);
436 432
437 433 cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP | CDGC_DISP2_GAP); cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP | CDGC_DISP2_GAP);
438 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP, DISP_GAP_IGNORE)
439 | set(CDGC_DISP2_GAP, DISP_GAP_IGNORE);
434 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP, CDGC_IGNORE)
435 | set(CDGC_DISP2_GAP, CDGC_IGNORE);
440 436
441 437 cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP_MCHG | CDGC_DISP2_GAP_MCHG); cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP_MCHG | CDGC_DISP2_GAP_MCHG);
442 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP_MCHG, DISP_GAP_VBLANK)
443 | set(CDGC_DISP2_GAP_MCHG, DISP_GAP_IGNORE);
438 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP_MCHG, CDGC_VBLANK)
439 | set(CDGC_DISP2_GAP_MCHG, CDGC_IGNORE);
444 440 LOG("display gap programming, CG_DISP_GAP_CTL=0x%08x", cg_disp_gap_ctl); LOG("display gap programming, CG_DISP_GAP_CTL=0x%08x", cg_disp_gap_ctl);
445 441 wr32(dev, cg_disp_gap_ctl, CG_DISP_GAP_CTL); wr32(dev, cg_disp_gap_ctl, CG_DISP_GAP_CTL);
446 442 } }
447 443
444 /*
445 * Callback for DCE code to notify the dynamic power management related
446 * hardware. This hardware block is insane once you think more than 1/2
447 * display/s...
448 */
449 void dyn_pm_new_display_notify(struct device *dev, u8 dps_active_cnt,
450 u8 dps_active_first)
451 {
452 struct pci_dev *pdev;
453 u32 cg_disp_gap_ctl;
454 u32 dccg_disp_slow_select;
455 u32 pipe;
456 long r;
457
458 pdev = container_of(dev, struct pci_dev, dev);
459
460 cg_disp_gap_ctl = rr32(pdev, CG_DISP_GAP_CTL);
461 cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP | CDGC_DISP2_GAP);
462
463 if (dps_active_cnt) {
464 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP,
465 CDGC_VBLANK_OR_WATERMARK);
466 pipe = dps_active_first;
467 } else {
468 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP, CDGC_IGNORE);
469 pipe = 0;
470 }
471
472 if (dps_active_cnt >= 2)
473 cg_disp_gap_ctl |= set(CDGC_DISP2_GAP,
474 CDGC_VBLANK_OR_WATERMARK);
475 else
476 cg_disp_gap_ctl |= set(CDGC_DISP2_GAP, CDGC_IGNORE);
477
478 /*-------------------------------------------------------------------*/
479
480 wr32(pdev, cg_disp_gap_ctl, CG_DISP_GAP_CTL);
481
482 dccg_disp_slow_select = rr32(pdev, DCCG_DISP_SLOW_SELECT);
483 dccg_disp_slow_select &= ~DDSSR_DISP1_SLOW_SELECT;
484 dccg_disp_slow_select |= set(DDSSR_DISP1_SLOW_SELECT, pipe);
485 wr32(pdev, dccg_disp_slow_select, DCCG_DISP_SLOW_SELECT);
486
487 /*-------------------------------------------------------------------*/
488
489 /*
490 * XXX: always tell the smc we have displays in order to use GPU
491 * to full performance even with no connected displays
492 */
493 r = smc_msg(pdev, SMC_MSG_HAS_DISPLAY);
494 if (r == -SI_ERR)
495 dev_err(dev, "dyn_pm:display_notify:smc:unable to notify the smc of display new configuration\n");
496 }
497
448 498 #define VRC_DEFAULT 0xc000b3 #define VRC_DEFAULT 0xc000b3
449 499 static void vc_program(struct pci_dev *dev) static void vc_program(struct pci_dev *dev)
450 500 { {
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.h changed (mode: 100644) (index b9ff2ff..1de22c1)
7 7 */ */
8 8 long dyn_pm_ena(struct pci_dev *dev); long dyn_pm_ena(struct pci_dev *dev);
9 9 void dyn_pm_dis(struct pci_dev *dev); void dyn_pm_dis(struct pci_dev *dev);
10 void dyn_pm_new_display_notify(struct device *dev, u8 dps_active_cnt,
11 u8 dps_active_first);
10 12 #endif #endif
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 9d3982e..cbc339f)
... ... static inline u32 get(u32 mask, u32 v)
35 35
36 36 #define MM_IDX_HI 0x18 #define MM_IDX_HI 0x18
37 37
38 #define CG_ENG_PLL_AUTOSCALE_CTL 0x62c
39 #define CEPAC_AUTOSCALE_ON_SS_CLR BIT(9)
38 #define DCCG_DISP_SLOW_SELECT 0x4fc
39 #define DDSSR_DISP1_SLOW_SELECT 0x00000007
40 #define DDSSR_DISP2_SLOW_SELECT 0x00000070
40 41
41 42 #define CG_ENG_PLL_FUNC_CTL_0 0x600 #define CG_ENG_PLL_FUNC_CTL_0 0x600
42 43 #define CEPFC0_RESET BIT(0) #define CEPFC0_RESET BIT(0)
 
... ... static inline u32 get(u32 mask, u32 v)
57 58 #define CG_ENG_PLL_SS_1 0x624 #define CG_ENG_PLL_SS_1 0x624
58 59 #define CEPS1_CLK_V 0x03ffffff #define CEPS1_CLK_V 0x03ffffff
59 60
61 #define CG_ENG_PLL_AUTOSCALE_CTL 0x62c
62 #define CEPAC_AUTOSCALE_ON_SS_CLR BIT(9)
63
60 64 #define CG_CLK_PIN_CTL_0 0x660 #define CG_CLK_PIN_CTL_0 0x660
61 65 #define CCC0_XTAL_IN_DIVIDE BIT(1) #define CCC0_XTAL_IN_DIVIDE BIT(1)
62 66 #define CCC0_BCLK_AS_XCLK BIT(2) #define CCC0_BCLK_AS_XCLK BIT(2)
 
... ... static inline u32 get(u32 mask, u32 v)
143 147 #define CG_DISP_GAP_CTL 0x828 #define CG_DISP_GAP_CTL 0x828
144 148 #define CDGC_DISP1_GAP 0x00000003 #define CDGC_DISP1_GAP 0x00000003
145 149 #define CDGC_DISP2_GAP 0x0000000c #define CDGC_DISP2_GAP 0x0000000c
150 #define CDGC_VBLANK_OR_WATERMARK 0
151 #define CDGC_VBLANK 1
152 #define CDGC_WATERMARK 2
153 #define CDGC_IGNORE 3
146 154 #define CDGC_VBI_TIMER_CNT 0x0003fff0 #define CDGC_VBI_TIMER_CNT 0x0003fff0
147 155 #define CDGC_VBI_TIMER_UNIT 0x00700000 #define CDGC_VBI_TIMER_UNIT 0x00700000
148 156 #define CDGC_DISP1_GAP_MCHG 0x03000000 #define CDGC_DISP1_GAP_MCHG 0x03000000
File include/alga/amd/dce6/dce6_dev.h changed (mode: 100644) (index a46bfe0..e693c23)
... ... struct dce6_dev {/* provides device specific services for dce6 */
10 10 u8 crtcs_n; u8 crtcs_n;
11 11 u32 (*rr32)(struct device *dev, u32 of); u32 (*rr32)(struct device *dev, u32 of);
12 12 void (*wr32)(struct device *dev, u32 val, u32 of); void (*wr32)(struct device *dev, u32 val, u32 of);
13 void (*dyn_pm_new_display_notify)(struct device *dev, u8 dps_active_cnt,
14 u8 dps_active_first);
13 15 struct atombios *atb; struct atombios *atb;
14 16 }; };
15 17 #endif #endif
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/linux-gpu-amd-si

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main