sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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master
List of commits:
Subject Hash Author Date (UTC)
smc_mc_arb_tbl init for the driver state 5d1868e75b11164dbb97caaddbc7992b252ab973 Sylvain BERTRAND 2014-02-14 13:01:26
smc_mc_reg tbl init for the driver state e8aa12b1c87571031098c4427822733a74133afc Sylvain BERTRAND 2014-02-14 11:32:04
installation of the perf pwr state continued 535c853e7d0a0ab04fbff3b0d5613ef9a34d525c Sylvain BERTRAND 2014-02-13 19:16:33
installation of the perf pwr state continued b229eef2798acbe053aa09e47c213e23749638dd Sylvain BERTRAND 2014-02-13 10:48:02
dyn pm second part continuation 95dd7b4754476a014d8f84854e5b2ce5c81d23b4 Sylvain BERTRAND 2014-02-12 20:15:03
beginning of dyn pm second part c32c19d884dbf1f440480bbea42140e9c5ed8cd3 Sylvain BERTRAND 2014-02-12 14:44:04
uvd does only mpeg, then switch off 7e36b98bcab47e9986a63093dbeed98ab290f85f Sylvain BERTRAND 2014-02-12 10:55:54
bug fixing, end of dyn pm first part 533a4bd6731205f71704886e5fa099063be985ea Sylvain BERTRAND 2014-02-11 13:49:27
bug fixing c3fc0d7b807c98d20c13f53dcfc09713309ad2fa Sylvain BERTRAND 2014-02-11 11:16:00
static bios tbls *must* be ok e050fa94c2f1e846bb051748347332e234a6b93a Sylvain BERTRAND 2014-02-10 10:17:33
bug fixing 7baa7069aa89a98d831d7def358766155771e9ca Sylvain BERTRAND 2014-02-07 15:08:53
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
tbls fixes 4795a3090a17bc486056301bc6bef509b9c5e339 Sylvain BERTRAND 2014-02-05 15:09:41
log more accurately the smc tbls 3d88d2a589a89e9a34f4046242f4a72a76069ddb Sylvain BERTRAND 2014-02-05 10:51:39
log more 5018f3c130cb9ce53e1834fcc586f00614a3ed86 Sylvain BERTRAND 2014-02-04 21:46:05
smc sw regs dump code 46acefa1d42984757cb1ba48a32130f2f9674687 Sylvain BERTRAND 2014-02-04 20:44:26
do dump the tbls c79209766b71e2d3231cf25673684762bf46dd8c Sylvain BERTRAND 2014-02-04 20:20:33
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
Commit 5d1868e75b11164dbb97caaddbc7992b252ab973 - smc_mc_arb_tbl init for the driver state
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-14 13:01
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-14 13:01
Parent(s): e8aa12b1c87571031098c4427822733a74133afc
Signing key:
Tree: ac8c8e3cafa0eb9d7fa7caae1e70c98ebd778b27
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/driver.c 51 2
drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.c 3 3
drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.h 1 1
drivers/gpu/alga/amd/si/dyn_pm/ulv.c 1 1
drivers/gpu/alga/amd/si/smc_tbls.h 3 3
File drivers/gpu/alga/amd/si/dyn_pm/driver.c changed (mode: 100644) (index 53742e2..9320c27)
38 38 #include "smc_lvl.h" #include "smc_lvl.h"
39 39 #include "smc_volt.h" #include "smc_volt.h"
40 40 #include "smc_mc_reg_tbl.h" #include "smc_mc_reg_tbl.h"
41 #include "smc_mc_arb_tbl.h"
41 42
42 43 static void smc_sw_state_init(struct ctx *ctx, struct smc_sw_state *state) static void smc_sw_state_init(struct ctx *ctx, struct smc_sw_state *state)
43 44 { {
 
... ... static void smc_mc_reg_sets_init(struct ctx *ctx, struct smc_mc_reg_set *sets)
335 336 smc_mc_reg_set_init(ctx, set_idx, &sets[set_idx]); smc_mc_reg_set_init(ctx, set_idx, &sets[set_idx]);
336 337 } }
337 338
339 static long smc_mc_arb_reg_set_init(struct ctx *ctx, u8 smc_set_idx,
340 struct smc_mc_arb_reg_set *set)
341 {
342 u32 eng_clk;
343 u32 mem_clk;
344
345 eng_clk = ctx->atb_performance.lvls[smc_set_idx].eng_clk;
346 mem_clk = ctx->atb_performance.lvls[smc_set_idx].mem_clk;
347
348 return smc_mc_arb_tbl_set_compute(ctx, set, eng_clk, mem_clk);
349 }
350
351 static long smc_mc_arb_reg_sets_init(struct ctx *ctx,
352 struct smc_mc_arb_reg_set *sets)
353 {
354 u8 set_idx;
355
356 for (set_idx = 0; set_idx < ctx->atb_performance.lvls_n; ++set_idx) {
357 long r;
358
359 r = smc_mc_arb_reg_set_init(ctx, set_idx, &sets[set_idx]);
360 if (r == -SI_ERR)
361 return -SI_ERR;
362 }
363 return 0;
364 }
365
338 366 static long smc_tbls_init(struct ctx *ctx) static long smc_tbls_init(struct ctx *ctx)
339 367 { {
340 368 struct smc_sw_state *smc_sw_state; struct smc_sw_state *smc_sw_state;
341 369 struct smc_lvl *smc_lvls; struct smc_lvl *smc_lvls;
342 370 struct smc_mc_reg_set *smc_mc_reg_sets; struct smc_mc_reg_set *smc_mc_reg_sets;
371 struct smc_mc_arb_reg_set *smc_mc_arb_reg_sets;
343 372 long r; long r;
344 373
345 374 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
 
... ... static long smc_tbls_init(struct ctx *ctx)
378 407
379 408 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
380 409
381 //TODO:mc_arb_regs...
410 smc_mc_arb_reg_sets = kzalloc(sizeof(*smc_mc_arb_reg_sets)
411 * ctx->atb_performance.lvls_n, GFP_KERNEL);
412 if (!smc_mc_arb_reg_sets) {
413 dev_err(&ctx->dev->dev, "dyn_pm:driver:unable to alloc the smc_mc_arb_reg_sets\n");
414 goto err_free_smc_mc_reg_sets;
415 }
382 416
383 //TODO:cpy in smc sram and dump the tables from smc sram
417 r = smc_mc_arb_reg_sets_init(ctx, smc_mc_arb_reg_sets);
418 if (r == -SI_ERR)
419 goto err_free_smc_mc_arb_reg_sets;
420
421 /*--------------------------------------------------------------------*/
422
423 //TODO:finish the tbls...
384 424
425 //TODO:cpy in smc sram and dump the tables from smc sram...
426
427 kfree(smc_mc_arb_reg_sets);
385 428 kfree(smc_mc_reg_sets); kfree(smc_mc_reg_sets);
386 429 kfree(smc_lvls); kfree(smc_lvls);
387 430 kfree(smc_sw_state); kfree(smc_sw_state);
388 431 return 0; return 0;
389 432
433 err_free_smc_mc_arb_reg_sets:
434 kfree(smc_mc_arb_reg_sets);
435
436 err_free_smc_mc_reg_sets:
437 kfree(smc_mc_reg_sets);
438
390 439 err_free_smc_lvls: err_free_smc_lvls:
391 440 kfree(smc_lvls); kfree(smc_lvls);
392 441
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.c changed (mode: 100644) (index dc0256e..a10de0a)
... ... void smc_mc_arb_tbl_dump(struct smc_mc_arb_tbl *tbl)
53 53 for (i = 0; i < 3; ++i) for (i = 0; i < 3; ++i)
54 54 L("rsvd[%u]=0x%02x",i,tbl->rsvd[i]); L("rsvd[%u]=0x%02x",i,tbl->rsvd[i]);
55 55
56 for (i = 0; i < SMC_ARB_TBL_SETS_N_MAX; ++i) {
56 for (i = 0; i < SMC_MC_ARB_TBL_SETS_N_MAX; ++i) {
57 57 u32 tmp; u32 tmp;
58 58 u8 j; u8 j;
59 59
 
... ... static u8 refresh_rate(struct ctx *ctx, u32 eng_clk)
100 100 / 64); / 64);
101 101 } }
102 102
103 long smc_mc_arb_tbl_set_compute(struct ctx *ctx, struct smc_mc_arb_regs *set,
103 long smc_mc_arb_tbl_set_compute(struct ctx *ctx, struct smc_mc_arb_reg_set *set,
104 104 u32 eng_clk, u32 mem_clk) u32 eng_clk, u32 mem_clk)
105 105 { {
106 106 struct dev_drv_data *dd; struct dev_drv_data *dd;
 
... ... static long initial_emergency_init(struct ctx *ctx,
141 141 { {
142 142 u32 eng_clk; u32 eng_clk;
143 143 u32 mem_clk; u32 mem_clk;
144 struct smc_mc_arb_regs *initial_set;
144 struct smc_mc_arb_reg_set *initial_set;
145 145 long r; long r;
146 146
147 147 /* /*
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.h changed (mode: 100644) (index 7e39060..98d49a6)
9 9 void smc_mc_arb_tbl_dump(struct smc_mc_arb_tbl *tbl); void smc_mc_arb_tbl_dump(struct smc_mc_arb_tbl *tbl);
10 10 #endif #endif
11 11
12 long smc_mc_arb_tbl_set_compute(struct ctx *ctx, struct smc_mc_arb_regs *set,
12 long smc_mc_arb_tbl_set_compute(struct ctx *ctx, struct smc_mc_arb_reg_set *set,
13 13 u32 eng_clk, u32 mem_clk); u32 eng_clk, u32 mem_clk);
14 14 long smc_mc_arb_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl, long smc_mc_arb_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
15 15 struct smc_mc_arb_tbl *smc_mc_arb_tbl); struct smc_mc_arb_tbl *smc_mc_arb_tbl);
File drivers/gpu/alga/amd/si/dyn_pm/ulv.c changed (mode: 100644) (index 4a7df4c..3b28c39)
... ... long smc_mc_arb_tbl_ulv_init(struct ctx *ctx,
106 106 { {
107 107 u32 eng_clk; u32 eng_clk;
108 108 u32 mem_clk; u32 mem_clk;
109 struct smc_mc_arb_regs *ulv_set;
109 struct smc_mc_arb_reg_set *ulv_set;
110 110 long r; long r;
111 111
112 112 /* /*
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index dd8abd9..f6fd27d)
... ... struct smc_mc_reg_tbl {
253 253 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
254 254 /* offset in smc address space SMC_FW_HDR_MC_ARB_TBL */ /* offset in smc address space SMC_FW_HDR_MC_ARB_TBL */
255 255 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
256 struct smc_mc_arb_regs {
256 struct smc_mc_arb_reg_set {
257 257 __be32 dram_timing_x_0; __be32 dram_timing_x_0;
258 258 __be32 dram_timing_x_1; __be32 dram_timing_x_1;
259 259 u8 refresh_rate; u8 refresh_rate;
 
... ... struct smc_mc_arb_regs {
261 261 u8 pad[2]; u8 pad[2];
262 262 } __packed; } __packed;
263 263
264 #define SMC_ARB_TBL_SETS_N_MAX 16
264 #define SMC_MC_ARB_TBL_SETS_N_MAX 16
265 265 struct smc_mc_arb_tbl { struct smc_mc_arb_tbl {
266 266 /* this is the *hw* set, not one of the following sets */ /* this is the *hw* set, not one of the following sets */
267 267 u8 arb_freq_fx_current; /* MAC_MC_CG_ARB_FREQ_Fx */ u8 arb_freq_fx_current; /* MAC_MC_CG_ARB_FREQ_Fx */
268 268 u8 rsvd[3]; u8 rsvd[3];
269 struct smc_mc_arb_regs sets[SMC_ARB_TBL_SETS_N_MAX];
269 struct smc_mc_arb_reg_set sets[SMC_MC_ARB_TBL_SETS_N_MAX];
270 270 } __packed; } __packed;
271 271 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
272 272
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