sylware / vulkan-misc (public) (License: public domain) (since 2019-10-25) (hash sha1)
misc vulkan based project
Clone URLs: https://rocketgit.com/user/sylware/vulkan-misc ssh://rocketgit@ssh.rocketgit.com/user/sylware/vulkan-misc git://git.rocketgit.com/user/sylware/vulkan-misc
master
List of commits:
Subject Hash Author Date (UTC)
partial and brainded pm4 disassembler 88bd38675091a9164583a05abb672c6d1962d133 Sylvain BERTRAND 2019-11-30 19:10:22
untested amd gcn gfx6 disassembler 942c2b45ce87dd3c031289acf662679933997c21 Sylvain BERTRAND 2019-11-28 18:45:56
typos 729922e37ff800683763794352533924250e8579 Sylvain BERTRAND 2019-11-17 16:33:36
braindead partial spir-v disassembler a347cbcc8284301ad6989d486373f0d2ffb9657c Sylvain BERTRAND 2019-11-16 17:48:29
Initial commit 1cd013eaa1466522d61c7b0e64d5858055fedbfa Sylvain BERTRAND 2019-10-25 18:49:16
Commit 88bd38675091a9164583a05abb672c6d1962d133 - partial and brainded pm4 disassembler
Author: Sylvain BERTRAND
Author date (UTC): 2019-11-30 19:10
Committer name: Sylvain BERTRAND
Committer date (UTC): 2019-11-30 19:10
Parent(s): 942c2b45ce87dd3c031289acf662679933997c21
Signing key:
Tree: 8df9d815374b3dacbfc13656cec33ac0e5591040
File Lines added Lines deleted
amd/gcn/pm4/README 12 0
amd/gcn/pm4/dis.c 523 0
amd/gcn/pm4/regs.h 634 0
File amd/gcn/pm4/README added (mode: 100644) (index 0000000..9abdc0b)
1 braindead, partial, hardly tested, amd gcn pm4 disassembler.
2 pm4 packets are the gpu commands.
3
4 very strong added values are the collected and expanded amd register acronyms.
5
6 PROS:
7 - it is not c++
8 - it is _simple_ C, then portable
9 - does not contain code generators using additional expensive dependencies
10
11 CONS:
12 - it is not risc-v assembly
File amd/gcn/pm4/dis.c added (mode: 100644) (index 0000000..36d598d)
1 #include <stdbool.h>
2 #include <stdio.h>
3 #include <stdint.h>
4 #include <stdlib.h>
5 #include <string.h>
6 /*
7 * ABBREVIATIONS:
8 * blk : BLocK
9 * cfg : ConFiG
10 * coher : COHERent
11 * ctx : ConTeX
12 * desc : DESCription
13 * dest : DESTination
14 * hdr :HeaDeR
15 * idx : InDeX
16 * me : Micro Engine
17 * n : couNt
18 * oft(s) : OFfseT(S)
19 * pfp : PreFetch Processor
20 * pkt : PacKeT
21 * reg(s) : REGister(S)
22 * sel : SELection
23 * src : SouRCe
24 * w(s) : Word(S)
25 */
26 #define u8 uint8_t
27 #define u16 uint16_t
28 #define u32 uint32_t
29 #define u64 uint64_t
30 #define constant enum
31 #define loop for(;;)
32 #define out(fmt,...) fprintf(stdout,fmt, ##__VA_ARGS__)
33 #define ARRAY_N(x) ((u64)(sizeof(x) / sizeof(x[0])))
34 /*----------------------------------------------------------------------------*/
35 static u32 pkt_hdr_w;
36 #define PKT_HDR_TYPE (pkt_hdr_w >> 30)
37 /* 0-based index of the last body w from the first body w */
38 #define PKT_HDR_BODY_WS_LAST ((pkt_hdr_w & 0x3fff0000) >> 16)
39 /* n of ws in body is all pkt types bits [29:16], aka 14 bits */
40 static u32 pkt_body_ws[0x3fff];
41 static u32 pkt_body_ws_n;
42 /*----------------------------------------------------------------------------*/
43 #define PKT3_OPCODE_NOP 0x10
44 #define PKT3_OPCODE_SET_BASE 0x11
45 #define PKT3_OPCODE_INDEX_BUFFER_SIZE 0x13
46 /* vulkan indirect draw */
47 #define PKT3_OPCODE_DRAW_INDIRECT 0x24
48 /* vulkan indirect draw */
49 #define PKT3_OPCODE_DRAW_INDEX_INDIRECT 0x25
50 #define PKT3_OPCODE_INDEX_BASE 0x26
51 /* vulkan draw_indexed */
52 #define PKT3_OPCODE_DRAW_INDEX_2 0x27
53 /* vulkan indirect draw */
54 #define PKT3_OPCODE_DRAW_INDIRECT_MULTI 0x2c
55 /* vulkan draw */
56 #define PKT3_OPCODE_DRAW_INDEX_AUTO 0x2d
57 #define PKT3_OPCODE_NUM_INSTANCES 0x2f
58 #define PKT3_OPCODE_WRITE_DATA 0x37
59 /* vulkan indirect draw */
60 #define PKT3_OPCODE_DRAW_INDEX_INDIRECT_MULTI 0x38
61 #define PKT3_OPCODE_COPY_DATA 0x40
62 #define PKT3_OPCODE_PFP_SYNC_ME 0x42
63 #define PKT3_OPCODE_SURFACE_SYNC 0x43 /* deprecated on CIK chips */
64 #define PKT3_OPCODE_EVENT_WRITE 0x46
65 #define PKT3_OPCODE_SET_CONFIG 0x68
66 #define PKT3_OPCODE_SET_CONTEXT 0x69
67 #define PKT3_OPCODE_SET_SH_REG 0x76
68 /*----------------------------------------------------------------------------*/
69 #define OK 0
70 #define END 1
71 #define ERR 2
72 static u8 pkt_hdr_w_read(void)
73 {
74 size_t read_bytes_n;
75
76 read_bytes_n = fread(&pkt_hdr_w, sizeof(pkt_hdr_w), 1, stdin);
77 if (read_bytes_n != sizeof(pkt_hdr_w)) {
78 if (feof(stdin) != 0)
79 return END;
80 if (ferror(stdin) != 0)
81 return ERR;
82 }
83 }
84
85 static u8 pkt_body_ws_read(void)
86
87 {
88 size_t read_bytes_n;
89
90 read_bytes_n = fread(pkt_body_ws, sizeof(u32), pkt_body_ws_n, stdin);
91 if (read_bytes_n != (sizeof(u32) * pkt_body_ws_n)) {
92 if (feof(stdin) != 0)
93 return END;
94 if (ferror(stdin) != 0)
95 return ERR;
96 }
97 }
98 /*----------------------------------------------------------------------------*/
99 #include "regs.h"
100 static u8 *reg_name(u8 blk, u64 w_oft)
101 {
102 u64 i;
103 u8 *name;
104 static u8 desc[256];
105 u64 global_w_oft;
106
107 i = 0;
108 loop {
109 if (i == ARRAY_N(reg_descs)) {
110 name = "no_register_description";
111 break;
112 }
113 if (reg_descs[i].blk == blk && reg_descs[i].w_oft == w_oft) {
114 name = reg_descs[i].name;
115 break;
116 }
117 ++i;
118 }
119 global_w_oft = reg_blk_w_ofts[blk] + w_oft;
120 snprintf(desc, 256, "%s[0x%016lx global byte offset/%lu global byte offset/0x%016lx global word offset]", name, global_w_oft * 4, global_w_oft * 4, global_w_oft);
121 return desc;
122 }
123 /*----------------------------------------------------------------------------*/
124 #define PKT0_BASE_IDX (pkt_hdr_w & 0x0000ffff)
125 static void pkt0_out(void)
126 {
127 u16 i;
128
129 out("\nPKT0(%u words):base_idx_w=0x%08x\n", pkt_body_ws_n, PKT0_BASE_IDX);
130
131 i = 0;
132 loop {
133 if (i == pkt_body_ws_n)
134 break;
135 out("\tREG_DATA[%u]=0x%08x\n", i, pkt_body_ws[i]);
136 ++i;
137 }
138 }
139
140 static void pkt1_out(void)
141 {
142 out("\nPKT1(UNSUPPORTED)\n");
143 }
144
145 static void pkt2_out(void)
146 {
147 out("\nPKT2(FILLER)\n");
148 }
149
150 static u8 *shader_type_to_str(u8 type)
151 {
152 if (type != 0)
153 return "compute";
154 return "graphics";
155 }
156
157 static u8 *engine_to_str(u8 engine)
158 {
159 switch (engine) {
160 case 0x00:
161 return "micro_engine";
162 case 0x01:
163 return "prefect_engine(unsupported)";
164 case 0x02:
165 return "constant_engine";
166 case 0x04:
167 return "reserved";
168 default:
169 return "unknown_engine_code";
170 }
171 }
172
173 static u8 *count_sel_to_str(u8 count_sel)
174 {
175 switch (count_sel) {
176 case 0:
177 return "32bits";
178 case 1:
179 return "64bits";
180 default:
181 return "unknown_w_count_selection_code";
182 }
183 }
184
185 static u8 *dest_sel_to_str(u8 dest_sel)
186 {
187 switch (dest_sel) {
188 case 0x00:
189 return "memory_mapped_register";
190 case 0x01:
191 return "memory(synchronous)";
192 case 0x02:
193 return "texture_cache(level_2)";
194 case 0x03:
195 return "global_data_share";
196 case 0x04:
197 return "reserved";
198 case 0x05:
199 return "memory(asynchronous)";
200 default:
201 return "unknown_destination_selection_code";
202 }
203 }
204
205 static u8 *src_sel_to_str(u8 src_sel)
206 {
207 switch (src_sel) {
208 case 0x00:
209 return "memory_mapped_register";
210 case 0x01:
211 return "memory";
212 case 0x02:
213 return "texture_cache(level_2)";
214 case 0x03:
215 return "global_data_share";
216 case 0x04:
217 return "reserved";
218 case 0x05:
219 return "immediate_data";
220 case 0x06:
221 return "atomic_return_data";
222 case 0x07:
223 return "global_data_share_return_data_0";
224 case 0x08:
225 return "global_data_share_return_data_1";
226 default:
227 return "unknown_source_selection_code";
228 }
229 }
230
231 #define WRITE_DATA_ENGINE ((u8)(pkt_body_ws[0] & 0xc0000000) >> 31)
232 #define WRITE_DATA_WRITE_IS_CONFIRMED ((pkt_body_ws[0] & 0x00100000) != 0)
233 #define WRITE_DATA_DOES_INCREMENT_ADDRESS ((u8)(pkt_body_ws[0] & 0x00010000) != 0)
234 #define WRITE_DATA_DEST_SEL ((u8)((pkt_body_ws[0] & 0x000000f00) >> 8))
235 static void opcode_write_data_out(void)
236 {
237 u16 i;
238
239 out("\tcontrol:engine=%s wait_write_confirmation=%s increment_address=%s destination_selection=%s\n", engine_to_str(WRITE_DATA_ENGINE), WRITE_DATA_WRITE_IS_CONFIRMED ? "yes" : "no", WRITE_DATA_DOES_INCREMENT_ADDRESS ? "yes" : "no", dest_sel_to_str(WRITE_DATA_DEST_SEL));
240 out("\tdestination_address_lo=0x%08x\n", pkt_body_ws[1]);
241 out("\tdestination_address_hi=0x%08x\n", pkt_body_ws[2]);
242
243 i = 3;
244 loop {
245 if (i == pkt_body_ws_n)
246 break;
247 out("\tdata[%u]=0x%08x\n", i - 3, pkt_body_ws[i]);
248 ++i;
249 }
250 }
251
252 #define COPY_DATA_ENGINE ((u8)(pkt_body_ws[0] & 0xc0000000) >> 31)
253 #define COPY_DATA_WRITE_IS_CONFIRMED ((pkt_body_ws[0] & 0x00100000) != 0)
254 #define COPY_DATA_COUNT_SEL ((u8)(pkt_body_ws[0] & 0x00010000) >> 16)
255 #define COPY_DATA_DEST_SEL ((u8)((pkt_body_ws[0] & 0x000000f00) >> 8))
256 #define COPY_DATA_SRC_SEL ((u8)(pkt_body_ws[0] & 0x0000000f))
257 static void opcode_copy_data_out(void)
258 {
259 out("\tcontrol:engine=%s wait_write_confirmation=%s count_selection=%s destination_selection=%s source_selection=%s\n", engine_to_str(COPY_DATA_ENGINE), COPY_DATA_WRITE_IS_CONFIRMED ? "yes" : "no", count_sel_to_str(COPY_DATA_COUNT_SEL), dest_sel_to_str(COPY_DATA_DEST_SEL), src_sel_to_str(COPY_DATA_SRC_SEL));
260 out("\tsrc_addr_lo=0x%08x\n", pkt_body_ws[1]);
261 out("\tsrc_addr_hi=0x%08x\n", pkt_body_ws[2]);
262 out("\tdest_addr_lo=0x%08x\n", pkt_body_ws[3]);
263 out("\tdest_addr_hi=0x%08x\n", pkt_body_ws[4]);
264 }
265
266 static u8 *opcode_to_str(u8 opcode)
267 {
268 /* TODO */
269 switch (opcode) {
270 case PKT3_OPCODE_NOP:
271 return "nop";
272 case PKT3_OPCODE_SET_SH_REG:
273 return "set_sh_reg";
274 case PKT3_OPCODE_WRITE_DATA:
275 return "write_data";
276 case PKT3_OPCODE_COPY_DATA:
277 return "copy_data";
278 case PKT3_OPCODE_DRAW_INDIRECT:
279 return "draw_indirect";
280 case PKT3_OPCODE_DRAW_INDEX_INDIRECT:
281 return "draw_index_indirect";
282 case PKT3_OPCODE_DRAW_INDEX_2:
283 return "draw_index_2";
284 case PKT3_OPCODE_DRAW_INDIRECT_MULTI:
285 return "draw_indirect_multi";
286 case PKT3_OPCODE_DRAW_INDEX_AUTO:
287 return "draw_index_auto";
288 case PKT3_OPCODE_DRAW_INDEX_INDIRECT_MULTI:
289 return "draw_index_indirect_multi";
290 case PKT3_OPCODE_SET_BASE:
291 return "set_base";
292 case PKT3_OPCODE_INDEX_BASE:
293 return "index_base";
294 case PKT3_OPCODE_INDEX_BUFFER_SIZE:
295 return "index_buffer_size";
296 case PKT3_OPCODE_SET_CONTEXT:
297 return "set_context";
298 case PKT3_OPCODE_SET_CONFIG:
299 return "set_config";
300 case PKT3_OPCODE_NUM_INSTANCES:
301 return "num_instances";
302 case PKT3_OPCODE_EVENT_WRITE:
303 return "event_write";
304 case PKT3_OPCODE_PFP_SYNC_ME:
305 return "pfp_sync_me";
306 case PKT3_OPCODE_SURFACE_SYNC:
307 return "surface_sync(deprecated on cik chips)";
308 default:
309 return "unknown_opcode";
310 }
311 }
312
313 /* an all chips, the register byte offset is 0x8000, or 0x2000 as a w offset */
314 static void opcode_set_config_reg_out(void)
315 {
316 u16 i;
317
318 out("\treg_offset_w=0x%08x\n", pkt_body_ws[0]);
319
320 i = 1;
321 loop {
322 if (i == pkt_body_ws_n)
323 break;
324 out("\treg_data[%u]=0x%08x %s\n", i - 1, pkt_body_ws[i], reg_name(reg_blk_cfg, (u64)pkt_body_ws[0] + i - 1));
325 ++i;
326 }
327 }
328
329 /* an all chips, the register byte offset is 0xb000, or 0x2c00 as a w offset */
330 static void opcode_set_sh_reg_out(void)
331 {
332 u16 i;
333
334 out("\treg_offset_w=0x%08x\n", pkt_body_ws[0]);
335
336 i = 1;
337 loop {
338 if (i == pkt_body_ws_n)
339 break;
340 out("\treg_data[%u]=0x%08x %s\n", i - 1, pkt_body_ws[i], reg_name(reg_blk_sh, (u64)pkt_body_ws[0] + i - 1));
341 ++i;
342 }
343 }
344
345 /* an all chips, the register byte offset is 0x28000, or 0xa000 as a w offset */
346 static void opcode_set_context_reg_out(void)
347 {
348 u16 i;
349
350 out("\treg_offset_w=0x%08x\n", pkt_body_ws[0]);
351
352 i = 1;
353 loop {
354 if (i == pkt_body_ws_n)
355 break;
356 out("\treg_data[%u]=0x%08x %s\n", i - 1, pkt_body_ws[i], reg_name(reg_blk_ctx, (u64)pkt_body_ws[0] + i - 1));
357 ++i;
358 }
359 }
360
361 static void opcode_event_write_out(void)
362 {
363 out("\tevent_cntl=0x%08x\n", pkt_body_ws[0]);
364 if (pkt_body_ws_n >= 2)
365 out("\taddress_lo=0x%08x", pkt_body_ws[1]);
366 if (pkt_body_ws_n >= 3)
367 out("\taddress_hi=0x%08x", pkt_body_ws[2]);
368 }
369
370 #define PKT3_HDR_IS_PREDICATE ((pkt_hdr_w & 0x1) != 0)
371 #define PKT3_HDR_SHADER_TYPE ((u8)((pkt_hdr_w & 0x2) >> 1))
372 #define PKT3_HDR_OPCODE ((u8)((pkt_hdr_w & 0x0000ff00) >> 8))
373 static void pkt3_out(void)
374 {
375 out("\nPKT3(%u words):opcode=%s(0x%x) is_predicate=%s shader_type_is=%s\n", pkt_body_ws_n, opcode_to_str(PKT3_HDR_OPCODE), PKT3_HDR_OPCODE, PKT3_HDR_IS_PREDICATE ? "yes" : "no", shader_type_to_str(PKT3_HDR_SHADER_TYPE));
376
377 /* TODO */
378 switch (PKT3_HDR_OPCODE) {
379 case PKT3_OPCODE_NOP:
380 /* discard the body ws */
381 break;
382 case PKT3_OPCODE_SET_SH_REG:
383 opcode_set_sh_reg_out();
384 break;
385 case PKT3_OPCODE_WRITE_DATA:
386 opcode_write_data_out();
387 break;
388 case PKT3_OPCODE_COPY_DATA:
389 opcode_copy_data_out();
390 break;
391 case PKT3_OPCODE_DRAW_INDEX_AUTO:
392 out("\tindexes_n(written to VGT_NUM_INDICE)=%u\n", pkt_body_ws[0]);
393 out("\tvgt_draw_initiator=0x%08x\n", pkt_body_ws[1]);
394 break;
395 case PKT3_OPCODE_DRAW_INDEX_2:
396 /* this is the hard limit for the dma engine */
397 out("\tindexes_n_max=%u\n", pkt_body_ws[0]);
398 out("\tindexes_buf_addr_lo=0x%08x\n", pkt_body_ws[1]);
399 out("\tindexes_buf_addr_hi=0x%08x\n", pkt_body_ws[2]);
400 out("\tindexes_n=%u\n", pkt_body_ws[3]);
401 out("\tvgt_draw_initiator=0x%08x\n", pkt_body_ws[4]);
402 break;
403 /*===================================================================*/
404 /*
405 * the command processor will read structs in a vram buffer which
406 * describes what to do. The vram buffer is setup with the PKT3
407 * SET_BASE, and for the index version, the index buffer should be
408 * setup (considering DMA memory access granularity) with PKT3
409 * INDEX_BASE and INDEX_BUFFER_SIZE (see AMD programing manuals).
410 */
411 case PKT3_OPCODE_DRAW_INDIRECT:
412 out("\tdata_offset=0x%08x\n", pkt_body_ws[0]);
413 out("\tbase_vertex_location=0x%08x(user sgpr selected via a register shader block word offset\n", pkt_body_ws[1]);
414 out("\tstart_instance_location=0x%08x\n(user sgpr selected via a register shader block word offset)", pkt_body_ws[2]);
415 out("\tvgt_draw_initiator=0x%08x\n", pkt_body_ws[3]);
416 break;
417 case PKT3_OPCODE_DRAW_INDEX_INDIRECT:
418 out("\tdata_offset=0x%08x\n", pkt_body_ws[0]);
419 out("\tbase_vertex_location=0x%08x(user sgpr selected via a register shader block word offset)\n", pkt_body_ws[1]);
420 out("\tstart_instance_location=0x%08x\n(user sgpr selected via a register shader block word offset)", pkt_body_ws[2]);
421 out("\tvgt_draw_initiator=0x%08x\n", pkt_body_ws[3]);
422 break;
423 /*===================================================================*/
424 /*
425 * non documented. based on driver code (radv_cmd_buffer.c). it seems
426 * to be the same than above, but with an array of lines of such
427 * buffers, hence with a stride to go from one line to the next one,
428 * and with a count specific for each line, namely with a array of
429 * counts in vram.
430 */
431 case PKT3_OPCODE_DRAW_INDIRECT_MULTI:
432 case PKT3_OPCODE_DRAW_INDEX_INDIRECT_MULTI:
433 out("\tdata_offset=0x%08x\n", pkt_body_ws[0]);
434 out("\tbase_vertex_location=0x%08x(user sgpr selected via a register shader block word offset)\n", pkt_body_ws[1]);
435 out("\tstart_instance_location=0x%08x\n(user sgpr selected via a register shader block word offset)", pkt_body_ws[2]);
436 out("\tnon_documented=0x%08x\n(user sgpr selected via a register shader block word offset with bits 31/30 enabling the index mode/indirect count)", pkt_body_ws[3]);
437 out("\tdraw_count=%u\n", pkt_body_ws[4]);
438 out("\tcount_va=0x%08x\n", pkt_body_ws[5]);
439 out("\tcount_va_hi=0x%08x\n", pkt_body_ws[6]);
440 out("\tstride=0x%08x\n", pkt_body_ws[7]);
441 out("\tvgt_draw_initiator=0x%08x\n", pkt_body_ws[8]);
442 break;
443 /*===================================================================*/
444 case PKT3_OPCODE_SET_BASE:
445 out("\tbase_index=0x%08x\n", pkt_body_ws[0]);
446 out("\taddress_0=0x%08x\n", pkt_body_ws[1]);
447 out("\taddress_1=0x%08x\n", pkt_body_ws[2]);
448 break;
449 case PKT3_OPCODE_INDEX_BASE:
450 out("\tindex_base_lo=0x%08x\n", pkt_body_ws[0]);
451 out("\tindex_base_hi=0x%08x\n", pkt_body_ws[1]);
452 break;
453 case PKT3_OPCODE_INDEX_BUFFER_SIZE:
454 out("\tindex_buffer_size=0x%08x\n", pkt_body_ws[0]);
455 break;
456 case PKT3_OPCODE_SET_CONTEXT:
457 opcode_set_context_reg_out();
458 break;
459 case PKT3_OPCODE_SET_CONFIG:
460 opcode_set_config_reg_out();
461 break;
462 case PKT3_OPCODE_NUM_INSTANCES:
463 out("\tnum_instances=%u\n", pkt_body_ws[0]);
464 break;
465 case PKT3_OPCODE_EVENT_WRITE:
466 opcode_event_write_out();
467 break;
468 case PKT3_OPCODE_PFP_SYNC_ME:
469 out("\tdummy_data=0x%08x\n", pkt_body_ws[0]);
470 break;
471 case PKT3_OPCODE_SURFACE_SYNC:
472 out("\tword[0]=0x%08x\n", pkt_body_ws[0]);
473 out("\tcoher_size=0x%08x\n", pkt_body_ws[1]);
474 out("\tcoher_base=0x%08x\n", pkt_body_ws[2]);
475 out("\tpoll_interval=0x%08x\n", pkt_body_ws[3]);
476 break;
477 default:
478 /* unknow opcode, we do not interpret the body ws */
479 break;
480 }
481 }
482
483 static void pkt_out(void)
484 {
485 switch (PKT_HDR_TYPE) {
486 case 0:
487 pkt0_out();
488 break;
489 case 1:
490 pkt1_out();
491 break;
492 case 2:
493 pkt2_out();
494 break;
495 case 3:
496 pkt3_out();
497 break;
498 }
499 }
500
501 int main(void)
502 {
503 clearerr(stdin);
504 loop {
505 u8 r;
506
507 r = pkt_hdr_w_read();
508 if (r != OK)
509 exit(0);
510
511 pkt_body_ws_n = PKT_HDR_BODY_WS_LAST + 1;
512
513 r = pkt_body_ws_read();
514
515 pkt_out();
516
517 if (r != OK) {
518 out("ERROR:packet is incomplete\n");
519 exit(1);
520 }
521 }
522 exit(0);
523 }
File amd/gcn/pm4/regs.h added (mode: 100644) (index 0000000..8ade1ab)
1 #ifndef REGS_H
2 #define REGS_H
3 /*****************************************************************************/
4 /* GFX6 */
5 /*
6 * ABBREVIATIONS:
7 *
8 * AA : AntiAliasing? (MSAA?)
9 * ADDR : ADDRess
10 * ADJ : ADJustment ?
11 * BARYC : BARYCentric
12 * BR : Bottom Right
13 * CB : Color Block
14 * CL : CLipper
15 * CNTL: CoNTroL
16 * COL : COLor
17 * CONFIG : CONFIGuration
18 * DB : Depth Block
19 * DISC : DISCipline ?
20 * EN/ENA : ENAble
21 * GB : Guard Band
22 * GS : Geometry Shader ?
23 * HI : HIgh ("high 32 bits of a 64 bits word)
24 * HORZ : HORiZontal
25 * IB : Indirect Buffer
26 * IN : INput
27 * INFO : INFOrmation
28 * INTERP : INTERPolator
29 * LO : LOw ("low 32 bits" of a 64 bits word)
30 * LOCS : LOCationS
31 * OFF : OFFset
32 * PA : Primitive Assembler
33 * PGM : ProGraM
34 * POS : POSition
35 * PRIM : PRIMitive
36 * PS : Pixel Shader
37 * RECT : RECTangle
38 * RSRC : ReSouRCe
39 * SC : Scan Converter
40 * SPI : Shader Processor Interpolator
41 * SU : Setup Unit
42 * TE : Transform Engine
43 * TL : Top Left
44 * TMP : TeMPorary
45 * VERT : VERTical
46 * VGT : Vertex Grouper Tesselator
47 * VPORT : ViewPORT
48 * VS : Vertex Shader
49 * VTE : Vertex TEsselator?
50 * VTX : VerTeX ?
51 */
52 /*****************************************************************************/
53 constant {
54 reg_blk_lo = 0,
55 reg_blk_cfg = 1, /* only 1 unlike ctxs */
56 reg_blk_sh = 2,
57 reg_blk_ctx = 3 /* there are N (depends on GFX) ctxs */
58 };
59
60 /*
61 * gfx[6-10]
62 * 64KiB reg space:
63 * low 32KiB, use PKT0:
64 * 0x00000000-0x00007ffff byte ofts
65 * 0x00000000-0x00001ffff w ofts
66 * hi 32KiB, use PKT3 with the right SET_* opcode
67 * 0x00008000-0x0000fffff byte ofts
68 * 0x00002000-0x00003ffff w ofts
69 */
70 u64 reg_blk_w_ofts[] = {
71 [reg_blk_lo] = 0,
72 /*-------------------------------------------------------------------*/
73 [reg_blk_cfg] = 0x0000000000002000,
74 [reg_blk_sh] = 0x0000000000002c00,
75 [reg_blk_ctx] = 0x000000000000a000,
76 };
77
78 struct reg_desc {
79 u8 blk;
80 u64 w_oft;
81 u8 *name;
82 };
83
84 /* may add a gfx blk version mask, gfx6 for now */
85 struct reg_desc reg_descs[] = {
86 {
87 reg_blk_cfg,
88 0x256,
89 "VGT_PRIMITIVE_TYPE"
90 },
91 /*-------------------------------------------------------------------*/
92 {
93 reg_blk_sh,
94 0x8,
95 "SPI_SHADER_PGM_LO_PS"
96 },
97 {
98 reg_blk_sh,
99 0x9,
100 "SPI_SHADER_PGM_HI_PS"
101 },
102 {
103 reg_blk_sh,
104 0xa,
105 "SPI_SHADER_PGM_RSRC1_PS"
106 },
107 {
108 reg_blk_sh,
109 0xb,
110 "SPI_SHADER_PGM_RSRC2_PS"
111 },
112 {
113 reg_blk_sh,
114 0xe,
115 "SPI_SHADER_USER_DATA_PS_2"
116 },
117 {
118 reg_blk_sh,
119 0xf,
120 "SPI_SHADER_USER_DATA_PS_3"
121 },
122 {
123 reg_blk_sh,
124 0x48,
125 "SPI_SHADER_PGM_LO_VS"
126 },
127 {
128 reg_blk_sh,
129 0x49,
130 "SPI_SHADER_PGM_HI_VS"
131 },
132 {
133 reg_blk_sh,
134 0x4a,
135 "SPI_SHADER_PGM_RSRC1_VS"
136 },
137 {
138 reg_blk_sh,
139 0x4b,
140 "SPI_SHADER_PGM_RSRC2_VS"
141 },
142 {
143 reg_blk_sh,
144 0x4e,
145 "SPI_SHADER_USER_DATA_VS_2"
146 },
147 {
148 reg_blk_sh,
149 0x4f,
150 "SPI_SHADER_USER_DATA_VS_3"
151 },
152 {
153 reg_blk_sh,
154 0x50,
155 "SPI_SHADER_USER_DATA_VS_4"
156 },
157 {
158 reg_blk_sh,
159 0x51,
160 "SPI_SHADER_USER_DATA_VS_5"
161 },
162 {
163 reg_blk_sh,
164 0x52,
165 "SPI_SHADER_USER_DATA_VS_6"
166 },
167 {
168 reg_blk_sh,
169 0x53,
170 "SPI_SHADER_USER_DATA_VS_7"
171 },
172 /*-------------------------------------------------------------------*/
173 {
174 reg_blk_ctx,
175 0x0,
176 "DB_RENDER_CONTROL"
177 },
178 {
179 reg_blk_ctx,
180 0x3,
181 "DB_RENDER_OVERRIDE"
182 },
183 {
184 reg_blk_ctx,
185 0x4,
186 "DB_RENDER_OVERRIDE2"
187 },
188 {
189 reg_blk_ctx,
190 0x10,
191 "DB_Z_INFO"
192 },
193 {
194 reg_blk_ctx,
195 0x11,
196 "DB_STENCIL_INFO"
197 },
198 {
199 reg_blk_ctx,
200 0x82,
201 "PA_SC_WINDOW_SCISSOR_BR"
202 },
203 {
204 reg_blk_ctx,
205 0x8e,
206 "CB_TARGET_MASK"
207 },
208 {
209 reg_blk_ctx,
210 0x83,
211 "PA_SC_CLIPRECT_RULE"
212 },
213 {
214 reg_blk_ctx,
215 0x8f,
216 "CB_SHADER_MASK"
217 },
218 {
219 reg_blk_ctx,
220 0x94,
221 "PA_SC_VPORT_SCISSOR_0_TL"
222 },
223 {
224 reg_blk_ctx,
225 0x95,
226 "PA_SC_VPORT_SCISSOR_0_BR"
227 },
228 {
229 reg_blk_ctx,
230 0xb4,
231 "PA_SC_VPORT_ZMIN_0"
232 },
233 {
234 reg_blk_ctx,
235 0xb5,
236 "PA_SC_VPORT_ZMAX_0"
237 },
238 {
239 reg_blk_ctx,
240 0x10b,
241 "DB_STENCIL_CONTROL"
242 },
243 {
244 reg_blk_ctx,
245 0x10f,
246 "PA_CL_VPORT_XSCALE"
247 },
248 {
249 reg_blk_ctx,
250 0x110,
251 "PA_CL_VPORT_XOFFSET"
252 },
253 {
254 reg_blk_ctx,
255 0x111,
256 "PA_CL_VPORT_YSCALE"
257 },
258 {
259 reg_blk_ctx,
260 0x112,
261 "PA_CL_VPORT_YOFFSET"
262 },
263 {
264 reg_blk_ctx,
265 0x113,
266 "PA_CL_VPORT_ZSCALE"
267 },
268 {
269 reg_blk_ctx,
270 0x114,
271 "PA_CL_VPORT_ZOFFSET"
272 },
273 {
274 reg_blk_ctx,
275 0x191,
276 "SPI_PS_INPUT_CNTL_0"
277 },
278 {
279 reg_blk_ctx,
280 0x1b1,
281 "SPI_VS_OUT_CONFIG"
282 },
283 {
284 reg_blk_ctx,
285 0x1b3,
286 "SPI_PS_INPUT_ENA"
287 },
288 {
289 reg_blk_ctx,
290 0x1b4,
291 "SPI_PS_INPUT_ADDR"
292 },
293 {
294 reg_blk_ctx,
295 0x1b5,
296 "SPI_INTERP_CONTROL_0"
297 },
298 {
299 reg_blk_ctx,
300 0x1b6,
301 "SPI_PS_IN_CONTROL"
302 },
303 {
304 reg_blk_ctx,
305 0x1b8,
306 "SPI_BARYC_CNTL"
307 },
308 {
309 reg_blk_ctx,
310 0x1ba,
311 "SPI_TMPRING_SIZE"
312 },
313 {
314 reg_blk_ctx,
315 0x1c3,
316 "SPI_SHADER_POS_FORMAT"
317 },
318 {
319 reg_blk_ctx,
320 0x1c4,
321 "SPI_SHADER_Z_FORMAT"
322 },
323 {
324 reg_blk_ctx,
325 0x1c5,
326 "SPI_SHADER_COL_FORMAT"
327 },
328 {
329 reg_blk_ctx,
330 0x1e0,
331 "CB_BLEND0_CONTROL"
332 },
333 {
334 reg_blk_ctx,
335 0x1e1,
336 "CB_BLEND1_CONTROL"
337 },
338 {
339 reg_blk_ctx,
340 0x1e2,
341 "CB_BLEND2_CONTROL"
342 },
343 {
344 reg_blk_ctx,
345 0x1e3,
346 "CB_BLEND3_CONTROL"
347 },
348 {
349 reg_blk_ctx,
350 0x1e4,
351 "CB_BLEND4_CONTROL"
352 },
353 {
354 reg_blk_ctx,
355 0x1e5,
356 "CB_BLEND5_CONTROL"
357 },
358 {
359 reg_blk_ctx,
360 0x1e6,
361 "CB_BLEND6_CONTROL"
362 },
363 {
364 reg_blk_ctx,
365 0x1e7,
366 "CB_BLEND7_CONTROL"
367 },
368 {
369 reg_blk_ctx,
370 0x200,
371 "DB_DEPTH_CONTROL"
372 },
373 {
374 reg_blk_ctx,
375 0x201,
376 "DB_EQAA"
377 },
378 {
379 reg_blk_ctx,
380 0x202,
381 "CB_COLOR_CONTROL"
382 },
383 {
384 reg_blk_ctx,
385 0x203,
386 "DB_SHADER_CONTROL"
387 },
388 {
389 reg_blk_ctx,
390 0x204,
391 "PA_CL_CLIP_CNTL"
392 },
393 {
394 reg_blk_ctx,
395 0x205,
396 "PA_SU_SC_MODE_CNTL"
397 },
398 {
399 reg_blk_ctx,
400 0x206,
401 "PA_CL_VTE_CNTL"
402 },
403 {
404 reg_blk_ctx,
405 0x207,
406 "PA_CL_VS_OUT_CNTL"
407 },
408 {
409 reg_blk_ctx,
410 0x20b,
411 "PA_SU_PRIM_FILTER_CNTL"
412 },
413 {
414 reg_blk_ctx,
415 0x290,
416 "VGT_GS_MODE"
417 },
418 {
419 reg_blk_ctx,
420 0x292,
421 "PA_SC_MODE_CNTL_0"
422 },
423 {
424 reg_blk_ctx,
425 0x293,
426 "PA_SC_MODE_CNTL_1"
427 },
428 {
429 reg_blk_ctx,
430 0x29b,
431 "VGT_GS_OUT_PRIM_TYPE"
432 },
433 {
434 reg_blk_ctx,
435 0x2a1,
436 "VGT_PRIMITIVEID_EN"
437 },
438 {
439 reg_blk_ctx,
440 0x2a5,
441 "VGT_MULTI_PRIM_IB_RESET_EN"
442 },
443 {
444 reg_blk_ctx,
445 0x2aa,
446 "IA_MULTI_VGT_PARAM"
447 },
448 {
449 reg_blk_ctx,
450 0x2ad,
451 "VGT_REUSE_OFF"
452 },
453 {
454 reg_blk_ctx,
455 0x2d5,
456 "VGT_SHADER_STAGES_EN"
457 },
458 {
459 reg_blk_ctx,
460 0x2dc,
461 "DB_ALPHA_TO_MASK"
462 },
463 {
464 reg_blk_ctx,
465 0x2f5,
466 "PA_SC_CENTROID_PRIORITY_0"
467 },
468 {
469 reg_blk_ctx,
470 0x2f6,
471 "PA_SC_CENTROID_PRIORITY_1"
472 },
473 {
474 reg_blk_ctx,
475 0x2f7,
476 "PA_SC_LINE_CNTL"
477 },
478 {
479 reg_blk_ctx,
480 0x2f8,
481 "PA_SC_AA_CONFIG"
482 },
483 {
484 reg_blk_ctx,
485 0x2f9,
486 "PA_SU_VTX_CNTL"
487 },
488 {
489 reg_blk_ctx,
490 0x2fa,
491 "PA_CL_GB_VERT_CLIP_ADJ"
492 },
493 {
494 reg_blk_ctx,
495 0x2fb,
496 "PA_CL_GB_VERT_DISC_ADJ"
497 },
498 {
499 reg_blk_ctx,
500 0x2fc,
501 "PA_CL_GB_HORZ_CLIP_ADJ"
502 },
503 {
504 reg_blk_ctx,
505 0x2fd,
506 "PA_CL_GB_HORZ_DISC_ADJ"
507 },
508 {
509 reg_blk_ctx,
510 0x2fe,
511 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
512 },
513 {
514 reg_blk_ctx,
515 0x302,
516 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0"
517 },
518 {
519 reg_blk_ctx,
520 0x306,
521 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0"
522 },
523 {
524 reg_blk_ctx,
525 0x30a,
526 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0"
527 },
528 {
529 reg_blk_ctx,
530 0x30e,
531 "PA_SC_AA_MASK_X0Y0_X1Y0"
532 },
533 {
534 reg_blk_ctx,
535 0x30f,
536 "PA_SC_AA_MASK_X0Y1_X1Y1"
537 },
538 {
539 reg_blk_ctx,
540 0x313,
541 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
542 },
543 {
544 reg_blk_ctx,
545 0x318,
546 "CB_COLOR0_BASE"
547 },
548 {
549 reg_blk_ctx,
550 0x319,
551 "CB_COLOR0_PITCH"
552 },
553 {
554 reg_blk_ctx,
555 0x31a,
556 "CB_COLOR0_SLICE"
557 },
558 {
559 reg_blk_ctx,
560 0x31b,
561 "CB_COLOR0_VIEW"
562 },
563 {
564 reg_blk_ctx,
565 0x31c,
566 "CB_COLOR0_INFO"
567 },
568 {
569 reg_blk_ctx,
570 0x31d,
571 "CB_COLOR0_ATTRIB"
572 },
573 {
574 reg_blk_ctx,
575 0x31e,
576 "CB_COLOR0_DCC_CONTROL"
577 },
578 {
579 reg_blk_ctx,
580 0x31f,
581 "CB_COLOR0_CMASK"
582 },
583 {
584 reg_blk_ctx,
585 0x320,
586 "CB_COLOR0_CMASK_SLICE"
587 },
588 {
589 reg_blk_ctx,
590 0x321,
591 "CB_COLOR0_FMASK"
592 },
593 {
594 reg_blk_ctx,
595 0x322,
596 "CB_COLOR0_FMASK_SLICE"
597 },
598 {
599 reg_blk_ctx,
600 0x32b,
601 "CB_COLOR1_INFO"
602 },
603 {
604 reg_blk_ctx,
605 0x33a,
606 "CB_COLOR2_INFO"
607 },
608 {
609 reg_blk_ctx,
610 0x349,
611 "CB_COLOR3_INFO"
612 },
613 {
614 reg_blk_ctx,
615 0x358,
616 "CB_COLOR4_INFO"
617 },
618 {
619 reg_blk_ctx,
620 0x367,
621 "CB_COLOR5_INFO"
622 },
623 {
624 reg_blk_ctx,
625 0x376,
626 "CB_COLOR6_INFO"
627 },
628 {
629 reg_blk_ctx,
630 0x385,
631 "CB_COLOR7_INFO"
632 },
633 };
634 #endif
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