File README added (mode: 100644) (index 0000000..09cf80c)
	1		This is a fork from the drm-core-next branch of the DRM.
	2
	3		Current goals (not set in ice):
	4		- AMD GPUs from si, but will try to stick to state of the art GPU
	5		generation. Once all the required features are in, start to keep code for
	6		all GPU generations.
	7		- 1 driver per GPU generation. But if in the same generation, one family is too
	8		different from the others, it may probably get its own module.
	9		- linux native integration-->no kernel abstraction plumbering.
	10		- Proper GNU GPL licencing: be sure optimal code stays open.
	11		- GPU kernel native interfaces to get the best of each GPU generation (GPU is
	12		all about speed).
	13		- kernel stubs to provide user space access to kernel native interfaces. Some
	14		of those interfaces *may* be generic across GPUs.
	15		- "compatibility" (opengl...) would be done in user space.
	16		- only display port support (hdmi seems royalty based).
	17
	18		Those are really different from official DRM goals.
	19
	20		The target license is GNU Affero GPL v3 with a similar exception than
	21		the current Linux GNU GPLv2.
	22
	23		************
	24		See agpl.txt
	25		************
	26
	27		To make things clear:user space programs which do contain significant hardware
	28		programming knowledge, are *not* "normal" user space programs, then are
	29		covered by the GNU GPL. An exception will be added to allow permissive
	30		linking to user space "compat" stubs, which will be covered probably by the
	31		GNU Affero GPLv3 with a library exception (for linking).
	32
	33		--------------------------------------------------------------------------------
	34
	35		How to use it?
	36
	37		Tested with linux 3.4.2
	38		- symlink drivers/video/Kconfig to drivers/video/Kconfig-3.4.2
	39		(actually it's just including alga Kconfig).
	40		- symlink drivers/gpu/alga.
	41		- symlink drivers/gpu/Makefile to drivers/gpu/video/Makefile-3.4.2
	42		(actually it's just adding the alga tree).
	43		- symlink include/alga in your main tree.
	44
	45		configure, then compile your linux kernel.
	46
	47		Sylvain

File agpl.txt added (mode: 100644) (index 0000000..dba13ed)
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	480		In the following three paragraphs, a "patent license" is any express
	481		agreement or commitment, however denominated, not to enforce a patent
	482		(such as an express permission to practice a patent or covenant not to
	483		sue for patent infringement). To "grant" such a patent license to a
	484		party means to make such an agreement or commitment not to enforce a
	485		patent against the party.
	486
	487		If you convey a covered work, knowingly relying on a patent license,
	488		and the Corresponding Source of the work is not available for anyone
	489		to copy, free of charge and under the terms of this License, through a
	490		publicly available network server or other readily accessible means,
	491		then you must either (1) cause the Corresponding Source to be so
	492		available, or (2) arrange to deprive yourself of the benefit of the
	493		patent license for this particular work, or (3) arrange, in a manner
	494		consistent with the requirements of this License, to extend the patent
	495		license to downstream recipients. "Knowingly relying" means you have
	496		actual knowledge that, but for the patent license, your conveying the
	497		covered work in a country, or your recipient's use of the covered work
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	504		receiving the covered work authorizing them to use, propagate, modify
	505		or convey a specific copy of the covered work, then the patent license
	506		you grant is automatically extended to all recipients of the covered
	507		work and works based on it.
	508
	509		A patent license is "discriminatory" if it does not include within
	510		the scope of its coverage, prohibits the exercise of, or is
	511		conditioned on the non-exercise of one or more of the rights that are
	512		specifically granted under this License. You may not convey a covered
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	514		in the business of distributing software, under which you make payment
	515		to the third party based on the extent of your activity of conveying
	516		the work, and under which the third party grants, to any of the
	517		parties who would receive the covered work from you, a discriminatory
	518		patent license (a) in connection with copies of the covered work
	519		conveyed by you (or copies made from those copies), or (b) primarily
	520		for and in connection with specific products or compilations that
	521		contain the covered work, unless you entered into that arrangement,
	522		or that patent license was granted, prior to 28 March 2007.
	523
	524		Nothing in this License shall be construed as excluding or limiting
	525		any implied license or other defenses to infringement that may
	526		otherwise be available to you under applicable patent law.
	527
	528		12. No Surrender of Others' Freedom.
	529
	530		If conditions are imposed on you (whether by court order, agreement or
	531		otherwise) that contradict the conditions of this License, they do not
	532		excuse you from the conditions of this License. If you cannot convey a
	533		covered work so as to satisfy simultaneously your obligations under this
	534		License and any other pertinent obligations, then as a consequence you may
	535		not convey it at all. For example, if you agree to terms that obligate you
	536		to collect a royalty for further conveying from those to whom you convey
	537		the Program, the only way you could satisfy both those terms and this
	538		License would be to refrain entirely from conveying the Program.
	539
	540		13. Remote Network Interaction; Use with the GNU General Public License.
	541
	542		Notwithstanding any other provision of this License, if you modify the
	543		Program, your modified version must prominently offer all users
	544		interacting with it remotely through a computer network (if your version
	545		supports such interaction) an opportunity to receive the Corresponding
	546		Source of your version by providing access to the Corresponding Source
	547		from a network server at no charge, through some standard or customary
	548		means of facilitating copying of software. This Corresponding Source
	549		shall include the Corresponding Source for any work covered by version 3
	550		of the GNU General Public License that is incorporated pursuant to the
	551		following paragraph.
	552
	553		Notwithstanding any other provision of this License, you have
	554		permission to link or combine any covered work with a work licensed
	555		under version 3 of the GNU General Public License into a single
	556		combined work, and to convey the resulting work. The terms of this
	557		License will continue to apply to the part which is the covered work,
	558		but the work with which it is combined will remain governed by version
	559		3 of the GNU General Public License.
	560
	561		14. Revised Versions of this License.
	562
	563		The Free Software Foundation may publish revised and/or new versions of
	564		the GNU Affero General Public License from time to time. Such new versions
	565		will be similar in spirit to the present version, but may differ in detail to
	566		address new problems or concerns.
	567
	568		Each version is given a distinguishing version number. If the
	569		Program specifies that a certain numbered version of the GNU Affero General
	570		Public License "or any later version" applies to it, you have the
	571		option of following the terms and conditions either of that numbered
	572		version or of any later version published by the Free Software
	573		Foundation. If the Program does not specify a version number of the
	574		GNU Affero General Public License, you may choose any version ever published
	575		by the Free Software Foundation.
	576
	577		If the Program specifies that a proxy can decide which future
	578		versions of the GNU Affero General Public License can be used, that proxy's
	579		public statement of acceptance of a version permanently authorizes you
	580		to choose that version for the Program.
	581
	582		Later license versions may give you additional or different
	583		permissions. However, no additional obligations are imposed on any
	584		author or copyright holder as a result of your choosing to follow a
	585		later version.
	586
	587		15. Disclaimer of Warranty.
	588
	589		THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
	590		APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
	591		HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
	592		OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
	593		THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	594		PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
	595		IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
	596		ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
	597
	598		16. Limitation of Liability.
	599
	600		IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
	601		WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
	602		THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
	603		GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
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	606		PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
	607		EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
	608		SUCH DAMAGES.
	609
	610		17. Interpretation of Sections 15 and 16.
	611
	612		If the disclaimer of warranty and limitation of liability provided
	613		above cannot be given local legal effect according to their terms,
	614		reviewing courts shall apply local law that most closely approximates
	615		an absolute waiver of all civil liability in connection with the
	616		Program, unless a warranty or assumption of liability accompanies a
	617		copy of the Program in return for a fee.
	618
	619		END OF TERMS AND CONDITIONS
	620
	621		How to Apply These Terms to Your New Programs
	622
	623		If you develop a new program, and you want it to be of the greatest
	624		possible use to the public, the best way to achieve this is to make it
	625		free software which everyone can redistribute and change under these terms.
	626
	627		To do so, attach the following notices to the program. It is safest
	628		to attach them to the start of each source file to most effectively
	629		state the exclusion of warranty; and each file should have at least
	630		the "copyright" line and a pointer to where the full notice is found.
	631
	632		<one line to give the program's name and a brief idea of what it does.>
	633		Copyright (C) <year> <name of author>
	634
	635		This program is free software: you can redistribute it and/or modify
	636		it under the terms of the GNU Affero General Public License as published by
	637		the Free Software Foundation, either version 3 of the License, or
	638		(at your option) any later version.
	639
	640		This program is distributed in the hope that it will be useful,
	641		but WITHOUT ANY WARRANTY; without even the implied warranty of
	642		MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	643		GNU Affero General Public License for more details.
	644
	645		You should have received a copy of the GNU Affero General Public License
	646		along with this program. If not, see <http://www.gnu.org/licenses/>.
	647
	648		Also add information on how to contact you by electronic and paper mail.
	649
	650		If your software can interact with users remotely through a computer
	651		network, you should also make sure that it provides a way for users to
	652		get its source. For example, if your program is a web application, its
	653		interface could display a "Source" link that leads users to an archive
	654		of the code. There are many ways you could offer source, and different
	655		solutions will be better for different programs; see section 13 for the
	656		specific requirements.
	657
	658		You should also get your employer (if you work as a programmer) or school,
	659		if any, to sign a "copyright disclaimer" for the program, if necessary.
	660		For more information on this, and how to apply and follow the GNU AGPL, see
	661		<http://www.gnu.org/licenses/>.

File drivers/gpu/Makefile-3.2.7 added (mode: 100644) (index 0000000..d0383f1)
	1		obj-y += alga/ drm/ vga/ stub/

File drivers/gpu/Makefile-3.4.1 added (mode: 100644) (index 0000000..d0383f1)
	1		obj-y += alga/ drm/ vga/ stub/

File drivers/gpu/Makefile-3.4.2 added (mode: 100644) (index 0000000..d0383f1)
	1		obj-y += alga/ drm/ vga/ stub/

File drivers/gpu/alga/Kconfig added (mode: 100644) (index 0000000..d89331b)
	1		menuconfig ALGA
	2		tristate "Advanced Linux Graphic Architecture"
	3		select SLOW_WORK
	4		help
	5		DRM refactoring with quite different goals for AMD GPUs
	6
	7		config ALGA_AMD
	8		tristate "AMD"
	9		depends on ALGA
	10		help
	11		Choose this option if you have an AMD graphics card.
	12
	13		source "drivers/gpu/alga/amd/Kconfig"

File drivers/gpu/alga/Makefile added (mode: 100644) (index 0000000..e9b0365)
	1		obj-$(CONFIG_ALGA)+=helpers/
	2		obj-$(CONFIG_ALGA_AMD)+=amd/

File drivers/gpu/alga/amd/ABBREVIATIONS added (mode: 100644) (index 0000000..f160ff8)
	1		accel acceleration
	2		ack ackknowledge
	3		addr address
	4		adev atombios device
	5		aper aperture
	6		arb arbitrer (silicium block)
	7		atb atombios
	8		attr attribute
	9		attrib(s) attribute(s)
	10		aux auxiliary
	11		ba Buse Aperture
	12		bN byte index N
	13		bif bus interface
	14		bios Basic Input/Output System
	15		bl Back Ligth
	16		blk block
	17		bot bottom
	18		bpc Bits Per color Component or Bits Per Color
	19		bpp Bits Per Pixel
	20		buf(s) buffer(s)
	21		cap(s) capability(ties)
	22		cb Color Block (silicium Block)
	23		cc Chip Configuration (regs name)
	24		cf Cp Fetch
	25		cf Cache Fifo
	26		cfg config
	27		cg Clock Generator
	28		cgts gpu block related to time stamps (they help to find out enabled render backends)
	29		chan(s) channel(s)
	30		chmap channel map
	31		cl Cas Latency (memory context)
	32		clk(s) clock(s)
	33		clr clear
	34		cmd command
	35		cmp compare
	36		cnt(s) count(s)
	37		comp compression
	38		cond condition
	39		(sub)conn (sub)connector
	40		cp Command Processor
	41		cp Clipper Plane
	42		cl CLipper (silicium block)
	43		cr clock recovery
	44		crtc Cathode Ray Tube Controller
	45		cs Compute Shader
	46		ctl control
	47		ctler controller
	48		ctx(s) context(s)
	49		cu compute unit
	50		cv Component Video
	51		db Depth Block (silicium block)
	52		db double buffer
	53		db_fb double buffer frame buffer
	54		dce display controller engine
	55		dcpll display controller pll
	56		dd driver data
	57		ddev dce device
	58		dec decimal
	59		dev device
	60		dim dimension
	61		disp display
	62		ddc Display Data Channel
	63		dig digital
	64		dis disable
	65		ddl Delay Lock Loop (usually memory context)
	66		ddr Double Data Rate (ram context)
	67		dfp Digital Flat Panel
	68		dmif Display Memory InterFace
	69		dp DisplayPort
	70		dpcd DisplayPort Configuration Data
	71		drr Dynamic Refrest Rate
	72		ds Domain Shader (tesselation)
	73		dst destination
	74		dvo Digital Video Output
	75		dw(s) dword(s) (32 bits)
	76		dyn dynamic
	77		enc encoder
	78		edp Embedded DisplayPort
	79		ee Event Engine
	80		emph emphasis
	81		emsr extented mode register
	82		ena enable
	83		eng engine
	84		evt event
	85		ext extern(al)
	86		fb Feed Back (pll context)
	87		fb Frame Buffer
	88		flg(s) flag(s)
	89		fmt format
	90		frag fragment
	91		freq frequency
	92		fsb Front Side Bus
	93		func function
	94		g global
	95		gart Graphics Address Remapping Table (=gtt)
	96		gb Graphic Backend
	97		gb Guard Band
	98		gc Graphic Controller
	99		gc Graphic Configuration
	100		gds Global Data Share
	101		gpio General Purpose Input/Output
	102		gpr(s) General Purpose Register(s)
	103		gnd GrouNd (voltage context)
	104		grbm Graphics Register Backbone Manager
	105		grph graphic
	106		gtt Graphics Translation Table
	107		guid Globally Uniq IDentifier
	108		h horizontal, height
	109		hbr High Bit-Rate
	110		hdp Host Data Path (silicium block for the PCI BAR 0)
	111		hdr header
	112		hpd HotPlug Detect
	113		hs Hull Shader (tesselation)
	114		ht Hyper Transport (memory context)
	115		htc Hardware Thermal Control
	116		hw hardware
	117		ib Indirect Buffer (used to aperture map some indirect buffer)
	118		ictx interpreter context
	119		id(s) identifier(s)
	120		id InDirect (atombios, argument access)
	121		idx index
	122		igp Integrated Graphic Processor
	123		ih Interrupt Handler
	124		iio indirect I/O (not supported because going PCI MMIO)
	125		imm immediat
	126		info information
	127		inst(s) instance(s)
	128		int interrupt
	129		intr(s) interrupt(s)
	130		invalidation invld
	131		iv divider (pll context)
	132		l lane
	133		lds Local Data Share
	134		len length
	135		lsb Least Significant Bit
	136		lut LookUp Table
	137		lvl(s) level(s)
	138		lvds Low-Voltage Differential Signaling
	139		max maximum
	140		mc Memory Controller
	141		me Micro Engine
	142		mem memory
	143		min minimum
	144		mgt management
	145		mm MultiMedia
	146		mng MaNaGer
	147		ms Modes
	148		msb Most Significant Bit
	149		msg message
	150		msr mode register (memory context)
	151		num number
	152		o object
	153		obj(s) object(s)
	154		obs obsolete
	155		oem Original Equipment Manufacturer
	156		of offset
	157		p path
	158		pa Primitive Assembler (silicium block)
	159		pa Physical Address (gpu address)
	160		parameter(s) param(s)
	161		pci Peripheral Component Interconnect
	162		pcie PCI Express
	163		PreFetch
	164		pf page flip
	165		pflip page flip
	166		pfp PreFetch Parser (part of cp)
	167		pkt packet
	168		pll Phase Locked Loop
	169		pgm program (as shaders)
	170		prim primitive
	171		pos position
	172		post Power-On Self Test
	173		pplib PowerPlay Library
	174		ppll Pixel Phase Locked Loop
	175		prio priority
	176		prog program
	177		pn Part Number
	178		rog program
	179		ps Parameter Space
	180		ps Pixel Shader
	181		pt Page Table
	182		pte(s) Page Table Entr/y(ies)
	183		ptr pointer
	184		pwr power
	185		qw(s) quadword(s) (64 bits)
	186		r refresh
	187		r ring
	188		ram random access memory
	189		rb(s) Render Backend(s)
	190		rb Ring Buffer
	191		rbm Register Backbone Manager
	192		rbbm Register BackBone Manager
	193		rd read
	194		rec(s) record(s)
	195		ref reference
	196		reg(s) register(s)
	197		req request
	198		res ressource
	199		resp responce
	200		ret return
	201		rev revision
	202		rgb Red Green Blue
	203		rlc unknown but related to the interrupt controller.
	204		rng RaNGe
	205		rop(s) Raster OPerator(s) (render backend(s))
	206		rq ReQuest
	207		rsvd reserved
	208		s spectrum
	209		sc Scan Convertor
	210		scr screen
	211		se(s) Shader Engine(s)
	212		sel Selection
	213		sg scatter gather
	214		sh shader block
	215		simd Single instruction Multiple Data
	216		smx Shader Memory eXchange
	217		sN N is a the scratch pad register number
	218		(off)scr (off)screen
	219		sp Shader Pipe
	220		spi Shader Processor Interpolator (silicium context)
	221		srbm System Register Backbone Manager
	222		src source
	223		ss Spread Spectrum
	224		sdvo Serial Digital Video Output
	225		spd Serial Presence Detect (memory context)
	226		str string
	227		struct structure
	228		su Setup Unit
	229		surface(s) surf(s)
	230		sw software
	231		sync synchronization
	232		sys system
	233		sx Shader eXport (silicium block)
	234		sz(s) size(s)
	235		t temperature, transaction, timing
	236		ta Texture Addresser
	237		tbd To Be Defined
	238		tbl(s) table(s)
	239		tc Texture Cache (silicium block)
	240		tc Test Controller
	241		tdp Thermal Design Power
	242		tex texture
	243		tgt target
	244		thd(s) thread(s)
	245		tlb Translation Lookaside Buffer
	246		tmds Transition Minimized Differential Signaling
	247		tmp temporary
	248		tp training pattern
	249		trans transmitter
	250		transac transaction
	251		ts timings
	252		ucp User Clipping Plane
	253		uma Uniform Memory Access (opposed to NUMA)
	254		umsk umask
	255		uvd Unified Video Decoder
	256		v vertical
	257		vbios Video bios
	258		vblank vertical blank (interrupt context)
	259		vline vertical line (interrupt context)
	260		vc Voltage Control
	261		vc Vertex Cache (silicium block)
	262		vect vector
	263		ver version
	264		vesa Video Electronics Standards Association
	265		vga Video Graphic Array
	266		vgt Vertex Grouper and Tessellator (silicium block)
	267		vgt Vertex Geometry Translator
	268		vpost video post
	269		vram video ram
	270		vs voltage swing
	271		vtx vertex
	272		w width
	273		wd(s) word(s)
	274		wN word index N
	275		win window
	276		wl Write Lantency (memory context)
	277		wr(s) write(s)
	278		ws WorkSpace

File drivers/gpu/alga/amd/Kconfig added (mode: 100644) (index 0000000..66f87f7)
	1		source "drivers/gpu/alga/amd/si/Kconfig"
	2		source "drivers/gpu/alga/amd/dce6/Kconfig"
	3		source "drivers/gpu/alga/amd/atombios/Kconfig"

File drivers/gpu/alga/amd/Makefile added (mode: 100644) (index 0000000..cfaf5de)
	1		obj-$(CONFIG_ALGA_AMD_ATOMBIOS)+=atombios/
	2		obj-$(CONFIG_ALGA_AMD_DCE6)+=dce6/
	3		obj-$(CONFIG_ALGA_AMD_SI)+=si/

File drivers/gpu/alga/amd/atombios/Kconfig added (mode: 100644) (index 0000000..278f0fe)
	1		config ALGA_AMD_ATOMBIOS
	2		tristate "atombios"
	3		depends on ALGA && ALGA_AMD
	4		help
	5		atombios found on AMD GPUs.
	6		If M is selected, the module will be called atombios.

File drivers/gpu/alga/amd/atombios/Makefile added (mode: 100644) (index 0000000..e861800)
	1		atombios-y := dp_paths.o mod.o dce.o interpreter.o iio_interpreter.o
	2		obj-$(CONFIG_ALGA_AMD_ATOMBIOS)+= atombios.o

File drivers/gpu/alga/amd/atombios/README added (mode: 100644) (index 0000000..b514dcf)
	1		0. what is the atombios?
	2
	3		It's the combinaison of memory table specifications with a byte code
	4		interpreter.
	5
	6		1. who?
	7
	8		It is intended for:
	9
	10		o PCB (Printed Ciruit Board) integrators. The atombios memory tables
	11		describe electronically their boards based on AMD GPUs. The atombios byte
	12		code interpreter allows them to provide platform independent basic
	13		functions while electronically stable and tested for their boards.
	14
	15		o OS (operating system) coders. The atombios shields them from the
	16		specifities of each PCB integration. The OS coders will set the board in
	17		an electronic stable state through execution of atombios byte code
	18		interpreter functions that would have been tuned by the PCB integrators.
	19
	20		2. code navigation
	21
	22		Keep an eye all the time on abbreviation file content. Indeed, much of the
	23		AMD GPU terminology is abbreviated throughout the code.
	24
	25		3. level of control on atombios byte code behavior
	26
	27		There is a level of control achievable throught some of the "scratch pad
	28		registers". Those registers are GPU registers.
	29
	30		4. calling atombios "functions"
	31
	32		The way arguments are passed to the interpreter is through the parameter
	33		space. This chunk of memory is filled with args specific to the revision
	34		of the "function".
	35
	36		5. silicium programming
	37
	38		Access methods are the same from evergreen:
	39		o regs are directly accessed.
	40		o regs are indirectly accessed throught indirect registers
	41		defined in the iio table from the master data table.
	42		(see tables/iio.h)
	43
	44		6. byte code description
	45
	46		The fist byte is the opcode. It is signed. Opcode 0 is reserved.
	47
	48		* op_move:
	49		op_and:
	50		op_or:
	51
	52		The first byte is the opcode which number defines the destination type. The
	53		second byte is the attribute:
	54		[7:6] destination alignment/size mapping based on source alignment/size
	55		(see dst_align_map array in interpret.c)
	56		[5:3] source alignment/size - selection of the part of the 32 bits
	57		dword:
	58		0 - dword - 0xFFFFFFFF
	59		1 - word0 - 0xFFFF
	60		2 - word8 - 0xFFFF00
	61		3 - word16 - 0xFFFF0000
	62		4 - byte0 - 0xFF
	63		5 - byte8 - 0xFF00
	64		6 - byte16 - 0xFF0000
	65		7 - byte24 - 0xFF000000
	66		[2:0] source argument type (where/how to fetch/write data) of the op:
	67		o register
	68		o parameter space
	69		o workspace
	70		o ...
	71
	72		For instance, if the attribute selects an alignment/size of a byte for its
	73		source, the destination will be a byte and its alignment is computed with
	74		the dst_align_map mapping table.
	75
	76		Follow two groups of bytes. The first one is the destination index which
	77		type, then size, is defined by the opcode number. The second one is the
	78		source index which type, then size, is encoded in the attribute byte. The
	79		source index may be an immediat value.
	80
	81		* op_shift_left:
	82		op_shift_right:
	83
	84		The first byte is the opcode which number defines the destination type. The
	85		second byte is the attribute:
	86		[7:6] not used
	87		[5:3] defined which part of the target 32 bits dword will be shifted. See
	88		op_move/op_and/op_or attribute.
	89		[2:0] not used
	90		The next group of bytes is the destination index.
	91		The next byte is the shift value.
	92		The next group of bytes is the source index.
	93		The aligmnent/size of the destination is the same than the source.
	94
	95		* op_mul:
	96		op_div:
	97
	98		The first byte is the opcode which number defines the destination type. The
	99		second byte is the attribute. See op_move/op_and/op_or attribute
	100		description.
	101		Follow 2 groups of bytes. The first one is the destination index, which is
	102		actually the first mul operand. The second one is the source index, which is
	103		actually the second mul operand.
	104		The mul/div result is stored in the interpreter context.
	105
	106
	107		* op_add:
	108		op_sub:
	109
	110		The first byte is the opcode which defines the destination type. The second
	111		byte is the attribute. See op_move/op_and/op_or attribute description.
	112		Follow 2 groups of bytes. The fist one is the destination index. The second
	113		one is the source index.
	114		The source is added/substraced to/from the destination.
	115
	116		* op_set_port
	117
	118		The first byte is the opcode which number defines the target port.
	119		The port defines the method to perform register operations.
	120		There are 3 ports:
	121
	122		o AMD port: it has 2 sub-ports:
	123
	124		* direct MMIO.
	125
	126		* indirect MMIO. See section 7 and iio_interpreter.c
	127
	128		In this case, the opcode byte is followed by a 16 bits word which
	129		defines the AMD port
	130
	131		o PCI port: ignored. The opcode byte is followed by an ignored byte.
	132
	133		o SYSIO port: ignored. The opcode byte is followed by an ignored byte.
	134
	135		weird thing: for the direct access using the AMD port, there is the special
	136		case of the first register, which is the index register for
	137		generic register access. The value which is put there from
	138		the atombios is a dword index, then it has to be multiplied by
	139		4 to become a byte index.
	140
	141		* op_set_regs_blk
	142
	143		The first byte is the opcode and the following 16 bits word is the base
	144		index to use when accessing registers
	145		For instance, you can select the targetted crtc based on that index.
	146
	147		* op_set_fb_wnd
	148
	149		The first byte is the opcode. The second byte is the attibute (see op_move/
	150		op_and/op_or).
	151		Follow the source index which value is actually the frame buffer window
	152		base.
	153
	154		* op_compare
	155
	156		The first byte is the opcode which number defines the destination type. The
	157		second byte is the attribute (see op_move/ op_and/op_or).
	158		Follow a group of bytes which is the destination index, the first comparison
	159		operand. The next group of bytes is the source index, the second comparison
	160		operand.
	161		The result is stored in the interpreter context.
	162
	163		* op_switch
	164
	165		The first byte is the opcode. The second byte is the attribute (see op_move/
	166		op_and/op_or).
	167		Follow a group of bytes which is the source index. It is the switch value.
	168		Follow the case statements:
	169		The first 16 bits word with a special value. If that special value is
	170		CASE_END, then there is no more case statements. If that special value is
	171		CASE_MAGIC, then the next group of byte is the immediat value for that
	172		case statement (alignment/size same than the source index). Follow a 16
	173		bits word which is the relative jump from the beginning of the currently
	174		executed atombios table if the switch value is equal to the case value.
	175
	176		* op_jump
	177
	178		The first byte is the opocode, which number defines the condition:
	179
	180		o COND_ABOVE
	181		o COND_ABOVEOREQUAL
	182		o COND_ALWAYS
	183		o COND_BELOW
	184		o COND_BELOWOREQUAL
	185		o COND_NOTEQUAL
	186
	187		Conditional jump based on the conditions stored in the interpreter context.
	188
	189		The next 16 bits word is the index for the jump, relative to the start of
	190		the currently executed table.
	191
	192		* op_test
	193
	194		The first byte is the opcode, which number defines the destination type.
	195		The second byte is the attribute (see op_move/op_and/op_or).
	196		The destination is ANDed with the source. If the result is 0 the test
	197		failed, otherwise it succeeded.
	198
	199		* op_delay
	200
	201		The first byte is the opcode which number defines the time unit,
	202		which can be milli-second or micro-second. The second byte is the count of
	203		units.
	204
	205		* op_call_tbl
	206
	207		The first byte is the opcode. The second byte is the index of the table to
	208		interpret in the master command table.
	209
	210		* op_repeat
	211
	212		Not implemented. Only one byte, the opcode.
	213
	214		* op_clear
	215
	216		The first byte is the opcode which number defines the destination type. The
	217		second byte is the attribute (see op_move/op_and/op_or). The following
	218		group of bytes defines what to clear based on the destination type.
	219
	220		* op_mask
	221
	222		The first byte is the opcode which number defines the destination type. The
	223		second byte is the attribute. The following group of bytes is the
	224		destination index which type is based on the attribute byte. The next group
	225		of bytes is the mask itself, based on the source index type. Then the
	226		following group of bytes is the source index, which type is defined by the
	227		attribute byte. The source value is masked then it is put in the
	228		destination.
	229
	230		* op_post_card
	231
	232		The first byte is the opcode. The second byte is unknown, but seems related
	233		to some output resulting from a POSTed card.
	234
	235		* op_beep
	236
	237		beep! First and only byte is the opcode.
	238
	239		* op_save_reg
	240		op_restore_reg
	241
	242		unimplemented. Seems there is only one byte, the opcode.
	243
	244		* op_set_data_blk
	245
	246		The first byte is the opcode. The seconde byte is the data index:
	247
	248		o 0 means the data index in the interpreter context is set to 0.
	249		o 255 means the data index in the interperter is set to the currently
	250		interpreted table (not data but command!).
	251		o other, is the index of a table in the master data table. The offset
	252		of the pointed data table will be stored in the data index in the
	253		interpreter context.
	254
	255		Then you cannot use the data table with index 0 (utility_pipeline which
	256		contains parser information)
	257
	258		* op_xor
	259
	260		The first byte is the opcode which number defines the destination type. The
	261		second byte is the attribute (see op_move/op_and/op_or). The following
	262		group of bytes is the destination index. The next group of bytes is the
	263		source index. The destination is XORed with the source.
	264
	265		* op_shl
	266
	267		The first byte is the opcode which numbre defines the destination type. The
	268		second byte is the attribute (see op_move/op_and/op_or). The following group
	269		of bytes is the destination index. The whole 32 bits dword containing the
	270		destination will be used. The next group of bytes is the source index,
	271		actually the shift value.
	272
	273		* op_shr
	274
	275		See op_shl.
	276
	277		* op_debug
	278
	279		Unimplemented. Only the opcode byte.
	280
	281		7. indirect input/output (iio)
	282
	283		There is another byte code defined in the atombios for iio. The iio data table
	284		does define up to 256 "programs" for iio. There are 128 slots for read
	285		programs and 128 slots for write programs.
	286		A program is a sequence of special opcodes with their operands:
	287
	288		o NOP
	289		o START
	290		o READ
	291		o WRITE
	292		o CLEAR
	293		o SET
	294		o MOVE_IDX
	295		o MOVE_DATA
	296		o MOVE_ATTR
	297		o END
	298
	299		See iio_interpreter.c for the details, it's quite straight forward.
	300
	301		One program, in the iio data table, starts with the START opcode and ends with
	302		the END opcode. The operand of the START opcode defines the slot of the
	303		program. Slots between 0 and 127 are for iio read programs. Slots between 128
	304		and 255 are for iio write programs.
	305
	306		8. displayport auxiliary channel
	307
	308		The dp_aux command table is used for displayport auxiliary channel operations.
	309		It uses the scratch memory for the data transfer. Basically, you fill the
	310		scratch memory with a message. This message has 2 parts: an header and the
	311		data payload requiered for this header (usually data to send over the
	312		displayport auxiliary channel).
	313
	314		scratch memory layout:
	315
	316		o before interpreting the dp_aux command table:
	317
	318		You have the copy the message header followed by the data to send.
	319
	320		+---------------------------------------------------
	321		| scratch memory
	322		|+----------------+-------------------------
	323		|| message header | request data payload ...
	324		|+----------------+------------------------
	325		+---------------------------------------------------
	326
	327		o after interpreting the dp_aux command table:
	328
	329		You have the reply data in the scratch memory from the offset
	330		you set in the parameters of the table (dp_aux_params->reply_data_offset).
	331		I don't know the details, but it seems that it must leave room for 16
	332		bytes, which is the maximum payload size you can send in a displayport
	333		auxiliary channel transaction. I bet those 16 bytes is the last request
	334		data payload, since the data payload is limited to 16 byte by the
	335		standard.
	336
	337		+---------------------------------------------------
	338		| scratch memory
	339		|+--------------+-------------------
	340		|| ??? 16 bytes | reply data payload ...
	341		|+--------------+-------------------
	342		+---------------------------------------------------
	343
	344		The message header is only "related" to the standard. Nevertheless it uses
	345		most of the time the same bit flag values for configuration.
	346
	347		little endian messager header is a 32 bits word:
	348		0 20 24 28
	349		+----------------------------------------------------------------+
	350		| address | command | data payload size - 1 | total message size |
	351		+----------------------------------------------------------------+
	352
	353		It is the same header message format for native and I2C-Over-Aux
	354		transaction. The command half-byte uses the value of the request command half
	355		byte from the displayport standard.

File drivers/gpu/alga/amd/atombios/atb.h added (mode: 100644) (index 0000000..5e3cb95)
	1		#ifndef _ATB_H
	2		#define _ATB_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		struct g_ctx
	9		{
	10		/* workspace data */
	11		u32 divmul[2];
	12		u32 fb_wnd;
	13		u16 data_blk;
	14		u16 regs_blk;
	15		u16 io_attr;
	16		u8 shift;
	17		u16 io_mode;
	18
	19		/* compare opcodes */
	20		bool equal;
	21		bool above;
	22
	23		/* parameter space management */
	24		u32 *ps_top;
	25		size_t ps_dws;
	26		};
	27
	28		struct atombios
	29		{
	30		struct mutex mutex;
	31
	32		struct atb_dev adev;
	33		struct rom_hdr *hdr;
	34		u32 *scratch;
	35		size_t scratch_sz;
	36
	37		/*
	38		* This is an array of 256 pointer indexes on indirect io programs.
	39		* The first part 0-127 is for read programs, the second part is
	40		* for write programs... in theory.
	41		*/
	42		u16 *iio;
	43
	44		struct g_ctx g_ctx;
	45
	46		u8 name[512];
	47		};
	48		#endif /* _ATB_H */

File drivers/gpu/alga/amd/atombios/dce.c added (mode: 100644) (index 0000000..0678a94)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		#include <linux/module.h>
	8		#include <linux/slab.h>
	9		#include <linux/device.h>
	10		#include <asm/unaligned.h>
	11		#include <linux/mutex.h>
	12		#include <linux/delay.h>
	13
	14		#include <alga/timing.h>
	15		#include <alga/dp.h>
	16		#include <alga/amd/atombios/atb.h>
	17		#include <alga/amd/atombios/dce.h>
	18
	19		#include "tables/atb.h"
	20		#include "tables/cmd.h"
	21		#include "tables/data.h"
	22		#include "tables/firmware_info.h"
	23		#include "tables/obj_hdr.h"
	24		#include "tables/trans_ctl.h"
	25		#include "tables/dp_aux.h"
	26		#include "tables/pixel_clock_set.h"
	27		#include "tables/enc_ctl.h"
	28		#include "tables/crtc_blank.h"
	29		#include "tables/crtc_mem_req.h"
	30		#include "tables/crtc.h"
	31		#include "tables/enc_crtc_src.h"
	32		#include "tables/crtc_db_regs.h"
	33		#include "tables/crtc_timing.h"
	34		#include "tables/crtc_overscan.h"
	35		#include "tables/crtc_scaler.h"
	36
	37		#include "atb.h"
	38		#include "regs.h"
	39		#include "scratch_pads.h"
	40		#include "interpreter.h"
	41
	42		static const size_t send_data_payload_sz_max = 16;/* dp standard */
	43		static const unsigned retries_n = 4;
	44
	45		static int dp_aux(struct atombios *atb, u8 aux_i2c_id, u8 hpd, u8 *send_buf,
	46		size_t send_buf_sz, u8 *recv_buf, size_t recv_buf_sz, u8 *ack)
	47		{
	48		u16 of;
	49		struct master_cmd_tbl *cmd_tbl;
	50		struct common_cmd_tbl_hdr *dp_aux;
	51		struct dp_aux_params *ps;
	52		int r;
	53		size_t min_recv_sz;
	54		const size_t send_data_payload_sz_max = 16;/* dp standard */
	55		unsigned scratch_reply_data_of;
	56
	57		/* shift of 4 bytes/1 dword */
	58		if ((sizeof(u32) + send_buf_sz) > atb->scratch_sz) {
	59		dev_err(atb->adev.dev, "atombios: dp send buffer too big "
	60		"(%zu bytes for %zu bytes)", send_buf_sz,
	61		atb->scratch_sz);
	62		return -ENOMEM;
	63		}
	64
	65		/* shift of 4 bytes/1 dword */
	66		memcpy(atb->scratch + 1, send_buf, send_buf_sz);
	67
	68		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	69		cmd_tbl = atb->adev.rom + of;
	70		of = get_unaligned_le16(&cmd_tbl->list.dp_aux);
	71
	72		dp_aux = atb->adev.rom + of;
	73
	74		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	75		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	76		if (!atb->g_ctx.ps_top) {
	77		dev_err(atb->adev.dev, "atombios: unable to allocate "
	78		"parameter space (stack) for dp_aux method call\n");
	79		return -ENOMEM;
	80		}
	81
	82		/* shift of 4 bytes/1 dword */
	83		scratch_reply_data_of = sizeof(u32) + send_data_payload_sz_max;
	84
	85		ps = (struct dp_aux_params *)atb->g_ctx.ps_top;
	86		/* req=0 is specific to asic_init */
	87		put_unaligned_le16(0 + sizeof(u32), &ps->req);
	88		put_unaligned_le16(scratch_reply_data_of, &ps->reply_data_of);
	89		ps->reply_data_sz = 0;
	90		ps->i2c_id = aux_i2c_id;
	91		ps->delay = 0;
	92		ps->hpd = hpd; /* support no HPD with invalid value 0xff */
	93
	94		/* reset some global runtime workspace data */
	95		atb->g_ctx.fb_wnd = 0;
	96		atb->g_ctx.regs_blk = 0;
	97		atb->g_ctx.io_mode = IO_MM;
	98
	99		r = interpret(atb, of, 0, 0);
	100		if (r != 0)
	101		goto ps_free;
	102
	103		*ack = ps->reply_status;
	104
	105		if (ps->reply_status == 1) {/* timeout */
	106		r = -ETIMEDOUT;
	107		dev_err(atb->adev.dev, "atombios: dp_aux timeout\n");
	108		goto ps_free;
	109		}
	110		if (ps->reply_status == 2) {/* flags not zero */
	111		r = -EBUSY;
	112		dev_err(atb->adev.dev, "atombios: dp_aux flags not zero\n");
	113		goto ps_free;
	114		}
	115		if (ps->reply_status == 3) {/* error */
	116		r = -EIO;
	117		dev_err(atb->adev.dev, "atombios: dp_aux error\n");
	118		goto ps_free;
	119		}
	120
	121		/* copy as much of the recv data in the recv buf */
	122		if (recv_buf_sz < ps->reply_data_sz)
	123		min_recv_sz = recv_buf_sz;
	124		else
	125		min_recv_sz = ps->reply_data_sz;
	126
	127		if ((recv_buf != NULL) && (min_recv_sz != 0))
	128		memcpy(recv_buf, (void *)atb->scratch
	129		+ scratch_reply_data_of, min_recv_sz);
	130		r = min_recv_sz;
	131		ps_free:
	132		kfree(atb->g_ctx.ps_top);
	133		return r;
	134		}
	135
	136		int atb_dp_aux_native_write(struct atombios *atb, u8 aux_i2c_id, u8 hpd,
	137		u32 addr, u8 *send_buf, size_t send_buf_sz)
	138		{
	139		__le32 *msg_hdr; /* only "related" to the dp standard */
	140		u8 msg[sizeof(*msg_hdr) + send_data_payload_sz_max]; /* 20 bytes */
	141		size_t msg_sz;
	142		u8 ack;
	143		unsigned retry;
	144		int r;
	145
	146		if (send_buf_sz > send_data_payload_sz_max)
	147		return -EINVAL;
	148
	149		msg_sz = sizeof(*msg_hdr) + send_buf_sz;
	150
	151		msg_hdr = (__le32 *)msg;
	152		*msg_hdr = cpu_to_le32(addr); /* dpcd address is 20 bits */
	153		*msg_hdr |= (DP_AUX_NATIVE_WRITE << 20);
	154		*msg_hdr |= (send_buf_sz - 1) << 24;
	155		*msg_hdr |= msg_sz << 28;
	156
	157		memcpy(msg + sizeof(*msg_hdr), send_buf, send_buf_sz);
	158
	159		for (retry = 0; retry < retries_n; ++retry) {
	160		ack = 0;
	161		r = dp_aux(atb, aux_i2c_id, hpd, msg, msg_sz, NULL, 0, &ack);
	162
	163		if (r == -EBUSY || r == -ETIMEDOUT) {
	164		continue;
	165		} else if (r < 0) {
	166		return r;
	167		}
	168
	169		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
	170		return send_buf_sz;
	171		} else if ((ack & DP_AUX_NATIVE_REPLY_MASK)
	172		== DP_AUX_NATIVE_REPLY_DEFER) {
	173		udelay(400); /* dp standard, 400 microsecs timeout */
	174		} else /* NACK */ {
	175		return -EIO;
	176		}
	177		}
	178		return -EIO;
	179		}
	180		EXPORT_SYMBOL_GPL(atb_dp_aux_native_write);
	181
	182		int atb_dp_aux_native_read(struct atombios *atb, u8 aux_i2c_id, u8 hpd,
	183		u32 addr, u8 *recv_buf, size_t recv_buf_sz)
	184		{
	185		__le32 msg_hdr; /* only "related" to the dp standard */
	186		size_t msg_sz;
	187		u8 ack;
	188		int r;
	189		unsigned retry;
	190
	191		msg_sz = sizeof(msg_hdr);
	192
	193		msg_hdr = cpu_to_le32(addr); /* dpcd address is 20 bits */
	194		msg_hdr |= (DP_AUX_NATIVE_READ << 20);
	195		msg_hdr |= (recv_buf_sz - 1) << 24;
	196		msg_hdr |= msg_sz << 28;
	197
	198		for (retry = 0; retry < retries_n; ++retry) {
	199		ack = 0;
	200		r = dp_aux(atb, aux_i2c_id, hpd, (u8 *)&msg_hdr, msg_sz,
	201		recv_buf, recv_buf_sz, &ack);
	202		if (r == -EBUSY || r == -ETIMEDOUT)
	203		continue;
	204		else if (r < 0)
	205		return r;
	206
	207		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
	208		return r;
	209		else if ((ack & DP_AUX_NATIVE_REPLY_MASK)
	210		== DP_AUX_NATIVE_REPLY_DEFER)
	211		udelay(400); /* dp standard, 400 microsecs timeout */
	212		else if (r == 0) /* NACK */
	213		return -EINVAL; /* dp standard says wrong address */
	214		else
	215		return -EIO;
	216		}
	217		return -EIO;
	218		}
	219		EXPORT_SYMBOL_GPL(atb_dp_aux_native_read);
	220
	221		int atb_dp_aux_i2c(struct atombios *atb, u8 aux_i2c_id, u8 hpd, u16 addr,
	222		unsigned mode, u8 byte_send, u8 *byte_recv)
	223		{
	224		__le32 *msg_hdr; /* only "related" to the dp standard */
	225		u8 msg[sizeof(*msg_hdr) + 1]; /* 5 bytes */
	226		unsigned msg_sz;
	227		int r;
	228		u8 ack;
	229
	230		memset(msg, 0, sizeof(msg));
	231		msg_hdr = (__le32 *)msg;
	232		*msg_hdr = cpu_to_le32(addr); /* i2c address is up to 10 bits */
	233		if (mode & ATB_MODE_I2C_READ)
	234		*msg_hdr |= (DP_AUX_I2C_READ << 20);
	235		else
	236		*msg_hdr |= (DP_AUX_I2C_WRITE << 20);
	237
	238		if (!(mode & ATB_MODE_I2C_STOP))
	239		*msg_hdr |= (DP_AUX_I2C_MOT << 20);
	240
	241		switch (mode) {
	242		case ATB_MODE_I2C_WRITE:
	243		msg_sz = sizeof(*msg_hdr) + 1;
	244		*msg_hdr |= (1-1) << 24;
	245		*msg_hdr |= msg_sz << 28;
	246		msg[sizeof(*msg_hdr)] = byte_send;
	247		break;
	248		case ATB_MODE_I2C_READ:
	249		msg_sz = sizeof(*msg_hdr);
	250		*msg_hdr |= msg_sz << 28;
	251		break;
	252		default:/* ATB_MODE_I2C_START/STOP */
	253		msg_sz = sizeof(*msg_hdr);
	254		/*
	255		* this is a "too small" size to notify an i2c address only
	256		* transaction?
	257		*/
	258		*msg_hdr |= (sizeof(*msg_hdr) - 1) << 28;
	259		break;
	260		}
	261
	262		r = dp_aux(atb, aux_i2c_id, hpd, msg, msg_sz, byte_recv, 1, &ack);
	263		if (r < 0) {
	264		if (r == -EBUSY || r == -ETIMEDOUT) {
	265		udelay(400); /* dp standard transaction timeout */
	266		return -EAGAIN; /* let the i2c core retry */
	267		} else {
	268		return r;
	269		}
	270		}
	271
	272		switch (ack & DP_AUX_NATIVE_REPLY_MASK) {
	273		case DP_AUX_NATIVE_REPLY_ACK:
	274		/* i2c Reply field is only valid with a native aux ack */
	275		break;
	276		case DP_AUX_NATIVE_REPLY_NACK:
	277		dev_err(atb->adev.dev, "atombios: dp sink unable to fetch "
	278		"all i2c data\n");
	279		return -EREMOTEIO;
	280		case DP_AUX_NATIVE_REPLY_DEFER:
	281		udelay(400); /* dp standard transaction timeout */
	282		return -EAGAIN; /* let the i2c core retry */
	283		default:
	284		dev_err(atb->adev.dev, "atombios: dp sink invalid native ack"
	285		" value\n");
	286		return -EREMOTEIO;
	287		}
	288
	289		switch (ack & DP_AUX_I2C_REPLY_MASK) {
	290		case DP_AUX_I2C_REPLY_ACK:
	291		return r;
	292		case DP_AUX_I2C_REPLY_NACK:
	293		dev_err(atb->adev.dev, "atombios: dp sink i2c nack\n");
	294		return -EREMOTEIO;
	295		case DP_AUX_I2C_REPLY_DEFER:
	296		udelay(400); /* dp standard transaction timeout */
	297		return -EAGAIN; /* let the i2c core retry */
	298		default:
	299		dev_err(atb->adev.dev, "atombios: dp sink invalid i2c ack "
	300		"value\n");
	301		return -EREMOTEIO;
	302		}
	303		}
	304		EXPORT_SYMBOL_GPL(atb_dp_aux_i2c);
	305
	306		/* XXX: need to fine grainely set the atombios states, not s0/3/6 in one shot */
	307		void atb_dp_state(struct atombios *atb, unsigned dfp, bool connected)
	308		{
	309		u32 s0, s3, s6;
	310
	311		mutex_lock(&atb->mutex);
	312
	313		s0 = atb->adev.rr32(atb->adev.dev, S0);
	314		s3 = atb->adev.rr32(atb->adev.dev, S3);
	315		s6 = atb->adev.rr32(atb->adev.dev, S6);
	316
	317		if (connected) {
	318		s0 |= vals_s0_dfp[dfp];
	319		s3 |= vals_s3_dfp[dfp];
	320		s6 |= vals_s6_dfp[dfp];
	321		} else {
	322		s0 &= ~vals_s0_dfp[dfp];
	323		s3 &= ~vals_s3_dfp[dfp];
	324		s6 &= ~vals_s6_dfp[dfp];
	325		}
	326
	327		atb->adev.wr32(atb->adev.dev, s0, S0);
	328		atb->adev.wr32(atb->adev.dev, s3, S3);
	329		atb->adev.wr32(atb->adev.dev, s6, S6);
	330
	331		mutex_unlock(&atb->mutex);
	332		}
	333		EXPORT_SYMBOL_GPL(atb_dp_state);
	334
	335		static int default_disp_clk_freq(struct atombios *atb, u32 *clk)
	336		{
	337		u16 of;
	338		struct master_data_tbl *data_tbl;
	339		struct firmware_info_v2_1 *info;
	340
	341		of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
	342		data_tbl = atb->adev.rom + of;
	343
	344		of = get_unaligned_le16(&data_tbl->list.firmware_info);
	345		info = atb->adev.rom + of;
	346
	347		if (info->subset.hdr.tbl_fmt_rev != 2
	348		&& info->subset.hdr.tbl_content_rev != 1) {
	349		dev_err(atb->adev.dev, "atombios: firmware_info (0x%04x) "
	350		"revision %u.%u not supported\n", of,
	351		info->subset.hdr.tbl_fmt_rev,
	352		info->subset.hdr.tbl_content_rev);
	353		return -ATB_ERR;
	354		}
	355		*clk = get_unaligned_le32(&info->default_disp_clk_freq);
	356		if (*clk == 0)
	357		*clk = 60000; /* 600 Mhz for DCE4 */
	358		return 0;
	359		}
	360
	361		static int dp_mode_ext_clk_freq(struct atombios *atb, u16 *clk)
	362		{
	363		u16 of;
	364		struct master_data_tbl *data_tbl;
	365		struct firmware_info_v2_1 *info;
	366
	367		of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
	368		data_tbl = atb->adev.rom + of;
	369
	370		of = get_unaligned_le16(&data_tbl->list.firmware_info);
	371		info = atb->adev.rom + of;
	372
	373		if (info->subset.hdr.tbl_fmt_rev != 2
	374		&& info->subset.hdr.tbl_content_rev != 1) {
	375		dev_err(atb->adev.dev, "atombios: firmware_info (0x%04x) "
	376		"revision %u.%u not supported\n", of,
	377		info->subset.hdr.tbl_fmt_rev,
	378		info->subset.hdr.tbl_content_rev);
	379		return -ATB_ERR;
	380		}
	381		*clk = get_unaligned_le16(&info->uniphy_dp_mode_ext_clk_freq);
	382		return 0;
	383		}
	384
	385		int atb_crtc_blank(struct atombios *atb, unsigned i, bool on)
	386		{
	387		u16 of;
	388		struct master_cmd_tbl *cmd_tbl;
	389		struct common_cmd_tbl_hdr *crtc_blank;
	390		struct crtc_blank_params *ps;
	391		int r;
	392
	393		mutex_lock(&atb->mutex);
	394
	395		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	396		cmd_tbl = atb->adev.rom + of;
	397		of = get_unaligned_le16(&cmd_tbl->list.crtc_blank);
	398
	399		crtc_blank = atb->adev.rom + of;
	400		dev_info(atb->adev.dev, "atombios: crtc_blank (0x%04x) revision "
	401		"%u.%u\n", of, crtc_blank->hdr.tbl_fmt_rev,
	402		crtc_blank->hdr.tbl_content_rev);
	403
	404		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	405		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	406		if (!atb->g_ctx.ps_top) {
	407		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	408		"space (stack)\n");
	409		r = -ATB_ERR;
	410		goto unlock_mutex;
	411		}
	412		ps = (struct crtc_blank_params *)atb->g_ctx.ps_top;
	413		ps->crtc = i;
	414
	415		if (on)
	416		ps->state = CRTC_BLANK_ON;
	417		else
	418		ps->state = CRTC_BLANK_OFF;
	419
	420		atb->g_ctx.fb_wnd = 0;
	421		atb->g_ctx.regs_blk = 0;
	422		atb->g_ctx.io_mode = IO_MM;
	423
	424		r = interpret(atb, of, 0, 0);
	425		kfree(atb->g_ctx.ps_top);
	426
	427		unlock_mutex:
	428		mutex_unlock(&atb->mutex);
	429		return r;
	430		}
	431		EXPORT_SYMBOL_GPL(atb_crtc_blank);
	432
	433		int atb_crtc_mem_req(struct atombios *atb, unsigned i, bool on)
	434		{
	435		u16 of;
	436		struct master_cmd_tbl *cmd_tbl;
	437		struct common_cmd_tbl_hdr *crtc_mem_req;
	438		struct crtc_mem_req_params *ps;
	439		int r;
	440
	441		mutex_lock(&atb->mutex);
	442
	443		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	444		cmd_tbl = atb->adev.rom + of;
	445		of = get_unaligned_le16(&cmd_tbl->list.crtc_mem_req);
	446
	447		crtc_mem_req = atb->adev.rom + of;
	448		dev_info(atb->adev.dev, "atombios: crtc_mem_req (0x%04x) revision "
	449		"%u.%u\n", of, crtc_mem_req->hdr.tbl_fmt_rev,
	450		crtc_mem_req->hdr.tbl_content_rev);
	451
	452		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	453		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	454		if (!atb->g_ctx.ps_top) {
	455		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	456		"space (stack)\n");
	457		r = -ATB_ERR;
	458		goto unlock_mutex;
	459		}
	460		ps = (struct crtc_mem_req_params *)atb->g_ctx.ps_top;
	461		ps->crtc = i;
	462
	463		if (on)
	464		ps->state = CRTC_MEM_REQ_ON;
	465		else
	466		ps->state = CRTC_MEM_REQ_OFF;
	467
	468		atb->g_ctx.fb_wnd = 0;
	469		atb->g_ctx.regs_blk = 0;
	470		atb->g_ctx.io_mode = IO_MM;
	471
	472		r = interpret(atb, of, 0, 0);
	473		kfree(atb->g_ctx.ps_top);
	474
	475		unlock_mutex:
	476		mutex_unlock(&atb->mutex);
	477		return r;
	478		}
	479		EXPORT_SYMBOL_GPL(atb_crtc_mem_req);
	480
	481		int atb_crtc(struct atombios *atb, unsigned i, bool on)
	482		{
	483		u16 of;
	484		struct master_cmd_tbl *cmd_tbl;
	485		struct common_cmd_tbl_hdr *crtc;
	486		struct crtc_params *ps;
	487		int r;
	488
	489		mutex_lock(&atb->mutex);
	490
	491		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	492		cmd_tbl = atb->adev.rom + of;
	493		of = get_unaligned_le16(&cmd_tbl->list.crtc);
	494
	495		crtc = atb->adev.rom + of;
	496		dev_info(atb->adev.dev, "atombios: crtc (0x%04x) revision %u.%u\n",
	497		of, crtc->hdr.tbl_fmt_rev,
	498		crtc->hdr.tbl_content_rev);
	499
	500		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	501		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	502		if (!atb->g_ctx.ps_top) {
	503		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	504		" space (stack)\n");
	505		r = -ATB_ERR;
	506		goto unlock_mutex;
	507		}
	508		ps = (struct crtc_params *)atb->g_ctx.ps_top;
	509		ps->crtc = i;
	510
	511		if (on)
	512		ps->state = CRTC_ON;
	513		else
	514		ps->state = CRTC_OFF;
	515
	516		atb->g_ctx.fb_wnd = 0;
	517		atb->g_ctx.regs_blk = 0;
	518		atb->g_ctx.io_mode = IO_MM;
	519
	520		r = interpret(atb, of, 0, 0);
	521		kfree(atb->g_ctx.ps_top);
	522
	523		unlock_mutex:
	524		mutex_unlock(&atb->mutex);
	525		return r;
	526		}
	527		EXPORT_SYMBOL_GPL(atb_crtc);
	528
	529		int atb_crtc_dcpll(struct atombios *atb)
	530		{
	531		u16 of;
	532		struct master_cmd_tbl *cmd_tbl;
	533		struct common_cmd_tbl_hdr *pixel_clk_set;
	534		struct pixel_clk_set_params_v1_5 *ps;
	535		int r;
	536		u32 clk_freq;
	537
	538		mutex_lock(&atb->mutex);
	539
	540		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	541		cmd_tbl = atb->adev.rom + of;
	542		of = get_unaligned_le16(&cmd_tbl->list.pixel_clk_set);
	543
	544		pixel_clk_set = atb->adev.rom + of;
	545		dev_info(atb->adev.dev, "atombios: pixel_clk_set (0x%04x) revision "
	546		"%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev,
	547		pixel_clk_set->hdr.tbl_content_rev);
	548		if (pixel_clk_set->hdr.tbl_fmt_rev != 1
	549		|| pixel_clk_set->hdr.tbl_content_rev != 5) {
	550		dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not "
	551		"supported");
	552		r = -ATB_ERR;
	553		goto unlock_mutex;
	554		}
	555
	556		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	557		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	558		if (!atb->g_ctx.ps_top) {
	559		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	560		"space (stack)\n");
	561		r = -ATB_ERR;
	562		goto unlock_mutex;
	563		}
	564		ps = (struct pixel_clk_set_params_v1_5 *)atb->g_ctx.ps_top;
	565
	566		r = default_disp_clk_freq(atb, &clk_freq);
	567		if (r != 0) {
	568		r = -ATB_ERR;
	569		goto unlock_mutex;
	570		}
	571
	572		/*
	573		* if the default dcpll clock is specified, pixel_clk_set provides the
	574		* dividers
	575		*/
	576		ps->crtc = CRTC_INVALID;
	577		put_unaligned_le16((u16)clk_freq, &ps->pixel_clk);
	578		ps->ppll = DCPLL;
	579
	580		atb->g_ctx.fb_wnd = 0;
	581		atb->g_ctx.regs_blk = 0;
	582		atb->g_ctx.io_mode = IO_MM;
	583
	584		r = interpret(atb, of, 0, 0);
	585		kfree(atb->g_ctx.ps_top);
	586
	587		unlock_mutex:
	588		mutex_unlock(&atb->mutex);
	589		return r;
	590		}
	591		EXPORT_SYMBOL_GPL(atb_crtc_dcpll);
	592
	593		int atb_crtc_virtual_pixel_clk(struct atombios *atb, unsigned i, unsigned clk)
	594		{
	595		u16 of;
	596		struct master_cmd_tbl *cmd_tbl;
	597		struct common_cmd_tbl_hdr *pixel_clk_set;
	598		struct pixel_clk_set_params_v1_5 *ps;
	599		int r;
	600
	601		mutex_lock(&atb->mutex);
	602
	603		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	604		cmd_tbl = atb->adev.rom + of;
	605		of = get_unaligned_le16(&cmd_tbl->list.pixel_clk_set);
	606
	607		pixel_clk_set = atb->adev.rom + of;
	608		dev_info(atb->adev.dev, "atombios: pixel_clk_set (0x%04x) revision "
	609		"%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev,
	610		pixel_clk_set->hdr.tbl_content_rev);
	611		if (pixel_clk_set->hdr.tbl_fmt_rev != 1
	612		|| pixel_clk_set->hdr.tbl_content_rev != 5) {
	613		dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not "
	614		"supported");
	615		r = -ATB_ERR;
	616		goto unlock_mutex;
	617		}
	618
	619		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	620		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	621		if (!atb->g_ctx.ps_top) {
	622		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	623		"space (stack)\n");
	624		r = -ATB_ERR;
	625		goto unlock_mutex;
	626		}
	627		ps = (struct pixel_clk_set_params_v1_5 *)atb->g_ctx.ps_top;
	628		ps->crtc = i;
	629		ps->ppll = 0xff; /* invalid pll id for dp virtual pixel clk */
	630		put_unaligned_le16((u16)(clk / 10), &ps->pixel_clk);
	631
	632		atb->g_ctx.fb_wnd = 0;
	633		atb->g_ctx.regs_blk = 0;
	634		atb->g_ctx.io_mode = IO_MM;
	635
	636		r = interpret(atb, of, 0, 0);
	637		kfree(atb->g_ctx.ps_top);
	638
	639		unlock_mutex:
	640		mutex_unlock(&atb->mutex);
	641		return r;
	642		}
	643		EXPORT_SYMBOL_GPL(atb_crtc_virtual_pixel_clk);
	644
	645		static int trans_link(struct atombios *atb, struct trans_ctl_params *ps)
	646		{
	647		u16 of;
	648		struct master_cmd_tbl *cmd_tbl;
	649		struct common_cmd_tbl_hdr *trans_ctl;
	650		int r;
	651
	652		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	653		cmd_tbl = atb->adev.rom + of;
	654		of = get_unaligned_le16(&cmd_tbl->list.trans_ctl);
	655
	656		trans_ctl = atb->adev.rom + of;
	657		dev_info(atb->adev.dev, "atombios: trans_ctl (0x%04x) revision "
	658		"%u.%u\n", of, trans_ctl->hdr.tbl_fmt_rev,
	659		trans_ctl->hdr.tbl_content_rev);
	660		if (trans_ctl->hdr.tbl_fmt_rev != 1
	661		|| trans_ctl->hdr.tbl_content_rev != 3) {
	662		dev_err(atb->adev.dev, "atombios: trans_ctl revision not "
	663		"supported");
	664		return -ATB_ERR;
	665		}
	666
	667		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	668		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	669		if (!atb->g_ctx.ps_top) {
	670		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	671		"space (stack)\n");
	672		return -ATB_ERR;
	673		}
	674		memcpy(atb->g_ctx.ps_top, ps, sizeof(*ps));
	675
	676		atb->g_ctx.fb_wnd = 0;
	677		atb->g_ctx.regs_blk = 0;
	678		atb->g_ctx.io_mode = IO_MM;
	679
	680		r = interpret(atb, of, 0, 0);
	681		kfree(atb->g_ctx.ps_top);
	682		return r;
	683		}
	684
	685		int atb_enc_video(struct atombios *atb, unsigned i, bool on)
	686		{
	687		u16 of;
	688		struct master_cmd_tbl *cmd_tbl;
	689		struct common_cmd_tbl_hdr *enc_ctl;
	690		struct enc_ctl_params *ps;
	691		int r;
	692
	693		mutex_lock(&atb->mutex);
	694
	695		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	696		cmd_tbl = atb->adev.rom + of;
	697		of = get_unaligned_le16(&cmd_tbl->list.enc_ctl);
	698
	699		enc_ctl = atb->adev.rom + of;
	700		dev_info(atb->adev.dev, "atombios: enc_ctl (0x%04x) revision %u.%u\n",
	701		of, enc_ctl->hdr.tbl_fmt_rev,
	702		enc_ctl->hdr.tbl_content_rev);
	703
	704		if (enc_ctl->hdr.tbl_fmt_rev != 1
	705		|| (enc_ctl->hdr.tbl_content_rev != 2
	706		&& enc_ctl->hdr.tbl_content_rev != 3)) {
	707		dev_err(atb->adev.dev, "atombios: enc_ctl revision not "
	708		"supported");
	709		r = -ATB_ERR;
	710		goto unlock_mutex;
	711		}
	712
	713		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	714		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	715		if (!atb->g_ctx.ps_top) {
	716		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	717		"space (stack)\n");
	718		return -ATB_ERR;
	719		}
	720		ps = (struct enc_ctl_params *)atb->g_ctx.ps_top;
	721		if (on)
	722		ps->action = ENC_ACTION_DP_VIDEO_ON;
	723		else
	724		ps->action = ENC_ACTION_DP_VIDEO_OFF;
	725		ps->cfg = (i << ENC_CFG_SEL_SHIFT);
	726
	727		atb->g_ctx.fb_wnd = 0;
	728		atb->g_ctx.regs_blk = 0;
	729		atb->g_ctx.io_mode = IO_MM;
	730
	731		r = interpret(atb, of, 0, 0);
	732		kfree(atb->g_ctx.ps_top);
	733
	734		unlock_mutex:
	735		mutex_unlock(&atb->mutex);
	736		return r;
	737		}
	738		EXPORT_SYMBOL_GPL(atb_enc_video);
	739
	740		int atb_enc_dp_training_start(struct atombios *atb, unsigned i)
	741		{
	742		u16 of;
	743		struct master_cmd_tbl *cmd_tbl;
	744		struct common_cmd_tbl_hdr *enc_ctl;
	745		struct enc_ctl_params *ps;
	746		int r;
	747
	748		mutex_lock(&atb->mutex);
	749
	750		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	751		cmd_tbl = atb->adev.rom + of;
	752		of = get_unaligned_le16(&cmd_tbl->list.enc_ctl);
	753
	754		enc_ctl = atb->adev.rom + of;
	755		dev_info(atb->adev.dev, "atombios: enc_ctl (0x%04x) revision %u.%u\n",
	756		of, enc_ctl->hdr.tbl_fmt_rev,
	757		enc_ctl->hdr.tbl_content_rev);
	758
	759		if (enc_ctl->hdr.tbl_fmt_rev != 1
	760		|| (enc_ctl->hdr.tbl_content_rev != 2
	761		&& enc_ctl->hdr.tbl_content_rev != 3)) {
	762		dev_err(atb->adev.dev, "atombios: enc_ctl revision not "
	763		"supported");
	764		r = -ATB_ERR;
	765		goto unlock_mutex;
	766		}
	767
	768		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	769		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	770		if (!atb->g_ctx.ps_top) {
	771		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	772		"space (stack)\n");
	773		return -ATB_ERR;
	774		}
	775		ps = (struct enc_ctl_params *)atb->g_ctx.ps_top;
	776		ps->action = ENC_ACTION_DP_LINK_TRAINING_START;
	777		ps->cfg = (i << ENC_CFG_SEL_SHIFT);
	778
	779		atb->g_ctx.fb_wnd = 0;
	780		atb->g_ctx.regs_blk = 0;
	781		atb->g_ctx.io_mode = IO_MM;
	782
	783		r = interpret(atb, of, 0, 0);
	784		kfree(atb->g_ctx.ps_top);
	785
	786		unlock_mutex:
	787		mutex_unlock(&atb->mutex);
	788		return r;
	789		}
	790		EXPORT_SYMBOL_GPL(atb_enc_dp_training_start);
	791
	792		int atb_enc_dp_training_complete(struct atombios *atb, unsigned i)
	793		{
	794		u16 of;
	795		struct master_cmd_tbl *cmd_tbl;
	796		struct common_cmd_tbl_hdr *enc_ctl;
	797		struct enc_ctl_params *ps;
	798		int r;
	799
	800		mutex_lock(&atb->mutex);
	801
	802		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	803		cmd_tbl = atb->adev.rom + of;
	804		of = get_unaligned_le16(&cmd_tbl->list.enc_ctl);
	805
	806		enc_ctl = atb->adev.rom + of;
	807		dev_info(atb->adev.dev, "atombios: enc_ctl (0x%04x) revision %u.%u\n",
	808		of, enc_ctl->hdr.tbl_fmt_rev, enc_ctl->hdr.tbl_content_rev);
	809
	810		if (enc_ctl->hdr.tbl_fmt_rev != 1
	811		|| (enc_ctl->hdr.tbl_content_rev != 2
	812		&& enc_ctl->hdr.tbl_content_rev != 3)) {
	813		dev_err(atb->adev.dev, "atombios: enc_ctl revision not "
	814		"supported");
	815		r = -ATB_ERR;
	816		goto unlock_mutex;
	817		}
	818
	819		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	820		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	821		if (!atb->g_ctx.ps_top) {
	822		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	823		"space (stack)\n");
	824		return -ATB_ERR;
	825		}
	826		ps = (struct enc_ctl_params *)atb->g_ctx.ps_top;
	827		ps->action = ENC_ACTION_DP_LINK_TRAINING_COMPLETE;
	828		ps->cfg = (i << ENC_CFG_SEL_SHIFT);
	829
	830		atb->g_ctx.fb_wnd = 0;
	831		atb->g_ctx.regs_blk = 0;
	832		atb->g_ctx.io_mode = IO_MM;
	833
	834		r = interpret(atb, of, 0, 0);
	835		kfree(atb->g_ctx.ps_top);
	836
	837		unlock_mutex:
	838		mutex_unlock(&atb->mutex);
	839		return r;
	840		}
	841		EXPORT_SYMBOL_GPL(atb_enc_dp_training_complete);
	842
	843		int atb_enc_dp_tp(struct atombios *atb, unsigned i, unsigned link_rate,
	844		unsigned lanes_n, unsigned tp)
	845		{
	846		u16 of;
	847		struct master_cmd_tbl *cmd_tbl;
	848		struct common_cmd_tbl_hdr *enc_ctl;
	849		struct enc_ctl_params *ps;
	850		int r;
	851
	852		mutex_lock(&atb->mutex);
	853
	854		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	855		cmd_tbl = atb->adev.rom + of;
	856		of = get_unaligned_le16(&cmd_tbl->list.enc_ctl);
	857
	858		enc_ctl = atb->adev.rom + of;
	859		dev_info(atb->adev.dev, "atombios: enc_ctl (0x%04x) revision %u.%u\n",
	860		of, enc_ctl->hdr.tbl_fmt_rev, enc_ctl->hdr.tbl_content_rev);
	861
	862		if (enc_ctl->hdr.tbl_fmt_rev != 1
	863		|| (enc_ctl->hdr.tbl_content_rev != 2
	864		&& enc_ctl->hdr.tbl_content_rev != 3)) {
	865		dev_err(atb->adev.dev, "atombios: enc_ctl revision not "
	866		"supported");
	867		r = -ATB_ERR;
	868		goto unlock_mutex;
	869		}
	870
	871		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	872		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	873		if (!atb->g_ctx.ps_top) {
	874		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	875		"space (stack)\n");
	876		return -ATB_ERR;
	877		}
	878		ps = (struct enc_ctl_params *)atb->g_ctx.ps_top;
	879
	880		switch (tp) {
	881		case 1:
	882		ps->action = ENC_ACTION_DP_LINK_TRAINING_PATTERN1;
	883		break;
	884		case 2:
	885		ps->action = ENC_ACTION_DP_LINK_TRAINING_PATTERN2;
	886		break;
	887		case 3:
	888		ps->action = ENC_ACTION_DP_LINK_TRAINING_PATTERN3;
	889		break;
	890		default:
	891		dev_err(atb->adev.dev, "atombios: unknown dp training pattern "
	892		"%u\n", tp);
	893		r = -ATB_ERR;
	894		goto free_ps;
	895		}
	896		ps->cfg = (i << ENC_CFG_SEL_SHIFT);
	897		ps->lanes_n = lanes_n;
	898		switch (link_rate) {/* multiple of 270MHz */
	899		case 6:
	900		ps->cfg |= ENC_CFG_LINK_RATE_1_62_GHZ;
	901		break;
	902		case 10:
	903		ps->cfg |= ENC_CFG_LINK_RATE_2_7_GHZ;
	904		break;
	905		case 20:
	906		ps->cfg |= ENC_CFG_LINK_CATE_5_4_GHZ;
	907		break;
	908		}
	909
	910		atb->g_ctx.fb_wnd = 0;
	911		atb->g_ctx.regs_blk = 0;
	912		atb->g_ctx.io_mode = IO_MM;
	913
	914		r = interpret(atb, of, 0, 0);
	915
	916		free_ps:
	917		kfree(atb->g_ctx.ps_top);
	918
	919		unlock_mutex:
	920		mutex_unlock(&atb->mutex);
	921		return r;
	922		}
	923		EXPORT_SYMBOL_GPL(atb_enc_dp_tp);
	924
	925		int atb_enc_setup(struct atombios *atb, unsigned i, unsigned dp_lanes_n,
	926		unsigned dp_link_rate, unsigned bpc, unsigned pixel_clk)
	927
	928		{
	929		u16 of;
	930		struct master_cmd_tbl *cmd_tbl;
	931		struct common_cmd_tbl_hdr *enc_ctl;
	932		struct enc_ctl_params *ps;
	933		int r;
	934
	935		mutex_lock(&atb->mutex);
	936
	937		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	938		cmd_tbl = atb->adev.rom + of;
	939		of = get_unaligned_le16(&cmd_tbl->list.enc_ctl);
	940
	941		enc_ctl = atb->adev.rom + of;
	942		dev_info(atb->adev.dev, "atombios: enc_video (0x%04x) revision %u.%u\n",
	943		of, enc_ctl->hdr.tbl_fmt_rev, enc_ctl->hdr.tbl_content_rev);
	944
	945		if (enc_ctl->hdr.tbl_fmt_rev != 1
	946		|| (enc_ctl->hdr.tbl_content_rev != 2
	947		&& enc_ctl->hdr.tbl_content_rev != 3)) {
	948		dev_err(atb->adev.dev, "atombios: enc_video revision not "
	949		"supported");
	950		r = -ATB_ERR;
	951		goto unlock_mutex;
	952		}
	953
	954		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	955		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	956		if (!atb->g_ctx.ps_top) {
	957		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	958		" space (stack)\n");
	959		return -ATB_ERR;
	960		}
	961		ps = (struct enc_ctl_params *)atb->g_ctx.ps_top;
	962
	963		ps->cfg = (i << ENC_CFG_SEL_SHIFT);
	964		ps->action = ENC_ACTION_SETUP;
	965		put_unaligned_le16((u16)(pixel_clk / 10), &ps->pixel_clk);
	966		switch (dp_link_rate) {/* multiple of 270MHz */
	967		case 6:
	968		ps->cfg |= ENC_CFG_LINK_RATE_1_62_GHZ;
	969		break;
	970		case 10:
	971		ps->cfg |= ENC_CFG_LINK_RATE_2_7_GHZ;
	972		break;
	973		case 20:
	974		ps->cfg |= ENC_CFG_LINK_CATE_5_4_GHZ;
	975		break;
	976		}
	977		ps->lanes_n = dp_lanes_n;
	978		switch (bpc) {
	979		case 0:
	980		ps->bpc = ENC_BPC_UNDEFINE;
	981		break;
	982		case 6:
	983		ps->bpc = ENC_6BITS_PER_COLOR;
	984		break;
	985		case 8:
	986		ps->bpc = ENC_8BITS_PER_COLOR;
	987		break;
	988		case 10:
	989		ps->bpc = ENC_10BITS_PER_COLOR;
	990		break;
	991		case 12:
	992		ps->bpc = ENC_12BITS_PER_COLOR;
	993		break;
	994		case 16:
	995		ps->bpc = ENC_16BITS_PER_COLOR;
	996		break;
	997		};
	998
	999		atb->g_ctx.fb_wnd = 0;
	1000		atb->g_ctx.regs_blk = 0;
	1001		atb->g_ctx.io_mode = IO_MM;
	1002
	1003		r = interpret(atb, of, 0, 0);
	1004		kfree(atb->g_ctx.ps_top);
	1005
	1006		unlock_mutex:
	1007		mutex_unlock(&atb->mutex);
	1008		return r;
	1009		}
	1010		EXPORT_SYMBOL_GPL(atb_enc_setup);
	1011
	1012		int atb_trans_link_output_off(struct atombios *atb, unsigned i)
	1013		{
	1014		struct trans_ctl_params ps;
	1015		int r;
	1016
	1017		mutex_lock(&atb->mutex);
	1018
	1019		memset(&ps, 0, sizeof(ps));
	1020		ps.action = TRANS_ACTION_DISABLE_OUTPUT;
	1021		ps.cfg |= (to_link(i) << TRANS_CFG_LINK_SEL_BIT);
	1022		ps.cfg |= (to_trans(i) << TRANS_CFG_SEL_SHIFT);
	1023
	1024		r = trans_link(atb, &ps);
	1025
	1026		mutex_unlock(&atb->mutex);
	1027		return r;
	1028		}
	1029		EXPORT_SYMBOL_GPL(atb_trans_link_output_off);
	1030
	1031		int atb_trans_link_pwr(struct atombios *atb, unsigned i, bool on)
	1032		{
	1033		struct trans_ctl_params ps;
	1034		int r;
	1035
	1036		mutex_lock(&atb->mutex);
	1037
	1038		memset(&ps, 0, sizeof(ps));
	1039		if (on)
	1040		ps.action = TRANS_ACTION_PWR_ON;
	1041		else
	1042		ps.action = TRANS_ACTION_PWR_OFF;
	1043		ps.cfg |= (to_link(i) << TRANS_CFG_LINK_SEL_BIT);
	1044		ps.cfg |= (to_trans(i) << TRANS_CFG_SEL_SHIFT);
	1045
	1046		r = trans_link(atb, &ps);
	1047
	1048		mutex_unlock(&atb->mutex);
	1049		return r;
	1050		}
	1051		EXPORT_SYMBOL_GPL(atb_trans_link_pwr);
	1052
	1053		int atb_trans_link_off(struct atombios *atb, unsigned i)
	1054		{
	1055		struct trans_ctl_params ps;
	1056		int r;
	1057
	1058		mutex_lock(&atb->mutex);
	1059
	1060		memset(&ps, 0, sizeof(ps));
	1061		ps.action = TRANS_ACTION_DISABLE;
	1062		ps.cfg |= (to_link(i) << TRANS_CFG_LINK_SEL_BIT);
	1063		ps.cfg |= (to_trans(i) << TRANS_CFG_SEL_SHIFT);
	1064
	1065		r = trans_link(atb, &ps);
	1066
	1067		mutex_unlock(&atb->mutex);
	1068		return r;
	1069		}
	1070		EXPORT_SYMBOL_GPL(atb_trans_link_off);
	1071
	1072		static int trans_link_clk_ref(struct atombios *atb, struct trans_ctl_params *ps)
	1073		{
	1074		int r;
	1075		u16 dp_ext_clk;
	1076
	1077		r = dp_mode_ext_clk_freq(atb, &dp_ext_clk);
	1078		if (r != 0)
	1079		return r;
	1080
	1081		/*
	1082		* if no external reference dp clock
	1083		* we will use dcpll on dce5 cause 540 MHz units for dp 5.4 GHz
	1084		* dp link rate
	1085		*/
	1086		if (dp_ext_clk > 0) {
	1087		ps->cfg |= (2 << TRANS_CFG_CLK_SRC_SHIFT);
	1088		} else {
	1089		dev_err(atb->adev.dev, "atombios: at this time, this driver "
	1090		"supports only external reference dp clock\n");
	1091		return r;
	1092		}
	1093		return 0;
	1094		}
	1095
	1096		static void trans_link_path(u8 *cfg, unsigned i)
	1097		{
	1098		*cfg |= (to_link(i) << TRANS_CFG_LINK_SEL_BIT);
	1099		*cfg |= (to_trans(i) << TRANS_CFG_SEL_SHIFT);
	1100		*cfg |= ((i & 1) << TRANS_CFG_ENC_SEL_BIT);
	1101		}
	1102
	1103		/*
	1104		* DCE5 will make the difference between ACTION_SETUP and ACTION_ENA:
	1105		* this is probably to avoid providing all parameters each time we turn on and
	1106		* off the transmitter.
	1107		*/
	1108		int atb_trans_link_on(struct atombios *atb, unsigned i, unsigned dp_lanes_n,
	1109		unsigned pixel_clk)
	1110		{
	1111		struct trans_ctl_params ps;
	1112		int r;
	1113
	1114		mutex_lock(&atb->mutex);
	1115
	1116		memset(&ps, 0, sizeof(ps));
	1117		ps.action = TRANS_ACTION_ENA;
	1118		put_unaligned_le16((u16)(pixel_clk / 10), &ps.pixel_clk);
	1119		ps.cfg = BIT(TRANS_CFG_COHERENT_MODE_BIT);
	1120		trans_link_path(&ps.cfg, i);
	1121		ps.lanes_n = dp_lanes_n;
	1122
	1123		r = trans_link_clk_ref(atb, &ps);
	1124		if (r != 0)
	1125		goto unlock_mutex;
	1126
	1127		r = trans_link(atb, &ps);
	1128
	1129		unlock_mutex:
	1130		mutex_unlock(&atb->mutex);
	1131		return r;
	1132		}
	1133		EXPORT_SYMBOL_GPL(atb_trans_link_on);
	1134
	1135		int atb_trans_link_output_on(struct atombios *atb, unsigned i,
	1136		unsigned dp_lanes_n, unsigned pixel_clk)
	1137		{
	1138		struct trans_ctl_params ps;
	1139		int r;
	1140
	1141		mutex_lock(&atb->mutex);
	1142
	1143		memset(&ps, 0, sizeof(ps));
	1144		ps.action = TRANS_ACTION_ENA_OUTPUT;
	1145		trans_link_path(&ps.cfg, i);
	1146
	1147		r = trans_link(atb, &ps);
	1148
	1149		mutex_unlock(&atb->mutex);
	1150		return r;
	1151		}
	1152		EXPORT_SYMBOL_GPL(atb_trans_link_output_on);
	1153
	1154		int atb_trans_link_vs_pre_emph(struct atombios *atb, unsigned i, u8 vs_pre_emph)
	1155		{
	1156		struct trans_ctl_params ps;
	1157		int r;
	1158
	1159		mutex_lock(&atb->mutex);
	1160
	1161		memset(&ps, 0, sizeof(ps));
	1162		ps.action = TRANS_ACTION_SETUP_VSEMPH;
	1163		/*
	1164		* probably a mask, but does not matter: the hardware only support
	1165		* one set of voltage swing and pre-emphasis for all lanes
	1166		*/
	1167		ps.mode.lane_sel = 0;
	1168		ps.mode.lane_set = vs_pre_emph;
	1169		ps.cfg |= (to_link(i) << TRANS_CFG_LINK_SEL_BIT);
	1170		ps.cfg |= (to_trans(i) << TRANS_CFG_SEL_SHIFT);
	1171
	1172		r = trans_link(atb, &ps);
	1173
	1174		mutex_unlock(&atb->mutex);
	1175		return r;
	1176		}
	1177		EXPORT_SYMBOL_GPL(atb_trans_link_vs_pre_emph);
	1178
	1179		int atb_trans_link_init(struct atombios *atb, unsigned i, bool edp)
	1180		{
	1181		struct trans_ctl_params ps;
	1182		int r;
	1183		u16 conn_sub_id;
	1184
	1185		mutex_lock(&atb->mutex);
	1186
	1187		memset(&ps, 0, sizeof(ps));
	1188		ps.action = TRANS_ACTION_INIT;
	1189		if (edp)
	1190		conn_sub_id = CONN_SUB_ID_EDP;
	1191		else
	1192		conn_sub_id = CONN_SUB_ID_DP;
	1193		put_unaligned_le16(conn_sub_id, &ps.init_info);
	1194		ps.cfg = BIT(TRANS_CFG_COHERENT_MODE_BIT);
	1195		trans_link_path(&ps.cfg, i);
	1196
	1197		r = trans_link(atb, &ps);
	1198
	1199		mutex_unlock(&atb->mutex);
	1200		return r;
	1201		}
	1202		EXPORT_SYMBOL_GPL(atb_trans_link_init);
	1203
	1204		void atb_lock(struct atombios *atb, bool lock)
	1205		{
	1206		u32 s6;
	1207
	1208		mutex_lock(&atb->mutex);
	1209
	1210		s6 = atb->adev.rr32(atb->adev.dev, S6);
	1211
	1212		if (lock) {
	1213		s6 |= S6_CRITICAL_STATE;
	1214		s6 &= ~S6_ACC_MODE;
	1215		} else {
	1216		s6 &= ~S6_CRITICAL_STATE;
	1217		s6 |= S6_ACC_MODE;
	1218		}
	1219
	1220		atb->adev.wr32(atb->adev.dev, s6, S6);
	1221
	1222		mutex_unlock(&atb->mutex);
	1223		}
	1224		EXPORT_SYMBOL_GPL(atb_lock);
	1225
	1226		int atb_enc_crtc_src(struct atombios *atb, unsigned i)
	1227		{
	1228		u16 of;
	1229		struct master_cmd_tbl *cmd_tbl;
	1230		struct common_cmd_tbl_hdr *enc_crtc_src;
	1231		struct enc_crtc_src_params *ps;
	1232		int r;
	1233
	1234		mutex_lock(&atb->mutex);
	1235
	1236		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	1237		cmd_tbl = atb->adev.rom + of;
	1238		of = get_unaligned_le16(&cmd_tbl->list.enc_crtc_src);
	1239
	1240		enc_crtc_src = atb->adev.rom + of;
	1241		dev_info(atb->adev.dev, "atombios: enc_crtc_src (0x%04x) revision "
	1242		"%u.%u\n", of, enc_crtc_src->hdr.tbl_fmt_rev,
	1243		enc_crtc_src->hdr.tbl_content_rev);
	1244
	1245		if (enc_crtc_src->hdr.tbl_fmt_rev != 1
	1246		|| enc_crtc_src->hdr.tbl_content_rev != 2) {
	1247		dev_err(atb->adev.dev, "atombios: enc_crtc_src revision not "
	1248		"supported");
	1249		return -ATB_ERR;
	1250		}
	1251
	1252		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	1253		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	1254		if (!atb->g_ctx.ps_top) {
	1255		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	1256		"space (stack)\n");
	1257		r = -ATB_ERR;
	1258		goto unlock_mutex;
	1259		}
	1260		ps = (struct enc_crtc_src_params *)atb->g_ctx.ps_top;
	1261		ps->crtc = i;
	1262
	1263		switch (i) {
	1264		case 0:
	1265		ps->enc_id = ENC_0_ID;
	1266		break;
	1267		case 1:
	1268		ps->enc_id = ENC_1_ID;
	1269		break;
	1270		case 2:
	1271		ps->enc_id = ENC_2_ID;
	1272		break;
	1273		case 3:
	1274		ps->enc_id = ENC_3_ID;
	1275		break;
	1276		case 4:
	1277		ps->enc_id = ENC_4_ID;
	1278		break;
	1279		case 5:
	1280		ps->enc_id = ENC_5_ID;
	1281		break;
	1282		}
	1283		ps->mode = ENC_MODE_DP;
	1284
	1285		atb->g_ctx.fb_wnd = 0;
	1286		atb->g_ctx.regs_blk = 0;
	1287		atb->g_ctx.io_mode = IO_MM;
	1288
	1289		r = interpret(atb, of, 0, 0);
	1290		kfree(atb->g_ctx.ps_top);
	1291
	1292		unlock_mutex:
	1293		mutex_unlock(&atb->mutex);
	1294		return r;
	1295		}
	1296		EXPORT_SYMBOL_GPL(atb_enc_crtc_src);
	1297
	1298		int atb_crtc_lock(struct atombios *atb, unsigned i, bool lock)
	1299		{
	1300		u16 of;
	1301		struct master_cmd_tbl *cmd_tbl;
	1302		struct common_cmd_tbl_hdr *crtc_db_regs;
	1303		struct crtc_db_regs_params *ps;
	1304		int r;
	1305
	1306		mutex_lock(&atb->mutex);
	1307
	1308		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	1309		cmd_tbl = atb->adev.rom + of;
	1310		of = get_unaligned_le16(&cmd_tbl->list.crtc_db_regs);
	1311
	1312		crtc_db_regs = atb->adev.rom + of;
	1313		dev_info(atb->adev.dev, "atombios: crtc_lock (0x%04x) revision "
	1314		"%u.%u\n", of, crtc_db_regs->hdr.tbl_fmt_rev,
	1315		crtc_db_regs->hdr.tbl_content_rev);
	1316
	1317		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	1318		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	1319		if (!atb->g_ctx.ps_top) {
	1320		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	1321		"space (stack)\n");
	1322		r = -ATB_ERR;
	1323		goto unlock_mutex;
	1324		}
	1325		ps = (struct crtc_db_regs_params *)atb->g_ctx.ps_top;
	1326		ps->crtc = i;
	1327
	1328		if (lock)
	1329		ps->state = CRTC_LOCK;
	1330		else
	1331		ps->state = CRTC_UNLOCK;
	1332
	1333		atb->g_ctx.fb_wnd = 0;
	1334		atb->g_ctx.regs_blk = 0;
	1335		atb->g_ctx.io_mode = IO_MM;
	1336
	1337		r = interpret(atb, of, 0, 0);
	1338		kfree(atb->g_ctx.ps_top);
	1339
	1340		unlock_mutex:
	1341		mutex_unlock(&atb->mutex);
	1342		return r;
	1343		}
	1344		EXPORT_SYMBOL_GPL(atb_crtc_lock);
	1345
	1346		int atb_crtc_timing(struct atombios *atb, unsigned i, struct alga_timing *t)
	1347		{
	1348		u16 of;
	1349		struct master_cmd_tbl *cmd_tbl;
	1350		struct common_cmd_tbl_hdr *crtc_timing;
	1351		struct crtc_timing_params *ps;
	1352		int r;
	1353		u16 info;
	1354
	1355		mutex_lock(&atb->mutex);
	1356
	1357		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	1358		cmd_tbl = atb->adev.rom + of;
	1359		of = get_unaligned_le16(&cmd_tbl->list.crtc_timing);
	1360
	1361		crtc_timing = atb->adev.rom + of;
	1362		dev_info(atb->adev.dev, "atombios: crtc_timing (0x%04x) revision "
	1363		"%u.%u\n", of, crtc_timing->hdr.tbl_fmt_rev,
	1364		crtc_timing->hdr.tbl_content_rev);
	1365
	1366		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	1367		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	1368		if (!atb->g_ctx.ps_top) {
	1369		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	1370		"space (stack)\n");
	1371		r = -ATB_ERR;
	1372		goto unlock_mutex;
	1373		}
	1374		ps = (struct crtc_timing_params *)atb->g_ctx.ps_top;
	1375		put_unaligned_le16(t->h, &ps->h);
	1376		put_unaligned_le16(t->h_bl, &ps->h_bl);
	1377		put_unaligned_le16(t->v, &ps->v);
	1378		put_unaligned_le16(t->v_bl, &ps->v_bl);
	1379		put_unaligned_le16(t->h_so - t->h, &ps->h_so);/* not EDID definition */
	1380		put_unaligned_le16(t->h_spw, &ps->h_spw);
	1381		put_unaligned_le16(t->v_so - t->v, &ps->v_so);/* not EDID definition */
	1382		put_unaligned_le16(t->v_spw, &ps->v_spw);
	1383		ps->crtc = i;
	1384
	1385		info = 0;
	1386		if (t->h_sp == 1)
	1387		info |= INFO_HSYNC_POLARITY;
	1388		if (t->v_sp == 1)
	1389		info |= INFO_VSYNC_POLARITY;
	1390
	1391		atb->g_ctx.fb_wnd = 0;
	1392		atb->g_ctx.regs_blk = 0;
	1393		atb->g_ctx.io_mode = IO_MM;
	1394
	1395		r = interpret(atb, of, 0, 0);
	1396		kfree(atb->g_ctx.ps_top);
	1397
	1398		unlock_mutex:
	1399		mutex_unlock(&atb->mutex);
	1400		return r;
	1401		}
	1402		EXPORT_SYMBOL_GPL(atb_crtc_timing);
	1403
	1404		int atb_crtc_overscan(struct atombios *atb, unsigned i)
	1405		{
	1406		u16 of;
	1407		struct master_cmd_tbl *cmd_tbl;
	1408		struct common_cmd_tbl_hdr *crtc_overscan;
	1409		struct crtc_overscan_params *ps;
	1410		int r;
	1411
	1412		mutex_lock(&atb->mutex);
	1413
	1414		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	1415		cmd_tbl = atb->adev.rom + of;
	1416		of = get_unaligned_le16(&cmd_tbl->list.crtc_overscan);
	1417
	1418		crtc_overscan = atb->adev.rom + of;
	1419		dev_info(atb->adev.dev, "atombios: crtc_overscan (0x%04x) revision "
	1420		"%u.%u\n", of, crtc_overscan->hdr.tbl_fmt_rev,
	1421		crtc_overscan->hdr.tbl_content_rev);
	1422
	1423		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	1424		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	1425		if (!atb->g_ctx.ps_top) {
	1426		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	1427		"space (stack)\n");
	1428		r = -ATB_ERR;
	1429		goto unlock_mutex;
	1430		}
	1431		ps = (struct crtc_overscan_params *)atb->g_ctx.ps_top;
	1432		ps->crtc = i;
	1433
	1434		atb->g_ctx.fb_wnd = 0;
	1435		atb->g_ctx.regs_blk = 0;
	1436		atb->g_ctx.io_mode = IO_MM;
	1437
	1438		r = interpret(atb, of, 0, 0);
	1439		kfree(atb->g_ctx.ps_top);
	1440
	1441		unlock_mutex:
	1442		mutex_unlock(&atb->mutex);
	1443		return r;
	1444		}
	1445		EXPORT_SYMBOL_GPL(atb_crtc_overscan);
	1446
	1447		int atb_crtc_scaler(struct atombios *atb, unsigned i)
	1448		{
	1449		u16 of;
	1450		struct master_cmd_tbl *cmd_tbl;
	1451		struct common_cmd_tbl_hdr *crtc_scaler;
	1452		struct crtc_scaler_params *ps;
	1453		int r;
	1454
	1455		mutex_lock(&atb->mutex);
	1456
	1457		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	1458		cmd_tbl = atb->adev.rom + of;
	1459		of = get_unaligned_le16(&cmd_tbl->list.crtc_scaler);
	1460
	1461		crtc_scaler = atb->adev.rom + of;
	1462		dev_info(atb->adev.dev, "atombios: crtc_scaler (0x%04x) revision "
	1463		"%u.%u\n", of, crtc_scaler->hdr.tbl_fmt_rev,
	1464		crtc_scaler->hdr.tbl_content_rev);
	1465
	1466		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	1467		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	1468		if (!atb->g_ctx.ps_top) {
	1469		dev_err(atb->adev.dev, "atombios: unable to allocate parameter "
	1470		"space (stack)\n");
	1471		r = -ATB_ERR;
	1472		goto unlock_mutex;
	1473		}
	1474		ps = (struct crtc_scaler_params *)atb->g_ctx.ps_top;
	1475		ps->crtc = i;
	1476		ps->mode = SCALER_DISABLE;
	1477
	1478		atb->g_ctx.fb_wnd = 0;
	1479		atb->g_ctx.regs_blk = 0;
	1480		atb->g_ctx.io_mode = IO_MM;
	1481
	1482		r = interpret(atb, of, 0, 0);
	1483		kfree(atb->g_ctx.ps_top);
	1484
	1485		unlock_mutex:
	1486		mutex_unlock(&atb->mutex);
	1487		return r;
	1488		}
	1489		EXPORT_SYMBOL_GPL(atb_crtc_scaler);

File drivers/gpu/alga/amd/atombios/dp_paths.c added (mode: 100644) (index 0000000..04fd67b)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/slab.h>
	8		#include <linux/device.h>
	9		#include <asm/unaligned.h>
	10		#include <linux/mutex.h>
	11		#include <linux/types.h>
	12
	13		#include <alga/amd/atombios/atb.h>
	14		#include <alga/amd/atombios/dp_paths.h>
	15
	16		#include "tables/atb.h"
	17		#include "tables/data.h"
	18		#include "tables/obj_hdr.h"
	19		#include "tables/gpio_pin_lut.h"
	20		#include "tables/records.h"
	21
	22		#include "atb.h"
	23
	24		struct ctx
	25		{
	26		struct atombios *atb;
	27		struct master_data_tbl *master_data_tbl;
	28
	29		struct atb_dp_path *dp_paths;
	30		size_t dp_paths_n;
	31
	32		struct obj_hdr *obj_hdr;
	33		struct path_tbl *path_tbl;
	34		struct obj_tbl *conn_tbl;
	35		struct obj_tbl *encoder_tbl;
	36		};
	37
	38		static int ctx_init(struct atombios *atb, struct ctx *ctx)
	39		{
	40		ctx->master_data_tbl = atb->adev.rom + get_unaligned_le16(
	41		&atb->hdr->master_data_tbl_of);
	42
	43		ctx->obj_hdr = atb->adev.rom + get_unaligned_le16(
	44		&ctx->master_data_tbl->list.obj_hdr);
	45
	46		ctx->path_tbl = (void*)ctx->obj_hdr + get_unaligned_le16(
	47		&ctx->obj_hdr->path_tbl_of);
	48
	49		ctx->conn_tbl = (void*)ctx->obj_hdr + get_unaligned_le16(
	50		&ctx->obj_hdr->conn_tbl_of);
	51
	52		ctx->encoder_tbl = (void*)ctx->obj_hdr + get_unaligned_le16(
	53		&ctx->obj_hdr->encoder_tbl_of);
	54
	55		ctx->atb = atb;
	56		ctx->dp_paths = NULL;
	57		ctx->dp_paths_n = 0;
	58		return 0;
	59		}
	60
	61		static unsigned grphs_n_compute(struct path *p)
	62		{
	63		unsigned sz;
	64		sz = get_unaligned_le16(&p->sz);
	65		return (sz - offsetof(struct path, grph_ids)) / sizeof(__le16);
	66		}
	67
	68		static bool is_valid_rec(struct rec_hdr *r)
	69		{
	70		return r->sz > 0 && r->type > 0 && r->type < REC_TYPE_MAX;
	71		}
	72
	73		static void uniphy_link_recs_parse(struct ctx *ctx, struct obj *u,
	74		struct encoder_caps **c)
	75		{
	76		struct rec_hdr *r;
	77
	78		r = (void*)ctx->obj_hdr + get_unaligned_le16(&u->rec_of);
	79
	80		while (is_valid_rec(r)) {
	81		if (r->type == REC_TYPE_ENCODER_CAPS) {
	82		*c = (struct encoder_caps*)r;
	83		break;
	84		}
	85		r = (void*)r + r->sz;
	86		}
	87		}
	88
	89		static struct obj *objs_parse(struct obj_tbl *tbl, u16 id)
	90		{
	91		unsigned i;
	92
	93		for (i = 0; i < tbl->n; ++i) {
	94		struct obj *o;
	95		u16 o_id;
	96
	97		o = (&tbl->objs) + i;
	98		o_id = get_unaligned_le16(&o->id);
	99
	100		if (o_id == id)
	101		return o;
	102		}
	103		return NULL;
	104		}
	105
	106		static void uniphy_link_hbr2_get(struct ctx *ctx, u16 id, bool *hbr2)
	107		{
	108		struct obj *uniphy_link;
	109
	110		uniphy_link = objs_parse(ctx->encoder_tbl, id);
	111
	112		if (uniphy_link) {
	113		struct encoder_caps *caps;
	114
	115		caps = NULL;
	116		uniphy_link_recs_parse(ctx, uniphy_link, &caps);
	117
	118		if (caps)
	119		*hbr2 = caps->flgs & ENCODER_CAPS_DP_HBR2;
	120		}
	121		}
	122
	123		/*
	124		* Get the dp uniphy transmitter link.
	125		* Encoder term is used for transmitter link here
	126		*/
	127		static int path_grphs_parse(struct ctx *ctx, unsigned idx, struct path *p)
	128		{
	129		size_t grphs_n;
	130		u16 id;
	131		u8 sub_id;
	132		u8 type;
	133
	134		grphs_n = grphs_n_compute(p);
	135		if (grphs_n != 1) {
	136		dev_err(ctx->atb->adev.dev, "atombios: error, only one encoder"
	137		"graphic object is supported (grphs_n=%zu)\n", grphs_n);
	138		return -ATB_ERR;
	139		}
	140
	141		id = get_unaligned_le16(&p->grph_ids);
	142		sub_id = id_decode_sub_id(id);
	143		type = id_decode_type(id);
	144
	145		if (type != GRPH_TYPE_ENCODER
	146		&& sub_id != ENCODER_SUB_ID_INTERNAL_UNIPHY0
	147		&& sub_id != ENCODER_SUB_ID_INTERNAL_UNIPHY1
	148		&& sub_id != ENCODER_SUB_ID_INTERNAL_UNIPHY2) {
	149		dev_err(ctx->atb->adev.dev, "atombios: error, only uniphy "
	150		"link encoder graphic object is supported "
	151		"(id=0x%04x)\n", id);
	152		return -ATB_ERR;
	153		}
	154		ctx->dp_paths[idx].i = trans(id) * 2 + link_type(id);
	155		ctx->dp_paths[idx].uniphy_link_hbr2 = false;
	156		uniphy_link_hbr2_get(ctx, id, &ctx->dp_paths[idx].uniphy_link_hbr2);
	157		return 0;
	158		}
	159
	160		static void hpd_parse(struct ctx *ctx, struct rec_hdr *r,
	161		struct atb_dp_path *atb_p)
	162		{
	163		struct gpio_pin_lut *t;
	164		size_t n;
	165		struct hpd_int *h;
	166		unsigned i;
	167
	168		t = ctx->atb->adev.rom + get_unaligned_le16(
	169		&ctx->master_data_tbl->list.gpio_pin_lut);
	170
	171		n = (get_unaligned_le16(&t->hdr.sz) - sizeof(t->hdr)) / sizeof(t->pin);
	172
	173		atb_p->hpd = 0xff; /* no hpd */
	174		h = (struct hpd_int *)r;
	175		for (i = 0; i < n; ++i) {
	176		struct gpio_pin_assignment *pin;
	177
	178		pin = &t->pin + i;
	179
	180		if (h->gpio_id == pin->id) {
	181		switch (pin->bit_shift) {
	182		case 0:
	183		atb_p->hpd = 0;
	184		break;
	185		case 8:
	186		atb_p->hpd = 1;
	187		break;
	188		case 6:
	189		atb_p->hpd = 2;
	190		break;
	191		case 24:
	192		atb_p->hpd = 3;
	193		break;
	194		case 26:
	195		atb_p->hpd = 4;
	196		break;
	197		case 28:
	198		atb_p->hpd = 5;
	199		break;
	200		default:
	201		dev_warn(ctx->atb->adev.dev, "atombios: no "
	202		"valid pin found for hpd gpio rec "
	203		"id=%u\n", h->gpio_id);
	204		break;
	205		}
	206		}
	207		}
	208		}
	209
	210		static int conn_parse(struct ctx *ctx, struct obj *c, struct atb_dp_path *atb_p)
	211		{
	212		struct rec_hdr *r;
	213		bool aux_found;
	214
	215		aux_found = false;
	216
	217		r =(void*)ctx->obj_hdr + get_unaligned_le16(&c->rec_of);
	218
	219		while (is_valid_rec(r)) {
	220		struct i2c_info *i;
	221		switch (r->type) {
	222		case REC_TYPE_I2C:
	223		aux_found = true;
	224		i = (struct i2c_info*)r;
	225		atb_p->aux_i2c_id = i->id;
	226		break;
	227		case REC_TYPE_HPD_INT:
	228		hpd_parse(ctx, r, atb_p);
	229		break;
	230		}
	231		r = (void*)r + r->sz;
	232		}
	233
	234		if (!aux_found)
	235		return -ATB_ERR;
	236		return 0;
	237		}
	238
	239		static int path_conn_parse(struct ctx *ctx, struct path *p,
	240		struct atb_dp_path *atb_p)
	241		{
	242		u16 id;
	243		struct obj *c;
	244
	245		id = get_unaligned_le16(&p->conn_id);
	246
	247		c = objs_parse(ctx->conn_tbl, id);
	248		if (!c) {
	249		dev_err(ctx->atb->adev.dev, "atombios: unable to find "
	250		"connector object (id=0x%04x)\n", id);
	251		return -ATB_ERR;
	252		}
	253		return conn_parse(ctx, c, atb_p);
	254		}
	255
	256		static int dfp_get(struct ctx *ctx, struct path *p, unsigned *dfp)
	257		{
	258		unsigned i;
	259		*dfp = DFPx_MAX; /* invalid value */
	260		for (i = 0; i < DFPx_MAX; ++i) {
	261		if (get_unaligned_le16(&p->disp_dev) & vals_dfp_support[i]) {
	262		if (*dfp == DFPx_MAX) {
	263		*dfp = i;
	264		} else {
	265		dev_err(ctx->atb->adev.dev, "atombios: a "
	266		"displayport path has 2 DFP "
	267		"devices\n");
	268		return -1;
	269		}
	270		}
	271		}
	272		if (*dfp == DFPx_MAX) {
	273		dev_err(ctx->atb->adev.dev, "atombios: a displayport path has "
	274		"no DFP devices\n");
	275		return -ATB_ERR;
	276		}
	277		return 0;
	278		}
	279
	280		static int path_parse(struct ctx *ctx, unsigned idx, struct path *p)
	281		{
	282		u8 sub_id;
	283		int r;
	284
	285		sub_id = id_decode_sub_id(get_unaligned_le16(&p->conn_id));
	286
	287		ctx->dp_paths[idx].edp = (sub_id == CONN_SUB_ID_EDP);
	288		r = dfp_get(ctx, p, &ctx->dp_paths[idx].dfp);
	289		if (r != 0)
	290		return r;
	291
	292		r = path_grphs_parse(ctx, idx, p);
	293		if (r != 0)
	294		return r;
	295		return path_conn_parse(ctx, p, ctx->dp_paths + idx);
	296		}
	297
	298		static int dp_paths_n_func(struct ctx *ctx, unsigned idx, struct path *p)
	299		{
	300		(void)idx;
	301		(void)p;
	302		++(ctx->dp_paths_n);
	303		return 0;
	304		}
	305
	306		static bool is_dp(u16 id)
	307		{
	308		u8 sub_id;
	309		u8 type;
	310
	311		sub_id = id_decode_sub_id(id);
	312		type = id_decode_type(id);
	313
	314		return type == GRPH_TYPE_CONN && (sub_id == CONN_SUB_ID_DP
	315		|| sub_id == CONN_SUB_ID_EDP);
	316		}
	317
	318		static int paths_parse_do(struct ctx *ctx, int (*dp_f)(struct ctx *ctx,
	319		unsigned dp_path_idx, struct path *p))
	320		{
	321		u16 disp_dev_support;
	322		unsigned i;
	323		unsigned p_of;
	324		unsigned dp_path_idx;
	325		int r;
	326
	327		disp_dev_support = get_unaligned_le16(&ctx->obj_hdr->disp_dev_support);
	328
	329		r = 0;
	330		p_of = 0;
	331		dp_path_idx = 0;
	332		for (i = 0; i < ctx->path_tbl->n; ++i) {
	333		struct path *p;
	334
	335		p = (struct path*)((void*)(&ctx->path_tbl->paths) + p_of);
	336		p_of += get_unaligned_le16(&p->sz);
	337
	338		if ((disp_dev_support & get_unaligned_le16(&p->disp_dev))
	339		&& is_dp(get_unaligned_le16(&p->conn_id))){
	340		r = dp_f(ctx, dp_path_idx, p);
	341		++dp_path_idx;
	342		if (r != 0)
	343		break;
	344		}
	345		}
	346		return r;
	347		}
	348
	349		/*
	350		* a display device in atombios context is a dfp or tv or another dfp... from
	351		* an atombios perspective, a graphic board support some of those display
	352		* devices, each one lighting a bit in obj_hdr->disp_dev_support
	353		*/
	354		static int paths_parse(struct ctx *ctx)
	355		{
	356		int r;
	357
	358		paths_parse_do(ctx, dp_paths_n_func); /* count valid dp paths */
	359
	360		r = 0;
	361		if (ctx->dp_paths_n) {
	362		ctx->dp_paths = kzalloc(sizeof(*ctx->dp_paths)
	363		* ctx->dp_paths_n, GFP_KERNEL);
	364		if (!ctx->dp_paths)
	365		return -ATB_ERR;
	366
	367		r = paths_parse_do(ctx, path_parse);
	368		if (r != 0)
	369		kfree(ctx->dp_paths);
	370		}
	371		return r;
	372		}
	373
	374		int atb_dp_paths(struct atombios *atb, struct atb_dp_path **dp_paths,
	375		size_t *dp_paths_n)
	376		{
	377		struct ctx ctx;
	378		int r;
	379
	380		mutex_lock(&atb->mutex);
	381		ctx_init(atb, &ctx);
	382
	383		r = paths_parse(&ctx);
	384		if (r != 0)
	385		goto err_free_mutex;
	386
	387		*dp_paths = ctx.dp_paths;
	388		*dp_paths_n = ctx.dp_paths_n;
	389
	390		err_free_mutex:
	391		mutex_unlock(&atb->mutex);
	392		return r;
	393		}
	394		EXPORT_SYMBOL_GPL(atb_dp_paths);

File drivers/gpu/alga/amd/atombios/iio_interpreter.c added (mode: 100644) (index 0000000..d9ebbb5)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		#include <asm/io.h>
	8		#include <linux/slab.h>
	9		#include <linux/device.h>
	10		#include <asm/unaligned.h>
	11		#include <linux/mutex.h>
	12
	13		#include <alga/amd/atombios/atb.h>
	14
	15		#include "tables/atb.h"
	16		#include "tables/data.h"
	17
	18		#include "atb.h"
	19		#include "interpreter.h"
	20		#include "tables/iio.h"
	21
	22		static u32 read(struct atombios *atb, u16 *ptr)
	23		{
	24		struct iio_readwrite *iio_read;
	25		u16 reg_u32_idx;
	26		u32 val;
	27
	28		iio_read = atb->adev.rom + *ptr;
	29
	30		reg_u32_idx = get_unaligned_le16(&iio_read->reg_u32_idx);
	31
	32		val = atb->adev.rr32(atb->adev.dev, 4 * reg_u32_idx);
	33
	34		*ptr += sizeof(*iio_read);
	35		return val;
	36		}
	37
	38		static void write(struct atombios *atb, u16 *ptr, u32 val)
	39		{
	40		struct iio_readwrite *iio_write;
	41		u16 reg_u32_idx;
	42
	43		iio_write = atb->adev.rom + *ptr;
	44
	45		reg_u32_idx = get_unaligned_le16(&iio_write->reg_u32_idx);
	46
	47		atb->adev.wr32(atb->adev.dev, val, 4 * reg_u32_idx);
	48
	49		*ptr += sizeof(*iio_write);
	50		}
	51
	52		static u32 clr(struct atombios *atb, u16 *ptr, u32 val)
	53		{
	54		struct iio_clr *iio_clr;
	55
	56		iio_clr = atb->adev.rom + *ptr;
	57
	58		val &= ~((0xffffffff >> (32 - iio_clr->bits)) << iio_clr->pos);
	59
	60		*ptr += sizeof(*iio_clr);
	61		return val;
	62		}
	63
	64		static u32 set(struct atombios *atb, u16 *ptr, u32 val)
	65		{
	66		struct iio_set *iio_set;
	67
	68		iio_set = atb->adev.rom + *ptr;
	69
	70		val |= (0xffffffff >> (32 - iio_set->bits)) << iio_set->pos;
	71
	72		*ptr += sizeof(*iio_set);
	73		return val;
	74		}
	75
	76		static u32 move_bits(struct atombios *atb, u16 *ptr, u32 dst, u32 src)
	77		{
	78		struct iio_move_bits *iio_move_bits;
	79
	80		iio_move_bits = atb->adev.rom + *ptr;
	81
	82		/* clear bits for the source bits */
	83		dst &= ~((0xffffffff >> (32 - iio_move_bits->sz))
	84		<< iio_move_bits->dst_pos);
	85
	86		/*
	87		* get the source bits from their source position and OR them at their
	88		* destination position
	89		*/
	90		dst |= ((src >> iio_move_bits->src_pos) & (0xffffffff >>
	91		(32 - iio_move_bits->sz))) << iio_move_bits->dst_pos;
	92
	93		*ptr += sizeof(*iio_move_bits);
	94		return dst;
	95		}
	96
	97		u32 iio_interpret(struct ictx *ictx, u16 iio_prog, u32 idx, u32 data)
	98		{
	99		u32 tmp;
	100		u16 ptr;
	101
	102		tmp = 0xcdcdcdcd;
	103		ptr = iio_prog;
	104
	105		while (1)
	106		switch (*(u8*)(ictx->atb->adev.rom + ptr)) {
	107		case IIO_NOP:
	108		ptr++;
	109		break;
	110		case IIO_READ:
	111		tmp = read(ictx->atb, &ptr);
	112		break;
	113		case IIO_WRITE:
	114		write(ictx->atb, &ptr, tmp);
	115		break;
	116		case IIO_CLR:
	117		tmp = clr(ictx->atb, &ptr, tmp);
	118		break;
	119		case IIO_SET:
	120		tmp = set(ictx->atb, &ptr, tmp);
	121		break;
	122		case IIO_MOVE_IDX:
	123		tmp = move_bits(ictx->atb, &ptr, tmp, idx);
	124		break;
	125		case IIO_MOVE_DATA:
	126		tmp = move_bits(ictx->atb, &ptr, tmp, data);
	127		break;
	128		case IIO_MOVE_ATTR:
	129		tmp = move_bits(ictx->atb, &ptr, tmp,
	130		ictx->atb->g_ctx.io_attr);
	131		break;
	132		case IIO_END:
	133		return tmp;
	134		default:
	135		dev_err(ictx->atb->adev.dev,
	136		"atombios: iio: unknown opcode %d\n",
	137		*(u8*)(ictx->atb->adev.rom + ptr));
	138		return 0;
	139		}
	140		}
	141
	142		static int iio_len[] = {
	143		sizeof(struct iio_nop),
	144		sizeof(struct iio_start),
	145		sizeof(struct iio_readwrite),
	146		sizeof(struct iio_readwrite),
	147		sizeof(struct iio_clr),
	148		sizeof(struct iio_set),
	149		sizeof(struct iio_move_bits),
	150		sizeof(struct iio_move_bits),
	151		sizeof(struct iio_move_bits),
	152		sizeof(struct iio_end)
	153		};
	154
	155		int iio_setup(struct atombios *atb)
	156		{
	157		u16 of;
	158		struct master_data_tbl *data;
	159		u16 iio;
	160		struct common_tbl_hdr *iio_tbl_hdr;
	161		struct iio_start *iio_start;
	162
	163		/* 256 slots for iio program indexes */
	164		atb->iio = kzalloc(2 * 256, GFP_KERNEL);
	165		if (!atb->iio)
	166		return -ATB_ERR;
	167
	168		of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
	169		data = atb->adev.rom + of;
	170		iio = get_unaligned_le16(&data->list.iio);
	171		iio_tbl_hdr = atb->adev.rom + iio;
	172		dev_info(atb->adev.dev, "atombios: iio (0x%04x) revision %u.%u\n",
	173		iio, iio_tbl_hdr->tbl_fmt_rev, iio_tbl_hdr->tbl_content_rev);
	174		iio += sizeof(*iio_tbl_hdr);
	175
	176		/*
	177		* Load the first iio operation index in the proper iio program slot.
	178		* See tables/iio.h
	179		*/
	180		while (*(u8*)(atb->adev.rom + iio) == IIO_START) {
	181		iio_start = atb->adev.rom + iio;
	182
	183		iio += sizeof(*iio_start);
	184		atb->iio[iio_start->prog_idx] = iio;
	185
	186		while (*(u8*)(atb->adev.rom + iio) != IIO_END)
	187		iio += iio_len[*(u8*)(atb->adev.rom + iio)];
	188
	189		iio += sizeof(struct iio_end);
	190		}
	191		return 0;
	192		}

File drivers/gpu/alga/amd/atombios/iio_interpreter.h added (mode: 100644) (index 0000000..18f1758)
	1		#ifndef _IIO_INTERPRETER_H
	2		#define _IIO_INTERPRETER_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		int iio_setup(struct atombios *atb);
	9		u32 iio_interpret(struct ictx *ictx, u16 iio_prog, u32 idx, u32 data);
	10		#endif /* _IIO_INTERPRETER_H */

File drivers/gpu/alga/amd/atombios/interpreter.c added (mode: 100644) (index 0000000..04c258c)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <asm/io.h>
	7		#include <linux/slab.h>
	8		#include <linux/device.h>
	9		#include <asm/unaligned.h>
	10		#include <linux/mutex.h>
	11		#include <linux/delay.h>
	12		#include <linux/hardirq.h>
	13		#include <linux/kgdb.h>
	14
	15		#include <alga/amd/atombios/atb.h>
	16
	17		#include "atb.h"
	18		#include "tables/atb.h"
	19		#include "tables/cmd.h"
	20		#include "tables/data.h"
	21		#include "tables/iio.h"
	22
	23		#include "interpreter.h"
	24		#include "regs.h"
	25		#include "iio_interpreter.h"
	26
	27		#define OPS_CNT 123
	28		#define OP_EOT 91
	29
	30		#define ARG_REG 0
	31		#define ARG_PS 1
	32		#define ARG_WS 2
	33		#define ARG_FB 3
	34		#define ARG_ID 4 /* InDirect */
	35		#define ARG_IMM 5
	36		#define ARG_PLL 6
	37		#define ARG_MC 7
	38
	39		#define COND_ABOVE 0
	40		#define COND_ABOVEOREQUAL 1
	41		#define COND_ALWAYS 2
	42		#define COND_BELOW 3
	43		#define COND_BELOWOREQUAL 4
	44		#define COND_EQUAL 5
	45		#define COND_NOTEQUAL 6
	46
	47		#define CASE_MAGIC 0x63
	48		#define CASE_END 0x5a5a
	49
	50		#define PORT_AMD 0 /* direct or indirect */
	51		#define PORT_PCI 1
	52		#define PORT_SYSIO 2
	53
	54
	55		#define UNIT_MICROSEC 0
	56		#define UNIT_MILLISEC 1
	57
	58		#define TGT_DW 0
	59		#define TGT_WD_0 1
	60		#define TGT_WD_8 2
	61		#define TGT_WD_16 3
	62		#define TGT_BYTE0 4
	63		#define TGT_BYTE8 5
	64		#define TGT_BYTE16 6
	65		#define TGT_BYTE24 7
	66
	67		#define WS_QUOTIENT 0x40
	68		#define WS_REMAINDER 0x41
	69		#define WS_DATA_PTR 0x42
	70		#define WS_SHIFT 0x43
	71		#define WS_OR_MASK 0x44
	72		#define WS_AND_MASK 0x45
	73		#define WS_FB_WND 0x46
	74		#define WS_ATTRIBS 0x47
	75		#define WS_REG_PTR 0x48
	76
	77		static u32 arg_mask[8] = {
	78		0xffffffff,
	79		0xffff,
	80		0xffff00,
	81		0xffff0000,
	82		0xff,
	83		0xff00,
	84		0xff0000,
	85		0xff000000
	86		};
	87		static int arg_shift[8] = {0, 0, 8, 16, 0, 8, 16, 24};
	88
	89		/*
	90		* map the attribute destination alignment/size mapping to be the same
	91		* than the source from the source alignment/size value
	92		*/
	93		static int dst_src_identity[8] = {0, 0, 1, 2, 0, 1, 2, 3};
	94
	95		/*
	96		* map destination argument alignment/size from source alignment/size
	97		* ([5:3] from the attribute byte) and [7:6] from the attribute byte.
	98		*/
	99		static int dst_align_map[8][4] = {
	100		{0, 0, 0, 0},
	101		{1, 2, 3, 0},
	102		{1, 2, 3, 0},
	103		{1, 2, 3, 0},
	104		{4, 5, 6, 7},
	105		{4, 5, 6, 7},
	106		{4, 5, 6, 7},
	107		{4, 5, 6, 7}
	108		};
	109
	110		/* adjust the size of the parameter space and zero the new space */
	111		static int ps_sz_zadjust(struct ictx *ictx, u32 idx)
	112		{
	113		size_t required_dws;
	114
	115		required_dws = ictx->ps_frame + idx + 1;
	116
	117		if (required_dws > ictx->atb->g_ctx.ps_dws) {
	118		u32 *new_ps_top;
	119		size_t new_dws;
	120
	121		new_ps_top = krealloc(ictx->atb->g_ctx.ps_top, required_dws,
	122		GFP_KERNEL);
	123		if (!new_ps_top)
	124		return -ATB_ERR;
	125
	126		new_dws = required_dws - ictx->atb->g_ctx.ps_dws;
	127		memset(new_ps_top + ictx->ps_frame + idx + 1 - new_dws, 0,
	128		new_dws * 4);
	129
	130		ictx->atb->g_ctx.ps_top = new_ps_top;
	131		ictx->atb->g_ctx.ps_dws = required_dws;
	132		}
	133		return 0;
	134		}
	135
	136		/*
	137		* return the target value properly masked and shifted. The u32 from where
	138		* the target value is from, is stored in saved, if provided.
	139		*/
	140		static u32 get_val(struct ictx *ictx, u8 attr, u16 *ptr, u32 *saved)
	141		{
	142		u32 idx;
	143		u32 val;
	144		u32 align;
	145		u32 arg;
	146
	147		val = 0xcdcdcdcd;
	148		arg = attr & 7;
	149		align = (attr >> 3) & 7;
	150
	151		switch (arg) {
	152		case ARG_REG:
	153		idx = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	154		*ptr += 2;
	155
	156		idx += ictx->atb->g_ctx.regs_blk;
	157
	158		if (ictx->atb->g_ctx.io_mode & IO_IIO) {
	159		if (!ictx->atb->iio[ictx->atb->g_ctx.io_mode & 0x7f]) {
	160		dev_err(ictx->atb->adev.dev, "atombios: "
	161		"undefined indirect io read program "
	162		"%d.\n", ictx->atb->g_ctx.io_mode
	163		& 0x7f);
	164		return 0;
	165		}
	166		val = iio_interpret(ictx,
	167		ictx->atb->iio[ictx->atb->g_ctx.io_mode & 0x7f], idx,
	168		0);
	169		} else {
	170		switch (ictx->atb->g_ctx.io_mode) {
	171		case IO_MM:
	172		val = ictx->atb->adev.rr32(
	173		ictx->atb->adev.dev, 4 * idx);
	174		break;
	175		case IO_PCI:
	176		case IO_SYSIO:
	177		break;
	178		default:
	179		dev_err(ictx->atb->adev.dev, "atombios: "
	180		"get: bad io mode\n");
	181		return 0;
	182		}
	183		}
	184		break;
	185		case ARG_PS:
	186		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	187		(*ptr)++;
	188
	189		/* in case it tries to access unallocated memory */
	190		if (ps_sz_zadjust(ictx, idx) != 0) {
	191		ictx->abort = true;
	192		return 0;
	193		}
	194
	195		val = ictx->atb->g_ctx.ps_top[ictx->ps_frame + idx];
	196		break;
	197		case ARG_WS:
	198		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	199		(*ptr)++;
	200
	201		switch (idx) {
	202		case WS_QUOTIENT:
	203		val = ictx->atb->g_ctx.divmul[0];
	204		break;
	205		case WS_REMAINDER:
	206		val = ictx->atb->g_ctx.divmul[1];
	207		break;
	208		case WS_DATA_PTR:
	209		val = ictx->atb->g_ctx.data_blk;
	210		break;
	211		case WS_SHIFT:
	212		val = ictx->atb->g_ctx.shift;
	213		break;
	214		case WS_OR_MASK:
	215		val = 1 << ictx->atb->g_ctx.shift;
	216		break;
	217		case WS_AND_MASK:
	218		val = ~(1 << ictx->atb->g_ctx.shift);
	219		break;
	220		case WS_FB_WND:
	221		val = ictx->atb->g_ctx.fb_wnd;
	222		break;
	223		case WS_ATTRIBS:
	224		val = ictx->atb->g_ctx.io_attr;
	225		break;
	226		case WS_REG_PTR:
	227		val = ictx->atb->g_ctx.regs_blk;
	228		break;
	229		default:
	230		val = get_unaligned_le32(ictx->ws + idx);
	231		}
	232		break;
	233		case ARG_ID:
	234		idx = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	235		*ptr += 2;
	236
	237		val = get_unaligned_le32(ictx->atb->adev.rom + idx
	238		+ ictx->atb->g_ctx.data_blk);
	239		break;
	240		case ARG_FB:
	241		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	242		(*ptr)++;
	243
	244		//XXX:carefull, upstream does not byteswap this
	245		val = le32_to_cpup(ictx->atb->scratch + ictx->atb->g_ctx.fb_wnd / 4
	246		+ idx);
	247		break;
	248		case ARG_IMM:/* immediate, then return raw value */
	249		switch (align) {
	250		case TGT_DW:
	251		val = get_unaligned_le32(ictx->atb->adev.rom + *ptr);
	252		*ptr += 4;
	253		return val;
	254		case TGT_WD_0:
	255		case TGT_WD_8:
	256		case TGT_WD_16:
	257		val = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	258		*ptr += 2;
	259		return val;
	260		case TGT_BYTE0:
	261		case TGT_BYTE8:
	262		case TGT_BYTE16:
	263		case TGT_BYTE24:
	264		val = *(u8*)(ictx->atb->adev.rom + *ptr);
	265		(*ptr)++;
	266		return val;
	267		}
	268		return 0;
	269		case ARG_PLL:
	270		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	271		(*ptr)++;
	272		val = 0;
	273		break;
	274		case ARG_MC:
	275		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	276		(*ptr)++;
	277		val = 0;
	278		break;
	279		}
	280
	281		if (saved)
	282		*saved = val;
	283		val &= arg_mask[align];
	284		val >>= arg_shift[align];
	285		return val;
	286		}
	287
	288		/*
	289		* return the dst value properly masked and shifted. The u32 from where
	290		* the dst value is from, is stored in saved, if provided.
	291		*/
	292		static u32 get_dst(struct ictx *ictx, int arg, u8 attr, u16 *ptr, u32 *saved)
	293		{
	294		return get_val(ictx, arg
	295		| dst_align_map[(attr >> 3) & 7][(attr >> 6) & 3] << 3, ptr,
	296		saved);
	297		}
	298
	299		static void skip_val(struct ictx *ictx, u8 attr, u16 *ptr)
	300		{
	301		u32 align;
	302		u32 arg;
	303
	304		align = (attr >> 3) & 7;
	305		arg = attr & 7;
	306
	307		switch (arg) {
	308		case ARG_REG:
	309		case ARG_ID:
	310		*ptr += 2;
	311		break;
	312		case ARG_PLL:
	313		case ARG_MC:
	314		case ARG_PS:
	315		case ARG_WS:
	316		case ARG_FB:
	317		(*ptr)++;
	318		break;
	319		case ARG_IMM:
	320		switch (align) {
	321		case TGT_DW:
	322		*ptr += 4;
	323		break;
	324		case TGT_WD_0:
	325		case TGT_WD_8:
	326		case TGT_WD_16:
	327		*ptr += 2;
	328		break;
	329		case TGT_BYTE0:
	330		case TGT_BYTE8:
	331		case TGT_BYTE16:
	332		case TGT_BYTE24:
	333		(*ptr)++;
	334		break;
	335		}
	336		break;
	337		}
	338		}
	339
	340		static void skip_dst(struct ictx *ictx, int arg, u8 attr, u16 *ptr)
	341		{
	342		skip_val(ictx, arg | dst_align_map[(attr >> 3) & 7][(attr >> 6) & 3]
	343		<< 3, ptr);
	344		}
	345
	346		static u32 get_src(struct ictx *ictx, u8 attr, u16 *ptr)
	347		{
	348		return get_val(ictx, attr, ptr, NULL);
	349		}
	350
	351		static void put_dst(struct ictx *ictx, int arg, u8 attr, u16 *ptr, u32 val,
	352		u32 saved)
	353		{
	354		u32 dst_align;
	355		u32 old_val;
	356		u32 idx;
	357
	358		dst_align = dst_align_map[(attr >> 3) & 7][(attr >> 6) & 3];
	359
	360		old_val = val;
	361		old_val &= arg_mask[dst_align] >> arg_shift[dst_align];
	362
	363		val <<= arg_shift[dst_align];
	364		val &= arg_mask[dst_align];
	365
	366		saved &= ~arg_mask[dst_align];
	367		val |= saved;
	368
	369		switch (arg) {
	370		case ARG_REG:
	371		idx = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	372		*ptr += 2;
	373
	374		idx += ictx->atb->g_ctx.regs_blk;
	375
	376		if (ictx->atb->g_ctx.io_mode & IO_IIO) {
	377		if (!ictx->atb->iio[ictx->atb->g_ctx.io_mode & 0xff]) {
	378		dev_err(ictx->atb->adev.dev, "atombios: "
	379		"undefined indirect io write program "
	380		"%d.\n", ictx->atb->g_ctx.io_mode
	381		& 0x7f);
	382		return;
	383		}
	384		iio_interpret(ictx,
	385		ictx->atb->iio[ictx->atb->g_ctx.io_mode & 0xff], idx,
	386		val);
	387		} else {
	388		switch (ictx->atb->g_ctx.io_mode) {
	389		case IO_MM:
	390		if (idx == 0) {
	391		/*
	392		* for indirect reg access val is
	393		* actually a reg dword index.
	394		*/
	395		ictx->atb->adev.wr32(
	396		ictx->atb->adev.dev, 4 * val,
	397		0);
	398		} else {
	399		ictx->atb->adev.wr32(
	400		ictx->atb->adev.dev, val,
	401		4 * idx);
	402		}
	403		break;
	404		case IO_PCI:
	405		case IO_SYSIO:
	406		break;
	407		default:
	408		dev_err(ictx->atb->adev.dev, "atombios:"
	409		" bad io mode\n");
	410		return;
	411		}
	412		}
	413		break;
	414		case ARG_PS:
	415		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	416		(*ptr)++;
	417
	418		if (ps_sz_zadjust(ictx, idx) != 0) {
	419		ictx->abort = true;
	420		return;
	421		}
	422
	423		ictx->atb->g_ctx.ps_top[ictx->ps_frame + idx] =
	424		cpu_to_le32(val);
	425		break;
	426		case ARG_WS:
	427		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	428		(*ptr)++;
	429
	430		switch (idx) {
	431		case WS_QUOTIENT:
	432		ictx->atb->g_ctx.divmul[0] = val;
	433		break;
	434		case WS_REMAINDER:
	435		ictx->atb->g_ctx.divmul[1] = val;
	436		break;
	437		case WS_DATA_PTR:
	438		ictx->atb->g_ctx.data_blk = val;
	439		break;
	440		case WS_SHIFT:
	441		ictx->atb->g_ctx.shift = val;
	442		break;
	443		case WS_OR_MASK:
	444		case WS_AND_MASK:
	445		break;
	446		case WS_FB_WND:
	447		ictx->atb->g_ctx.fb_wnd = val;
	448		break;
	449		case WS_ATTRIBS:
	450		ictx->atb->g_ctx.io_attr = val;
	451		break;
	452		case WS_REG_PTR:
	453		ictx->atb->g_ctx.regs_blk = val;
	454		break;
	455		default:
	456		ictx->ws[idx] = cpu_to_le32(val);
	457		}
	458		break;
	459		case ARG_FB:
	460		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	461		(*ptr)++;
	462
	463		//XXX:carefull, upstream does not byteswap this
	464		ictx->atb->scratch[ictx->atb->g_ctx.fb_wnd / 4 + idx] =
	465		cpu_to_le32(val);
	466		break;
	467		case ARG_PLL:
	468		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	469		(*ptr)++;
	470		break;
	471		case ARG_MC:
	472		idx = *(u8*)(ictx->atb->adev.rom + *ptr);
	473		(*ptr)++;
	474		break;
	475		}
	476		}
	477
	478		static void op_move(struct ictx *ictx, u16 *ptr, int arg)
	479		{
	480		u8 attr;
	481		u32 src;
	482		u32 saved_dst_u32;
	483		u16 dst_ptr;
	484
	485		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	486		dst_ptr = *ptr;
	487
	488		if (((attr >> 3) & 7) != TGT_DW)
	489		get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	490		else {
	491		skip_dst(ictx, arg, attr, ptr);
	492		saved_dst_u32 = 0xcdcdcdcd;
	493		}
	494		src = get_src(ictx, attr, ptr);
	495		put_dst(ictx, arg, attr, &dst_ptr, src, saved_dst_u32);
	496		}
	497
	498		static void op_and(struct ictx *ictx, u16 *ptr, int arg)
	499		{
	500		u8 attr;
	501		u32 dst;
	502		u32 src;
	503		u32 saved_dst_u32;
	504		u16 dst_ptr;
	505
	506		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	507		dst_ptr = *ptr;
	508
	509		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	510		src = get_src(ictx, attr, ptr);
	511
	512		dst &= src;
	513
	514		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	515		}
	516
	517		static void op_or(struct ictx *ictx, u16 *ptr, int arg)
	518		{
	519		u8 attr;
	520		u32 dst;
	521		u32 src;
	522		u32 saved_dst_u32;
	523		u16 dst_ptr;
	524
	525		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	526		dst_ptr = *ptr;
	527
	528		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	529		src = get_src(ictx, attr, ptr);
	530
	531		dst |= src;
	532
	533		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	534		}
	535
	536		static u32 get_val_direct(struct ictx *ictx, u8 align, u16 *ptr)
	537		{
	538		u32 val;
	539
	540		val = 0xcdcdcdcd;
	541
	542		switch (align) {
	543		case TGT_DW:
	544		val = get_unaligned_le32(ictx->atb->adev.rom + *ptr);
	545		*ptr += 4;
	546		break;
	547		case TGT_WD_0:
	548		case TGT_WD_8:
	549		case TGT_WD_16:
	550		val = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	551		*ptr += 2;
	552		break;
	553		case TGT_BYTE0:
	554		case TGT_BYTE8:
	555		case TGT_BYTE16:
	556		case TGT_BYTE24:
	557		val = *(u8*)(ictx->atb->adev.rom + *ptr);
	558		(*ptr)++;
	559		break;
	560		}
	561		return val;
	562		}
	563
	564		static void op_shift_left(struct ictx *ictx, u16 *ptr, int arg)
	565		{
	566		u8 attr;
	567		u8 shift;
	568		u32 dst;
	569		u32 saved_dst_u32;
	570		u16 dst_ptr;
	571
	572		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	573		dst_ptr = *ptr;
	574
	575		/*
	576		* build attribute destination alignment/size mapping in order to
	577		* get destination the same alignment/size than source
	578		*/
	579		attr &= 0x38;
	580		attr |= dst_src_identity[attr >> 3] << 6;
	581
	582		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	583		shift = (u8)get_val_direct(ictx, TGT_BYTE0, ptr);
	584
	585		dst <<= shift;
	586
	587		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	588		}
	589
	590		static void op_shift_right(struct ictx *ictx, u16 *ptr, int arg)
	591		{
	592		u8 attr;
	593		u8 shift;
	594		u32 dst;
	595		u32 saved_dst_u32;
	596		u16 dst_ptr;
	597
	598		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	599		dst_ptr = *ptr;
	600
	601		/* see op_shift_left */
	602		attr &= 0x38;
	603		attr |= dst_src_identity[attr >> 3] << 6;
	604
	605		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	606		shift = get_val_direct(ictx, TGT_BYTE0, ptr);
	607
	608		dst >>= shift;
	609
	610		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	611		}
	612
	613		static void op_mul(struct ictx *ictx, u16 *ptr, int arg)
	614		{
	615		u8 attr;
	616		u32 dst;
	617		u32 src;
	618
	619		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	620
	621		dst = get_dst(ictx, arg, attr, ptr, NULL);
	622		src = get_src(ictx, attr, ptr);
	623
	624		ictx->atb->g_ctx.divmul[0] = dst * src;
	625		}
	626
	627		static void op_div(struct ictx *ictx, u16 *ptr, int arg)
	628		{
	629		u8 attr;
	630		u32 dst;
	631		u32 src;
	632
	633		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	634
	635		dst = get_dst(ictx, arg, attr, ptr, NULL);
	636		src = get_src(ictx, attr, ptr);
	637
	638		if (src != 0) {
	639		ictx->atb->g_ctx.divmul[0] = dst / src;
	640		ictx->atb->g_ctx.divmul[1] = dst % src;
	641		} else {
	642		ictx->atb->g_ctx.divmul[0] = 0;
	643		ictx->atb->g_ctx.divmul[1] = 0;
	644		}
	645		}
	646
	647		static void op_add(struct ictx *ictx, u16 *ptr, int arg)
	648		{
	649		u8 attr;
	650		u32 dst;
	651		u32 src;
	652		u32 saved_dst_u32;
	653		u16 dst_ptr;
	654
	655		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	656		dst_ptr = *ptr;
	657
	658		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	659		src = get_src(ictx, attr, ptr);
	660
	661		dst += src;
	662
	663		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	664		}
	665
	666		static void op_sub(struct ictx *ictx, u16 *ptr, int arg)
	667		{
	668		u8 attr;
	669		u32 dst;
	670		u32 src;
	671		u32 saved_dst_u32;
	672		u16 dst_ptr;
	673
	674		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	675		dst_ptr = *ptr;
	676
	677		dst = get_dst(ictx, arg, attr, ptr, &saved_dst_u32);
	678		src = get_src(ictx, attr, ptr);
	679
	680		dst -= src;
	681
	682		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_dst_u32);
	683		}
	684
	685		static void op_set_port(struct ictx *ictx, u16 *ptr, int arg)
	686		{
	687		u16 port;
	688
	689		switch (arg) {
	690		case PORT_AMD:
	691		port = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	692		if (!port)
	693		ictx->atb->g_ctx.io_mode = IO_MM;
	694		else
	695		ictx->atb->g_ctx.io_mode = IO_IIO | port;
	696		*ptr += 2;
	697		break;
	698		case PORT_PCI:
	699		ictx->atb->g_ctx.io_mode = IO_PCI;
	700		(*ptr)++;
	701		break;
	702		case PORT_SYSIO:
	703		ictx->atb->g_ctx.io_mode = IO_SYSIO;
	704		(*ptr)++;
	705		break;
	706		}
	707		}
	708
	709		//XXX:checked-->exactly the same
	710		static void op_set_regs_blk(struct ictx *ictx, u16 *ptr, int arg)
	711		{
	712		ictx->atb->g_ctx.regs_blk = get_unaligned_le16(ictx->atb->adev.rom
	713		+ *ptr);
	714		*ptr += 2;
	715		}
	716
	717		static void op_set_fb_wnd(struct ictx *ictx, u16 *ptr, int arg)
	718		{
	719		u8 attr;
	720
	721		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	722		ictx->atb->g_ctx.fb_wnd = get_src(ictx, attr, ptr);
	723		}
	724
	725		static void op_compare(struct ictx *ictx, u16 *ptr, int arg)
	726		{
	727		u8 attr;
	728		u32 dst;
	729		u32 src;
	730
	731		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	732
	733		dst = get_dst(ictx, arg, attr, ptr, NULL);
	734		src = get_src(ictx, attr, ptr);
	735
	736		ictx->atb->g_ctx.equal = (dst == src);
	737		ictx->atb->g_ctx.above = (dst > src);
	738		}
	739
	740		static void op_switch(struct ictx *ictx, u16 *ptr, int arg)
	741		{
	742		u8 attr;
	743		u32 src;
	744		u32 val;
	745		u32 tgt;
	746
	747		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	748
	749		src = get_src(ictx, attr, ptr);
	750
	751		while (get_unaligned_le16(ictx->atb->adev.rom + *ptr) != CASE_END)
	752		if (*(u8*)(ictx->atb->adev.rom + *ptr) == CASE_MAGIC) {
	753		(*ptr)++;
	754		val = get_src(ictx, (attr & 0x38) | ARG_IMM, ptr);
	755		tgt = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	756		if (val == src) {
	757		*ptr = ictx->tbl + tgt; /* relative jump */
	758		return;
	759		}
	760		*ptr += 2;
	761		} else {
	762		dev_warn(ictx->atb->adev.dev, "wrong switch case\n");
	763		return;
	764		}
	765		*ptr += 2;
	766		}
	767
	768		static void op_jump(struct ictx *ictx, u16 *ptr, int arg)
	769		{
	770		bool do_jump;
	771		u16 tgt;
	772
	773		do_jump = false;
	774		tgt = get_unaligned_le16(ictx->atb->adev.rom + *ptr);
	775
	776		*ptr += 2;
	777		switch (arg) {
	778		case COND_ABOVE:
	779		do_jump = ictx->atb->g_ctx.above;
	780		break;
	781		case COND_ABOVEOREQUAL:
	782		do_jump = ictx->atb->g_ctx.above || ictx->atb->g_ctx.equal;
	783		break;
	784		case COND_ALWAYS:
	785		do_jump = true;
	786		break;
	787		case COND_BELOW:
	788		do_jump = !(ictx->atb->g_ctx.above || ictx->atb->g_ctx.equal);
	789		break;
	790		case COND_BELOWOREQUAL:
	791		do_jump = !ictx->atb->g_ctx.above;
	792		break;
	793		case COND_EQUAL:
	794		do_jump = ictx->atb->g_ctx.equal;
	795		break;
	796		case COND_NOTEQUAL:
	797		do_jump = !ictx->atb->g_ctx.equal;
	798		break;
	799		}
	800
	801		if (do_jump)
	802		*ptr = ictx->tbl + tgt;
	803		}
	804
	805		static void op_test(struct ictx *ictx, u16 *ptr, int arg)
	806		{
	807		u8 attr;
	808		u32 dst;
	809		u32 src;
	810
	811		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	812
	813		dst = get_dst(ictx, arg, attr, ptr, NULL);
	814		src = get_src(ictx, attr, ptr);
	815
	816		ictx->atb->g_ctx.equal = ((dst & src) == 0);
	817		}
	818
	819		static void op_delay(struct ictx *ictx, u16 *ptr, int arg)
	820		{
	821		u8 count;
	822
	823		count = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	824
	825		/* using proper timer API can become tricky, see linux doc */
	826		if (arg == UNIT_MICROSEC)
	827		udelay(count);
	828		/* warning: in_atomic should not be used in driver */
	829		else if (in_atomic() || in_dbg_master() || irqs_disabled())
	830		mdelay(count);
	831		else
	832		msleep(count);
	833		}
	834
	835		static void op_call_tbl(struct ictx *ictx, u16 *ptr, int arg)
	836		{
	837		u8 idx;
	838		u16 of;
	839		struct master_cmd_tbl *cmd_hdr;
	840		struct common_cmd_tbl_hdr *tbl_hdr;
	841		u32 ps_frame_next;
	842		int r;
	843
	844		idx = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	845
	846		of = get_unaligned_le16(&ictx->atb->hdr->master_cmd_tbl_of);
	847		cmd_hdr = ictx->atb->adev.rom + of;
	848
	849		of = get_unaligned_le16((__le16*)(&cmd_hdr->list) + idx);
	850		if (!of) {
	851		dev_err(ictx->atb->adev.dev, "atombios: table code missing\n");
	852		ictx->abort = true;
	853		return;
	854		}
	855
	856		tbl_hdr = ictx->atb->adev.rom + of;
	857		ps_frame_next = ictx->ps_frame + ictx->ps_frame_dws;
	858
	859		r = interpret(ictx->atb, of, ps_frame_next, idx);
	860
	861		if (r)
	862		ictx->abort = true;
	863		}
	864
	865		static void op_repeat(struct ictx *ictx, u16 *ptr, int arg)
	866		{
	867		dev_warn(ictx->atb->adev.dev, "atombios: op_repeat unimplemented\n");
	868		}
	869
	870		static void op_clr(struct ictx *ictx, u16 *ptr, int arg)
	871		{
	872		u8 attr;
	873		u32 saved_u32_dst;
	874		u16 dst_ptr;
	875
	876		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	877		dst_ptr = *ptr;
	878
	879		attr &= 0x38;
	880		attr |= dst_src_identity[attr >> 3] << 6;
	881
	882		get_dst(ictx, arg, attr, ptr, &saved_u32_dst);
	883
	884		put_dst(ictx, arg, attr, &dst_ptr, 0, saved_u32_dst);
	885		}
	886
	887		static void op_nop(struct ictx *ictx, u16 *ptr, int arg)
	888		{
	889		/* nothing */
	890		}
	891
	892		static void op_eot(struct ictx *ictx, u16 *ptr, int arg)
	893		{
	894		/* functionally, a nop */
	895		}
	896
	897		static void op_mask(struct ictx *ictx, u16 *ptr, int arg)
	898		{
	899		u8 attr;
	900		u32 dst;
	901		u32 mask;
	902		u32 src;
	903		u32 saved_u32_dst;
	904		u16 dst_ptr;
	905
	906		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	907		dst_ptr = *ptr;
	908
	909		dst = get_dst(ictx, arg, attr, ptr, &saved_u32_dst);
	910		mask = get_val_direct(ictx, ((attr >> 3) & 7), ptr);
	911		src = get_src(ictx, attr, ptr);
	912
	913		dst &= mask;
	914		dst |= src;
	915
	916		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_u32_dst);
	917		}
	918
	919		static void op_post_card(struct ictx *ictx, u16 *ptr, int arg)
	920		{
	921		u8 val;
	922		val = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	923		}
	924
	925		static void op_beep(struct ictx *ictx, u16 *ptr, int arg)
	926		{
	927		dev_warn(ictx->atb->adev.dev, "atombios: beep!\n");
	928		}
	929
	930		static void op_save_reg(struct ictx *ictx, u16 *ptr, int arg)
	931		{
	932		dev_warn(ictx->atb->adev.dev, "atombios: op_save_reg unimplemented\n");
	933		}
	934
	935		static void op_restore_reg(struct ictx *ictx, u16 *ptr, int arg)
	936		{
	937		dev_warn(ictx->atb->adev.dev, "atombios: op_restore_reg "
	938		"unimplemented\n");
	939		}
	940
	941		//XXX:checked-->exactly the same
	942		static void op_set_data_blk(struct ictx *ictx, u16 *ptr, int arg)
	943		{
	944		u8 idx;
	945		u16 of;
	946		struct master_data_tbl *data;
	947
	948		idx = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	949
	950		if (!idx)
	951		ictx->atb->g_ctx.data_blk = 0;
	952		else if (idx == 255)
	953		ictx->atb->g_ctx.data_blk = ictx->tbl; /* current cmd table?! */
	954		else {
	955		of = get_unaligned_le16(
	956		&ictx->atb->hdr->master_data_tbl_of);
	957		data = ictx->atb->adev.rom + of;
	958
	959		ictx->atb->g_ctx.data_blk = get_unaligned_le16(
	960		(__le16*)(&data->list) + idx);
	961		}
	962		}
	963
	964		//XXX:not used
	965		static void op_xor(struct ictx *ictx, u16 *ptr, int arg)
	966		{
	967		u8 attr;
	968		u32 dst;
	969		u32 src;
	970		u32 saved_u32_dst;
	971		u16 dst_ptr;
	972
	973		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	974		dst_ptr = *ptr;
	975
	976		dst = get_dst(ictx, arg, attr, ptr, &saved_u32_dst);
	977		src = get_src(ictx, attr, ptr);
	978
	979		dst ^= src;
	980
	981		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_u32_dst);
	982		}
	983
	984		//XXX:not used
	985		static void op_shl(struct ictx *ictx, u16 *ptr, int arg)
	986		{
	987		u8 attr;
	988		u8 shift;
	989		u32 saved_u32_dst;
	990		u32 dst;
	991		u16 dst_ptr;
	992		u32 dst_align;
	993
	994		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	995		dst_ptr = *ptr;
	996
	997		dst_align = dst_align_map[(attr >> 3) & 7][(attr >> 6) & 3];
	998
	999		dst = get_dst(ictx, arg, attr, ptr, &saved_u32_dst);
	1000
	1001		/* op needs the whole dst u32 value */
	1002		dst = saved_u32_dst;
	1003		shift = get_src(ictx, attr, ptr);
	1004
	1005		dst <<= shift;
	1006		dst &= arg_mask[dst_align];
	1007		dst >>= arg_shift[dst_align];
	1008
	1009		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_u32_dst);
	1010		}
	1011
	1012		//XXX:not used
	1013		static void op_shr(struct ictx *ictx, u16 *ptr, int arg)
	1014		{
	1015		u8 attr;
	1016		u8 shift;
	1017		u32 saved_u32_dst;
	1018		u32 dst;
	1019		u16 dst_ptr;
	1020		u32 dst_align;
	1021
	1022		attr = *(u8*)(ictx->atb->adev.rom + (*ptr)++);
	1023		dst_ptr = *ptr;
	1024		dst_align = dst_align_map[(attr >> 3) & 7][(attr >> 6) & 3];
	1025
	1026		dst = get_dst(ictx, arg, attr, ptr, &saved_u32_dst);
	1027
	1028		/* op needs the whole u32 dst value */
	1029		dst = saved_u32_dst;
	1030		shift = get_src(ictx, attr, ptr);
	1031
	1032		dst >>= shift;
	1033		dst &= arg_mask[dst_align];
	1034		dst >>= arg_shift[dst_align];
	1035
	1036		put_dst(ictx, arg, attr, &dst_ptr, dst, saved_u32_dst);
	1037		}
	1038
	1039		static void op_debug(struct ictx *ictx, u16 *ptr, int arg)
	1040		{
	1041		dev_warn(ictx->atb->adev.dev, "atombios: op_debug unimplemented\n");
	1042		}
	1043
	1044		struct op
	1045		{
	1046		void (*func)(struct ictx *, u16 *, int);
	1047		int arg;
	1048		};
	1049
	1050		static struct op ops_tbl[OPS_CNT] = {
	1051		{NULL, 0},
	1052		{op_move, ARG_REG},
	1053		{op_move, ARG_PS},
	1054		{op_move, ARG_WS},
	1055		{op_move, ARG_FB},
	1056		{op_move, ARG_PLL},
	1057		{op_move, ARG_MC},
	1058		{op_and, ARG_REG},
	1059		{op_and, ARG_PS},
	1060		{op_and, ARG_WS},
	1061		{op_and, ARG_FB},
	1062		{op_and, ARG_PLL},
	1063		{op_and, ARG_MC},
	1064		{op_or, ARG_REG},
	1065		{op_or, ARG_PS},
	1066		{op_or, ARG_WS},
	1067		{op_or, ARG_FB},
	1068		{op_or, ARG_PLL},
	1069		{op_or, ARG_MC},
	1070		{op_shift_left, ARG_REG},
	1071		{op_shift_left, ARG_PS},
	1072		{op_shift_left, ARG_WS},
	1073		{op_shift_left, ARG_FB},
	1074		{op_shift_left, ARG_PLL},
	1075		{op_shift_left, ARG_MC},
	1076		{op_shift_right, ARG_REG},
	1077		{op_shift_right, ARG_PS},
	1078		{op_shift_right, ARG_WS},
	1079		{op_shift_right, ARG_FB},
	1080		{op_shift_right, ARG_PLL},
	1081		{op_shift_right, ARG_MC},
	1082		{op_mul, ARG_REG},
	1083		{op_mul, ARG_PS},
	1084		{op_mul, ARG_WS},
	1085		{op_mul, ARG_FB},
	1086		{op_mul, ARG_PLL},
	1087		{op_mul, ARG_MC},
	1088		{op_div, ARG_REG},
	1089		{op_div, ARG_PS},
	1090		{op_div, ARG_WS},
	1091		{op_div, ARG_FB},
	1092		{op_div, ARG_PLL},
	1093		{op_div, ARG_MC},
	1094		{op_add, ARG_REG},
	1095		{op_add, ARG_PS},
	1096		{op_add, ARG_WS},
	1097		{op_add, ARG_FB},
	1098		{op_add, ARG_PLL},
	1099		{op_add, ARG_MC},
	1100		{op_sub, ARG_REG},
	1101		{op_sub, ARG_PS},
	1102		{op_sub, ARG_WS},
	1103		{op_sub, ARG_FB},
	1104		{op_sub, ARG_PLL},
	1105		{op_sub, ARG_MC},
	1106		{op_set_port, PORT_AMD},
	1107		{op_set_port, PORT_PCI},
	1108		{op_set_port, PORT_SYSIO},
	1109		{op_set_regs_blk, 0},
	1110		{op_set_fb_wnd, 0},
	1111		{op_compare, ARG_REG},
	1112		{op_compare, ARG_PS},
	1113		{op_compare, ARG_WS},
	1114		{op_compare, ARG_FB},
	1115		{op_compare, ARG_PLL},
	1116		{op_compare, ARG_MC},
	1117		{op_switch, 0},
	1118		{op_jump, COND_ALWAYS},
	1119		{op_jump, COND_EQUAL},
	1120		{op_jump, COND_BELOW},
	1121		{op_jump, COND_ABOVE},
	1122		{op_jump, COND_BELOWOREQUAL},
	1123		{op_jump, COND_ABOVEOREQUAL},
	1124		{op_jump, COND_NOTEQUAL},
	1125		{op_test, ARG_REG},
	1126		{op_test, ARG_PS},
	1127		{op_test, ARG_WS},
	1128		{op_test, ARG_FB},
	1129		{op_test, ARG_PLL},
	1130		{op_test, ARG_MC},
	1131		{op_delay, UNIT_MILLISEC},
	1132		{op_delay, UNIT_MICROSEC},
	1133		{op_call_tbl, 0},
	1134		{op_repeat, 0},
	1135		{op_clr, ARG_REG},
	1136		{op_clr, ARG_PS},
	1137		{op_clr, ARG_WS},
	1138		{op_clr, ARG_FB},
	1139		{op_clr, ARG_PLL},
	1140		{op_clr, ARG_MC},
	1141		{op_nop, 0},
	1142		{op_eot, 0},
	1143		{op_mask, ARG_REG},
	1144		{op_mask,ARG_PS},
	1145		{op_mask, ARG_WS},
	1146		{op_mask, ARG_FB},
	1147		{op_mask, ARG_PLL},
	1148		{op_mask, ARG_MC},
	1149		{op_post_card, 0},
	1150		{op_beep, 0},
	1151		{op_save_reg, 0},
	1152		{op_restore_reg, 0},
	1153		{op_set_data_blk, 0},
	1154		{op_xor, ARG_REG},
	1155		{op_xor, ARG_PS},
	1156		{op_xor, ARG_WS},
	1157		{op_xor, ARG_FB},
	1158		{op_xor, ARG_PLL},
	1159		{op_xor, ARG_MC},
	1160		{op_shl, ARG_REG},
	1161		{op_shl, ARG_PS},
	1162		{op_shl, ARG_WS},
	1163		{op_shl, ARG_FB},
	1164		{op_shl, ARG_PLL},
	1165		{op_shl, ARG_MC},
	1166		{op_shr, ARG_REG},
	1167		{op_shr, ARG_PS},
	1168		{op_shr, ARG_WS},
	1169		{op_shr, ARG_FB},
	1170		{op_shr, ARG_PLL},
	1171		{op_shr, ARG_MC},
	1172		{op_debug, 0}
	1173		};
	1174
	1175		int interpret(struct atombios *atb, u16 tbl, u32 ps_frame, u8 idx)
	1176		{
	1177		int r;
	1178		struct ictx ictx;
	1179		struct common_cmd_tbl_hdr *hdr;
	1180		u16 ptr;
	1181		s8 op;
	1182
	1183		memset(&ictx, 0, sizeof(ictx));
	1184		ictx.atb = atb;
	1185		ictx.tbl = tbl;
	1186		ictx.ps_frame = ps_frame;
	1187		ictx.abort = false;
	1188
	1189		hdr = atb->adev.rom + tbl;
	1190
	1191		ictx.ps_frame_dws = (hdr->ps_frame_sz & ATTRIB_PS_SZ_MASK) / 4;
	1192
	1193		if (hdr->ws_dws) {
	1194		ictx.ws = kzalloc(4 * hdr->ws_dws, GFP_KERNEL);
	1195		if (!ictx.ws) {
	1196		dev_err(atb->adev.dev, "atombios: unable to allocate"
	1197		" workspace\n");
	1198		return -ATB_ERR;
	1199		}
	1200		} else
	1201		ictx.ws = NULL;
	1202
	1203		ptr = tbl + sizeof(*hdr);
	1204		r = 0;
	1205		while (1) {
	1206		op = *(s8*)(atb->adev.rom + ptr++);
	1207
	1208		if (0 < op && op < OPS_CNT)
	1209		ops_tbl[op].func(&ictx, &ptr, ops_tbl[op].arg);
	1210		else
	1211		break;
	1212
	1213		if (ictx.abort) {
	1214		dev_err(atb->adev.dev, "atombios: stuck executing "
	1215		"@0x%04x\n", ptr);
	1216		r = -ATB_ERR;
	1217		break;
	1218		}
	1219
	1220		if (op == OP_EOT)
	1221		break;
	1222		}
	1223
	1224		if (ictx.ws)
	1225		kfree(ictx.ws);
	1226		return r;
	1227		}

File drivers/gpu/alga/amd/atombios/interpreter.h added (mode: 100644) (index 0000000..5f0d1a4)
	1		#ifndef _INTERPRETER_H
	2		#define _INTERPRETER_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		struct ictx
	10		{
	11		struct atombios *atb;
	12		u16 tbl;
	13		u32 ps_frame;
	14		size_t ps_frame_dws;
	15		u32 *ws;
	16		bool abort;
	17		};
	18
	19		#define IO_MM 0 /* AMD port: direct */
	20		#define IO_PCI 1
	21		#define IO_SYSIO 2
	22		#define IO_IIO 0x80 /* AMD port: indirect */
	23
	24		int interpret(struct atombios *atb, u16 tbl, u32 ps_frame, u8 idx);
	25		#endif /* _INTERPRETER_H */

File drivers/gpu/alga/amd/atombios/mod.c added (mode: 100644) (index 0000000..6a28bd3)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		#include <linux/module.h>
	8		#include <linux/slab.h>
	9		#include <asm/io.h>
	10		#include <linux/device.h>
	11		#include <asm/unaligned.h>
	12		#include <linux/mutex.h>
	13
	14		#include <alga/amd/atombios/atb.h>
	15
	16		#include "tables/atb.h"
	17		#include "tables/cmd.h"
	18		#include "tables/data.h"
	19		#include "tables/firmware_info.h"
	20		#include "tables/asic_init.h"
	21		#include "tables/firmware_vram_usage.h"
	22
	23		#include "atb.h"
	24		#include "regs.h"
	25		#include "scratch_pads.h"
	26		#include "interpreter.h"
	27		#include "iio_interpreter.h"
	28
	29		int atb_asic_init(struct atombios *atb)
	30		{
	31		u16 of;
	32		struct master_data_tbl *data_tbl;
	33		struct firmware_info_subset *info;
	34		struct master_cmd_tbl *cmd_tbl;
	35		struct common_cmd_tbl_hdr *asic_init;
	36		struct asic_init_params *ps;
	37		int r;
	38
	39		mutex_lock(&atb->mutex);
	40
	41		/* engine and memory default clocks */
	42		of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
	43		data_tbl = atb->adev.rom + of;
	44
	45		of = get_unaligned_le16(&data_tbl->list.firmware_info);
	46		info = atb->adev.rom + of;
	47
	48		dev_info(atb->adev.dev, "atombios: firmware_info (0x%04x) revision "
	49		"%u.%u\n", of, info->hdr.tbl_fmt_rev,
	50		info->hdr.tbl_content_rev);
	51		dev_info(atb->adev.dev, "atombios: firmware revision 0x%08x\n",
	52		get_unaligned_le32(&info->firmware_rev));
	53		dev_info(atb->adev.dev, "atombios: default engine clock %ukHz\n",
	54		get_unaligned_le32(&info->default_eng_clk) * 10);
	55		dev_info(atb->adev.dev, "atombios: default memory clock %ukHz\n",
	56		get_unaligned_le32(&info->default_mem_clk) * 10);
	57
	58		/* asic_init call */
	59		of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
	60		cmd_tbl = atb->adev.rom + of;
	61		of = get_unaligned_le16(&cmd_tbl->list.asic_init);
	62
	63		asic_init = atb->adev.rom + of;
	64		dev_info(atb->adev.dev, "atombios: asic_init (0x%04x) revision %u.%u\n",
	65		of, asic_init->hdr.tbl_fmt_rev, asic_init->hdr.tbl_content_rev);
	66
	67		atb->g_ctx.ps_dws = 0x80;/* max for ps index */
	68		atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
	69		if (!atb->g_ctx.ps_top) {
	70		dev_err(atb->adev.dev, "atombios: unable to allocate parameter"
	71		" space (stack)\n");
	72		r = -ATB_ERR;
	73		goto unlock_mutex;
	74		}
	75
	76		ps = (struct asic_init_params *)atb->g_ctx.ps_top;
	77		put_unaligned_le32(get_unaligned_le32(&info->default_eng_clk),
	78		&ps->default_eng_clk);
	79		put_unaligned_le32(get_unaligned_le32(&info->default_mem_clk),
	80		&ps->default_mem_clk);
	81
	82		/* reset some global runtime workspace data */
	83		atb->g_ctx.fb_wnd = 0;
	84		atb->g_ctx.regs_blk = 0;
	85		atb->g_ctx.io_mode = IO_MM;
	86
	87		r = interpret(atb, of, 0, 0);
	88		kfree(atb->g_ctx.ps_top);
	89
	90		unlock_mutex:
	91		mutex_unlock(&atb->mutex);
	92		return r;
	93		}
	94		EXPORT_SYMBOL_GPL(atb_asic_init);
	95
	96		struct atombios *atb_alloc(struct atb_dev *adev)
	97		{
	98		struct atombios *atb;
	99
	100		atb = kzalloc(sizeof(struct atombios), GFP_KERNEL);
	101		if (!atb)
	102		return NULL;
	103		atb->adev = *adev;
	104		return atb;
	105		}
	106		EXPORT_SYMBOL_GPL(atb_alloc);
	107
	108		static void scratch_regs_setup(struct atombios *atb)
	109		{
	110		u32 s2;
	111		u32 s6;
	112
	113		s2 = atb->adev.rr32(atb->adev.dev, S2);
	114		s6 = atb->adev.rr32(atb->adev.dev, S6);
	115
	116		/* let the bios control the backlight */
	117		s2 &= ~S2_VRI_BRIGHT_ENA;
	118
	119		/* tell the bios not to handle mode switching */
	120		s6 |= S6_ACC_BLK_DISP_SWITCH;
	121
	122		atb->adev.wr32(atb->adev.dev, s2, S2);
	123		atb->adev.wr32(atb->adev.dev, s6, S6);
	124		}
	125
	126		static int scratch_mem_setup(struct atombios *atb)
	127		{
	128		struct master_data_tbl *data_tbl;
	129		struct firmware_vram_usage *usage; /* use rev 1.1 table layout */
	130		u16 of;
	131		size_t bytes;
	132		u64 start_addr;
	133		u16 sz;
	134
	135		of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
	136		data_tbl = atb->adev.rom + of;
	137
	138		of = get_unaligned_le16(&data_tbl->list.firmware_vram_usage);
	139		usage = atb->adev.rom + of;
	140
	141		start_addr = (u64)get_unaligned_le32(&usage->info.start_addr);
	142		if (usage->hdr.tbl_content_rev >= 4)
	143		start_addr = start_addr * 1024;
	144		sz = get_unaligned_le16(&usage->info.sz);
	145
	146		/*
	147		* This table defines a large data buffer for the interpreter.
	148		* It's actually in kernel RAM. The "vram" name comes from the
	149		* fact that this large data buffer is in vram when running
	150		* in POST real mode.
	151		*/
	152		dev_info(atb->adev.dev, "atombios: firmware_(v)ram_usage (0x%04x) "
	153		"revision %u.%u\n", of, usage->hdr.tbl_fmt_rev,
	154		usage->hdr.tbl_content_rev);
	155		dev_info(atb->adev.dev, "atombios: firmware_(v)ram_usage address is"
	156		" 0x%016llx\n", start_addr);
	157		dev_info(atb->adev.dev, "atombios: firmware_(v)ram_usage size is "
	158		"%zukB\n", (size_t)sz);
	159
	160		if (sz != 0)
	161		bytes = sz * 1024;
	162		else
	163		bytes = 20 * 1024; /* quirk: get 20kB if zero or not defined */
	164
	165		atb->scratch = kzalloc(bytes, GFP_KERNEL);
	166		if (!atb->scratch) {
	167		dev_err(atb->adev.dev, "atombios: unable to allocate scratch "
	168		"kernel memory\n");
	169		return -ATB_ERR;
	170		}
	171		atb->scratch_sz = bytes;
	172		dev_info(atb->adev.dev, "atombios: %zuB allocated for scratch "
	173		"memory\n", bytes);
	174		return 0;
	175		}
	176
	177		static void atb_name_build(struct atombios *atb, u8 *str)
	178		{
	179		int i;
	180
	181		while (*str && ((*str == '\n') || (*str == '\r')))
	182		str++;
	183		/* name string isn't always 0 terminated */
	184		for (i = 0; i < 511; ++i) {
	185		atb->name[i] = str[i];
	186		if (atb->name[i] < '.' || atb->name[i] > 'z') {
	187		atb->name[i] = 0;
	188		break;
	189		}
	190		}
	191		}
	192
	193		int atb_init(struct atombios *atb)
	194		{
	195		int err;
	196		u16 hdr_of;
	197		__le16 *hdr_of_ptr;
	198		u8 *bootup_msg;
	199
	200		hdr_of_ptr = (__le16*)(atb->adev.rom + 0x48);
	201		hdr_of = get_unaligned_le16(hdr_of_ptr);
	202		atb->hdr = (struct rom_hdr*)(atb->adev.rom + hdr_of);
	203		dev_info(atb->adev.dev, "atombios: rom (0x%04x) revision %u.%u\n",
	204		hdr_of, atb->hdr->hdr.tbl_fmt_rev,
	205		atb->hdr->hdr.tbl_content_rev);
	206
	207		if (memcmp(atb->hdr->firmware_signature, "ATOM", 4)) {
	208		dev_err(atb->adev.dev, "atombios: wrong signature");
	209		return -ATB_ERR;
	210		}
	211
	212		if (memcmp(atb->adev.rom + 0x30, " 761295520", 10)) {
	213		dev_err(atb->adev.dev, "atombios: wrong AMD signature");
	214		return -ATB_ERR;
	215		}
	216
	217		scratch_regs_setup(atb);
	218		err = scratch_mem_setup(atb);
	219		if (err)
	220		return err;
	221
	222		err = iio_setup(atb);
	223		if (err)
	224		goto free_scratch_mem;
	225
	226		bootup_msg = atb->adev.rom + get_unaligned_le16(
	227		&atb->hdr->bios_bootup_msg_of);
	228		atb_name_build(atb, bootup_msg);
	229		dev_info(atb->adev.dev, "atombios: %s\n", atb->name);
	230		mutex_init(&atb->mutex);
	231		return 0;
	232
	233		free_scratch_mem:
	234		kfree(atb->scratch);
	235		return err;
	236		}
	237		EXPORT_SYMBOL_GPL(atb_init);
	238
	239		void atb_cleanup(struct atombios *atb)
	240		{
	241		if (atb->scratch)
	242		kfree(atb->scratch);
	243		kfree(atb->iio);
	244		}
	245		EXPORT_SYMBOL_GPL(atb_cleanup);
	246
	247		static int __init init(void)
	248		{
	249		return 0;
	250		}
	251
	252		static void __exit cleanup(void)
	253		{
	254		}
	255
	256		module_init(init);
	257		module_exit(cleanup);
	258
	259		MODULE_AUTHOR("Sylvain Bertrand <digital.ragnarok@gmail.com>");
	260		MODULE_DESCRIPTION("AMD atombios");
	261		MODULE_LICENSE("GPL");

File drivers/gpu/alga/amd/atombios/regs.h added (mode: 100644) (index 0000000..8885b83)
	1		#ifndef _REGS_H
	2		#define _REGS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		/* scratch pad registers */
	10		#define S0 0x1724
	11		#define S1 0x1728
	12		#define S2 0x172c
	13		#define S3 0x1730
	14		#define S4 0x1734
	15		#define S5 0x1738
	16		#define S6 0x173c
	17		#define S7 0x1740
	18
	19		#endif /* _REGS_H */

File drivers/gpu/alga/amd/atombios/scratch_pads.h added (mode: 100644) (index 0000000..5a489e1)
	1		#ifndef _SCRATCH_PADS_H
	2		#define _SCRATCH_PADS_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	10		#define S0_DFP0 0x00010000L
	11		#define S0_DFP1 0x00020000L
	12		#define S0_LCD1 0x00040000L
	13		#define S0_LCD2 0x00080000L
	14		#define S0_DFP5 0x00100000L
	15		#define S0_DFP2 0x00200000L
	16		#define S0_DFP3 0x00400000L
	17		#define S0_DFP4 0x00800000L
	18
	19		static u32 vals_s0_dfp[DFPx_MAX] __attribute__ ((unused)) = {
	20		S0_DFP0,
	21		S0_DFP1,
	22		S0_DFP2,
	23		S0_DFP3,
	24		S0_DFP4,
	25		S0_DFP5
	26		};
	27		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 0 END~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	28
	29		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 2~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	30		#define S2_TV1_STANDARD_MASK 0x0000000fL
	31		#define S2_CURRENT_BL_LVL_MASK 0x0000ff00L
	32		#define S2_CURRENT_BL_LVL_SHIFT 8
	33
	34		#define S2_FORCED_LOW_PWR_MODE_STATE_MASK 0x0c000000L
	35		#define S2_FORCED_LOW_PWR_MODE_STATE_MASK_SHIFT 26
	36		#define S2_FORCED_LOW_PWR_MODE_STATE_CHANGE 0x10000000L
	37
	38		#define S2_DEV_DPMS_STATE 0x00010000L
	39		#define S2_VRI_BRIGHT_ENA 0x20000000L
	40
	41		#define S2_DISP_ROTATION_0_DEGREE 0x0
	42		#define S2_DISP_ROTATION_90_DEGREE 0x1
	43		#define S2_DISP_ROTATION_180_DEGREE 0x2
	44		#define S2_DISP_ROTATION_270_DEGREE 0x3
	45		#define S2_DISP_ROTATION_DEGREE_SHIFT 30
	46		#define S2_DISP_ROTATION_ANGLE_MASK 0xc0000000L
	47
	48		/* byte aligned definitions for bios usage */
	49		#define S2_B0_TV1_STANDARD_MASK 0x0f
	50		#define S2_B1_CURRENT_BL_LEVEL_MASK 0xff
	51		#define S2_B2_DEVICE_DPMS_STATE 0x01
	52
	53		#define S2_W1_DEV_DPMS_MASK 0x3ff
	54		#define S2_B3_FORCED_LOW_PWR_MODE_STATE_MASK 0x0C
	55		#define S2_B3_FORCED_LOW_PWR_MODE_STATE_CHANGE 0x10
	56		#define S2_B3_VRI_BRIGHT_ENA 0x20
	57		#define S2_B3_ROTATION_STATE_MASK 0xC0
	58		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 2 END~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	59
	60		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 3~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	61		#define S3_CRT1_ACTIVE 0x00000001L
	62		#define S3_LCD1_ACTIVE 0x00000002L
	63		#define S3_TV1_ACTIVE 0x00000004L
	64		#define S3_DFP0_ACTIVE 0x00000008L
	65		#define S3_CRT2_ACTIVE 0x00000010L
	66		#define S3_LCD2_ACTIVE 0x00000020L
	67		#define S3_DFP5_ACTIVE 0x00000040L
	68		#define S3_DFP1_ACTIVE 0x00000080L
	69		#define S3_CV_ACTIVE 0x00000100L
	70		#define S3_DFP2_ACTIVE 0x00000200L
	71		#define S3_DFP3_ACTIVE 0x00000400L
	72		#define S3_DFP4_ACTIVE 0x00000800L
	73
	74		static u32 vals_s3_dfp[DFPx_MAX] __attribute__ ((unused)) = {
	75		S3_DFP0_ACTIVE,
	76		S3_DFP1_ACTIVE,
	77		S3_DFP2_ACTIVE,
	78		S3_DFP3_ACTIVE,
	79		S3_DFP4_ACTIVE,
	80		S3_DFP5_ACTIVE
	81		};
	82
	83		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 3 END~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	84
	85		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 5~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	86		/* scrach pad 5 is used by firmware only */
	87		#define S5_B0_DOS_REQ_CRT1 0x01
	88		#define S5_B0_DOS_REQ_LCD1 0x02
	89		#define S5_B0_DOS_REQ_TV1 0x04
	90		#define S5_B0_DOS_REQ_DFP1 0x08
	91		#define S5_B0_DOS_REQ_CRT2 0x10
	92		#define S5_B0_DOS_REQ_LCD2 0x20
	93		#define S5_B0_DOS_REQ_DFP6 0x40
	94		#define S5_B0_DOS_REQ_DFP2 0x80
	95		#define S5_B1_DOS_REQ_CV 0x01
	96		#define S5_B1_DOS_REQ_DFP3 0x02
	97		#define S5_B1_DOS_REQ_DFP4 0x04
	98		#define S5_B1_DOS_REQ_DFP5 0x08
	99
	100		#define S5_W0_DOS_REQ_DEV 0x0fff
	101
	102		#define S5_DOS_REQ_CRT1 0x0001
	103		#define S5_DOS_REQ_LCD1 0x0002
	104		#define S5_DOS_REQ_TV1 0x0004
	105		#define S5_DOS_REQ_DFP1 0x0008
	106		#define S5_DOS_REQ_CRT2 0x0010
	107		#define S5_DOS_REQ_LCD2 0x0020
	108		#define S5_DOS_REQ_DFP6 0x0040
	109		#define S5_DOS_REQ_DFP2 0x0080
	110		#define S5_DOS_REQ_CV 0x0100
	111		#define S5_DOS_REQ_DFP3 0x0200
	112		#define S5_DOS_REQ_DFP4 0x0400
	113		#define S5_DOS_REQ_DFP5 0x0800
	114
	115		#define S5_B2_DOS_FORCE_CRT1 S5_B0_DOS_REQ_CRT1
	116		#define S5_B2_DOS_FORCE_TV1 S5_B0_DOS_REQ_TV1
	117		#define S5_B2_DOS_FORCE_CRT2 S5_B0_DOS_REQ_CRT2
	118		#define S5_B3_DOS_FORCE_CV S5_B1_DOS_REQ_CV
	119		#define S5_W1_DOS_FORCE_DEV (S5_B2_DOS_FORCE_CRT1 \
	120		+ S5_B2_DOS_FORCE_TV1 \
	121		+ S5_B2_DOS_FORCE_CRT2 \
	122		+ (S5_B3_DOS_FORCE_CV << 8))
	123		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 5 END~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	124
	125		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scracth pad 6~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	126		#define S6_DEV_CHANGE 0x00000001L
	127		#define S6_SCALER_CHANGE 0x00000002L
	128		#define S6_LID_CHANGE 0x00000004L
	129		#define S6_DOCKING_CHANGE 0x00000008L
	130		#define S6_ACC_MODE 0x00000010L
	131		#define S6_EXT_DESKTOP_MODE 0x00000020L
	132		#define S6_LID_STATE 0x00000040L
	133		#define S6_DOCK_STATE 0x00000080L
	134		#define S6_CRITICAL_STATE 0x00000100L
	135		#define S6_HW_I2C_BUSY_STATE 0x00000200L
	136		#define S6_THERMAL_STATE_CHANGE 0x00000400L
	137		#define S6_INTERRUPT_SET_BY_BIOS 0x00000800L
	138		/* normal expansion request bit for lcd */
	139		#define S6_REQ_LCD_EXPANSION_FULL 0x00001000L
	140		/* aspect ratio expansion request bit for lcd */
	141		#define S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L
	142
	143		/*
	144		* this bit is recycled when ATB_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,
	145		* previously it's scl2_h_expansion
	146		*/
	147		#define S6_DISP_STATE_CHANGE 0x00004000L
	148		/*
	149		* this bit is recycled when ATB_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,
	150		* previously it's scl2_v_expansion
	151		*/
	152		#define S6_I2C_STATE_CHANGE 0x00008000L
	153
	154		#define S6_ACC_REQ_CRT1 0x00010000L
	155		#define S6_ACC_REQ_LCD1 0x00020000L
	156		#define S6_ACC_REQ_TV1 0x00040000L
	157		#define S6_ACC_REQ_DFP0 0x00080000L
	158		#define S6_ACC_REQ_CRT2 0x00100000L
	159		#define S6_ACC_REQ_LCD2 0x00200000L
	160		#define S6_ACC_REQ_DFP5 0x00400000L
	161		#define S6_ACC_REQ_DFP1 0x00800000L
	162		#define S6_ACC_REQ_CV 0x01000000L
	163		#define S6_ACC_REQ_DFP2 0x02000000L
	164		#define S6_ACC_REQ_DFP3 0x04000000L
	165		#define S6_ACC_REQ_DFP4 0x08000000L
	166
	167		static u32 vals_s6_dfp[DFPx_MAX] __attribute__ ((unused)) = {
	168		S6_ACC_REQ_DFP0,
	169		S6_ACC_REQ_DFP1,
	170		S6_ACC_REQ_DFP2,
	171		S6_ACC_REQ_DFP3,
	172		S6_ACC_REQ_DFP4,
	173		S6_ACC_REQ_DFP5
	174		};
	175
	176		#define S6_ACC_REQ_MASK 0x0fff0000L
	177		#define S6_SYSTEM_PWR_MODE_CHANGE 0x10000000L
	178		#define S6_ACC_BLK_DISP_SWITCH 0x20000000L
	179		#define S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
	180		#define S6_CFG_DISP_CHANGE_MASK 0x80000000L
	181
	182		/* byte aligned definitions for bios usage */
	183		#define S6_DEV_CHANGE_B0 0x01
	184		#define S6_SCALER_CHANGE_B0 0x02
	185		#define S6_LID_CHANGE_B0 0x04
	186		#define S6_DOCKING_CHANGE_B0 0x08
	187		#define S6_ACC_MODE_B0 0x10
	188		#define S6_EXT_DESKTOP_MODE_B0 0x20
	189		#define S6_LID_STATE_B0 0x40
	190		#define S6_DOCK_STATE_B0 0x80
	191		#define S6_B1_CRITICAL_STATE 0x01
	192		#define S6_B1_HW_I2C_BUSY_STATE 0x02
	193		#define S6_B1_THERMAL_STATE_CHANGE 0x04
	194		#define S6_B1_INTERRUPT_SET_BY_BIOS 0x08
	195		#define S6_B1_REQ_LCD_EXPANSION_FULL 0x10
	196		#define S6_B1_REQ_LCD_EXPANSION_ASPEC_RATIO 0x20
	197
	198		#define S6_B2_ACC_REQ_CRT1 0x01
	199		#define S6_B2_ACC_REQ_LCD1 0x02
	200		#define S6_B2_ACC_REQ_TV1 0x04
	201		#define S6_B2_ACC_REQ_DFP1 0x08
	202		#define S6_B2_ACC_REQ_CRT2 0x10
	203		#define S6_B2_ACC_REQ_LCD2 0x20
	204		#define S6_B2_ACC_REQ_DFP6 0x40
	205		#define S6_B2_ACC_REQ_DFP2 0x80
	206		#define S6_B3_ACC_REQ_CV 0x01
	207		#define S6_B3_ACC_REQ_DFP3 0x02
	208		#define S6_B3_ACC_REQ_DFP4 0x04
	209		#define S6_B3_ACC_REQ_DFP5 0x08
	210
	211		#define S6_W1_ACC_REQ_DEVw1 S5_W0_DOS_REQ_DEV
	212		#define S6_B3_SYS_PWR_MODE_CHANGE 0x10
	213		#define S6_B3_ACC_BLK_DISP_SWITCH 0x20
	214		#define S6_B3_VRI_BRIGHTNESS_CHANGE 0x40
	215		#define S6_B3_CFG_DISP_CHANGE 0x80
	216
	217		#define S6_DEV_CHANGE_SHIFT 0
	218		#define S6_SCALER_CHANGE_SHIFT 1
	219		#define S6_LID_CHANGE_SHIFT 2
	220		#define S6_DOCKING_CHANGE_SHIFT 3
	221		#define S6_ACC_MODE_SHIFT 4
	222		#define S6_EXT_DESKTOP_MODE_SHIFT 5
	223		#define S6_LID_STATE_SHIFT 6
	224		#define S6_DOCK_STATE_SHIFT 7
	225		#define S6_CRITICAL_STATE_SHIFT 8
	226		#define S6_HW_I2C_BUSY_STATE_SHIFT 9
	227		#define S6_THERMAL_STATE_CHANGE_SHIFT 10
	228		#define S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
	229		#define S6_REQ_SCALER_SHIFT 12
	230		#define S6_REQ_SCALER_ARATIO_SHIFT 13
	231		#define S6_DISP_STATE_CHANGE_SHIFT 14
	232		#define S6_I2C_STATE_CHANGE_SHIFT 15
	233		#define S6_SYS_PWR_MODE_CHANGE_SHIFT 28
	234		#define S6_ACC_BLK_DISP_SWITCH_SHIFT 29
	235		#define S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
	236		#define S6_CFG_DISP_CHANGE_SHIFT 31
	237		/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~scratch pad 6 END~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
	238		#endif /* _SCRATCH_PADS_H */

File drivers/gpu/alga/amd/atombios/tables/asic_init.h added (mode: 100644) (index 0000000..a5f15e0)
	1		#ifndef _TABLES_ASIC_INIT_H
	2		#define _TABLES_ASIC_INIT_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		struct asic_init_params {
	10		__le32 default_eng_clk;/* in 10kHz unit */
	11		__le32 default_mem_clk;/* in 10kHz unit */
	12		} __packed;
	13		#endif /* _TABLES_ASIC_INIT_H */

File drivers/gpu/alga/amd/atombios/tables/atb.h added (mode: 100644) (index 0000000..fe6b003)
	1		#ifndef _TABLES_ATB_H
	2		#define _TABLES_ATB_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#ifndef __aligned
	10		# error "no byte alignment cpp macro defined for your compiler"
	11		#endif
	12		struct common_tbl_hdr
	13		{
	14		__le16 sz;
	15		u8 tbl_fmt_rev; /* change it when the parser is not backward
	16		compatible */
	17		u8 tbl_content_rev; /* change it only when the table needs to change
	18		but the firmware image can't be updated,
	19		while driver needs to carry the new table! */
	20		} __packed;
	21
	22		struct rom_hdr
	23		{
	24		struct common_tbl_hdr hdr;
	25
	26		u8 firmware_signature[4]; /* signature to distinguish between
	27		atombios and non-atombios, atombios
	28		should init it as "ATOM", don't
	29		change the position */
	30		u8 unused0[8];
	31
	32		__le16 bios_bootup_msg_of;
	33
	34		u8 unused1[12];
	35
	36		__le16 master_cmd_tbl_of; /* offset for sw to get all command
	37		table offsets, don't change the
	38		position */
	39		__le16 master_data_tbl_of; /* offset for sw to get all data table
	40		offsets, don't change the position */
	41		u8 unused2[2];
	42		} __packed;
	43
	44		#define DFPx_MAX 6
	45		#endif /* _TABLES_ATB_H */

File drivers/gpu/alga/amd/atombios/tables/cmd.h added (mode: 100644) (index 0000000..f8a0843)
	1		#ifndef _TABLES_CMD_H
	2		#define _TABLES_CMD_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/* structures used in cmd.mtb */
	10		struct cmd_tbls_list
	11		{
	12		__le16 asic_init;
	13		u16 unused0[3];
	14		__le16 enc_ctl;
	15		u16 unused1;
	16		__le16 crtc_mem_req;
	17		u16 unused2[5];
	18		__le16 pixel_clk_set;
	19		u16 unused3[20];
	20		__le16 crtc_scaler;
	21		__le16 crtc_blank;
	22		__le16 crtc;
	23		u16 unused4[4];
	24		__le16 crtc_overscan;
	25		u16 unused5;
	26		__le16 enc_crtc_src;
	27		u16 unused6;
	28		__le16 crtc_db_regs;
	29		u16 unused7[4];
	30		__le16 crtc_timing;
	31		u16 unused8[26];
	32		__le16 trans_ctl;
	33		u16 unused9;
	34		__le16 dp_aux;
	35		u16 unused10;
	36		} __packed;
	37
	38		struct master_cmd_tbl
	39		{
	40		u8 unused[4];
	41		struct cmd_tbls_list list;
	42		} __packed;
	43
	44		/*
	45		* common header for all command tables
	46		* every table pointed by master_cmd_tbl has this common header and the pointer
	47		* actually points to this header
	48		*/
	49		struct common_cmd_tbl_hdr
	50		{
	51		struct common_tbl_hdr hdr;
	52		u8 ws_dws;
	53		u8 ps_frame_sz; /* [8] updated by utility
	54		[7:0] bytes (multiple of dwords) */
	55		} __packed;
	56
	57		#define ATTRIB_PS_SZ_MASK 0x7f
	58		#define ATTRIB_UPDATED_BY_UTILITY (1 << 7) /* ps_sz byte */
	59		#endif /* _TABLES_CMD_H */

File drivers/gpu/alga/amd/atombios/tables/crtc.h added (mode: 100644) (index 0000000..b2200be)
	1		#ifndef _TABLES_CRTC_H
	2		#define _TABLES_CRTC_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		#define CRTC_OFF 0
	9		#define CRTC_ON 1
	10		struct crtc_params {
	11		u8 crtc;
	12		u8 state;
	13		u8 pad[2];
	14		} __packed;
	15		#endif
	16

File drivers/gpu/alga/amd/atombios/tables/crtc_blank.h added (mode: 100644) (index 0000000..ad7b071)
	1		#ifndef _TABLES_CRTC_BLANK_H
	2		#define _TABLES_CRTC_BLANK_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define CRTC_BLANK_OFF 0
	10		#define CRTC_BLANK_ON 1
	11		struct crtc_blank_params {
	12		u8 crtc;
	13		u8 state;
	14		__le16 black_color_rcr;
	15		__le16 black_color_gy;
	16		__le16 black_color_bcb;
	17		} __packed;
	18		#endif

File drivers/gpu/alga/amd/atombios/tables/crtc_db_regs.h added (mode: 100644) (index 0000000..58be06a)
	1		#ifndef _TABLES_CRTC_DB_REGS_H
	2		#define _TABLES_CRTC_DB_REGS_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		#define CRTC_UNLOCK 0
	9		#define CRTC_LOCK 1
	10		struct crtc_db_regs_params {
	11		u8 crtc;
	12		u8 state;
	13		u8 pad[2];
	14		} __packed;
	15		#endif

File drivers/gpu/alga/amd/atombios/tables/crtc_mem_req.h added (mode: 100644) (index 0000000..4cb48ae)
	1		#ifndef _TABLES_CRTC_MEM_REQ_H
	2		#define _TABLES_CRTC_MEM_REQ_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define CRTC_MEM_REQ_OFF 0
	10		#define CRTC_MEM_REQ_ON 1
	11		struct crtc_mem_req_params {
	12		u8 crtc;
	13		u8 state;
	14		u8 pad[2];
	15		} __packed;
	16		#endif
	17

File drivers/gpu/alga/amd/atombios/tables/crtc_overscan.h added (mode: 100644) (index 0000000..cc032e7)
	1		#ifndef _TABLES_CRTC_OVERSCAN_H
	2		#define _TABLES_CRTC_OVERSCAN_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		struct crtc_overscan_params {
	9		__le16 right;
	10		__le16 left;
	11		__le16 bottom;
	12		__le16 top;
	13		u8 crtc;
	14		u8 pad[3];
	15		} __packed;
	16		#endif

File drivers/gpu/alga/amd/atombios/tables/crtc_scaler.h added (mode: 100644) (index 0000000..bb31776)
	1		#ifndef _TABLES_CRTC_SCALER_H
	2		#define _TABLES_CRTC_SCALER_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define SCALER_DISABLE 0
	10		#define SCALER_CENTER 1
	11		#define SCALER_EXPANSION 2
	12		#define SCALER_MULTI_EX 3
	13		#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
	14		#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
	15		#define SCALER_ENA_2TAP_ALPHA_MODE 2
	16		#define SCALER_ENA_MULTITAP_MODE 3
	17
	18		struct crtc_scaler_params {
	19		u8 crtc;
	20		u8 mode;
	21		u8 tv;
	22		u8 pad;
	23		} __packed;
	24		#endif

File drivers/gpu/alga/amd/atombios/tables/crtc_timing.h added (mode: 100644) (index 0000000..6cf7d27)
	1		#ifndef _TABLES_CRTC_TIMING_H
	2		#define _TABLES_CRTC_TIMING_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		#define INFO_H_CUTOFF 0x01
	9		#define INFO_HSYNC_POLARITY 0x02/* 0: high/positive, 1: low/negative */
	10		#define INFO_VSYNC_POLARITY 0x04/* 0: high/positive, 1: low/negative */
	11		#define INFO_V_CUTOFF 0x08
	12		#define INFO_H_REPLICATIONBY2 0x10
	13		#define INFO_V_REPLICATIONBY2 0x20
	14		#define INFO_COMPOSITESYNC 0x40
	15		#define INFO_INTERLACE 0x80
	16		#define INFO_DBL_CLK_MODE 0x100
	17		#define INFO_RGB888_MODE 0x200
	18
	19		/* horizontal as pixels, vertical as lines */
	20		struct crtc_timing_params {
	21		__le16 h;
	22		__le16 h_bl;
	23		__le16 v;
	24		__le16 v_bl;
	25		__le16 h_so;
	26		__le16 h_spw;
	27		__le16 v_so;
	28		__le16 v_spw;
	29		__le16 info;
	30		u8 h_b;
	31		u8 v_b;
	32		u8 crtc;
	33		u8 pad[3];
	34		} __packed;
	35		#endif

File drivers/gpu/alga/amd/atombios/tables/data.h added (mode: 100644) (index 0000000..e67186d)
	1		#ifndef _TABLES_DATA_H
	2		#define _TABLES_DATA_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/* structures used in data.mtb */
	10		struct data_tbls_list
	11		{
	12		u16 unused0[4];
	13
	14		__le16 firmware_info;
	15
	16		u16 unused1[6];
	17
	18		__le16 firmware_vram_usage;
	19		__le16 gpio_pin_lut;
	20
	21		u16 unused2[9];
	22
	23		__le16 obj_hdr;
	24		__le16 iio;
	25
	26		u16 unused3[10];
	27		} __packed;
	28
	29		struct master_data_tbl
	30		{
	31		u8 unused[4];
	32		struct data_tbls_list list;
	33		} __packed;
	34		#endif /* _TABLES_DATA_H */

File drivers/gpu/alga/amd/atombios/tables/dp_aux.h added (mode: 100644) (index 0000000..f418e38)
	1		#ifndef _TABLES_DP_AUX_H
	2		#define _TABLES_DP_AUX_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		struct dp_aux_params {/* DCE4 */
	10		__le16 req;
	11		__le16 reply_data_of;
	12		u8 i2c_id;
	13		union {
	14		u8 reply_status;
	15		u8 delay;
	16		};
	17		u8 reply_data_sz;
	18		u8 hpd;
	19		} __packed;
	20		#endif

File drivers/gpu/alga/amd/atombios/tables/enc_crtc_src.h added (mode: 100644) (index 0000000..a76f441)
	1		#ifndef _TABLES_ENC_CRTC_SRC_H
	2		#define _TABLES_ENC_CRTC_SRC_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		#define ENC_0_ID 0x03
	9		#define ENC_1_ID 0x09
	10		#define ENC_2_ID 0x0a
	11		#define ENC_3_ID 0x0b
	12		#define ENC_4_ID 0x0c
	13		#define ENC_5_ID 0x0d
	14
	15		#define ENC_MODE_DP 0
	16
	17		struct enc_crtc_src_params {
	18		u8 crtc;
	19		u8 enc_id;
	20		u8 mode;
	21		u8 pad;
	22		} __packed;
	23		#endif

File drivers/gpu/alga/amd/atombios/tables/enc_ctl.h added (mode: 100644) (index 0000000..496b5b6)
	1		#ifndef _TABLES_ENC_CTL_H
	2		#define _TABLES_ENC_CTL_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define ENC_ACTION_DISABLE 0x00
	10		#define ENC_ACTION_ENA 0x01
	11		#define ENC_ACTION_DP_LINK_TRAINING_START 0x08
	12		#define ENC_ACTION_DP_LINK_TRAINING_PATTERN1 0x09
	13		#define ENC_ACTION_DP_LINK_TRAINING_PATTERN2 0x0a
	14		#define ENC_ACTION_DP_LINK_TRAINING_PATTERN3 0x13
	15		#define ENC_ACTION_DP_LINK_TRAINING_COMPLETE 0x0b
	16		#define ENC_ACTION_DP_VIDEO_OFF 0x0c
	17		#define ENC_ACTION_DP_VIDEO_ON 0x0d
	18		#define ENC_ACTION_QUERY_DP_LINK_TRAINING_STATUS 0x0e
	19		#define ENC_ACTION_SETUP 0x0f
	20		#define ENC_ACTION_SETUP_PANEL_MODE 0x10
	21
	22		#define ENC_CFG_SEL_MASK 0x70
	23		#define ENC_CFG_SEL_SHIFT 4
	24		#define ENC_CFG_LINK_RATE_1_62_GHZ 0x0
	25		#define ENC_CFG_LINK_RATE_2_7_GHZ 0x1
	26		#define ENC_CFG_LINK_CATE_5_4_GHZ 0x2
	27
	28		#define ENC_BPC_UNDEFINE 0x00
	29		#define ENC_6BITS_PER_COLOR 0x01
	30		#define ENC_8BITS_PER_COLOR 0x02
	31		#define ENC_10BITS_PER_COLOR 0x03
	32		#define ENC_12BITS_PER_COLOR 0x04
	33		#define ENC_16BITS_PER_COLOR 0x05
	34
	35		struct enc_ctl_params {
	36		u16 pixel_clk; /* in 10kHz unit */
	37		u8 cfg; /* [7] rsvd
	38		[6:4] encoder selection 0~5
	39		[3:1] rsvd
	40		[0] link rate
	41		0: 1.62GHz
	42		1: 2.7 GHz */
	43		u8 action;
	44		union {
	45		u8 mode; /* 0: DP encoder
	46		1: LVDS encoder
	47		2: DVI encoder
	48		3: HDMI encoder
	49		4: SDVO encoder
	50		5: DP audio */
	51		u8 panel_mode; /* valid when action
	52		= ENC_ACTION_SETUP_PANEL_MODE
	53		0: external DP
	54		1: internal DP2
	55		0x11: internal DP1 for NutMeg/Travis DP
	56		translator */
	57		};
	58		u8 lanes_n; /* how many lanes to enable */
	59		u8 bpc; /* bit per color component, valid for DP mode
	60		when action = ENCODER_ACTION_SETUP */
	61		u8 rsvd;
	62		} __packed;
	63		#endif

File drivers/gpu/alga/amd/atombios/tables/firmware_info.h added (mode: 100644) (index 0000000..a243c3d)
	1		#ifndef _TABLES_FIRMWARE_INFO_H
	2		#define _TABLES_FIRMWARE_INFO_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/*
	10		* common subset of all firmware_info revisions used of asic_init, as far as our
	11		* specs are uptodate
	12		*/
	13		struct firmware_info_subset {
	14		struct common_tbl_hdr hdr;
	15		__le32 firmware_rev;
	16		__le32 default_eng_clk; /* in 10kHz unit */
	17		__le32 default_mem_clk; /* in 10kHz unit */
	18		} __packed;
	19
	20		struct firmware_info_v2_1 {
	21		struct firmware_info_subset subset;
	22		__le32 rsvd0[2];
	23		__le32 unused0[4];
	24		__le32 default_disp_clk_freq; /* in 10 kHz unit */
	25		u8 rsvd1;
	26		u8 unused1;
	27		__le16 unused2[3];
	28		__le32 rsvd2;
	29		__le32 unused3;
	30		__le16 unused4[13];
	31		__le16 uniphy_dp_mode_ext_clk_freq; /* in 10kHz unit, if 0; dp uses
	32		internal pll as input clock,
	33		else dp uses an external
	34		clock */
	35		u8 unused5;
	36		u8 rsvd3[3];
	37		} __packed;
	38		#endif /* _TABLES_FIRMWARE_INFO_H */

File drivers/gpu/alga/amd/atombios/tables/firmware_vram_usage.h added (mode: 100644) (index 0000000..f54daca)
	1		#ifndef _TABLES_FIRMWARE_VRAM_USAGE
	2		#define _TABLES_FIRMWARE_VRAM_USAGE
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/*
	10		* note1: from rv770, the memory is more than 32bits addressable, so we will
	11		* change from tbl_fmt_rev = 1 tbl_content_rev = 4, the structure remains
	12		* exactly same as 1.1 and 1.2 (1.3 is never in use), but
	13		* start_addr (in offset to start of memory address) is kB aligned
	14		* instead of byte aligned.
	15		*
	16		* note2: actually it's in kernel RAM and not VRAM. VRAM comes from the fact
	17		* it is actually in VRAM when in POST real mode.
	18		*/
	19		struct firmware_vram_reserve_info
	20		{
	21		__le32 start_addr; /* byte aligned */
	22		__le16 sz; /* in kB */
	23		u16 rsvd;
	24		} __packed;
	25
	26		struct firmware_vram_usage
	27		{
	28		struct common_tbl_hdr hdr;
	29		struct firmware_vram_reserve_info info;
	30		} __packed;
	31		#endif /* _TABLES_FIRMWARE_VRAM_USAGE */

File drivers/gpu/alga/amd/atombios/tables/gpio_pin_lut.h added (mode: 100644) (index 0000000..6e8fb79)
	1		#ifndef _GPIO_PIN_LUT_H
	2		#define _GPIO_PIN_LUT_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		struct gpio_pin_assignment
	9		{
	10		__le16 reg_idx;
	11		u8 bit_shift;
	12		u8 id;
	13		} __packed;
	14
	15		struct gpio_pin_lut
	16		{
	17		struct common_tbl_hdr hdr;
	18		struct gpio_pin_assignment pin;
	19		} __packed;
	20		#endif /* GPIO_PIN_LUT_H */

File drivers/gpu/alga/amd/atombios/tables/i2c.h added (mode: 100644) (index 0000000..1b10f25)
	1		#ifndef _TABLES_I2C_H
	2		#define _TABLES_I2C_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		struct gpio_i2c_assignment
	10		{
	11		__le16 clk_mask_reg_idx;
	12		__le16 clk_en_reg_idx;
	13		__le16 clk_y_reg_idx;
	14		__le16 clk_a_reg_idx;
	15		__le16 data_mask_reg_idx;
	16		__le16 data_en_reg_idx;
	17		__le16 data_y_reg_idx;
	18		__le16 data_a_reg_idx;
	19		u8 i2c_id;
	20		u8 clk_mask_shift;
	21		u8 clk_en_shift;
	22		u8 clk_y_shift;
	23		u8 clk_a_shift;
	24		u8 data_mask_shift;
	25		u8 data_en_shift;
	26		u8 data_y_shift;
	27		u8 data_a_shift;
	28		u8 rsvd1;
	29		u8 rsvd2;
	30		} __packed;
	31
	32		/* struct atb_gpio_i2c_assignment.i2c_id bits */
	33		#define I2C_HW_CAPABLE 0xf0
	34		#define I2C_HW_ENG_ID_MASK 0x70
	35		#define I2C_HW_ENG_ID_SHIFT 4
	36		#define I2C_LINE_MUX_MASK 0x0f
	37
	38		#define I2C_MM_ENG_ID 0x02
	39
	40		struct gpio_i2c_info
	41		{
	42		struct common_tbl_hdr hdr;
	43		struct gpio_i2c_assignment info[];
	44		} __packed;
	45		#endif /* _TABLES_I2C_H */

File drivers/gpu/alga/amd/atombios/tables/iio.h added (mode: 100644) (index 0000000..0847065)
	1		#ifndef _TABLES_IIO_H
	2		#define _TABLES_IIO_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define IIO_NOP 0
	10		#define IIO_START 1
	11		#define IIO_READ 2
	12		#define IIO_WRITE 3
	13		#define IIO_CLR 4
	14		#define IIO_SET 5
	15		#define IIO_MOVE_IDX 6
	16		#define IIO_MOVE_ATTR 7
	17		#define IIO_MOVE_DATA 8
	18		#define IIO_END 9
	19
	20		struct iio_nop
	21		{
	22		u8 opcode;
	23		} __packed;
	24
	25		struct iio_start
	26		{
	27		u8 opcode;
	28		u8 prog_idx;
	29		} __packed;
	30
	31		struct iio_readwrite
	32		{
	33		u8 opcode;
	34		__le16 reg_u32_idx; /* index of the u32 dword */
	35		} __packed;
	36
	37		struct iio_clr
	38		{
	39		u8 opcode;
	40		u8 bits; /* number of bits to clear */
	41		u8 pos; /* position at which start those bits to clear */
	42		} __packed;
	43
	44		struct iio_set
	45		{
	46		u8 opcode;
	47		u8 bits; /* number of bits to set */
	48		u8 pos; /* position at which starts those bits to set */
	49		} __packed;
	50
	51		/* same for: iio_move_idx, iio_move_data and iio_move_attr */
	52		struct iio_move_bits
	53		{
	54		u8 opcode;
	55		u8 sz; /* size in bits of the index */
	56		u8 src_pos; /* position of bits in the source 32 bits dword */
	57		u8 dst_pos; /* position of bits in the destination 32 bits dword */
	58		} __packed;
	59
	60		struct iio_end
	61		{
	62		u8 opcode;
	63		u8 unknown[2];
	64		} __packed;
	65		#endif /* _TABLES_IIO_H */

File drivers/gpu/alga/amd/atombios/tables/obj_hdr.h added (mode: 100644) (index 0000000..05673be)
	1		#ifndef _OBJ_HDR_H
	2		#define _OBJ_HDR_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		/* path->conn/gpu/grph_id, obj->id*/
	10		#define ID_SUB_ID_MASK 0x00ff
	11		#define ID_N_MASK 0x0700
	12		#define ID_RSVD1_MASK 0x0800
	13		#define ID_TYPE_MASK 0x7000
	14		#define ID_RSVD2_MASK 0x8000
	15
	16		#define ID_SUB_ID_SHIFT 0x00
	17		#define ID_N_SHIFT 0x08
	18		#define ID_TYPE_SHIFT 0x0c
	19
	20		/* obj_hdr->disp_dev_support and path->disp_dev */
	21		#define DISP_DEV_CRT1_SUPPORT BIT(0)
	22		#define DISP_DEV_LCD1_SUPPORT BIT(1)
	23		#define DISP_DEV_TV1_SUPPORT BIT(2)
	24		#define DISP_DEV_DFP0_SUPPORT BIT(3)
	25		#define DISP_DEV_CRT2_SUPPORT BIT(4)
	26		#define DISP_DEV_LCD2_SUPPORT BIT(5)
	27		#define DISP_DEV_DFP5_SUPPORT BIT(6)
	28		#define DISP_DEV_DFP1_SUPPORT BIT(7)
	29		#define DISP_DEV_CV_SUPPORT BIT(8)
	30		#define DISP_DEV_DFP2_SUPPORT BIT(9)
	31		#define DISP_DEV_DFP3_SUPPORT BIT(10)
	32		#define DISP_DEV_DFP4_SUPPORT BIT(11)
	33
	34		static u32 vals_dfp_support[DFPx_MAX] __attribute__ ((unused)) = {
	35		DISP_DEV_DFP0_SUPPORT,
	36		DISP_DEV_DFP1_SUPPORT,
	37		DISP_DEV_DFP2_SUPPORT,
	38		DISP_DEV_DFP3_SUPPORT,
	39		DISP_DEV_DFP4_SUPPORT,
	40		DISP_DEV_DFP5_SUPPORT
	41		};
	42
	43		struct obj_hdr
	44		{
	45		struct common_tbl_hdr hdr;
	46		__le16 disp_dev_support; /* list all the display devices supported */
	47		__le16 conn_tbl_of;
	48		__le16 router_tbl_of;
	49		__le16 encoder_tbl_of;
	50		/* only available when protection block is independent */
	51		__le16 protection_tbl_of;
	52		__le16 path_tbl_of;
	53		} __packed;
	54
	55		struct path
	56		{
	57		__le16 disp_dev; /* the display device this path defines */
	58		__le16 sz; /* the size of this struct path */
	59		__le16 conn_id; /* connector id, path is to this connector */
	60		__le16 gpu_id; /* gpu id, path is from this gpu */
	61		__le16 grph_ids; /* from the first grph obj, connected to
	62		the gpu, to the last grph obj, connected
	63		to the connector */
	64		} __packed;
	65
	66		struct path_tbl
	67		{
	68		u8 n;
	69		u8 ver;
	70		u8 padding[2];
	71		struct path paths;
	72		} __packed;
	73
	74		/* graphics object type definition */
	75		#define GRPH_TYPE_NONE 0x0
	76		#define GRPH_TYPE_GPU 0x1
	77		#define GRPH_TYPE_ENCODER 0x2
	78		#define GRPH_TYPE_CONN 0x3
	79		#define GRPH_TYPE_ROUTER 0x4
	80		/* deleted */
	81		#define GRPH_TYPE_DISP_PATH 0x6
	82		#define GRPH_TYPE_GENERIC 0x7
	83
	84		/* connector type object sub id definitions */
	85		#define CONN_SUB_ID_NONE 0x00
	86		#define CONN_SUB_ID_SINGLE_LINK_DVI_I 0x01
	87		#define CONN_SUB_ID_DUAL_LINK_DVI_I 0x02
	88		#define CONN_SUB_ID_SINGLE_LINK_DVI_D 0x03
	89		#define CONN_SUB_ID_DUAL_LINK_DVI_D 0x04
	90		#define CONN_SUB_ID_VGA 0x05
	91		#define CONN_SUB_ID_COMPOSITE 0x06
	92		#define CONN_SUB_ID_SVIDEO 0x07
	93		#define CONN_SUB_ID_YPbPr 0x08
	94		#define CONN_SUB_ID_D_CONN 0x09
	95		#define CONN_SUB_ID_9PIN_DIN 0x0a /* supports both cv & tv */
	96		#define CONN_SUB_ID_SCART 0x0b
	97		#define CONN_SUB_ID_HDMI_TYPE_A 0x0c
	98		#define CONN_SUB_ID_HDMI_TYPE_B 0x0d
	99		#define CONN_SUB_ID_LVDS 0x0e
	100		#define CONN_SUB_ID_7PIN_DIN 0x0f
	101		#define CONN_SUB_ID_PCIE_CONN 0x10
	102		#define CONN_SUB_ID_CROSSFIRE 0x11
	103		#define CONN_SUB_ID_HARDCODE_DVI 0x12
	104		#define CONN_SUB_ID_DP 0x13
	105		#define CONN_SUB_ID_EDP 0x14
	106		#define CONN_SUB_ID_MXM 0x15
	107		#define CONN_SUB_ID_LVDS_EDP 0x16
	108
	109		/* encoder object sub id definitions */
	110		#define ENCODER_SUB_ID_NONE 0x00
	111
	112		/* radeon class display hardware */
	113		#define ENCODER_SUB_ID_INTERNAL_LVDS 0x01
	114		#define ENCODER_SUB_ID_INTERNAL_TMDS1 0x02
	115		#define ENCODER_SUB_ID_INTERNAL_TMDS2 0x03
	116		#define ENCODER_SUB_ID_INTERNAL_DAC1 0x04
	117		#define ENCODER_SUB_ID_INTERNAL_DAC2 0x05 /* tv/cv dac */
	118		#define ENCODER_SUB_ID_INTERNAL_SDVOA 0x06
	119		#define ENCODER_SUB_ID_INTERNAL_SDVOB 0x07
	120
	121		/* external third party encoders */
	122		#define ENCODER_SUB_ID_SI170B 0x08
	123		#define ENCODER_SUB_ID_CH7303 0x09
	124		#define ENCODER_SUB_ID_CH7301 0x0a
	125		#define ENCODER_SUB_ID_INTERNAL_DVO1 0x0b /* from radeon hdw */
	126		#define ENCODER_SUB_ID_EXTERNAL_SDVOA 0x0c
	127		#define ENCODER_SUB_ID_EXTERNAL_SDVOB 0x0d
	128		#define ENCODER_SUB_ID_TITFP513 0x0e
	129		#define ENCODER_SUB_ID_INTERNAL_LVTM1 0x0f /* not used for radeon */
	130		#define ENCODER_SUB_ID_VT1623 0x10
	131		#define ENCODER_SUB_ID_HDMI_SI1930 0x11
	132		#define ENCODER_SUB_ID_HDMI_INTERNAL 0x12
	133		#define ENCODER_SUB_ID_ALMOND 0x22
	134		#define ENCODER_SUB_ID_TRAVIS 0x23
	135		#define ENCODER_SUB_ID_NUTMEG 0x22
	136		/* kaleidoscope (kldscp) class display hardware (internal) */
	137		#define ENCODER_SUB_ID_INTERNAL_KLDSCP_TMDS1 0x13
	138		#define ENCODER_SUB_ID_INTERNAL_KLDSCP_DVO1 0x14
	139		#define ENCODER_SUB_ID_INTERNAL_KLDSCP_DAC1 0x15
	140		#define ENCODER_SUB_ID_INTERNAL_KLDSCP_DAC2 0x16 /* cv/tv and crt */
	141		#define ENCODER_SUB_ID_SI178 0X17 /* external tmds */
	142		#define ENCODER_SUB_ID_MVPU_FPGA 0x18 /* mvpu fpga chip */
	143		#define ENCODER_SUB_ID_INTERNAL_DDI 0x19
	144		#define ENCODER_SUB_ID_VT1625 0x1a
	145		#define ENCODER_SUB_ID_HDMI_SI1932 0x1b
	146		#define ENCODER_SUB_ID_DP_AN9801 0x1c
	147		#define ENCODER_SUB_ID_DP_DP501 0x1d
	148		#define ENCODER_SUB_ID_INTERNAL_UNIPHY0 0x1e
	149		#define ENCODER_SUB_ID_INTERNAL_KLDSCP_LVTMA 0x1f
	150		#define ENCODER_SUB_ID_INTERNAL_UNIPHY1 0x20
	151		#define ENCODER_SUB_ID_INTERNAL_UNIPHY2 0x21
	152
	153		#define ENCODER_SUB_ID_GENERAL_EXTERNAL_DVO 0xff
	154
	155		/* each object has this structure */
	156		struct obj
	157		{
	158		__le16 id;
	159		__le16 src_dst_tbl_of;
	160		__le16 rec_of; /* this pointing to a bunch of records defined
	161		later on */
	162		__le16 rsvd;
	163		} __packed;
	164
	165		/*
	166		* above 4 object table offset pointing to a bunch of objects all have this
	167		* structure
	168		*/
	169		struct obj_tbl
	170		{
	171		u8 n;
	172		u8 padding[3];
	173		struct obj objs;
	174		} __packed;
	175
	176		/* some inline helpers */
	177		static inline u8 id_decode_sub_id(u16 id)
	178		{
	179		return (id & ID_SUB_ID_MASK) >> ID_SUB_ID_SHIFT;
	180		}
	181
	182		static inline u8 id_decode_n(u16 id)
	183		{
	184		return (id & ID_N_MASK) >> ID_N_SHIFT;
	185		}
	186
	187		static inline u8 id_decode_type(u16 id)
	188		{
	189		return (id & ID_TYPE_MASK) >> ID_TYPE_SHIFT;
	190		}
	191
	192		static inline s8 trans(u16 id)
	193		{
	194		switch (id_decode_sub_id(id)) {
	195		case ENCODER_SUB_ID_INTERNAL_UNIPHY0:
	196		return 0;
	197		case ENCODER_SUB_ID_INTERNAL_UNIPHY1:
	198		return 1;
	199		case ENCODER_SUB_ID_INTERNAL_UNIPHY2:
	200		return 2;
	201		}
	202		unreachable();
	203		}
	204
	205		static inline u8 link_type(u16 id)
	206		{
	207		if (id_decode_n(id) == 2)
	208		return 1;/* transmitter secondary link B/D/F */
	209		else
	210		return 0;/* transmitter primary link A/C/E */
	211		}
	212
	213		static inline u8 to_link(unsigned i)
	214		{
	215		return i & 1;
	216		}
	217
	218		static inline u8 to_trans(unsigned i)
	219		{
	220		return (i & ~1) / 2;
	221		}
	222
	223		/* XXX: the following is not used yet */
	224
	225		struct atb_disp_ext_obj_path
	226		{
	227		u16 dev_tag; /* supported device */
	228		u16 sz; /* the sz of atb_disp_object_path */
	229		u16 conn_obj_id; /* connector object id */
	230		u16 gpu_obj_id; /* gpu id */
	231		u16 graphic_obj_ids[2]; /* graphic_obj_ids[0]: gpu internal encoder
	232		graphic_obj_ids[1]: external encoder */
	233		} __packed;
	234
	235
	236
	237		/* src_dst_tbl_offset pointing to this structure */
	238		struct atb_src_dst_tbl_for_one_obj
	239		{
	240		u8 num_of_src;
	241		u16 src_obj_id[1];
	242		u8 num_of_dst;
	243		u16 dst_obj_id[1];
	244		} __packed;
	245		#endif /* _OBJ_HDR_H */

File drivers/gpu/alga/amd/atombios/tables/pixel_clock_set.h added (mode: 100644) (index 0000000..b20e62d)
	1		#ifndef _TABLES_PIXEL_CLK_SET_H
	2		#define _TABLES_PIXEL_CLK_SET_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define CRTC0 0
	10		#define CRTC1 1
	11		#define CRTC2 2
	12		#define CRTC3 3
	13		#define CRTC4 4
	14		#define CRTC5 5
	15		#define CRTC_INVALID 0xff
	16
	17		#define PPLL1 0
	18		#define PPLL2 1
	19		#define DCPLL 2
	20		#define PPLL0 2
	21		#define EXT_PLL1 8
	22		#define EXT_PLL2 9
	23		#define EXT_CLK 10
	24		#define PPLL_INVALID 0xff
	25
	26		struct pixel_clk_set_params_v1_5 {
	27		u8 crtc; /* CRTC0~5, indicate the CRTC controller to
	28		drive the pixel clock. Not used for DCPLL
	29		case. */
	30		union {
	31		u8 rsvd0;
	32		u8 frac_fb_div; /* not supposed to be around */
	33		};
	34		__le16 pixel_clk; /* Target the pixel clock to drive the CRTC
	35		timing. 0 means disable PPLL/DCPLL. 10kHz unit. */
	36		__le16 fb_div; /* feedback divider integer part */
	37		u8 post_div; /* post divider */
	38		u8 ref_div; /* Reference divider */
	39		u8 ppll; /* PPLL1/PPLL2/DCPLL */
	40		u8 trans_id; /* transmitter object id */
	41		u8 enc_mode; /* encoder mode */
	42		u8 misc_info; /* [0] Force program PPLL
	43		[1] when VGA timing is used
	44		[3:2] HDMI panel bit depth
	45		0: 24bpp
	46		1: 30bpp
	47		2: 32bpp
	48		[4] RefClock source for PPLL
	49		0: XTLAIN (default mode)
	50		1: other external clock source, which
	51		is pre-defined by VBIOS depend on
	52		the feature required.
	53		[7:5] reserved */
	54		__le32 fb_div_dec_frac; /* 20bits feedback divider decimal fraction
	55		part, range from 1~999999 (0.000001 to
	56		0.999999) */
	57
	58		} __packed;
	59		#endif

File drivers/gpu/alga/amd/atombios/tables/records.h added (mode: 100644) (index 0000000..b916a5b)
	1		#ifndef _RECORDS_H
	2		#define _RECORDS_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8		/* struct rec_hdr->type */
	9		#define REC_TYPE_I2C 1
	10		#define REC_TYPE_HPD_INT 2
	11		#define REC_TYPE_OUTPUT_PROTECTION 3
	12		#define REC_TYPE_CONN_DEV_TAG 4
	13		#define REC_TYPE_CONN_DVI_EXT_INPUT 5 /* use GPIO_CTL */
	14		#define REC_TYPE_ENCODER_FPGA_CTL 6 /* use GPIO_CTL */
	15		#define REC_TYPE_CONN_CVTV_SHARE_DIN 7
	16		#define REC_TYPE_JTAG 8 /* use GPIO_CTL */
	17		#define REC_TYPE_OBJ_GPIO_CTL 9
	18		#define REC_TYPE_ENCODER_DVO_CF 10
	19		#define REC_TYPE_CONN_CF 11
	20		#define REC_TYPE_CONN_HARDCODE_DTD 12
	21		#define REC_TYPE_CONN_PCIE_SUBCONN 13
	22		#define REC_TYPE_ROUTER_DDC_PATH_SELECT 14
	23		#define REC_TYPE_ROUTER_DATA_CLK_PATH_SELECT 15
	24		#define REC_TYPE_CONN_HPDPIN_LUT 16 /* for connectors
	25		unknown in object
	26		table */
	27		#define REC_TYPE_CONN_AUXDDC_LUT 17 /* see above */
	28		#define REC_TYPE_OBJ_LINK 18 /* this object is linked
	29		to another object
	30		described by the
	31		record */
	32		#define REC_TYPE_CONN_REMOTE_CAPS 19
	33		#define REC_TYPE_ENCODER_CAPS 20
	34		#define REC_TYPE_MAX REC_TYPE_ENCODER_CAPS
	35
	36		struct rec_hdr
	37		{
	38		u8 type;
	39		u8 sz; /* whole record in bytes */
	40		} __packed;
	41
	42		/* struct encoder_caps->flgs */
	43		#define ENCODER_CAPS_DP_HBR2 0x0001
	44
	45		struct encoder_caps
	46		{
	47		struct rec_hdr hdr;
	48		__le16 flgs;
	49		} __packed;
	50
	51		#define I2C_ID_HW_CAPABLE 0x01
	52		#define I2C_ID_ENG_ID_MASK 0x70
	53		#define I2C_ID_ENG_ID_SHIFT 4
	54		#define I2C_ID_LINE_MUX_MASK 0x0f
	55		#define I2C_ID_LINE_MUX_SHIFT 0
	56		struct i2c_info
	57		{
	58		struct rec_hdr hdr;
	59		u8 id;
	60		u8 addr; /* slave addr which is 0 for connector ddc */
	61		} __packed;
	62
	63		struct hpd_int
	64		{
	65		struct rec_hdr hdr;
	66		u8 gpio_id;
	67		u8 plugged_pinstate;
	68		} __packed;
	69		#endif /* _RECORDS_H */

File drivers/gpu/alga/amd/atombios/tables/trans_ctl.h added (mode: 100644) (index 0000000..4fd14e1)
	1		#ifndef _TABLES_TRANS_CTL_H
	2		#define _TABLES_TRANS_CTL_H
	3		/*
	4		* Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
	5		* This fork is protected by the GNU affero GPLv3 with additionnal rights
	6		* Original code from Advanced Micro Devices, Inc.
	7		*/
	8
	9		#define TRANS_ACTION_DISABLE 0
	10		#define TRANS_ACTION_ENA 1
	11		#define TRANS_ACTION_LCD_BLOFF 2
	12		#define TRANS_ACTION_LCD_BLON 3
	13		#define TRANS_ACTION_BL_BRIGHTNESS_CTL 4
	14		#define TRANS_ACTION_LCD_SELFTEST_START 5
	15		#define TRANS_ACTION_LCD_SELFTEST_STOP 6
	16		#define TRANS_ACTION_INIT 7
	17		#define TRANS_ACTION_DISABLE_OUTPUT 8
	18		#define TRANS_ACTION_ENA_OUTPUT 9
	19		#define TRANS_ACTION_SETUP 10
	20		#define TRANS_ACTION_SETUP_VSEMPH 11
	21		#define TRANS_ACTION_PWR_ON 12
	22		#define TRANS_ACTION_PWR_OFF 13
	23
	24		#define TRANS_CFG_SEL_MASK 0xc0
	25		#define TRANS_CFG_SEL_SHIFT 6
	26		#define TRANS_CFG_CLK_SRC_MASK 0x20
	27		#define TRANS_CFG_CLK_SRC_SHIFT 4
	28		#define TRANS_CFG_ENC_SEL_BIT 3
	29		#define TRANS_CFG_LINK_SEL_BIT 2
	30		#define TRANS_CFG_COHERENT_MODE_BIT 1
	31		#define TRANS_CFG_DUAL_LINK_CON_BIT 0
	32
	33		struct vs_pre_emph {
	34		u8 lane_sel;
	35		u8 lane_set;
	36		} __packed;
	37
	38		struct trans_ctl_params {
	39		union {
	40		__le16 pixel_clk; /* in 10kHz unit */
	41		__le16 init_info; /* when init uniphy, lower 8bit is used
	42		for connector type defined as an
	43		object id */
	44		struct vs_pre_emph mode;/* dp voltage swing/pre-emphasis mode */
	45		} __packed;
	46		u8 cfg; /* [7:6] transmitter selection
	47		0: transmitter 1 (uniphy AB)
	48		1: transmitter 2 (uniphy CD)
	49		2: transmitter 3 (uniphy EF)
	50		[5:4] clock source reference
	51		0: pll1
	52		1: pll2
	53		2: external clock
	54		[3] encoder selection
	55		0: data/clock for encoders A/C/E
	56		1: data/clock for encoders B/D/F
	57		[2] link selection
	58		0: uniphy link A/C/E (primary) when
	59		dual link connector bit is 0
	60		or
	61		master link is A/C/E when
	62		dual link connector bit is 1
	63		1: uniphy link B/D/F (secondary)
	64		when dual link connector bit is
	65		0
	66		or
	67		master link is B/D/F when
	68		dual link connector mit is 1
	69		[1]
	70		1:coherent mode (DVI/HDMI)
	71		[0]
	72		1:dual link dvi connector */
	73
	74
	75		u8 action; /* define as TRANS_ACTION_XXX */
	76		u8 lanes_n;
	77		u8 rsvd[3];
	78		} __packed;
	79		#endif

File drivers/gpu/alga/amd/dce6/Kconfig added (mode: 100644) (index 0000000..087fed3)
	1		config ALGA_AMD_DCE6
	2		tristate "dce6"
	3		depends on ALGA && ALGA_AMD
	4		select ALGA_AMD_ATOMBIOS
	5		select I2C
	6		help
	7		DCE6, Diplay Control Engine v6 found on AMD GPUs.
	8		If M is selected, the module will be called dce6.

File drivers/gpu/alga/amd/dce6/Makefile added (mode: 100644) (index 0000000..59c84de)
	1		dce6-y := mod.o hpd.o sink.o i2c.o dpcd.o dp_link_train.o crtc.o irq.o
	2		obj-$(CONFIG_ALGA_AMD_DCE6)+= dce6.o

File drivers/gpu/alga/amd/dce6/crtc.c added (mode: 100644) (index 0000000..05302e1)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/device.h>
	8		#include <linux/i2c.h>
	9		#include <linux/delay.h>
	10		#include <linux/wait.h>
	11
	12		#include <alga/pixel_fmts.h>
	13		#include <alga/timing.h>
	14		#include <alga/amd/dce6/dce6.h>
	15		#include <alga/amd/dce6/dce6_dev.h>
	16		#include <alga/amd/atombios/atb.h>
	17		#include <alga/amd/atombios/dce.h>
	18
	19		#include "dce6.h"
	20		#include "regs.h"
	21
	22		#define WR32(val, of) dce->ddev.wr32(dce->ddev.dev, (val), (of))
	23		#define RR32(of) dce->ddev.rr32(dce->ddev.dev, (of))
	24		int crtc_fb(struct dce6 *dce, unsigned i, struct db_fb *db_fb)
	25		{
	26		u32 fb_fmt;
	27		u32 fb_swap;
	28		u32 viewport_h;
	29		u32 viewport_v;
	30		u32 tmp;
	31
	32		fb_swap = SET(GRPH_ENDIAN_SWAP, GRPH_ENDIAN_NONE);
	33		switch (db_fb->pixel_fmt) {
	34		case ALGA_ARGB6666:
	35		case ALGA_ARGB8888:
	36		fb_fmt = (SET(GRPH_DEPTH, GRPH_DEPTH_32BPP)
	37		| SET(GRPH_FMT, GRPH_FMT_ARGB8888));
	38		#ifdef __BIG_ENDIAN
	39		fb_swap = SET(GRPH_ENDIAN_SWAP, GRPH_ENDIAN_8IN32);
	40		#endif
	41		break;
	42		case ALGA_ARGB2101010:
	43		fb_fmt = (SET(GRPH_DEPTH, GRPH_DEPTH_32BPP)
	44		| SET(GRPH_FMT, GRPH_FMT_ARGB8888));
	45		#ifdef __BIG_ENDIAN
	46		fb_swap = SET(GRPH_ENDIAN_SWAP, GRPH_ENDIAN_8IN32);
	47		#endif
	48		break;
	49		default:
	50		dev_err(dce->ddev.dev, "unsupported pixel format %d\n",
	51		db_fb->pixel_fmt);
	52		return -DCE6_ERR;
	53		}
	54
	55		WR32(upper_32_bits(db_fb->primary),
	56		regs_grph_primary_surf_addr_high[i]);
	57		WR32(upper_32_bits(db_fb->secondary),
	58		regs_grph_secondary_surf_addr_high[i]);
	59		WR32((u32)(db_fb->primary) & GRPH_SURF_ADDR_MASK,
	60		regs_grph_primary_surf_addr[i]);
	61		WR32((u32)(db_fb->secondary) & GRPH_SURF_ADDR_MASK,
	62		regs_grph_secondary_surf_addr[i]);
	63
	64		/*
	65		* store the surface gpu addresses for page flipping without reading
	66		* the content of the regs
	67		*/
	68		dce->dps[i].pf.crtc_surfs.primary = db_fb->primary;
	69		dce->dps[i].pf.crtc_surfs.secondary = db_fb->secondary;
	70
	71		WR32(fb_fmt, regs_grph_ctl[i]);
	72		WR32(fb_swap, regs_grph_swap_ctl[i]);
	73		WR32(0, regs_grph_surf_of_x[i]);
	74		WR32(0, regs_grph_surf_of_y[i]);
	75		/* pixels */
	76		WR32(0, regs_grph_x_start[i]);
	77		WR32(0, regs_grph_y_start[i]);
	78		WR32(db_fb->timing.h, regs_grph_x_end[i]);
	79		WR32(db_fb->timing.v, regs_grph_y_end[i]);
	80		WR32(db_fb->pitch, regs_grph_pitch[i]);
	81		WR32(1, regs_grph_ena[i]);
	82		WR32(db_fb->timing.v, regs_desktop_height[i]);
	83		WR32((0 << 16) | 0, regs_viewport_start[i]);
	84		viewport_h = db_fb->timing.h;
	85		viewport_v = (db_fb->timing.v + 1) & ~1;
	86		WR32((viewport_h << 16) | viewport_v, regs_viewport_sz[i]);
	87
	88		/* XXX: obsolete pageflip setup */
	89		/* make sure flip is at vb rather than hb */
	90		tmp = dce->ddev.rr32(dce->ddev.dev, regs_grph_flip_ctl[i]);
	91		tmp &= ~GRPH_SURF_UPDATE_H_RETRACE_ENA;
	92		WR32(tmp, regs_grph_flip_ctl[i]);
	93
	94		/* set pageflip to happen anywhere in vblank interval */
	95		WR32(0, regs_master_update_mode[i]);
	96		return 0;
	97		}
	98
	99		void crtc_lut(struct dce6 *dce, unsigned i)
	100		{
	101		unsigned j;
	102		u16 v;
	103
	104		WR32(0, regs_lut_ctl[i]);
	105
	106		WR32(0, regs_lut_black_of_blue[i]);
	107		WR32(0, regs_lut_black_of_green[i]);
	108		WR32(0, regs_lut_black_of_red[i]);
	109
	110		WR32(0xffff, regs_lut_white_of_blue[i]);
	111		WR32(0xffff, regs_lut_white_of_green[i]);
	112		WR32(0xffff, regs_lut_white_of_red[i]);
	113
	114		WR32(0, regs_lut_rw_mode[i]);
	115		WR32(0x00000007, regs_lut_write_ena_mask[i]);
	116
	117		WR32(0, regs_lut_rw_idx[i]);
	118
	119		/*
	120		* XXX: gamma hardcoded, 256 linear values of 10 bits, range 0x400
	121		* (1024)
	122		*/
	123		for (v = 0, j = 0; j < 256; ++j, v+=4)
	124		WR32((v << 20) | (v << 10) | (v << 0), regs_lut_30_color[i]);
	125		}
	126
	127		void crtcs_intr_reset(struct dce6 *dce)
	128		{
	129		unsigned i;
	130
	131		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	132		WR32(0, regs_crtc_int_mask[i]);
	133
	134		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	135		WR32(0, regs_crtc_grph_int_ctl[i]);
	136
	137		/* XXX: should know if we have a DAC before */
	138		WR32(0, DACA_AUTODETECT_INT_CTL);
	139		WR32(0, DACB_AUTODETECT_INT_CTL);
	140		}
	141
	142		int dce6_mem_req(struct dce6 *dce, bool ena)
	143		{
	144		unsigned i;
	145		int r;
	146
	147		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	148		r = atb_crtc_mem_req(dce->ddev.atb, i, ena);
	149		if (r != 0)
	150		return -DCE6_ERR;
	151		}
	152		return 0;
	153		}
	154		EXPORT_SYMBOL_GPL(dce6_mem_req);
	155
	156		static void page_flip(struct dce6 *dce, unsigned i)
	157		{
	158		u32 tmp;
	159		u64 swap;
	160		struct crtc_surfs *css;
	161		unsigned j;
	162
	163		css = &dce->dps[i].pf.crtc_surfs;
	164
	165		swap = css->secondary;
	166		css->secondary = css->primary;
	167		css->primary = swap;
	168
	169		tmp = RR32(regs_grph_update[i]);
	170		tmp |= GRPH_UPDATE_LOCK;
	171		WR32(tmp, regs_grph_update[i]);
	172
	173		WR32(upper_32_bits(css->primary), regs_grph_primary_surf_addr_high[i]);
	174		WR32(upper_32_bits(css->secondary),
	175		regs_grph_secondary_surf_addr_high[i]);
	176		WR32((u32)(css->primary) & GRPH_SURF_ADDR_MASK,
	177		regs_grph_primary_surf_addr[i]);
	178		WR32((u32)(css->secondary) & GRPH_SURF_ADDR_MASK,
	179		regs_grph_secondary_surf_addr[i]);
	180
	181		#define TIMEOUT 100000
	182		for (j = 0; j < TIMEOUT; ++j) { /* 100 ms */
	183		if (RR32(regs_grph_update[i]) & GRPH_SURF_UPDATE_PENDING)
	184		break;
	185		udelay(1);
	186		}
	187		if (j == TIMEOUT)
	188		dev_warn(dce->ddev.dev, "dce6: page flip %u timed out\n", i);
	189
	190		tmp &= ~GRPH_UPDATE_LOCK;
	191		WR32(tmp, regs_grph_update[i]);
	192		}
	193
	194		/*
	195		* this is executed in hard irq context because we want the page flip to happen
	196		* as soon as possible
	197		*/
	198		void dce6_pf_irq(struct dce6 *dce, unsigned i)
	199		{
	200		u32 tmp;
	201
	202		/* disabling page flip is disabling the vblank interrupt */
	203		tmp = RR32(regs_crtc_int_mask[i]);
	204		tmp &= ~VBLANK_INT_MASK;
	205		WR32(tmp, regs_crtc_int_mask[i]);
	206
	207		page_flip(dce, i);
	208
	209		atomic_set(&dce->dps[i].pf.occurred, 1);
	210
	211		wake_up(&dce->dps[i].pf.event);
	212		}
	213		EXPORT_SYMBOL_GPL(dce6_pf_irq);
	214
	215		int dce6_pf(struct dce6 *dce, unsigned i, unsigned *vblanks_n)
	216		{
	217		u32 tmp;
	218
	219		/* enabling page flip is enabling vblank interrupt */
	220		tmp = RR32(regs_crtc_int_mask[i]);
	221		tmp |= VBLANK_INT_MASK;
	222		WR32(tmp, regs_crtc_int_mask[i]);
	223
	224		wait_event(dce->dps[i].pf.event,
	225		atomic_read(&dce->dps[i].pf.occurred) != 0);
	226
	227		atomic_set(&dce->dps[i].pf.occurred, 0);
	228
	229		*vblanks_n = RR32(regs_crtc_status_frame_cnt[i]);
	230		return 0;
	231		}
	232		EXPORT_SYMBOL_GPL(dce6_pf);

File drivers/gpu/alga/amd/dce6/crtc.h added (mode: 100644) (index 0000000..bac4e4c)
	1		#ifndef _CRTC_H
	2		#define _CRTC_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		int crtc_fb(struct dce6 *dce, unsigned i, struct db_fb *db_fb);
	9		void crtc_lut(struct dce6 *dce, unsigned i);
	10		void crtcs_intr_ena(struct dce6 *dce);
	11		void crtcs_intr_reset(struct dce6 *dce);
	12		#endif

File drivers/gpu/alga/amd/dce6/dce6.h added (mode: 100644) (index 0000000..69bb7fc)
	1		#ifndef _DCE6_H
	2		#define _DCE6_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		static const unsigned width_max = 8192;
	9		static const unsigned height_max = 8192;
	10
	11		/* XXX: should go up in alga */
	12		enum link_rate {/* factor of 270 MHz units */
	13		GHZ_1_62 = 6,
	14		GHZ_2_7 = 10,
	15		GHZ_5_4 = 20
	16		};
	17
	18		/* XXX: should go up in alga */
	19		static inline char *link_rate_names(enum link_rate link_rate)
	20		{
	21		switch (link_rate) {
	22		case GHZ_1_62:
	23		return "1.62 GHz";
	24		case GHZ_2_7:
	25		return "2.70 GHz";
	26		case GHZ_5_4:
	27		return "5.40 GHz";
	28		default:
	29		return "unregistered GHz";
	30		}
	31		}
	32		/* page flipping only */
	33		struct crtc_surfs {
	34		u64 primary;
	35		u64 secondary;
	36		};
	37
	38		struct pf {
	39		struct crtc_surfs crtc_surfs;
	40		wait_queue_head_t event;
	41		atomic_t occurred; /* to avoid race */
	42		};
	43
	44		struct dp {
	45		bool edp;
	46		unsigned atb_dfp;
	47
	48		u8 atb_aux_i2c_id;
	49		struct i2c_adapter i2c_adapter;
	50		void *edid; /* NULL is not fatal */
	51
	52		unsigned lanes_n;
	53		enum link_rate link_rate;
	54		enum link_rate trans_link_rate_max;
	55
	56		bool connected;
	57		u8 hpd; /* no hpd->0xff */
	58
	59		u8 dpcd_info[8]; /* see dp specs */
	60
	61		struct pf pf;
	62		};
	63
	64		struct irq {
	65		spinlock_t lock;
	66		unsigned hpds;
	67		};
	68
	69
	70		struct dce6 {
	71		struct mutex mutex;
	72
	73		unsigned hpds_used; /* carefull: hpd index may not be crtc index */
	74		unsigned dps_used;
	75		struct dp dps[CRTCS_N_MAX];
	76
	77		struct dce6_dev ddev;
	78
	79		struct irq irq;
	80		};
	81
	82		static inline void lock(struct dce6 *dce)
	83		{
	84		mutex_lock(&dce->mutex);
	85		}
	86
	87		static inline void unlock(struct dce6 *dce)
	88		{
	89		mutex_unlock(&dce->mutex);
	90		}
	91		#endif

File drivers/gpu/alga/amd/dce6/dp_link_train.c added (mode: 100644) (index 0000000..486127f)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		/*
	8		* NOTE: do not even try to understand this code without the displayport
	9		* specifications
	10		*/
	11		#include <linux/i2c.h>
	12		#include <linux/delay.h>
	13
	14		#include <alga/alga.h>
	15		#include <alga/pixel_fmts.h>
	16		#include <alga/timing.h>
	17		#include <alga/dp.h>
	18
	19		#include <alga/amd/atombios/atb.h>
	20		#include <alga/amd/atombios/dce.h>
	21		#include <alga/amd/dce6/dce6.h>
	22		#include <alga/amd/dce6/dce6_dev.h>
	23
	24		#include "dce6.h"
	25		#include "dpcd.h"
	26
	27		static char *vs_names(u8 vs_pre_emph)
	28		{
	29		vs_pre_emph &= DPCD_VOLTAGE_SWING_MASK;
	30
	31		switch (vs_pre_emph) {
	32		case DPCD_VOLTAGE_SWING_400:
	33		return "400 mV";
	34		case DPCD_VOLTAGE_SWING_600:
	35		return "600 mV";
	36		case DPCD_VOLTAGE_SWING_800:
	37		return "800 mV";
	38		case DPCD_VOLTAGE_SWING_1200:
	39		return "1200 mV";
	40		default:
	41		return "unregistered mV";
	42		}
	43		}
	44
	45		static char *pre_emph_names(u8 vs_pre_emph)
	46		{
	47		vs_pre_emph &= DPCD_PRE_EMPHASIS_MASK;
	48
	49		switch (vs_pre_emph) {
	50		case DPCD_PRE_EMPHASIS_0:
	51		return "0 dB";
	52		case DPCD_PRE_EMPHASIS_3_5:
	53		return "3.5 dB";
	54		case DPCD_PRE_EMPHASIS_6:
	55		return "6 dB";
	56		case DPCD_PRE_EMPHASIS_9_5:
	57		return "9.5 dB";
	58		default:
	59		return "unregistered dB";
	60		}
	61		}
	62
	63		static int tp_set(struct dce6 *dce, unsigned i, u8 tp)
	64		{
	65		int r;
	66
	67		dev_info(dce->ddev.dev, "dce6:dp%u:link training: setting training "
	68		"pattern %u\n", i, tp);
	69		r = atb_enc_dp_tp(dce->ddev.atb, i, dce->dps[i].link_rate,
	70		dce->dps[i].lanes_n, tp);
	71		if (r < 0){
	72		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to set "
	73		"training pattern on encoder\n", i);
	74		return -DCE6_ERR;
	75		}
	76
	77		r = dpcd_wr(dce, i, DPCD_TRAINING_PATTERN_SET, tp);
	78		if (r < 0) {
	79		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to "
	80		"dpcd write the training pattern for dp sink\n", i);
	81		return r;
	82		}
	83		return 0;
	84		}
	85
	86		static int vs_pre_emph_set(struct dce6 *dce, unsigned i, u8 vs_pre_emph)
	87		{
	88		int r;
	89
	90		dev_info(dce->ddev.dev, "dce6:dp%u:link training: setting vs=%s pre "
	91		"emph=%s at rate=%s\n", i, vs_names(vs_pre_emph),
	92		pre_emph_names(vs_pre_emph), link_rate_names(
	93		dce->dps[i].link_rate));
	94		/*
	95		* set the initial vs/pre-emph on the dp source, all lanes at once, and
	96		* there is only one value for the DCE transmitter.
	97		*/
	98		r = atb_trans_link_vs_pre_emph(dce->ddev.atb, i, vs_pre_emph);
	99		if (r < 0) {
	100		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to set "
	101		"vs and pre-emph on transmitter\n", i);
	102		return -DCE6_ERR;
	103		}
	104
	105		/*
	106		* set the vs/pre-emph on the dp sink for all lanes in one auxiliary
	107		* channel transaction, see dp specifications
	108		*/
	109		r = dpcd_lanes_vs_pre_emph_wr(dce, i, vs_pre_emph);
	110		if (r < 0)
	111		return r;
	112		return 0;
	113		}
	114
	115		static u8 lane_status_extract(u8 *link_status, unsigned l)
	116		{
	117		u8 lanes_pair_status;
	118
	119		lanes_pair_status = link_status[l >> 1];/* lanes 0,1->0
	120		lanes 2,3->1 */
	121		if ((l & 1) != 0) /* 0,2->lsbs, 1,3->msbs */
	122		lanes_pair_status = lanes_pair_status >> 4;
	123		return lanes_pair_status & 0xf;
	124		}
	125
	126		static bool clock_recovered(struct dce6 *dce, unsigned i, u8 *link_status)
	127		{
	128		unsigned l;
	129
	130		for (l = 0; l < dce->dps[i].lanes_n; ++l) {
	131		u8 lane_status;
	132
	133		lane_status = lane_status_extract(link_status, l);
	134		if ((lane_status & DPCD_LANE_CR_DONE) == 0)
	135		return false;
	136		}
	137		return true;
	138		}
	139
	140		static int link_rate_downshift(struct dce6 *dce, unsigned i)
	141		{
	142		switch (dce->dps[i].link_rate) {
	143		case GHZ_1_62:
	144		return -DCE6_ERR;
	145		case GHZ_2_7:
	146		dce->dps[i].link_rate = GHZ_1_62;
	147		break;
	148		case GHZ_5_4:
	149		dce->dps[i].link_rate = GHZ_2_7;
	150		break;
	151		}
	152		dev_info(dce->ddev.dev, "dce6:dp%u:link training: downshifting link "
	153		"rate to %s\n", i, link_rate_names(dce->dps[i].link_rate));
	154		return dpcd_wr(dce, i, DPCD_LINK_BW_SET, dce->dps[i].link_rate);
	155		}
	156
	157		static void lane_adjust_req_extract(u8 *link_status, unsigned l, u8 *vs,
	158		u8 *pre_emph)
	159		{
	160		u8 vs_pre_emph;
	161
	162		vs_pre_emph = link_status[DPCD_ADJUST_REQUEST_LANE0_1
	163		- DPCD_LANE0_1_STATUS + (l >> 1)];
	164		if (l & 1)
	165		vs_pre_emph = vs_pre_emph >>
	166		DPCD_ADJUST_VOLTAGE_SWING_LANEY_SHIFT;
	167
	168		*vs = vs_pre_emph & DPCD_ADJUST_VOLTAGE_SWING_LANEX_MASK;
	169		*pre_emph = vs_pre_emph & DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK;
	170		}
	171
	172		/* those return values are significant only for the clock recovery sequence */
	173		#define VS_DIFFERENT 1
	174		#define VS_SAME 0
	175		static int drive_adjust(struct dce6 *dce, unsigned i, u8 *vs_pre_emph,
	176		u8 *link_status)
	177		{
	178		int r;
	179		unsigned l;
	180		u8 current_vs;
	181		/*
	182		* only one vs and pre emph (highest values) for all lanes in DCE dp
	183		* transmitter
	184		*/
	185		u8 vs = 0;
	186		u8 pre_emph = 0;
	187
	188		r = VS_SAME;
	189
	190		/* get the adjust request highest values */
	191		for (l = 0; l < dce->dps[i].lanes_n; ++l) {
	192		u8 adjust_req_vs;
	193		u8 adjust_req_pre_emph;
	194
	195		lane_adjust_req_extract(link_status, l, &adjust_req_vs,
	196		&adjust_req_pre_emph);
	197
	198		if (adjust_req_vs > vs)
	199		vs = adjust_req_vs;
	200		if (adjust_req_pre_emph > pre_emph)
	201		pre_emph = adjust_req_pre_emph;
	202		}
	203
	204		pre_emph <<= 1; /* shift request bits for lane set register */
	205
	206		current_vs = *vs_pre_emph & DPCD_VOLTAGE_SWING_MASK;
	207		if (vs != current_vs)
	208		r = VS_DIFFERENT;
	209
	210		if (vs >= DPCD_VOLTAGE_SWING_1200)
	211		vs |= DPCD_MAX_VOLTAGE_SWING_REACHED;
	212		if (pre_emph >= DPCD_PRE_EMPHASIS_9_5)
	213		pre_emph |= DPCD_MAX_PRE_EMPHASIS_REACHED;
	214
	215		*vs_pre_emph = pre_emph | vs;
	216		return r;
	217		}
	218
	219		#define CLOCK_RECOVERY_LINK_RATE_DOWNSHIFT_REQUEST 1
	220		static int clock_recovery(struct dce6 *dce, unsigned i, u8 *vs_pre_emph)
	221		{
	222		int r;
	223		u8 link_status[DPCD_LINK_STATUS_SZ];
	224		unsigned same_vs_loop_count;
	225
	226		r = tp_set(dce, i, 1);
	227		if (r < 0)
	228		return r;
	229
	230		*vs_pre_emph = 0;
	231		r = vs_pre_emph_set(dce, i, *vs_pre_emph);
	232		if (r < 0)
	233		return r;
	234
	235		/* be sure the aux chan is ready, waiting for its timeout (dp specs) */
	236		udelay(400);
	237
	238		same_vs_loop_count = 1;
	239		while (1) {
	240		dev_info(dce->ddev.dev, "dce6:dp%u:link training: clock"
	241		" recovery test %u at %s\n", i, same_vs_loop_count,
	242		vs_names(*vs_pre_emph));
	243
	244		udelay(100);/* from dp 1.2, dpcd provides this value */
	245
	246		r = dpcd_link_status(dce, i, link_status);
	247		if (r < 0)
	248		return r;
	249
	250		if (clock_recovered(dce, i, link_status))
	251		break;
	252
	253		if (same_vs_loop_count >= 5 || ((*vs_pre_emph
	254		& DPCD_MAX_VOLTAGE_SWING_REACHED) != 0))
	255		return CLOCK_RECOVERY_LINK_RATE_DOWNSHIFT_REQUEST;
	256
	257		r = drive_adjust(dce, i, vs_pre_emph, link_status);
	258		if (r == VS_SAME)
	259		++same_vs_loop_count;
	260		else if (r == VS_DIFFERENT)
	261		same_vs_loop_count = 1;
	262
	263		r = vs_pre_emph_set(dce, i, *vs_pre_emph);
	264		if (r < 0)
	265		return r;
	266		}
	267		dev_info(dce->ddev.dev, "dce6:dp%u:link training: clock recovery "
	268		"successful for vs=%s pre emph=%s at rate=%s, %u lanes\n", i,
	269		vs_names(*vs_pre_emph), pre_emph_names(*vs_pre_emph),
	270		link_rate_names(dce->dps[i].link_rate), dce->dps[i].lanes_n);
	271		return 0;
	272		}
	273
	274		static int clock_recovery_link_rate_loop(struct dce6 *dce, unsigned i,
	275		u8 *vs_pre_emph)
	276		{
	277		int r;
	278
	279		while (1) {
	280		r = clock_recovery(dce, i, vs_pre_emph);
	281		if (r < 0)
	282		return r;
	283		if (r == 0)
	284		break;
	285
	286		r = link_rate_downshift(dce, i);
	287		if (r < 0)
	288		return r;
	289		}
	290		return r;
	291		}
	292
	293		static int train_init(struct dce6 *dce, unsigned i)
	294		{
	295		int r;
	296		u8 tmp;
	297
	298		/* be sure the sink is in active power state */
	299		r = dpcd_wr(dce, i, DPCD_SET_PWR, DPCD_SET_PWR_D0);
	300		if (r < 0)
	301		return r;
	302
	303		/* enable dp downspread */
	304		if ((dce->dps[i].dpcd_info[DPCD_MAX_DOWNSPREAD]
	305		& DPCD_MAX_DOWNSPREAD_SUPPORT) != 0) {
	306		r = dpcd_wr(dce, i, DPCD_DOWNSPREAD_CTL, DPCD_SPREAD_AMP_0_5);
	307		if (r < 0)
	308		return r;
	309		}
	310
	311		/* get the maximum lanes we can get */
	312		tmp = (u8)(dce->dps[i].lanes_n);
	313		if ((dce->dps[i].dpcd_info[DPCD_MAX_LANE_COUNT]
	314		& DPCD_LANE_COUNT_ENHANCED_FRAME_EN) != 0)
	315		tmp |= DPCD_LANE_COUNT_ENHANCED_FRAME_EN;
	316
	317		r = dpcd_wr(dce, i, DPCD_LANE_COUNT_SET, tmp);
	318		if (r < 0)
	319		return r;
	320
	321		/* start with the best link rate we can have */
	322		r = dpcd_wr(dce, i, DPCD_LINK_BW_SET, dce->dps[i].link_rate);
	323		if (r < 0)
	324		return r;
	325
	326		/* tell the digital encoder we are about to emit training patterns */
	327		r = atb_enc_dp_training_start(dce->ddev.atb, i);
	328		if (r < 0)
	329		return -DCE6_ERR;
	330
	331		/* be sure the sink is not in training state */
	332		r = dpcd_wr(dce, i, DPCD_TRAINING_PATTERN_SET,
	333		DPCD_TRAINING_PATTERN_DISABLE);
	334		if (r < 0)
	335		return r;
	336		return 0;
	337		}
	338
	339		static bool channel_equalized(struct dce6 *dce, unsigned i, u8 *link_status)
	340		{
	341		u8 align_status;
	342		unsigned l;
	343
	344		align_status = link_status[DPCD_LANE_ALIGN_STATUS_UPDATED
	345		- DPCD_LANE0_1_STATUS];
	346
	347		if ((align_status & DPCD_INTERLANE_ALIGN_DONE) == 0)
	348		return false;
	349
	350		for (l = 0; l < dce->dps[i].lanes_n; ++l) {
	351		u8 lane_status;
	352		lane_status = lane_status_extract(link_status, l);
	353
	354		if (((lane_status & DPCD_LANE_CHANNEL_EQ_DONE) == 0)
	355		|| ((lane_status & DPCD_LANE_SYMBOL_LOCKED) == 0))
	356		return false;
	357		}
	358		return true;
	359		}
	360
	361		#define CLOCK_RECOVERY_REQUEST 1
	362		static int channel_equalization(struct dce6 *dce, unsigned i, u8 *vs_pre_emph)
	363		{
	364		int r;
	365		unsigned loop_count;
	366		u8 link_status[DPCD_LINK_STATUS_SZ];
	367
	368		r = tp_set(dce, i, 2); /* from dp 1.2, there is a 3rd pattern */
	369		if (r < 0)
	370		return r;
	371
	372		r = vs_pre_emph_set(dce, i, *vs_pre_emph);
	373		if (r < 0)
	374		return r;
	375
	376		loop_count = 1;
	377		while (1) {
	378		dev_info(dce->ddev.dev, "dce6:dp%u:link training: channel"
	379		" equalization test %u\n", i, loop_count);
	380
	381		udelay(400);
	382
	383		r = dpcd_link_status(dce, i, link_status);
	384		if (r < 0)
	385		return r;
	386
	387		if (!clock_recovered(dce, i, link_status)) {
	388		r = link_rate_downshift(dce, i);
	389		if (r < 0)
	390		return r;
	391		return CLOCK_RECOVERY_REQUEST;
	392		}
	393
	394		if (channel_equalized(dce, i, link_status))
	395		break;
	396
	397		if (loop_count > 5) {
	398		r = link_rate_downshift(dce, i);
	399		if (r < 0)
	400		return r;
	401		return CLOCK_RECOVERY_REQUEST;
	402		}
	403
	404		drive_adjust(dce, i, vs_pre_emph, link_status);
	405
	406		r = vs_pre_emph_set(dce, i, *vs_pre_emph);
	407		if (r < 0)
	408		return r;
	409
	410		++loop_count;
	411		}
	412		dev_info(dce->ddev.dev, "dce6:dp%u:link training: channel equalization "
	413		"successful for vs=%s pre emph=%s at rate=%s, %u lanes\n", i,
	414		vs_names(*vs_pre_emph), pre_emph_names(*vs_pre_emph),
	415		link_rate_names(dce->dps[i].link_rate), dce->dps[i].lanes_n);
	416		return 0;
	417		}
	418
	419		static int train_finish(struct dce6 *dce, unsigned i)
	420		{
	421		int r;
	422
	423		udelay(400);
	424
	425		r = dpcd_wr(dce, i, DPCD_TRAINING_PATTERN_SET, 0);
	426		if (r < 0) {
	427		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to "
	428		"dpcd disable the training pattern for dp sink\n", i);
	429		return r;
	430		}
	431
	432		r = atb_enc_dp_training_complete(dce->ddev.atb, i);
	433		if (r < 0) {
	434		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to "
	435		"disable the training pattern on encoder\n", i);
	436		return -DCE6_ERR;
	437		}
	438		return 0;
	439		}
	440
	441		/* bw is the amount of MB per second we want the link to transfer */
	442		int dp_link_train(struct dce6 *dce, unsigned i)
	443		{
	444		int r;
	445		u8 vs_pre_emph;
	446
	447		r = train_init(dce, i);
	448		if (r < 0) {
	449		dev_err(dce->ddev.dev, "dce6:dp%u:link training: init failed\n",
	450		i);
	451		return r;
	452		}
	453
	454		while (1) {
	455		r = clock_recovery_link_rate_loop(dce, i, &vs_pre_emph);
	456		if (r < 0)
	457		return r;
	458
	459		r = channel_equalization(dce, i, &vs_pre_emph);
	460		if (r < 0)
	461		return r;
	462		if (r == 0)
	463		break;
	464		}
	465		if (r < 0)
	466		dev_err(dce->ddev.dev, "dce6:dp%u:link training: failure, "
	467		"last attempt is vs=%s pre emph=%s at rate=%s\n", i,
	468		vs_names(vs_pre_emph), pre_emph_names(vs_pre_emph),
	469		link_rate_names(dce->dps[i].link_rate));
	470		r = train_finish(dce, i);
	471		return r;
	472		}

File drivers/gpu/alga/amd/dce6/dp_link_train.h added (mode: 100644) (index 0000000..417ec9a)
	1		#ifndef _DP_LINK_TRAIN_H
	2		#define _DP_LINK_TRAIN_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		int dp_link_train(struct dce6 *dce, unsigned i);
	9		#endif

File drivers/gpu/alga/amd/dce6/dpcd.c added (mode: 100644) (index 0000000..8220d13)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/device.h>
	7		#include <linux/i2c.h>
	8
	9		#include <alga/alga.h>
	10		#include <alga/pixel_fmts.h>
	11		#include <alga/timing.h>
	12		#include <alga/dp.h>
	13		#include <alga/amd/atombios/atb.h>
	14		#include <alga/amd/atombios/dce.h>
	15		#include <alga/amd/dce6/dce6.h>
	16		#include <alga/amd/dce6/dce6_dev.h>
	17
	18		#include "dce6.h"
	19
	20		int dpcd_wr(struct dce6 *dce, unsigned i, u16 addr, u8 byte)
	21		{
	22		int r;
	23
	24		r = atb_dp_aux_native_write(dce->ddev.atb, dce->dps[i].atb_aux_i2c_id,
	25		dce->dps[i].hpd, addr, &byte, 1);
	26		if (r <= 0)
	27		return -DCE6_ERR;
	28		return 0;
	29		}
	30
	31		int dpcd_lanes_vs_pre_emph_wr(struct dce6 *dce, unsigned i, u8 vs_pre_emph)
	32		{
	33		int r;
	34		u8 lanes_training_set[DP_MAX_LANES_N];
	35
	36		memset(lanes_training_set, vs_pre_emph, dce->dps[i].lanes_n);
	37
	38		r = atb_dp_aux_native_write(dce->ddev.atb, dce->dps[i].atb_aux_i2c_id,
	39		dce->dps[i].hpd, DPCD_TRAINING_LANE0_SET, lanes_training_set,
	40		dce->dps[i].lanes_n);
	41		if (r < dce->dps[i].lanes_n) {
	42		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to "
	43		"dpcd write vs and pre emph for dp sink\n", i);
	44		return -DCE6_ERR;
	45		}
	46		return 0;
	47		}
	48
	49		int dpcd_link_status(struct dce6 *dce, unsigned i, u8 *link_status)
	50		{
	51		int r;
	52
	53		r = atb_dp_aux_native_read(dce->ddev.atb, dce->dps[i].atb_aux_i2c_id,
	54		dce->dps[i].hpd, DPCD_LANE0_1_STATUS, link_status,
	55		DPCD_LINK_STATUS_SZ);
	56		if (r < DPCD_LINK_STATUS_SZ) {
	57		dev_err(dce->ddev.dev, "dce6:dp%u:link training: unable to read"
	58		"link status\n", i);
	59		return -DCE6_ERR;
	60		}
	61		return 0;
	62		}
	63
	64		int dpcd_info(struct dce6 * dce, unsigned i)
	65		{
	66		struct dp *dp;
	67		int r;
	68
	69		dp = &dce->dps[i];
	70
	71		memset(dp->dpcd_info, 0, sizeof(dp->dpcd_info));
	72		r = atb_dp_aux_native_read(dce->ddev.atb, dp->atb_aux_i2c_id, dp->hpd,
	73		DPCD_REV, dp->dpcd_info, sizeof(dp->dpcd_info));
	74		if (r <= 0)
	75		return -DCE6_ERR;
	76
	77		dev_info(dce->ddev.dev, "dce6: dp%u dpcd=0x%02x 0x%02x 0x%02x 0x%02x "
	78		"0x%02x 0x%02x 0x%02x 0x%02x\n", i, dp->dpcd_info[0],
	79		dp->dpcd_info[1], dp->dpcd_info[2], dp->dpcd_info[3],
	80		dp->dpcd_info[4], dp->dpcd_info[5], dp->dpcd_info[6],
	81		dp->dpcd_info[7]);
	82		return 0;
	83		}

File drivers/gpu/alga/amd/dce6/dpcd.h added (mode: 100644) (index 0000000..fb3768d)
	1		#ifndef _DPCD_H
	2		#define _DPCD_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		int dpcd_wr(struct dce6 *dce, unsigned i, u16 addr, u8 byte);
	9		int dpcd_lanes_vs_pre_emph_wr(struct dce6 *dce, unsigned i, u8 vs_pre_emph);
	10		int dpcd_link_status(struct dce6 *dce, unsigned i, u8 *link_status);
	11		int dpcd_info(struct dce6 * dce, unsigned i);
	12		#endif

File drivers/gpu/alga/amd/dce6/hpd.c added (mode: 100644) (index 0000000..1fa52e9)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/device.h>
	7		#include <linux/module.h>
	8		#include <linux/i2c.h>
	9		#include <linux/slab.h>
	10		#include <linux/spinlock.h>
	11		#include <linux/bitops.h>
	12
	13		#include <alga/alga.h>
	14		#include <alga/pixel_fmts.h>
	15		#include <alga/timing.h>
	16		#include <alga/edid.h>
	17		#include <alga/amd/atombios/atb.h>
	18		#include <alga/amd/atombios/dce.h>
	19		#include <alga/amd/dce6/dce6.h>
	20		#include <alga/amd/dce6/dce6_dev.h>
	21
	22		#include "dce6.h"
	23		#include "i2c.h"
	24		#include "dpcd.h"
	25		#include "regs.h"
	26
	27		#define RR32(of) dce->ddev.rr32(dce->ddev.dev, (of))
	28		#define WR32(v, of) dce->ddev.wr32(dce->ddev.dev, (v), (of))
	29		static void off(struct dce6 *dce, u8 hpd)
	30		{
	31		WR32(0, regs_hpd_ctl[hpd]);
	32		}
	33
	34		static void on(struct dce6 *dce, u8 hpd)
	35		{
	36		u32 tmp;
	37
	38		/*
	39		* This is hardcoded for displayport with the 2 ms threshold in mind.
	40		* In theory, the irq is not supposed to be raised until the hpd logic
	41		* knows if it is a disconnection or a dp sink irq.
	42		*/
	43		tmp = SET(HPDx_CTL_CONN_TIMER, 2500) | SET(HPDx_CTL_RX_INT_TIMER, 250)
	44		| HPDx_CTL_ENA;
	45		WR32(tmp, regs_hpd_ctl[hpd]);
	46		}
	47
	48		bool hpd_sense(struct dce6 *dce, u8 hpd)
	49		{
	50		return ((RR32(regs_hpd_int_status[hpd]) & HPDx_INT_STATUS_SENSE) != 0);
	51		}
	52
	53
	54		void hpd_polarity_rearm(struct dce6 *dce, u8 hpd, bool connected)
	55		{
	56		u32 tmp;
	57
	58		tmp = RR32(regs_hpd_int_ctl[hpd]);
	59		if (connected)
	60		tmp &= ~HPDx_INT_CTL_INT_POLARITY;
	61		else
	62		tmp |= HPDx_INT_CTL_INT_POLARITY;
	63		WR32(tmp, regs_hpd_int_ctl[hpd]);
	64		}
	65
	66		void hpds_polarity_refresh(struct dce6 *dce)
	67		{
	68		unsigned i;
	69		u32 tmp;
	70
	71		/* keep polarity */
	72		for (i = 0; i < HPDS_N; ++i) {
	73		if ((dce->hpds_used & BIT(i)) != 0) {
	74		tmp = RR32(regs_hpd_int_ctl[i])
	75		& HPDx_INT_CTL_INT_POLARITY;
	76		WR32(tmp, regs_hpd_int_ctl[i]);
	77		}
	78		}
	79		}
	80
	81		void hpds_off(struct dce6 *dce)
	82		{
	83		unsigned i;
	84
	85		for (i = 0; i < HPDS_N; ++i)
	86		off(dce, i);
	87		}
	88
	89		void hpds_init(struct dce6 *dce)
	90		{
	91		unsigned i;
	92
	93		for (i = 0; i < HPDS_N; ++i) {
	94		if ((dce->hpds_used & BIT(i)) == 0) {
	95		off(dce, i);
	96		dev_info(dce->ddev.dev, "dce6: hpd%u off\n", i);
	97		continue;
	98		}
	99
	100		on(dce, i);
	101		dev_info(dce->ddev.dev, "dce6: hpd%u on\n", i);
	102		}
	103		}
	104
	105		static int dp_toggle_connected(struct dce6 *dce, unsigned i)
	106		{
	107		int r;
	108
	109		r = dp_i2c_adapter_init(dce, i);
	110		if (r != 0) {
	111		dev_warn(dce->ddev.dev, "dce6: unable to create i2c adapter "
	112		"for newly connected dp%u\n", i);
	113		return r;
	114		}
	115
	116		/* dp specs: must query dcpd info before 100 ms */
	117		r = dpcd_info(dce, i);
	118		if (r != 0) {
	119		dev_warn(dce->ddev.dev, "dce6: unable to query dcpd info for "
	120		"newly connected dp%u\n", i);
	121		i2c_del_adapter(&dce->dps[i].i2c_adapter);
	122		goto err;
	123		}
	124
	125		/* get the edid, failing to get it is not fatal */
	126		r = alga_i2c_edid_fetch(dce->ddev.dev, &dce->dps[i].i2c_adapter,
	127		&dce->dps[i].edid);
	128		if (r != 0) {
	129		dev_warn(dce->ddev.dev, "dce6: unable to fetch edid for dp%u\n",
	130		i);
	131		r = 0;
	132		goto err;
	133		}
	134		r = 0;
	135		err:
	136		return r;
	137		}
	138
	139		/* must be called with the lock held */
	140		static int dp_toggle(struct dce6 *dce, unsigned i)
	141		{
	142		int r;
	143		dce->dps[i].connected = !dce->dps[i].connected;
	144
	145		r = 0;
	146		if(dce->dps[i].connected) {
	147		dev_info(dce->ddev.dev, "dce6: dp%u was connected\n", i);
	148		r = dp_toggle_connected(dce, i);
	149		if (r != 0) /* restore disconnected state */
	150		dce->dps[i].connected = false;
	151		} else {
	152		dev_info(dce->ddev.dev, "dce6: dp%u was disconnected\n", i);
	153		i2c_del_adapter(&dce->dps[i].i2c_adapter);
	154		if (dce->dps[i].edid != NULL) {
	155		kfree(dce->dps[i].edid);
	156		dce->dps[i].edid = NULL;
	157		}
	158		}
	159		atb_dp_state(dce->ddev.atb, dce->dps[i].atb_dfp, dce->dps[i].connected);
	160		return r;
	161		}
	162
	163		static void dp_sink_irq(void)
	164		{
	165		//DEBUG
	166		printk(KERN_INFO "DP SINK IRQ RECEIVED\n");
	167		}
	168
	169		int hpd_irq(struct dce6 *dce, u8 hpd)
	170		{
	171		int r;
	172		unsigned i;
	173
	174		if ((dce->hpds_used & BIT(hpd)) == 0) {
	175		dev_warn(dce->ddev.dev, "dce6: irq on unused hpd%u\n, hpd",
	176		hpd);
	177		return 0;
	178		}
	179
	180		r = 0;
	181		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	182		if (dce->dps[i].hpd == hpd) {
	183		bool sense;
	184
	185		sense = hpd_sense(dce, hpd);
	186		hpd_polarity_rearm(dce, hpd, sense);
	187
	188		lock(dce);
	189		if (dce->dps[i].connected != sense) {
	190		r = dp_toggle(dce, i);
	191		} else {
	192		dp_sink_irq();
	193		}
	194		unlock(dce);
	195		break;
	196		}
	197		}
	198		return r;
	199		}
	200
	201		void dce6_hpds_intr_ena(struct dce6 *dce)
	202		{
	203		u32 hpds[HPDS_N];
	204		unsigned i;
	205
	206		for (i = 0; i < HPDS_N; ++i) {
	207		if (dce->hpds_used & BIT(i))
	208		hpds[i] = RR32(regs_hpd_int_ctl[i])
	209		| HPDx_INT_CTL_INT_ENA;
	210		else
	211		hpds[i] = 0;
	212
	213		}
	214		for (i = 0; i < HPDS_N; ++i)
	215		WR32(hpds[i], regs_hpd_int_ctl[i]);
	216		}
	217		EXPORT_SYMBOL_GPL(dce6_hpds_intr_ena);
	218
	219		void dce6_hpd_irq(struct dce6 *dce, unsigned hpd)
	220		{
	221		unsigned long flgs;
	222
	223		spin_lock_irqsave(&dce->irq.lock, flgs);
	224		dce->irq.hpds |= BIT(hpd);
	225		spin_unlock_irqrestore(&dce->irq.lock, flgs);
	226		}
	227		EXPORT_SYMBOL_GPL(dce6_hpd_irq);

File drivers/gpu/alga/amd/dce6/hpd.h added (mode: 100644) (index 0000000..40c7492)
	1		#ifndef _HPD_H
	2		#define _HPD_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		void hpds_init(struct dce6 *dce);
	9		void hpd_polarity_rearm(struct dce6 *dce, u8 hpd, bool connected);
	10		void hpds_polarity_refresh(struct dce6 *dce);
	11		bool hpd_sense(struct dce6 *dce, u8 hpd);
	12		int hpd_irq(struct dce6 *dce, u8 hpd);
	13		void hpds_off(struct dce6 *dce);
	14		#endif

File drivers/gpu/alga/amd/dce6/i2c.c added (mode: 100644) (index 0000000..301e5e3)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/i2c.h>
	8		#include <linux/slab.h>
	9
	10		#include <alga/alga.h>
	11		#include <alga/pixel_fmts.h>
	12		#include <alga/timing.h>
	13		#include <alga/amd/atombios/atb.h>
	14		#include <alga/amd/atombios/dce.h>
	15		#include <alga/amd/dce6/dce6.h>
	16		#include <alga/amd/dce6/dce6_dev.h>
	17
	18		#include "dce6.h"
	19
	20		static int start_send(struct i2c_adapter *a, u16 addr, bool read)
	21		{
	22		unsigned mode;
	23		struct dce6 *dce;
	24		struct dp *dp;
	25
	26		mode = ATB_MODE_I2C_START;
	27		if (read)
	28		mode |= ATB_MODE_I2C_READ;
	29		else
	30		mode |= ATB_MODE_I2C_WRITE;
	31
	32		dce = a->algo_data;
	33		dp = container_of(a, struct dp, i2c_adapter);
	34		return atb_dp_aux_i2c(dce->ddev.atb, dp->atb_aux_i2c_id, dp->hpd, addr,
	35		mode, 0, NULL);
	36		}
	37
	38		static int stop_send(struct i2c_adapter *a, u16 addr, bool read)
	39		{
	40		unsigned mode;
	41		struct dce6 *dce;
	42		struct dp *dp;
	43
	44		mode = ATB_MODE_I2C_STOP;
	45		if (read)
	46		mode |= ATB_MODE_I2C_READ;
	47		else
	48		mode |= ATB_MODE_I2C_WRITE;
	49
	50		dce = a->algo_data;
	51		dp = container_of(a, struct dp, i2c_adapter);
	52		return atb_dp_aux_i2c(dce->ddev.atb, dp->atb_aux_i2c_id, dp->hpd, addr,
	53		mode, 0, NULL);
	54		}
	55
	56		static int byte_send(struct i2c_adapter *a, u16 addr, u8 byte)
	57		{
	58		struct dce6 *dce;
	59		struct dp *dp;
	60
	61		dce = a->algo_data;
	62		dp = container_of(a, struct dp, i2c_adapter);
	63		return atb_dp_aux_i2c(dce->ddev.atb, dp->atb_aux_i2c_id, dp->hpd, addr,
	64		ATB_MODE_I2C_WRITE, byte, NULL);
	65		}
	66
	67		static int byte_recv(struct i2c_adapter *a, u16 addr, u8 *byte)
	68		{
	69		struct dce6 *dce;
	70		struct dp *dp;
	71
	72		dce = a->algo_data;
	73		dp = container_of(a, struct dp, i2c_adapter);
	74		return atb_dp_aux_i2c(dce->ddev.atb, dp->atb_aux_i2c_id, dp->hpd, addr,
	75		ATB_MODE_I2C_READ, 0, byte);
	76		}
	77
	78		static int i2c_transac(struct i2c_adapter *a, struct i2c_msg *msgs, int num)
	79		{
	80		int r;
	81		bool read;
	82		unsigned m;
	83		unsigned b;
	84
	85		r = 0;
	86		read = false;
	87		for (m = 0; m < num; ++m) {
	88		u16 len = msgs[m].len;
	89		u8 *buf = msgs[m].buf;
	90		read = (msgs[m].flags & I2C_M_RD) != 0;
	91
	92		r = start_send(a, msgs[m].addr, read); /* or restart */
	93		if (r < 0)
	94		break;
	95
	96		if (read) {
	97		for (b = 0; b < len; ++b) {
	98		r = byte_recv(a, msgs[m].addr, &buf[b]);
	99		if (r < 0)
	100		break;
	101		}
	102		} else {
	103		for (b = 0; b < len; ++b) {
	104		r = byte_send(a, msgs[m].addr, buf[b]);
	105		if (r < 0)
	106		break;
	107		}
	108		}
	109		if (r < 0)
	110		break;
	111		}
	112		if (num > 0)
	113		r = stop_send(a, msgs[num-1].addr, read);
	114		if (r >= 0)
	115		r = num;
	116		return r;
	117		}
	118
	119		static u32 functionality(struct i2c_adapter *a)
	120		{
	121		return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
	122		I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
	123		I2C_FUNC_10BIT_ADDR;
	124		}
	125
	126		static const struct i2c_algorithm dp_i2c_algo = {
	127		.master_xfer = i2c_transac,
	128		.functionality = functionality
	129		};
	130
	131		int dp_i2c_adapter_init(struct dce6 *dce, unsigned i)
	132		{
	133		struct i2c_adapter *a;
	134		int r;
	135
	136		a = &dce->dps[i].i2c_adapter;
	137
	138		memset(a, 0, sizeof(*a));
	139		a->owner = THIS_MODULE;
	140		a->class = I2C_CLASS_DDC;
	141		a->algo = &dp_i2c_algo;
	142		a->algo_data = dce;
	143		a->retries = 3;
	144		a->dev.parent = dce->ddev.dev;
	145		snprintf(a->name, sizeof(a->name), "dp%u", i);
	146		r = i2c_add_adapter(a);
	147		if (r != 0)
	148		r = -DCE6_ERR;
	149		return r;
	150		}
	151
	152		void dp_i2c_cleanup(struct dce6 *dce)
	153		{
	154		unsigned i;
	155
	156		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	157		if ((dce->dps_used & BIT(i)) == 0)
	158		continue;
	159
	160		if (!dce->dps[i].connected)
	161		continue;
	162
	163		i2c_del_adapter(&dce->dps[i].i2c_adapter);
	164		}
	165		}

File drivers/gpu/alga/amd/dce6/i2c.h added (mode: 100644) (index 0000000..a216a8f)
	1		#ifndef _ALGA_AMD_DCE6_I2C_H
	2		#define _ALGA_AMD_DCE6_I2C_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		int dp_i2c_adapter_init(struct dce6 *dce, unsigned i);
	9		void dp_i2c_cleanup(struct dce6 *dce);
	10		#endif

File drivers/gpu/alga/amd/dce6/irq.c added (mode: 100644) (index 0000000..54dfacf)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/device.h>
	8		#include <linux/i2c.h>
	9
	10		#include <alga/pixel_fmts.h>
	11		#include <alga/timing.h>
	12		#include <alga/amd/dce6/dce6.h>
	13		#include <alga/amd/dce6/dce6_dev.h>
	14
	15		#include "dce6.h"
	16		#include "hpd.h"
	17		#include "crtc.h"
	18
	19		#include "regs.h"
	20
	21		#define RR32(of) dce->ddev.rr32(dce->ddev.dev, (of))
	22		#define WR32(v, of) dce->ddev.wr32(dce->ddev.dev, (v), (of))
	23
	24		/*
	25		* The dce irqs are not acked by the rlc (block in charge of irq management).
	26		* It seems the rlc block does not have xrbm access (the block in charge of
	27		* register management).
	28		* Then those irqs must be acked manually by the CPU.
	29		* This is called in hard interrupt context, it does not lock the dce.
	30		*/
	31		void dce6_irqs_ack(struct dce6 *dce)
	32		{
	33		u32 disps[CRTCS_N_MAX];
	34		u32 grphs[CRTCS_N_MAX];
	35		unsigned i;
	36		u32 tmp;
	37
	38		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	39		disps[i] = RR32(regs_disp_int_status[i]);
	40
	41		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	42		grphs[i] = RR32(regs_crtc_grph_int_status[i]);
	43
	44		/* XXX: obsolete page flipping */
	45		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	46		if (grphs[i] & GRPH_PFLIP_INT_OCCURRED)
	47		WR32(GRPH_PFLIP_INT_CLR, regs_crtc_grph_int_status[i]);
	48
	49		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	50		if (disps[i] & vals_lb_d_vblank_int[i])
	51		WR32(VBLANK_ACK, regs_crtc_vblank_status[i]);
	52		if (disps[i] & vals_lb_d_vline_int[i])
	53		WR32(VLINE_ACK, regs_crtc_vline_status[i]);
	54		}
	55
	56		for (i = 0; i < HPDS_N; ++i)
	57		if (disps[i] & vals_hpd_int[i]) {
	58		tmp = RR32(regs_hpd_int_ctl[i]);
	59		tmp |= HPDx_INT_CTL_INT_ACK;
	60		WR32(tmp, regs_hpd_int_ctl[i]);
	61		}
	62		}
	63		EXPORT_SYMBOL_GPL(dce6_irqs_ack);
	64
	65		int dce6_irqs_thd(struct dce6 *dce)
	66		{
	67		int r;
	68		unsigned i;
	69		unsigned hpds;
	70		unsigned long flgs;
	71
	72		spin_lock_irqsave(&dce->irq.lock, flgs);
	73		hpds = dce->irq.hpds;
	74		dce->irq.hpds = 0;
	75		spin_unlock_irqrestore(&dce->irq.lock, flgs);
	76
	77		r = 0;
	78		for (i = 0; i < HPDS_N; ++i)
	79		if (hpds & BIT(i)) {
	80		r = hpd_irq(dce, i);
	81		if (r != 0)
	82		dev_err(dce->ddev.dev, "dce6: unable to service"
	83		" hpd%u interrupt request\n", i);
	84		}
	85		return r;
	86		}
	87		EXPORT_SYMBOL_GPL(dce6_irqs_thd);

File drivers/gpu/alga/amd/dce6/mod.c added (mode: 100644) (index 0000000..de3c93a)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/slab.h>
	8		#include <linux/delay.h>
	9		#include <linux/i2c.h>
	10		#include <linux/atomic.h>
	11
	12		#include <alga/alga.h>
	13		#include <alga/pixel_fmts.h>
	14		#include <alga/timing.h>
	15		#include <alga/dp.h>
	16		#include <alga/edid.h>
	17		#include <alga/amd/atombios/atb.h>
	18		#include <alga/amd/atombios/dce.h>
	19		#include <alga/amd/dce6/dce6.h>
	20		#include <alga/amd/dce6/dce6_dev.h>
	21
	22		#include "dce6.h"
	23		#include "hpd.h"
	24		#include "sink.h"
	25		#include "i2c.h"
	26		#include "dpcd.h"
	27		#include "crtc.h"
	28		#include "regs.h"
	29
	30		static int paths_parse(struct dce6 *dce)
	31		{
	32		struct atb_dp_path *ps;
	33		size_t ps_n;
	34		int r;
	35
	36		dce->dps_used = 0;
	37		dce->hpds_used = 0;
	38		r = atb_dp_paths(dce->ddev.atb, &ps, &ps_n);
	39		if (r == 0 && ps_n ==0)
	40		dev_warn(dce->ddev.dev, "dce6: no displayport path found\n");
	41		else if (r == 0 && ps_n !=0) {
	42		unsigned i;
	43		for (i = 0; i < ps_n; ++i) {
	44		struct dp *dp;
	45		dce->dps_used |= BIT(ps[i].i);
	46
	47		dp = &dce->dps[ps[i].i];
	48		dp->atb_dfp = ps[i].dfp;
	49		dp->atb_aux_i2c_id = ps[i].aux_i2c_id;
	50		dp->edp = ps[i].edp;
	51		dp->hpd = ps[i].hpd;
	52		if (dp->hpd != 0xff)
	53		dce->hpds_used |= BIT(dp->hpd);
	54
	55		if (ps[i].uniphy_link_hbr2)
	56		dp->trans_link_rate_max = GHZ_5_4;
	57		else
	58		dp->trans_link_rate_max = GHZ_2_7;
	59		}
	60		kfree(ps);
	61		}
	62		return r;
	63		}
	64
	65		static void dp_dump(struct dce6 *dce, unsigned i)
	66		{
	67		struct dp *dp;
	68		const char *s;
	69
	70		dp = &dce->dps[i];
	71		if (dp->edp)
	72		s = "embedded displayport connector";
	73		else
	74		s = "displayport connector";
	75		dev_info(dce->ddev.dev, "\t%s DFP%u atb_aux_i2c_id=0x%02x", s,
	76		dp->atb_dfp, dp->atb_aux_i2c_id);
	77
	78		switch (dp->trans_link_rate_max) {
	79		case GHZ_1_62:
	80		s = "1.62 GHz";
	81		break;
	82		case GHZ_2_7:
	83		s = "2.7 GHz";
	84		break;
	85		case GHZ_5_4:
	86		s = "5.4 GHz";
	87		break;
	88		}
	89		dev_info(dce->ddev.dev, "\ttransmitter max link rate %s\n", s);
	90
	91		if (dp->hpd != 0xff)
	92		dev_info(dce->ddev.dev, "\thpd%u is used\n",dp->hpd);
	93		else
	94		dev_info(dce->ddev.dev, "\tno hpd found\n");
	95		}
	96
	97		static void dps_dump(struct dce6 *dce)
	98		{
	99		unsigned i;
	100
	101		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	102		if ((dce->dps_used & BIT(i)) == 0) {
	103		dev_info(dce->ddev.dev, "dce6: dp%u not used\n", i);
	104		continue;
	105		}
	106		dev_info(dce->ddev.dev, "dce6: dp%u used\n", i);
	107		dp_dump(dce, i);
	108		}
	109		}
	110
	111		static void dce_dump(struct dce6 *dce)
	112		{
	113		dps_dump(dce);
	114		}
	115
	116		static int trans_links_init(struct dce6 *dce)
	117		{
	118		unsigned i;
	119
	120		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	121		int r;
	122
	123		if ((dce->dps_used & BIT(i)) == 0)
	124		continue;
	125
	126		r = atb_trans_link_init(dce->ddev.atb, i, dce->dps[i].edp);
	127		if (r != 0) {
	128		dev_err(dce->ddev.dev, "dce6: failed to init uniphy "
	129		"link for dp%u\n", i);
	130		return -DCE6_ERR;
	131		}
	132		}
	133		return 0;
	134		}
	135
	136		static int dps_sense(struct dce6 *dce)
	137		{
	138		unsigned i;
	139
	140		dev_info(dce->ddev.dev, "dce6: dps coldplug start:\n");
	141		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	142		struct dp *dp;
	143		bool sense;
	144		int r;
	145		char *s;
	146
	147		if ((dce->dps_used & BIT(i)) == 0)
	148		continue;
	149
	150		dp = &dce->dps[i];
	151
	152		/* no hpd, presume edp and always connected */
	153		if (dp->hpd == 0xff) {
	154		dev_info(dce->ddev.dev, "dce6: \tdp%u has no hpd\n", i);
	155		r = dp_i2c_adapter_init(dce, i);
	156		if (r != 0)
	157		return r;
	158
	159		dp->connected = true;
	160		atb_dp_state(dce->ddev.atb, dp->atb_dfp, true);
	161		continue;
	162		}
	163
	164		sense = hpd_sense(dce, dp->hpd);
	165		hpd_polarity_rearm(dce, dp->hpd, sense);
	166
	167		if (sense){
	168		s = "connected";
	169		} else {
	170		s = "disconnected";
	171		}
	172		dev_info(dce->ddev.dev, "dce6: \tdp%u is on hpd%u and is %s\n",
	173		i, dp->hpd, s);
	174
	175		r = dp_i2c_adapter_init(dce, i);
	176		if (r != 0)
	177		return r;
	178		dp->connected = sense;
	179		atb_dp_state(dce->ddev.atb, dp->atb_dfp, sense);
	180		}
	181		return 0;
	182		}
	183
	184		static int dp_dpm_off(struct dce6 *dce, unsigned i)
	185		{
	186		int r;
	187
	188		r = atb_trans_link_output_off(dce->ddev.atb, i);
	189		if (r != 0) {
	190		r = -DCE6_ERR;
	191		goto err;
	192		}
	193
	194		r = atb_enc_video(dce->ddev.atb, i, false);
	195		if (r != 0) {
	196		r = -DCE6_ERR;
	197		goto err;
	198		}
	199
	200		if (dce->dps[i].edp) {/* shutdown sink power only for edp */
	201		r = atb_trans_link_pwr(dce->ddev.atb, i, false);
	202		if (r != 0) {
	203		r = -DCE6_ERR;
	204		goto err;
	205		}
	206		}
	207
	208		r = atb_crtc_blank(dce->ddev.atb, i, true);
	209		if (r != 0) {
	210		r = -DCE6_ERR;
	211		goto err;
	212		}
	213
	214		r = atb_crtc_mem_req(dce->ddev.atb, i, false);
	215		if (r != 0) {
	216		r = -DCE6_ERR;
	217		goto err;
	218		}
	219
	220		r = atb_crtc(dce->ddev.atb, i, false);
	221		if (r != 0)
	222		r = -DCE6_ERR;
	223		err:
	224		return r;
	225		}
	226
	227		static int dps_used_pwr_on(struct dce6 *dce)
	228		{
	229		int r;
	230		unsigned i;
	231
	232		r = 0;
	233		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	234		if ((dce->dps_used & BIT(i)) == 0)
	235		continue;
	236		r = atb_trans_link_pwr(dce->ddev.atb, i , true);
	237		if (r != 0) {
	238		r = -DCE6_ERR;
	239		goto err;
	240		}
	241		}
	242		msleep(300);/* follow timing specs from AMD code */
	243		err:
	244		return r;
	245		}
	246
	247		static int dps_used_dpm_off(struct dce6 *dce)
	248		{
	249		int r;
	250		unsigned i;
	251
	252		r = 0;
	253		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	254		if ((dce->dps_used & BIT(i)) == 0)
	255		continue;
	256
	257		r = dp_dpm_off(dce, i);
	258		if (r != 0)
	259		break;
	260		}
	261		return r;
	262		}
	263
	264		static int dp_off(struct dce6 *dce, unsigned i)
	265		{
	266		int r;
	267
	268		r = atb_trans_link_output_off(dce->ddev.atb, i);
	269		if (r != 0) {
	270		r = -DCE6_ERR;
	271		goto err;
	272		}
	273
	274		r = atb_trans_link_pwr(dce->ddev.atb, i, false);
	275		if (r != 0) {
	276		r = -DCE6_ERR;
	277		goto err;
	278		}
	279
	280		r = atb_trans_link_off(dce->ddev.atb, i);
	281		if (r != 0) {
	282		r = -DCE6_ERR;
	283		goto err;
	284		}
	285
	286		r = atb_enc_video(dce->ddev.atb, i, false);
	287		if (r != 0) {
	288		r = -DCE6_ERR;
	289		goto err;
	290		}
	291
	292		r = atb_crtc_blank(dce->ddev.atb, i, true);
	293		if (r != 0) {
	294		r = -DCE6_ERR;
	295		goto err;
	296		}
	297
	298		r = atb_crtc_mem_req(dce->ddev.atb, i, false);
	299		if (r != 0) {
	300		r = -DCE6_ERR;
	301		goto err;
	302		}
	303
	304		r = atb_crtc(dce->ddev.atb, i, false);
	305		if (r != 0)
	306		r = -DCE6_ERR;
	307		err:
	308		return r;
	309		}
	310
	311		static int dps_unused_off(struct dce6 *dce)
	312		{
	313		int r;
	314		unsigned i;
	315
	316		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	317		if ((dce->dps_used & BIT(i)) != 0)
	318		continue;
	319
	320		r = dp_off(dce, i);
	321		if (r != 0)
	322		break;
	323		}
	324		return r;
	325		}
	326
	327		static int dps_connected_dpcd_info(struct dce6 *dce)
	328		{
	329		int r;
	330		unsigned i;
	331
	332		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	333		if ((dce->dps_used & BIT(i)) == 0)
	334		continue;
	335
	336		if (!dce->dps[i].connected)
	337		continue;
	338
	339		r = dpcd_info(dce, i);
	340		if (r != 0)
	341		break;
	342		}
	343		return r;
	344		}
	345
	346		int dce6_sink_mode_set(struct dce6 *dce, unsigned i, struct db_fb *db_fb)
	347		{
	348		int r;
	349
	350		lock(dce);
	351
	352		if ((dce->dps_used & BIT(i)) == 0) {
	353		r = -DCE6_ERR;
	354		goto unlock;
	355		}
	356
	357		if (!dce->dps[i].connected) {
	358		r = -DCE6_ERR;
	359		goto unlock;
	360		}
	361
	362		r = sink_mode_set(dce, i, db_fb);
	363		unlock:
	364		unlock(dce);
	365		return r;
	366		}
	367		EXPORT_SYMBOL_GPL(dce6_sink_mode_set);
	368
	369		int dce6_dp_dpm(struct dce6 *dce, unsigned i)
	370		{
	371		int r;
	372
	373		lock(dce);
	374
	375		if ((dce->dps_used & BIT(i)) == 0) {
	376		r = -DCE6_ERR;
	377		goto unlock;
	378		}
	379
	380		if (!dce->dps[i].connected) {
	381		r = -DCE6_ERR;
	382		goto unlock;
	383		}
	384		r = dp_dpm_off(dce, i);
	385		unlock:
	386		unlock(dce);
	387		return r;
	388		}
	389		EXPORT_SYMBOL_GPL(dce6_dp_dpm);
	390
	391		static void dps_used_off(struct dce6 *dce)
	392		{
	393		unsigned i;
	394
	395		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	396		if ((dce->dps_used & BIT(i)) == 0)
	397		continue;
	398
	399		dp_off(dce, i);
	400		}
	401		}
	402
	403		static void dps_edid_free(struct dce6 *dce)
	404		{
	405		unsigned i;
	406
	407		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	408		if (dce->dps[i].edid != NULL) {
	409		kfree(dce->dps[i].edid);
	410		dce->dps[i].edid = NULL;
	411		}
	412		}
	413
	414		static void edid(struct dce6 *dce, unsigned i)
	415		{
	416		int r;
	417
	418		r = alga_i2c_edid_fetch(dce->ddev.dev, &dce->dps[i].i2c_adapter,
	419		&dce->dps[i].edid);
	420		if (r != 0)
	421		dev_warn(dce->ddev.dev, "dce6: unable to fetch edid for dp%u\n",
	422		i);
	423		}
	424
	425		static void dps_connected_edid(struct dce6 *dce)
	426		{
	427		unsigned i;
	428
	429		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	430		if ((dce->dps_used & BIT(i)) == 0)
	431		continue;
	432
	433		if (!dce->dps[i].connected)
	434		continue;
	435
	436		/* it's not fatal to fail to get the edid */
	437		edid(dce, i);
	438		}
	439		}
	440
	441		int dce6_dps_info(struct dce6 *dce, unsigned *used, unsigned *connected,
	442		enum alga_pixel_fmt (*fmts)[CRTCS_N_MAX][ALGA_PIXEL_FMTS_MAX],
	443		struct alga_timing (*ts)[CRTCS_N_MAX][ALGA_TIMINGS_MAX])
	444		{
	445		int r;
	446		unsigned i;
	447
	448		lock(dce);
	449
	450		*used = dce->dps_used;
	451
	452		*connected = 0;
	453		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	454		if ((dce->dps_used & BIT(i)) == 0)
	455		continue;
	456
	457		if (!dce->dps[i].connected)
	458		continue;
	459
	460		*connected |= BIT(i);
	461		}
	462
	463		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	464		if ((*connected & BIT(i)) == 0)
	465		continue;
	466
	467		r = sink_timings(dce, i, &(*ts)[i]);
	468		if (r != 0) {
	469		*connected &= ~BIT(i);
	470		continue;
	471		}
	472		sink_pixel_fmts(dce, i, &(*fmts)[i]);
	473		}
	474		r = 0;
	475		unlock(dce);
	476		return r;
	477		}
	478		EXPORT_SYMBOL_GPL(dce6_dps_info);
	479
	480		void dce6_intrs_reset(struct dce6 *dce)
	481		{
	482		crtcs_intr_reset(dce);
	483		hpds_polarity_refresh(dce);
	484		}
	485		EXPORT_SYMBOL_GPL(dce6_intrs_reset);
	486
	487		#define WR32(v, of) dce->ddev.wr32(dce->ddev.dev, (v), (of))
	488		#define RR32(of) dce->ddev.rr32(dce->ddev.dev, (of))
	489		void dce6_vga_off(struct dce6 *dce)
	490		{
	491		unsigned i;
	492
	493		/* lockout access to vga mem through hdp */
	494		WR32(VGA_MEM_DIS, VGA_HDP_CTL);
	495		WR32(RR32(VGA_RENDER_CTL) & VGA_VSTATUS_CTL_CLR, VGA_RENDER_CTL);
	496		for (i = 0; i < dce->ddev.crtcs_n; ++i)
	497		WR32(0, regs_vga_ctl[i]);
	498
	499		}
	500		EXPORT_SYMBOL_GPL(dce6_vga_off);
	501
	502		static void dps_used_pf_init(struct dce6 *dce)
	503		{
	504		unsigned i;
	505
	506		for (i = 0; i < dce->ddev.crtcs_n; ++i) {
	507		if ((dce->dps_used & BIT(i)) == 0)
	508		continue;
	509
	510		init_waitqueue_head(&dce->dps[i].pf.event);
	511		atomic_set(&dce->dps[i].pf.occurred, 0);
	512		}
	513		}
	514
	515		int dce6_init(struct dce6 *dce, u32 dmif_addr_cfg)
	516		{
	517		int r;
	518
	519		/* configure the dce memory interface */
	520		WR32(dmif_addr_cfg, DMIF_ADDR_CFG);
	521
	522		mutex_init(&dce->mutex);
	523		spin_lock_init(&dce->irq.lock);
	524
	525		r = paths_parse(dce);
	526		if (r != 0)
	527		goto err;
	528
	529		dce_dump(dce);
	530
	531		r = trans_links_init(dce);
	532		if (r != 0)
	533		goto err;
	534
	535		r = atb_crtc_dcpll(dce->ddev.atb);
	536		if (r != 0)
	537		goto err;
	538
	539		hpds_init(dce);
	540
	541		dps_used_pf_init(dce);
	542
	543		r = dps_used_pwr_on(dce);
	544		if (r != 0)
	545		goto err;
	546
	547		r = dps_used_dpm_off(dce);
	548		if (r != 0)
	549		goto err;
	550
	551		r = dps_unused_off(dce);
	552		if (r != 0)
	553		goto err;
	554
	555		r = dps_sense(dce);
	556		if (r != 0)
	557		goto err;
	558
	559		r = dps_connected_dpcd_info(dce);
	560		if (r != 0)
	561		goto err;
	562
	563		dps_connected_edid(dce);
	564
	565		err:
	566		return r;
	567		}
	568		EXPORT_SYMBOL_GPL(dce6_init);
	569
	570		static void off(struct dce6 *dce)
	571		{
	572		dps_used_off(dce);
	573		hpds_off(dce);
	574		}
	575
	576		void dce6_shutdown(struct dce6 *dce)
	577		{
	578		lock(dce);
	579		off(dce);
	580		dps_edid_free(dce);
	581		dp_i2c_cleanup(dce);
	582		unlock(dce);
	583		}
	584		EXPORT_SYMBOL_GPL(dce6_shutdown);
	585
	586		struct dce6 *dce6_alloc(struct dce6_dev *ddev)
	587		{
	588		struct dce6 *dce;
	589
	590		dce = kzalloc(sizeof(struct dce6), GFP_KERNEL);
	591		if (!dce)
	592		return NULL;
	593		dce->ddev = *ddev;
	594		return dce;
	595		}
	596		EXPORT_SYMBOL_GPL(dce6_alloc);
	597
	598		static int __init init(void)
	599		{
	600		return 0;
	601		}
	602
	603		static void __exit cleanup(void)
	604		{
	605		}
	606
	607		module_init(init);
	608		module_exit(cleanup);
	609
	610		MODULE_AUTHOR("Sylvain Bertrand <digital.ragnarok@gmail.com>");
	611		MODULE_DESCRIPTION("AMD DCE6");
	612		MODULE_LICENSE("GPL");

File drivers/gpu/alga/amd/dce6/regs.h added (mode: 100644) (index 0000000..4559852)
	1		#ifndef _REGS_H
	2		#define _REGS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		/*
	10		* many masks are 0xfffffff because we need the info from AMD
	11		* or need to deduce from other values in the register
	12		*/
	13
	14		#define SET(n, x) (((x) << n##_SHIFT) & n##_MASK)
	15		#define GET(n, x) (((x) & n##_MASK) >> n##_SHIFT)
	16
	17		#define VGA_RENDER_CTL 0x300
	18		#define VGA_VSTATUS_CTL_MASK 0x00030000
	19		#define VGA_VSTATUS_CTL_CLR 0xfffcffff
	20
	21		#define VGA_MEM_BASE_ADDR 0x310
	22		#define VGA_MEM_BASE_ADDR_HIGH 0x324
	23
	24		#define VGA_HDP_CTL 0x328
	25		#define VGA_MEM_PAGE_SELECT_ENA BIT(0)
	26		#define VGA_MEM_DIS BIT(4)
	27		#define VGA_RBBM_LOCK_DIS BIT(8)
	28		#define VGA_SOFT_RESET BIT(16)
	29
	30		#define D0VGA_CTL 0x330
	31		#define DVGA_CTL_MODE_ENA BIT(0)
	32		#define DVGA_CTL_TIMING_SELECT BIT(8)
	33		#define DVGA_CTL_SYNC_POLARITY_SELECT BIT(9)
	34		#define DVGA_CTL_OVERSCAN_TIMING_SELECT BIT(10)
	35		#define DVGA_CTL_OVERSCAN_COLOR_ENA BIT(16)
	36		#define DVGA_CTL_ROTATE BIT(24)
	37		#define D1VGA_CTL 0x338
	38		#define D2VGA_CTL 0x3e0
	39		#define D3VGA_CTL 0x3e4
	40		#define D4VGA_CTL 0x3e8
	41		#define D5VGA_CTL 0x3ec
	42
	43		#define DMIF_ADDR_CFG 0xbd4
	44
	45		/*----------------------------------------------------------------------------*/
	46		#define HPD0_INT_STATUS 0x601c
	47		#define HPD0_INT_CTL 0x6020
	48		#define HPD0_CTL 0x6024
	49
	50		#define HPD1_INT_STATUS 0x6028
	51		#define HPD1_INT_CTL 0x602c
	52		#define HPD1_CTL 0x6030
	53
	54		#define HPD2_INT_STATUS 0x6034
	55		#define HPD2_INT_CTL 0x6038
	56		#define HPD2_CTL 0x603c
	57
	58		#define HPD3_INT_STATUS 0x6040
	59		#define HPD3_INT_CTL 0x6044
	60		#define HPD3_CTL 0x6048
	61
	62		#define HPD4_INT_STATUS 0x604c
	63		#define HPD4_INT_CTL 0x6050
	64		#define HPD4_CTL 0x6054
	65
	66		#define HPD5_INT_STATUS 0x6058
	67		#define HPD5_INT_CTL 0x605c
	68		#define HPD5_CTL 0x6060
	69
	70		#define HPDx_INT_STATUS BIT(0)
	71		#define HPDx_INT_STATUS_SENSE BIT(1)
	72		#define HPDx_INT_STATUS_RX BIT(8)
	73
	74		#define HPDx_INT_CTL_INT_ACK BIT(0)
	75		#define HPDx_INT_CTL_INT_POLARITY BIT(8)
	76		#define HPDx_INT_CTL_INT_ENA BIT(16)
	77		#define HPDx_INT_CTL_RX_INT_ACK BIT(20)
	78		#define HPDx_INT_CTL_RX_INT_ENA BIT(24)
	79
	80		/* timers are micro seconds */
	81		#define HPDx_CTL_CONN_TIMER_MASK 0xffffffff
	82		#define HPDx_CTL_CONN_TIMER_SHIFT 0
	83		#define HPDx_CTL_RX_INT_TIMER_MASK 0xffffffff
	84		#define HPDx_CTL_RX_INT_TIMER_SHIFT 16
	85		#define HPDx_CTL_ENA BIT(28)
	86		/*----------------------------------------------------------------------------*/
	87
	88		#define DISP0_INT_STATUS 0x60f4
	89		#define LB_D0_VLINE_INT BIT(2)
	90		#define LB_D0_VBLANK_INT BIT(3)
	91		#define HPD0_INT BIT(17)
	92		#define HPD0_RX_INT BIT(18)
	93		#define DACA_AUTODETECT_INT BIT(22)
	94		#define DACB_AUTODETECT_INT BIT(23)
	95		#define I2C_SW_DONE_INT BIT(24)
	96		#define I2C_HW_DONE_INT BIT(25)
	97		#define DISP1_INT_STATUS 0x60f8
	98		#define LB_D1_VLINE_INT BIT(2)
	99		#define LB_D1_VBLANK_INT BIT(3)
	100		#define HPD1_INT BIT(17)
	101		#define HPD1_RX_INT BIT(18)
	102		#define DISP_TIMER_INT BIT(24)
	103		#define DISP2_INT_STATUS 0x60fc
	104		#define LB_D2_VLINE_INT BIT(2)
	105		#define LB_D2_VBLANK_INT BIT(3)
	106		#define HPD2_INT BIT(17)
	107		#define HPD2_RX_INT BIT(18)
	108		#define DISP3_INT_STATUS 0x6100
	109		#define LB_D3_VLINE_INT BIT(2)
	110		#define LB_D3_VBLANK_INT BIT(3)
	111		#define HPD3_INT BIT(17)
	112		#define HPD3_RX_INT BIT(18)
	113		#define DISP4_INT_STATUS 0x614c
	114		#define LB_D4_VLINE_INT BIT(2)
	115		#define LB_D4_VBLANK_INT BIT(3)
	116		#define HPD4_INT BIT(17)
	117		#define HPD4_RX_INT BIT(18)
	118		#define DISP5_INT_STATUS 0x6150
	119		#define LB_D5_VLINE_INT BIT(2)
	120		#define LB_D5_VBLANK_INT BIT(3)
	121		#define HPD5_INT BIT(17)
	122		#define HPD5_RX_INT BIT(18)
	123
	124		#define GPIO_HPD_MASK 0x65b0
	125		#define GPIO_HPD_A 0x65b4
	126		#define GPIO_HPD_ENA 0x65b8
	127		#define GPIO_HPD_Y 0x65bc
	128
	129		#define DACA_AUTODETECT_INT_CTL 0x66c8
	130		#define DACB_AUTODETECT_INT_CTL 0x67c8
	131
	132		/* one line buffer for 2 dce blocks */
	133		#define DC_LB_MEM_SPLIT 0x6b0c
	134		#define DC_LB_MEM_CFG_MASK 0xffffffff
	135		#define DC_LB_MEM_CFG_SHIFT 20
	136
	137
	138		/*----------------------------------------------------------------------------*/
	139		/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
	140		#define CRTC0_REG_OF (0x6df0 - 0x6df0)
	141		#define CRTC1_REG_OF (0x79f0 - 0x6df0)
	142		/* many regs here */
	143		#define CRTC2_REG_OF (0x105f0 - 0x6df0)
	144		#define CRTC3_REG_OF (0x111f0 - 0x6df0)
	145		#define CRTC4_REG_OF (0x11df0 - 0x6df0)
	146		#define CRTC5_REG_OF (0x129f0 - 0x6df0)
	147		/*----------------------------------------------------------------------------*/
	148
	149		/* grph blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
	150		#define GRPH_ENA 0x6800
	151		#define GRPH_CTL 0x6804
	152		#define GRPH_DEPTH_MASK 0x00000003
	153		#define GRPH_DEPTH_SHIFT 0
	154		#define GRPH_DEPTH_8BPP 0
	155		#define GRPH_DEPTH_16BPP 1
	156		#define GRPH_DEPTH_32BPP 2
	157		#define GRPH_BANKS_N_MASK 0x0000000c
	158		#define GRPH_BANKS_N_SHIFT 2
	159		#define ADDR_SURF_2_BANK 0
	160		#define ADDR_SURF_4_BANK 1
	161		#define ADDR_SURF_8_BANK 2
	162		#define ADDR_SURF_16_BANK 3
	163		#define GRPH_Z_MASK 0x00000030
	164		#define GRPH_Z_SHIFT 4
	165		#define GRPH_BANK_W_MASK 0x000000c0
	166		#define GRPH_BANK_W_SHIFT 6
	167		#define ADDR_SURF_BANK_WIDTH_1 0
	168		#define ADDR_SURF_BANK_WIDTH_2 1
	169		#define ADDR_SURF_BANK_WIDTH_4 2
	170		#define ADDR_SURF_BANK_WIDTH_8 3
	171		#define GRPH_FMT_MASK 0x00000700
	172		#define GRPH_FMT_SHIFT 8
	173		/* 8 bpp */
	174		#define GRPH_FMT_INDEXED 0
	175		/* 16 bpp */
	176		#define GRPH_FMT_ARGB1555 0
	177		#define GRPH_FMT_ARGB565 1
	178		#define GRPH_FMT_ARGB4444 2
	179		#define GRPH_FMT_AI88 3
	180		#define GRPH_FMT_MONO16 4
	181		#define GRPH_FMT_BGRA5551 5
	182		/* 32 bpp */
	183		#define GRPH_FMT_ARGB8888 0
	184		#define GRPH_FMT_ARGB2101010 1
	185		#define GRPH_FMT_32BPP_DIG 2
	186		#define GRPH_FMT_8B_ARGB2101010 3
	187		#define GRPH_FMT_BGRA1010102 4
	188		#define GRPH_FMT_8B_BGRA1010102 5
	189		#define GRPH_FMT_RGB111110 6
	190		#define GRPH_FMT_BGR101111 7
	191		#define GRPH_BANK_H_MASK 0x00001800
	192		#define GRPH_BANK_H_SHIFT 11
	193		#define ADDR_SURF_BANK_HEIGHT_1 0
	194		#define ADDR_SURF_BANK_HEIGHT_2 1
	195		#define ADDR_SURF_BANK_HEIGHT_4 2
	196		#define ADDR_SURF_BANK_HEIGHT_8 3
	197		#define GRPH_TILE_SPLIT_MASK 0x0000e000
	198		#define GRPH_TILE_SPLIT_SHIFT 13
	199		#define ADDR_SURF_TILE_SPLIT_64B 0
	200		#define ADDR_SURF_TILE_SPLIT_128B 1
	201		#define ADDR_SURF_TILE_SPLIT_256B 2
	202		#define ADDR_SURF_TILE_SPLIT_512B 3
	203		#define ADDR_SURF_TILE_SPLIT_1KB 4
	204		#define ADDR_SURF_TILE_SPLIT_2KB 5
	205		#define ADDR_SURF_TILE_SPLIT_4KB 6
	206		#define GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000
	207		#define GRPH_MACRO_TILE_ASPECT_SHIFT 18
	208		#define ADDR_SURF_MACRO_TILE_ASPECT_1 0
	209		#define ADDR_SURF_MACRO_TILE_ASPECT_2 1
	210		#define ADDR_SURF_MACRO_TILE_ASPECT_4 2
	211		#define ADDR_SURF_MACRO_TILE_ASPECT_8 3
	212		#define GRPH_ARRAY_MODE_MASK 0x00700000
	213		#define GRPH_ARRAY_MODE_SHIFT 20
	214		#define GRPH_ARRAY_LINEAR_GENERAL 0
	215		#define GRPH_ARRAY_LINEAR_ALIGNED 1
	216		#define GRPH_ARRAY_1D_TILED_THIN1 2
	217		#define GRPH_ARRAY_2D_TILED_THIN1 4
	218		#define GRPH_PIPE_CFG_MASK 0x1f000000
	219		#define GRPH_PIPE_CFG_SHIFT 24
	220		#define ADDR_SURF_P2 0
	221		#define ADDR_SURF_P4_8x16 4
	222		#define ADDR_SURF_P4_16x16 5
	223		#define ADDR_SURF_P4_16x32 6
	224		#define ADDR_SURF_P4_32x32 7
	225		#define ADDR_SURF_P8_16x16_8x16 8
	226		#define ADDR_SURF_P8_16x32_8x16 9
	227		#define ADDR_SURF_P8_32x32_8x16 10
	228		#define ADDR_SURF_P8_16x32_16x16 11
	229		#define ADDR_SURF_P8_32x32_16x16 12
	230		#define ADDR_SURF_P8_32x32_16x32 13
	231		#define ADDR_SURF_P8_32x64_32x32 14
	232		#define GRPH_SWAP_CTL 0x680c
	233		#define GRPH_ENDIAN_SWAP_MASK 0x00000003
	234		#define GRPH_ENDIAN_SWAP_SHIFT 0
	235		#define GRPH_ENDIAN_NONE 0
	236		#define GRPH_ENDIAN_8IN16 1
	237		#define GRPH_ENDIAN_8IN32 2
	238		#define GRPH_ENDIAN_8IN64 3
	239		#define GRPH_RED_CROSSBAR_MASK 0x00000030
	240		#define GRPH_RED_CROSSBAR_SHIFT 4
	241		#define GRPH_RED_SEL_R 0
	242		#define GRPH_RED_SEL_G 1
	243		#define GRPH_RED_SEL_B 2
	244		#define GRPH_RED_SEL_A 3
	245		#define GRPH_GREEN_CROSSBAR_MASK 0x000000c0
	246		#define GRPH_GREEN_CROSSBAR_SHIFT 6
	247		#define GRPH_GREEN_SEL_G 0
	248		#define GRPH_GREEN_SEL_B 1
	249		#define GRPH_GREEN_SEL_A 2
	250		#define GRPH_GREEN_SEL_R 3
	251		#define GRPH_BLUE_CROSSBAR_MASK 0x00000300
	252		#define GRPH_BLUE_CROSSBAR_SHIFT 8
	253		#define GRPH_BLUE_SEL_B 0
	254		#define GRPH_BLUE_SEL_A 1
	255		#define GRPH_BLUE_SEL_R 2
	256		#define GRPH_BLUE_SEL_G 3
	257		#define GRPH_ALPHA_CROSSBAR_MASK 0x00000c00
	258		#define GRPH_ALPHA_CROSSBAR_SHIFT 10
	259		#define GRPH_ALPHA_SEL_A 0
	260		#define GRPH_ALPHA_SEL_R 1
	261		#define GRPH_ALPHA_SEL_G 2
	262		#define GRPH_ALPHA_SEL_B 3
	263		#define GRPH_PRIMARY_SURF_ADDR 0x6810
	264		#define GRPH_SECONDARY_SURF_ADDR 0x6814
	265		#define GRPH_DFQ_ENA BIT(0)
	266		#define GRPH_SURF_ADDR_MASK 0xffffff00
	267		#define GRPH_PITCH 0x6818
	268		#define GRPH_PRIMARY_SURF_ADDR_HIGH 0x681c
	269		#define GRPH_SECONDARY_SURF_ADDR_HIGH 0x6820
	270		#define GRPH_SURF_OF_X 0x6824
	271		#define GRPH_SURF_OF_Y 0x6828
	272		#define GRPH_X_START 0x682c
	273		#define GRPH_Y_START 0x6830
	274		#define GRPH_X_END 0x6834
	275		#define GRPH_Y_END 0x6838
	276		#define GRPH_UPDATE 0x6844
	277		#define GRPH_SURF_UPDATE_PENDING BIT(2)
	278		#define GRPH_UPDATE_LOCK BIT(16)
	279		#define GRPH_FLIP_CTL 0x6848
	280		#define GRPH_SURF_UPDATE_H_RETRACE_ENA BIT(0)
	281
	282		/* 0x6858 ... */
	283		#define GRPH_INT_STATUS 0x6858
	284		#define GRPH_PFLIP_INT_OCCURRED BIT(0)
	285		#define GRPH_PFLIP_INT_CLR BIT(8)
	286
	287		/* 0x685c ... */
	288		#define GRPH_INT_CTL 0x685c
	289		#define GRPH_PFLIP_INT_MASK BIT(0)
	290		#define GRPH_PFLIP_INT_TYPE BIT(8)
	291
	292		/* 0x69e0 ... */
	293		#define LUT_RW_MODE 0x69e0
	294		#define LUT_RW_IDX 0x69e4
	295		#define LUT_30_COLOR 0x69f0
	296		#define LUT_WR_ENA_MASK 0x69f8
	297		#define LUT_CTL 0x6a00
	298		#define LUT_BLACK_OF_BLUE 0x6a04
	299		#define LUT_BLACK_OF_GREEN 0x6a08
	300		#define LUT_BLACK_OF_RED 0x6a0c
	301		#define LUT_WHITE_OF_BLUE 0x6a10
	302		#define LUT_WHITE_OF_GREEN 0x6a14
	303		#define LUT_WHITE_OF_RED 0x6a18
	304
	305		/* 0x6b04 ... */
	306		#define DESKTOP_HEIGHT 0x6b04
	307		#define VLINE_START_END 0x6b08
	308		/* watermarks */
	309		#define PRIORITY_A_CNT 0x6b18
	310		#define PRIORITY_MARK_MASK 0x7fff
	311		#define PRIORITY_OFFBIT BIT(16)
	312		#define PRIORITY_ALWAYS_ON BIT(20)
	313		#define PRIORITY_B_CNT 0x6b1c
	314
	315
	316		/* 0x6b40 ... */
	317		#define INT_MASK 0x6b40
	318		#define VBLANK_INT_MASK BIT(0)
	319		#define VLINE_INT_MASK BIT(4)
	320
	321		/* 0x6bb8 ... */
	322		#define VLINE_STATUS 0x6bb8
	323		#define VLINE_OCCURRED BIT(0)
	324		#define VLINE_ACK BIT(4)
	325		#define VLINE_STAT BIT(12)
	326		#define VLINE_INT BIT(16)
	327		#define VLINE_INT_TYPE BIT(17)
	328
	329		/* 0x6bbc ... */
	330		#define VBLANK_STATUS 0x6bbc
	331		#define VBLANK_OCCURRED BIT(0)
	332		#define VBLANK_ACK BIT(4)
	333		#define VBLANK_STAT BIT(12)
	334		#define VBLANK_INT BIT(16)
	335		#define VBLANK_INT_TYPE BIT(17)
	336
	337		/* watermarks */
	338		#define DPG_PIPE_ARBITRATION_CTL_3 0x6cc8
	339		#define LATENCY_WATERMARK_MASK_MASK 0xffffffff
	340		#define LATENCY_WATERMARK_MASK_SHIFT 16
	341		#define DPG_PIPE_LATENCY_CTL 0x6ccc
	342		#define LATENCY_LOW_WATERMARK_MASK 0xffffffff
	343		#define LATENCY_LOW_WATERMARK_SHIFT 0
	344		#define LATENCY_HIGH_WATERMARK_MASK 0xffffffff
	345		#define LATENCY_HIGH_WATERMARK_SHIFT 16
	346
	347		#define VIEWPORT_START 0x6d70
	348		#define VIEWPORT_SZ 0x6d74
	349
	350		/* 0x6e70 ... */
	351		#define CRTC_CTL 0x6e70
	352		#define CRTC_MASTER_ENA BIT(0)
	353		#define CRTC_DISP_READ_REQ_DIS BIT(24)
	354		#define CRTC_STATUS_FRAME_CNT 0x6e98
	355		#define CRTC_UPDATE_LOCK 0x6ed4
	356		#define MASTER_UPDATE_MODE 0x6ef8
	357
	358		static u32 regs_lut_30_color[CRTCS_N_MAX] __attribute__ ((unused)) = {
	359		LUT_30_COLOR + CRTC0_REG_OF,
	360		LUT_30_COLOR + CRTC1_REG_OF,
	361		LUT_30_COLOR + CRTC2_REG_OF,
	362		LUT_30_COLOR + CRTC3_REG_OF,
	363		LUT_30_COLOR + CRTC4_REG_OF,
	364		LUT_30_COLOR + CRTC5_REG_OF
	365		};
	366
	367		static u32 regs_lut_rw_idx[CRTCS_N_MAX] __attribute__ ((unused)) = {
	368		LUT_RW_IDX + CRTC0_REG_OF,
	369		LUT_RW_IDX + CRTC1_REG_OF,
	370		LUT_RW_IDX + CRTC2_REG_OF,
	371		LUT_RW_IDX + CRTC3_REG_OF,
	372		LUT_RW_IDX + CRTC4_REG_OF,
	373		LUT_RW_IDX + CRTC5_REG_OF
	374		};
	375
	376		static u32 regs_lut_write_ena_mask[CRTCS_N_MAX] __attribute__ ((unused)) = {
	377		LUT_WR_ENA_MASK + CRTC0_REG_OF,
	378		LUT_WR_ENA_MASK + CRTC1_REG_OF,
	379		LUT_WR_ENA_MASK + CRTC2_REG_OF,
	380		LUT_WR_ENA_MASK + CRTC3_REG_OF,
	381		LUT_WR_ENA_MASK + CRTC4_REG_OF,
	382		LUT_WR_ENA_MASK + CRTC5_REG_OF
	383		};
	384
	385		static u32 regs_lut_rw_mode[CRTCS_N_MAX] __attribute__ ((unused)) = {
	386		LUT_RW_MODE + CRTC0_REG_OF,
	387		LUT_RW_MODE + CRTC1_REG_OF,
	388		LUT_RW_MODE + CRTC2_REG_OF,
	389		LUT_RW_MODE + CRTC3_REG_OF,
	390		LUT_RW_MODE + CRTC4_REG_OF,
	391		LUT_RW_MODE + CRTC5_REG_OF
	392		};
	393
	394		static u32 regs_lut_white_of_red[CRTCS_N_MAX] __attribute__ ((unused)) = {
	395		LUT_WHITE_OF_RED + CRTC0_REG_OF,
	396		LUT_WHITE_OF_RED + CRTC1_REG_OF,
	397		LUT_WHITE_OF_RED + CRTC2_REG_OF,
	398		LUT_WHITE_OF_RED + CRTC3_REG_OF,
	399		LUT_WHITE_OF_RED + CRTC4_REG_OF,
	400		LUT_WHITE_OF_RED + CRTC5_REG_OF
	401		};
	402
	403		static u32 regs_lut_white_of_green[CRTCS_N_MAX] __attribute__ ((unused)) = {
	404		LUT_WHITE_OF_GREEN + CRTC0_REG_OF,
	405		LUT_WHITE_OF_GREEN + CRTC1_REG_OF,
	406		LUT_WHITE_OF_GREEN + CRTC2_REG_OF,
	407		LUT_WHITE_OF_GREEN + CRTC3_REG_OF,
	408		LUT_WHITE_OF_GREEN + CRTC4_REG_OF,
	409		LUT_WHITE_OF_GREEN + CRTC5_REG_OF
	410		};
	411
	412		static u32 regs_lut_white_of_blue[CRTCS_N_MAX] __attribute__ ((unused)) = {
	413		LUT_WHITE_OF_BLUE + CRTC0_REG_OF,
	414		LUT_WHITE_OF_BLUE + CRTC1_REG_OF,
	415		LUT_WHITE_OF_BLUE + CRTC2_REG_OF,
	416		LUT_WHITE_OF_BLUE + CRTC3_REG_OF,
	417		LUT_WHITE_OF_BLUE + CRTC4_REG_OF,
	418		LUT_WHITE_OF_BLUE + CRTC5_REG_OF
	419		};
	420
	421		static u32 regs_lut_black_of_red[CRTCS_N_MAX] __attribute__ ((unused)) = {
	422		LUT_BLACK_OF_RED + CRTC0_REG_OF,
	423		LUT_BLACK_OF_RED + CRTC1_REG_OF,
	424		LUT_BLACK_OF_RED + CRTC2_REG_OF,
	425		LUT_BLACK_OF_RED + CRTC3_REG_OF,
	426		LUT_BLACK_OF_RED + CRTC4_REG_OF,
	427		LUT_BLACK_OF_RED + CRTC5_REG_OF
	428		};
	429
	430		static u32 regs_lut_black_of_green[CRTCS_N_MAX] __attribute__ ((unused)) = {
	431		LUT_BLACK_OF_GREEN + CRTC0_REG_OF,
	432		LUT_BLACK_OF_GREEN + CRTC1_REG_OF,
	433		LUT_BLACK_OF_GREEN + CRTC2_REG_OF,
	434		LUT_BLACK_OF_GREEN + CRTC3_REG_OF,
	435		LUT_BLACK_OF_GREEN + CRTC4_REG_OF,
	436		LUT_BLACK_OF_GREEN + CRTC5_REG_OF
	437		};
	438
	439		static u32 regs_lut_black_of_blue[CRTCS_N_MAX] __attribute__ ((unused)) = {
	440		LUT_BLACK_OF_BLUE + CRTC0_REG_OF,
	441		LUT_BLACK_OF_BLUE + CRTC1_REG_OF,
	442		LUT_BLACK_OF_BLUE + CRTC2_REG_OF,
	443		LUT_BLACK_OF_BLUE + CRTC3_REG_OF,
	444		LUT_BLACK_OF_BLUE + CRTC4_REG_OF,
	445		LUT_BLACK_OF_BLUE + CRTC5_REG_OF
	446		};
	447
	448		static u32 regs_lut_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	449		LUT_CTL + CRTC0_REG_OF,
	450		LUT_CTL + CRTC1_REG_OF,
	451		LUT_CTL + CRTC2_REG_OF,
	452		LUT_CTL + CRTC3_REG_OF,
	453		LUT_CTL + CRTC4_REG_OF,
	454		LUT_CTL + CRTC5_REG_OF
	455		};
	456
	457		static u32 regs_master_update_mode[CRTCS_N_MAX] __attribute__ ((unused)) = {
	458		MASTER_UPDATE_MODE + CRTC0_REG_OF,
	459		MASTER_UPDATE_MODE + CRTC1_REG_OF,
	460		MASTER_UPDATE_MODE + CRTC2_REG_OF,
	461		MASTER_UPDATE_MODE + CRTC3_REG_OF,
	462		MASTER_UPDATE_MODE + CRTC4_REG_OF,
	463		MASTER_UPDATE_MODE + CRTC5_REG_OF
	464		};
	465
	466		static u32 regs_grph_flip_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	467		GRPH_FLIP_CTL + CRTC0_REG_OF,
	468		GRPH_FLIP_CTL + CRTC1_REG_OF,
	469		GRPH_FLIP_CTL + CRTC2_REG_OF,
	470		GRPH_FLIP_CTL + CRTC3_REG_OF,
	471		GRPH_FLIP_CTL + CRTC4_REG_OF,
	472		GRPH_FLIP_CTL + CRTC5_REG_OF
	473		};
	474
	475		static u32 regs_viewport_sz[CRTCS_N_MAX] __attribute__ ((unused)) = {
	476		VIEWPORT_SZ + CRTC0_REG_OF,
	477		VIEWPORT_SZ + CRTC1_REG_OF,
	478		VIEWPORT_SZ + CRTC2_REG_OF,
	479		VIEWPORT_SZ + CRTC3_REG_OF,
	480		VIEWPORT_SZ + CRTC4_REG_OF,
	481		VIEWPORT_SZ + CRTC5_REG_OF
	482		};
	483
	484		static u32 regs_viewport_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	485		VIEWPORT_START + CRTC0_REG_OF,
	486		VIEWPORT_START + CRTC1_REG_OF,
	487		VIEWPORT_START + CRTC2_REG_OF,
	488		VIEWPORT_START + CRTC3_REG_OF,
	489		VIEWPORT_START + CRTC4_REG_OF,
	490		VIEWPORT_START + CRTC5_REG_OF
	491		};
	492
	493		static u32 regs_desktop_height[CRTCS_N_MAX] __attribute__ ((unused)) = {
	494		DESKTOP_HEIGHT + CRTC0_REG_OF,
	495		DESKTOP_HEIGHT + CRTC1_REG_OF,
	496		DESKTOP_HEIGHT + CRTC2_REG_OF,
	497		DESKTOP_HEIGHT + CRTC3_REG_OF,
	498		DESKTOP_HEIGHT + CRTC4_REG_OF,
	499		DESKTOP_HEIGHT + CRTC5_REG_OF
	500		};
	501
	502		static u32 regs_grph_ena[CRTCS_N_MAX] __attribute__ ((unused)) = {
	503		GRPH_ENA + CRTC0_REG_OF,
	504		GRPH_ENA + CRTC1_REG_OF,
	505		GRPH_ENA + CRTC2_REG_OF,
	506		GRPH_ENA + CRTC3_REG_OF,
	507		GRPH_ENA + CRTC4_REG_OF,
	508		GRPH_ENA + CRTC5_REG_OF
	509		};
	510
	511		static u32 regs_grph_pitch[CRTCS_N_MAX] __attribute__ ((unused)) = {
	512		GRPH_PITCH + CRTC0_REG_OF,
	513		GRPH_PITCH + CRTC1_REG_OF,
	514		GRPH_PITCH + CRTC2_REG_OF,
	515		GRPH_PITCH + CRTC3_REG_OF,
	516		GRPH_PITCH + CRTC4_REG_OF,
	517		GRPH_PITCH + CRTC5_REG_OF
	518		};
	519
	520		static u32 regs_grph_y_end[CRTCS_N_MAX] __attribute__ ((unused)) = {
	521		GRPH_Y_END + CRTC0_REG_OF,
	522		GRPH_Y_END + CRTC1_REG_OF,
	523		GRPH_Y_END + CRTC2_REG_OF,
	524		GRPH_Y_END + CRTC3_REG_OF,
	525		GRPH_Y_END + CRTC4_REG_OF,
	526		GRPH_Y_END + CRTC5_REG_OF
	527		};
	528
	529		static u32 regs_grph_x_end[CRTCS_N_MAX] __attribute__ ((unused)) = {
	530		GRPH_X_END + CRTC0_REG_OF,
	531		GRPH_X_END + CRTC1_REG_OF,
	532		GRPH_X_END + CRTC2_REG_OF,
	533		GRPH_X_END + CRTC3_REG_OF,
	534		GRPH_X_END + CRTC4_REG_OF,
	535		GRPH_X_END + CRTC5_REG_OF
	536		};
	537
	538		static u32 regs_grph_y_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	539		GRPH_Y_START + CRTC0_REG_OF,
	540		GRPH_Y_START + CRTC1_REG_OF,
	541		GRPH_Y_START + CRTC2_REG_OF,
	542		GRPH_Y_START + CRTC3_REG_OF,
	543		GRPH_Y_START + CRTC4_REG_OF,
	544		GRPH_Y_START + CRTC5_REG_OF
	545		};
	546
	547		static u32 regs_grph_x_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	548		GRPH_X_START + CRTC0_REG_OF,
	549		GRPH_X_START + CRTC1_REG_OF,
	550		GRPH_X_START + CRTC2_REG_OF,
	551		GRPH_X_START + CRTC3_REG_OF,
	552		GRPH_X_START + CRTC4_REG_OF,
	553		GRPH_X_START + CRTC5_REG_OF
	554		};
	555
	556		static u32 regs_grph_surf_of_y[CRTCS_N_MAX] __attribute__ ((unused)) = {
	557		GRPH_SURF_OF_Y + CRTC0_REG_OF,
	558		GRPH_SURF_OF_Y + CRTC1_REG_OF,
	559		GRPH_SURF_OF_Y + CRTC2_REG_OF,
	560		GRPH_SURF_OF_Y + CRTC3_REG_OF,
	561		GRPH_SURF_OF_Y + CRTC4_REG_OF,
	562		GRPH_SURF_OF_Y + CRTC5_REG_OF
	563		};
	564
	565		static u32 regs_grph_surf_of_x[CRTCS_N_MAX] __attribute__ ((unused)) = {
	566		GRPH_SURF_OF_X + CRTC0_REG_OF,
	567		GRPH_SURF_OF_X + CRTC1_REG_OF,
	568		GRPH_SURF_OF_X + CRTC2_REG_OF,
	569		GRPH_SURF_OF_X + CRTC3_REG_OF,
	570		GRPH_SURF_OF_X + CRTC4_REG_OF,
	571		GRPH_SURF_OF_X + CRTC5_REG_OF
	572		};
	573
	574		static u32 regs_grph_swap_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	575		GRPH_SWAP_CTL + CRTC0_REG_OF,
	576		GRPH_SWAP_CTL + CRTC1_REG_OF,
	577		GRPH_SWAP_CTL + CRTC2_REG_OF,
	578		GRPH_SWAP_CTL + CRTC3_REG_OF,
	579		GRPH_SWAP_CTL + CRTC4_REG_OF,
	580		GRPH_SWAP_CTL + CRTC5_REG_OF
	581		};
	582
	583		static u32 regs_grph_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	584		GRPH_CTL + CRTC0_REG_OF,
	585		GRPH_CTL + CRTC1_REG_OF,
	586		GRPH_CTL + CRTC2_REG_OF,
	587		GRPH_CTL + CRTC3_REG_OF,
	588		GRPH_CTL + CRTC4_REG_OF,
	589		GRPH_CTL + CRTC5_REG_OF
	590		};
	591
	592		static u32 regs_grph_update[CRTCS_N_MAX] __attribute__ ((unused)) = {
	593		GRPH_UPDATE + CRTC0_REG_OF,
	594		GRPH_UPDATE + CRTC1_REG_OF,
	595		GRPH_UPDATE + CRTC2_REG_OF,
	596		GRPH_UPDATE + CRTC3_REG_OF,
	597		GRPH_UPDATE + CRTC4_REG_OF,
	598		GRPH_UPDATE + CRTC5_REG_OF
	599		};
	600
	601		static u32 regs_crtc_status_frame_cnt[CRTCS_N_MAX]
	602		__attribute__ ((unused)) = {
	603		CRTC_STATUS_FRAME_CNT + CRTC0_REG_OF,
	604		CRTC_STATUS_FRAME_CNT + CRTC1_REG_OF,
	605		CRTC_STATUS_FRAME_CNT + CRTC2_REG_OF,
	606		CRTC_STATUS_FRAME_CNT + CRTC3_REG_OF,
	607		CRTC_STATUS_FRAME_CNT + CRTC4_REG_OF,
	608		CRTC_STATUS_FRAME_CNT + CRTC5_REG_OF
	609		};
	610
	611		static u32 regs_crtc_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	612		CRTC_CTL + CRTC0_REG_OF,
	613		CRTC_CTL + CRTC1_REG_OF,
	614		CRTC_CTL + CRTC2_REG_OF,
	615		CRTC_CTL + CRTC3_REG_OF,
	616		CRTC_CTL + CRTC4_REG_OF,
	617		CRTC_CTL + CRTC5_REG_OF
	618		};
	619
	620		static u32 regs_grph_primary_surf_addr_high[CRTCS_N_MAX]
	621		__attribute__ ((unused)) = {
	622		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC0_REG_OF,
	623		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC1_REG_OF,
	624		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC2_REG_OF,
	625		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC3_REG_OF,
	626		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC4_REG_OF,
	627		GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC5_REG_OF
	628		};
	629
	630		static u32 regs_grph_secondary_surf_addr_high[CRTCS_N_MAX]
	631		__attribute__ ((unused)) = {
	632		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC0_REG_OF,
	633		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC1_REG_OF,
	634		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC2_REG_OF,
	635		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC3_REG_OF,
	636		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC4_REG_OF,
	637		GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC5_REG_OF
	638		};
	639
	640		static u32 regs_grph_primary_surf_addr[CRTCS_N_MAX]
	641		__attribute__ ((unused)) = {
	642		GRPH_PRIMARY_SURF_ADDR + CRTC0_REG_OF,
	643		GRPH_PRIMARY_SURF_ADDR + CRTC1_REG_OF,
	644		GRPH_PRIMARY_SURF_ADDR + CRTC2_REG_OF,
	645		GRPH_PRIMARY_SURF_ADDR + CRTC3_REG_OF,
	646		GRPH_PRIMARY_SURF_ADDR + CRTC4_REG_OF,
	647		GRPH_PRIMARY_SURF_ADDR + CRTC5_REG_OF
	648		};
	649
	650		static u32 regs_grph_secondary_surf_addr[CRTCS_N_MAX]
	651		__attribute__ ((unused)) = {
	652		GRPH_SECONDARY_SURF_ADDR + CRTC0_REG_OF,
	653		GRPH_SECONDARY_SURF_ADDR + CRTC1_REG_OF,
	654		GRPH_SECONDARY_SURF_ADDR + CRTC2_REG_OF,
	655		GRPH_SECONDARY_SURF_ADDR + CRTC3_REG_OF,
	656		GRPH_SECONDARY_SURF_ADDR + CRTC4_REG_OF,
	657		GRPH_SECONDARY_SURF_ADDR + CRTC5_REG_OF
	658		};
	659
	660		static u32 regs_hpd_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	661		HPD0_INT_STATUS,
	662		HPD1_INT_STATUS,
	663		HPD2_INT_STATUS,
	664		HPD3_INT_STATUS,
	665		HPD4_INT_STATUS,
	666		HPD5_INT_STATUS
	667		};
	668
	669		static u32 regs_hpd_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	670		HPD0_INT_CTL,
	671		HPD1_INT_CTL,
	672		HPD2_INT_CTL,
	673		HPD3_INT_CTL,
	674		HPD4_INT_CTL,
	675		HPD5_INT_CTL
	676		};
	677
	678		static u32 regs_hpd_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	679		HPD0_CTL,
	680		HPD1_CTL,
	681		HPD2_CTL,
	682		HPD3_CTL,
	683		HPD4_CTL,
	684		HPD5_CTL
	685		};
	686
	687		static u32 regs_crtc_int_mask[CRTCS_N_MAX] __attribute__ ((unused)) = {
	688		INT_MASK + CRTC0_REG_OF,
	689		INT_MASK + CRTC1_REG_OF,
	690		INT_MASK + CRTC2_REG_OF,
	691		INT_MASK + CRTC3_REG_OF,
	692		INT_MASK + CRTC4_REG_OF,
	693		INT_MASK + CRTC5_REG_OF
	694		};
	695
	696		static u32 regs_crtc_grph_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	697		GRPH_INT_CTL + CRTC0_REG_OF,
	698		GRPH_INT_CTL + CRTC1_REG_OF,
	699		GRPH_INT_CTL + CRTC2_REG_OF,
	700		GRPH_INT_CTL + CRTC3_REG_OF,
	701		GRPH_INT_CTL + CRTC4_REG_OF,
	702		GRPH_INT_CTL + CRTC5_REG_OF
	703		};
	704
	705		static u32 regs_disp_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	706		DISP0_INT_STATUS,
	707		DISP1_INT_STATUS,
	708		DISP2_INT_STATUS,
	709		DISP3_INT_STATUS,
	710		DISP4_INT_STATUS,
	711		DISP5_INT_STATUS
	712		};
	713
	714		static u32 regs_crtc_grph_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	715		GRPH_INT_STATUS + CRTC0_REG_OF,
	716		GRPH_INT_STATUS + CRTC1_REG_OF,
	717		GRPH_INT_STATUS + CRTC2_REG_OF,
	718		GRPH_INT_STATUS + CRTC3_REG_OF,
	719		GRPH_INT_STATUS + CRTC4_REG_OF,
	720		GRPH_INT_STATUS + CRTC5_REG_OF
	721		};
	722
	723		static u32 regs_crtc_vblank_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	724		VBLANK_STATUS + CRTC0_REG_OF,
	725		VBLANK_STATUS + CRTC1_REG_OF,
	726		VBLANK_STATUS + CRTC2_REG_OF,
	727		VBLANK_STATUS + CRTC3_REG_OF,
	728		VBLANK_STATUS + CRTC4_REG_OF,
	729		VBLANK_STATUS + CRTC5_REG_OF
	730		};
	731
	732		static u32 regs_crtc_vline_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	733		VLINE_STATUS + CRTC0_REG_OF,
	734		VLINE_STATUS + CRTC1_REG_OF,
	735		VLINE_STATUS + CRTC2_REG_OF,
	736		VLINE_STATUS + CRTC3_REG_OF,
	737		VLINE_STATUS + CRTC4_REG_OF,
	738		VLINE_STATUS + CRTC5_REG_OF
	739		};
	740
	741		static u32 regs_crtc_update_lock[CRTCS_N_MAX] __attribute__ ((unused)) = {
	742		CRTC_UPDATE_LOCK + CRTC0_REG_OF,
	743		CRTC_UPDATE_LOCK + CRTC1_REG_OF,
	744		CRTC_UPDATE_LOCK + CRTC2_REG_OF,
	745		CRTC_UPDATE_LOCK + CRTC3_REG_OF,
	746		CRTC_UPDATE_LOCK + CRTC4_REG_OF,
	747		CRTC_UPDATE_LOCK + CRTC5_REG_OF
	748		};
	749
	750		static u32 vals_hpd_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	751		HPD0_INT,
	752		HPD1_INT,
	753		HPD2_INT,
	754		HPD3_INT,
	755		HPD4_INT,
	756		HPD5_INT
	757		};
	758
	759		static u32 vals_lb_d_vblank_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	760		LB_D0_VBLANK_INT,
	761		LB_D1_VBLANK_INT,
	762		LB_D2_VBLANK_INT,
	763		LB_D3_VBLANK_INT,
	764		LB_D4_VBLANK_INT,
	765		LB_D5_VBLANK_INT
	766		};
	767
	768		static u32 vals_lb_d_vline_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	769		LB_D0_VLINE_INT,
	770		LB_D1_VLINE_INT,
	771		LB_D2_VLINE_INT,
	772		LB_D3_VLINE_INT,
	773		LB_D4_VLINE_INT,
	774		LB_D5_VLINE_INT
	775		};
	776
	777		static u32 regs_vga_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	778		D0VGA_CTL,
	779		D1VGA_CTL,
	780		D2VGA_CTL,
	781		D3VGA_CTL,
	782		D4VGA_CTL,
	783		D5VGA_CTL
	784		};
	785		#endif

File drivers/gpu/alga/amd/dce6/silicium_blks/dce added (mode: 100644) (index 0000000..8f70a72)
	1		ate: Wed, 25 May 2011 12:07:33 -0400
	2		From: Alex Deucher <alexdeucher@gmail.com>
	3		Cc: dri-devel@lists.freedesktop.org
	4
	5		The general idea is this:
	6		framebuffer -> crtc -> encoder -> connector -> monitor
	7
	8		- The framebuffer is just a buffer vram that has an image encoded in
	9		it as an array of pixels.
	10		- The crtc reads the data out of the framebuffer and generates the
	11		video mode timing in conjunction with a PLL. The crtc also determines
	12		what part of the framebuffer is read; e.g., when multi-head is
	13		enabled, each crtc scans out of a different part of vram; in clone
	14		mode, each crtc scans out of the same part of vram.
	15		- The encoder takes the digital bitstream from the crtc and converts
	16		it to the appropriate analog levels for transmission across the
	17		connector to the monitor.
	18		- The connector provides the appropriate physical plug (HDMI, DVI-D,
	19		VGA, S-video, etc.) for the monitor to connect to.
	20
	21		crtcs are usually routeable and can be connected to one or many
	22		encoders simultaneously. The encoders can also be connected to one or
	23		more connectors (e.g., you might have a single TMDS encoder that is
	24		connected to the digital portion of a DVI-I port and also to a HDMI
	25		port, or you might have a DAC that is connected to a VGA port and an
	26		S-video port). Finally i2c lines are associated with connectors,
	27		since generally the i2c pins are wired to the connector and in many
	28		cases, each connectors has it's own i2c line. For example, you might
	29		have a single TMDS encoder that is wired to a DVI-D port with its own
	30		i2c line and an HDMI port with its own i2c line. Each connector may
	31		have it's own hotplug (HPD) pin as well. That way you could query the
	32		EDID from each connector separately for example.
	33
	34		Is the sii9022 being driven by the output of a DVO encoder from your
	35		display hw? If so your display path would look like:
	36
	37		crtc -> DVO (master encoder) -> sii9022 (slave encoder) -> HDMI plug -> monitor
	38
	39		The general GPU driver might register the i2c buses that are used by
	40		the various parts (encoder, connector), then it's just a matter of
	41		plugging in the right parts for each component (e.g. you'd hook up the
	42		sii9022 i2c control bus to the DVO encoder, and the ddc i2c bus to the
	43		hdmi connector object, etc.).
	44
	45		I hope this helps.
	46
	47		--------------------------------------------------------------------------------
	48
	49		DIG Encoder/Transmitter Setup
	50
	51		links A/C/E: primary
	52		links B/D/F: secondary
	53		"primary link + secondary link" means dual link mode, both links are used
	54
	55		DCE 4.0/5.0
	56		- 3 DIG transmitter blocks UNIPHY0/1/2 (links A/C/E and B/D/F).
	57		Supports up to 6 digital outputs
	58		- 6 DIG encoder blocks.
	59		- DIG to PHY mapping is hardcoded
	60		DIG1 drives UNIPHY0 link A, A+B
	61		DIG2 drives UNIPHY0 link B
	62		DIG3 drives UNIPHY1 link C, C+D
	63		DIG4 drives UNIPHY1 link D
	64		DIG5 drives UNIPHY2 link E, E+F
	65		DIG6 drives UNIPHY2 link F
	66
	67		DCE 4.1
	68		- 3 DIG transmitter blocks UNIPHY0/1/2 (links A/C/E and B/D/F).
	69		Supports up to 6 digital outputs
	70		- 2 DIG encoder blocks.
	71		DIG1/2 can drive UNIPHY0/1/2 link A/C/E or link B/D/F
	72
	73		Routing
	74		crtc -> dig encoder -> UNIPHY (1 or 2 links)
	75
	76		Examples:
	77		crtc1 -> dig1 -> UNIPHY0 link B -> DP
	78		crtc0 -> dig1 -> UNIPHY2 link E -> LVDS
	79		crtc1 -> dig2 -> UNIPHY1 link C+D -> TMDS/HDMI
	80
	81		--------------------------------------------------------------------------------
	82
	83		The DCE sub-blocks do support an optional atomic update of their registers,
	84		namely it can be transaction based.
	85
	86		For instance when programming the frame buffer, you lock, namely start a
	87		transaction, configure the registers, then unlock, namely commit the changes.
	88
	89		Page flipping is done like this with an addionnal contraint: you have to
	90		wait for a specific bit to go high before committing the changes (UPDATE_PENDING
	91		bit).

File drivers/gpu/alga/amd/dce6/silicium_blks/plls added (mode: 100644) (index 0000000..aaf5eaa)
	1		There are 3 Phase Locked Loops to drive the DCE:
	2		o pll0
	3		o pll1
	4		o dcpll
	5
	6		The reference signal for those 3 plls is the core oscillator. You get the
	7		frequency of the core oscillator from the atombios firmware_info tables.
	8
	9		Those plls have 3 dividers (see www for pll dividers):
	10		- the reference divider
	11		- the feedback fractional divider
	12		- the post divider
	13
	14		The feedback fractional divider is a base feeback divider integer plus its
	15		fractional part (20bits):
	16		feedback fractional divider = base_integer.fractional_20bits
	17
	18		Then, the output frequency of one of the pll is:
	19		(core oscillator freq) * (feedback fractional div/reference div) * (1/post div)
	20
	21		For displayport support in the uniphy block, you may have an external
	22		oscillator to drive it. The dcpll should be used if no external oscillator is
	23		present.

File drivers/gpu/alga/amd/dce6/sink.c added (mode: 100644) (index 0000000..9e9acb7)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/i2c.h>
	7		#include <linux/slab.h>
	8		#include <linux/delay.h>
	9		#include <asm/uaccess.h>
	10
	11		#include <alga/alga.h>
	12		#include <alga/pixel_fmts.h>
	13		#include <alga/timing.h>
	14		#include <alga/dp.h>
	15		#include <alga/edid.h>
	16		#include <alga/amd/atombios/atb.h>
	17		#include <alga/amd/atombios/dce.h>
	18		#include <alga/amd/dce6/dce6.h>
	19		#include <alga/amd/dce6/dce6_dev.h>
	20
	21		#include "dce6.h"
	22		#include "dp_link_train.h"
	23		#include "crtc.h"
	24
	25
	26		/* code related to the displayport sink, usually the display */
	27
	28		int sink_timings(struct dce6 *dce, unsigned i,
	29		struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	30		{
	31		int r;
	32
	33		if (dce->dps[i].edid == NULL) {
	34		alga_dp_safe_timing(ts);
	35		return 0;
	36		}
	37		r = alga_edid_timings(dce->ddev.dev, dce->dps[i].edid, ts);
	38		if (r != 0)
	39		return -DCE6_ERR;
	40		return 0;
	41		}
	42
	43		void sink_pixel_fmts(struct dce6 *dce, unsigned i,
	44		enum alga_pixel_fmt (*fmts)[ALGA_PIXEL_FMTS_MAX])
	45		{
	46		int bpc;
	47		unsigned j;
	48
	49		for (j = 0; j < ALGA_PIXEL_FMTS_MAX; ++j)
	50		(*fmts)[i] = ALGA_PIXEL_FMT_INVALID;
	51
	52		if (dce->dps[i].edid == NULL) {
	53		(*fmts)[0] = ALGA_ARGB6666;
	54		return;
	55		}
	56
	57		bpc = alga_edid_bpc(dce->ddev.dev, dce->dps[i].edid);
	58		if (bpc == 0) {
	59		(*fmts)[0] = ALGA_ARGB6666;
	60		return;
	61		}
	62
	63		j = 0;
	64		switch (bpc) { /* we are not getting above ALGA_PIXEL_FMTS_MAX */
	65		case 16:
	66		case 14:
	67		case 12:
	68		case 10:
	69		(*fmts)[j++] = ALGA_ARGB2101010;
	70		case 8:
	71		(*fmts)[j++] = ALGA_ARGB8888;
	72		case 6:
	73		(*fmts)[j++] = ALGA_ARGB6666;
	74		}
	75		}
	76
	77		static unsigned sink_link_lanes_n(struct dce6 *dce, unsigned i)
	78		{
	79		switch (dce->dps[i].dpcd_info[DPCD_MAX_LANE_COUNT]
	80		& DPCD_MAX_LANE_COUNT_MASK) {
	81		case 0x1:
	82		return 1;
	83		case 0x2:
	84		return 2;
	85		case 0x4:
	86		return 4;
	87		}
	88		unreachable();
	89		}
	90
	91		/*
	92		* link configuration heuristics
	93		* help to avoid signal power shortage side effects and more, in theory...
	94		* Others heuristics would be a sequence of minimum number of lanes for
	95		* each supported link rate able to handle the video mode bandwidth.
	96		*/
	97		static void link_rate_cfg(struct dce6 *dce, unsigned i, struct db_fb *db_fb)
	98		{
	99		enum link_rate max;
	100		unsigned link_rate_bw_max;
	101		unsigned bw;
	102		unsigned long bw_overhead;
	103
	104		/* Mbits per second for the timing/pixel format (pixel clk is in kHz) */
	105		bw = db_fb->timing.pixel_clk * 8 * alga_pixel_fmts_sz[db_fb->pixel_fmt]
	106		/ 1000;
	107		/* +20 % average overhead: (8b/10b) encoding and more... */
	108		bw_overhead = 120 * bw / 100;
	109
	110		/*
	111		* the transmitter has 4 lanes, then the limiting factor is the
	112		* sink lane number
	113		*/
	114		dce->dps[i].lanes_n = sink_link_lanes_n(dce, i);
	115
	116		/* max link rate sink and transmitter can support */
	117		if (dce->dps[i].dpcd_info[DPCD_MAX_LINK_RATE]
	118		>= dce->dps[i].trans_link_rate_max)
	119		max = dce->dps[i].trans_link_rate_max;
	120		else
	121		max = (enum link_rate)(
	122		dce->dps[i].dpcd_info[DPCD_MAX_LINK_RATE]);
	123
	124		/*
	125		* heuristics step one: we want to spread that bandwidth plus the
	126		* overhead on maximum lanes at the lowest link rate
	127		*/
	128		link_rate_bw_max = GHZ_1_62 * DP_LINK_RATE_UNIT_MHZ
	129		* dce->dps[i].lanes_n;
	130		if ((bw_overhead < link_rate_bw_max) || (GHZ_1_62 == max)) {
	131		dce->dps[i].link_rate = GHZ_1_62;
	132		} else {
	133		link_rate_bw_max = GHZ_2_7 * DP_LINK_RATE_UNIT_MHZ
	134		* dce->dps[i].lanes_n;
	135		if ((bw_overhead < link_rate_bw_max) || (GHZ_2_7 == max)) {
	136		dce->dps[i].link_rate = GHZ_2_7;
	137		} else {
	138		link_rate_bw_max = GHZ_5_4 * DP_LINK_RATE_UNIT_MHZ
	139		* dce->dps[i].lanes_n;
	140		if ((bw_overhead < link_rate_bw_max)
	141		|| (GHZ_5_4 == max)) {
	142		dce->dps[i].link_rate = GHZ_5_4;
	143		}
	144		}
	145		}
	146
	147		/*
	148		* heuristics step two : see if we can reduce the number of lanes: 1 or
	149		* 2. dce->dps[i].lanes is set to the max number of sink lanes.
	150		*/
	151		if ((dce->dps[i].lanes_n == 2) || (dce->dps[i].lanes_n == 4)) {
	152		/* bw plus overhead fits on 1 lane? */
	153		link_rate_bw_max = dce->dps[i].link_rate
	154		* DP_LINK_RATE_UNIT_MHZ * 1;
	155		if (bw_overhead < link_rate_bw_max) {
	156		dce->dps[i].lanes_n = 1;
	157		} else if (dce->dps[i].lanes_n == 4) {
	158		/* bw plus overhead fits on 2 lanes? */
	159		link_rate_bw_max = dce->dps[i].link_rate
	160		* DP_LINK_RATE_UNIT_MHZ * 2;
	161		if (bw_overhead < link_rate_bw_max) {
	162		dce->dps[i].lanes_n = 2;
	163		}
	164		}
	165		}
	166		dev_info(dce->ddev.dev, "dce6: dp%u link selected configuration is"
	167		" %u lanes at %s\n", i, dce->dps[i].lanes_n,
	168		link_rate_names(dce->dps[i].link_rate));
	169		}
	170
	171		int sink_mode_set(struct dce6 *dce, unsigned i, struct db_fb *db_fb)
	172		{
	173		struct atombios *atb;
	174		int r;
	175
	176		atb = dce->ddev.atb;
	177
	178		link_rate_cfg(dce, i, db_fb); /* heuristics for link rate/lanes cfg */
	179
	180		atb_lock(atb, true);
	181
	182		/* prepare encoder and transmitter */
	183		r = atb_trans_link_output_off(atb, i);
	184		if (r != 0) {
	185		dev_err(dce->ddev.dev, "dce6:dp%u: unable to switch off "
	186		"transmitter link output\n", i);
	187		r = -DCE6_ERR;
	188		goto unlock_atb;
	189		}
	190
	191		r = atb_enc_video(atb, i, false);
	192		if (r != 0) {
	193		dev_err(dce->ddev.dev, "dce6:dp%u: unable to switch off "
	194		"encoder video output\n", i);
	195		r = -DCE6_ERR;
	196		goto unlock_atb;
	197		}
	198
	199		if (dce->dps[i].edp) {
	200		r = atb_trans_link_pwr(atb, i, true);
	201		if (r != 0) {
	202		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable "
	203		"power pins on connector\n", i);
	204		r = -DCE6_ERR;
	205		goto unlock_atb;
	206		}
	207		msleep(300);/* follow timing specs from AMD code */
	208		}
	209
	210		r = atb_enc_crtc_src(atb, i);
	211		if (r != 0) {
	212		dev_err(dce->ddev.dev, "dce6:dp%u: unable to link crtc and "
	213		"encoder together\n", i);
	214		r = -DCE6_ERR;
	215		goto unlock_atb;
	216		}
	217
	218		/* prepare crtc */
	219		r = atb_crtc_lock(atb, i, true);
	220		if (r != 0) {
	221		dev_err(dce->ddev.dev, "dce6:dp%u: unable to lock the crtc\n",
	222		i);
	223		r = -DCE6_ERR;
	224		goto unlock_atb;
	225		}
	226
	227		r = atb_crtc_blank(atb, i, true);
	228		if (r != 0) {
	229		dev_err(dce->ddev.dev, "dce6:dp%u: unable to blank the crtc\n",
	230		i);
	231		r = -DCE6_ERR;
	232		goto unlock_atb;
	233		}
	234
	235		r = atb_crtc_mem_req(atb, i, false);
	236		if (r != 0) {
	237		dev_err(dce->ddev.dev, "dce6:dp%u: unable to disable crtc "
	238		"memory requests\n", i);
	239		r = -DCE6_ERR;
	240		goto unlock_atb;
	241		}
	242
	243		r = atb_crtc(atb, i, false);
	244		if (r != 0) {
	245		dev_err(dce->ddev.dev, "dce6:dp%u: unable to disable the "
	246		"crtc\n", i);
	247		r = -DCE6_ERR;
	248		goto unlock_atb;
	249		}
	250
	251		/* crtc mode set */
	252		r = atb_crtc_virtual_pixel_clk(atb, i, db_fb->timing.pixel_clk);
	253		if (r != 0) {
	254		dev_err(dce->ddev.dev, "dce6:dp%u: unable to program the "
	255		"virtual pixel clock\n", i);
	256		r = -DCE6_ERR;
	257		goto unlock_atb;
	258		}
	259
	260		r = atb_crtc_timing(atb, i, &db_fb->timing);
	261		if (r != 0) {
	262		dev_err(dce->ddev.dev, "dce6:dp%u: unable to program timings\n",
	263		i);
	264		r = -DCE6_ERR;
	265		goto unlock_atb;
	266		}
	267
	268		r = crtc_fb(dce, i, db_fb);
	269		if (r != 0) {
	270		dev_err(dce->ddev.dev, "dce6:dp%u: unable to setup the frame "
	271		"buffer\n", i);
	272		goto unlock_atb;
	273		}
	274
	275		r = atb_crtc_overscan(atb, i);
	276		if (r != 0) {
	277		dev_err(dce->ddev.dev, "dce6:dp%u: unable to setup the "
	278		"overscan\n", i);
	279		r = -DCE6_ERR;
	280		goto unlock_atb;
	281		}
	282
	283		r = atb_crtc_scaler(atb, i);
	284		if (r != 0) {
	285		dev_err(dce->ddev.dev, "dce6:dp%u: unable to setup the "
	286		"scaler\n", i);
	287		r = -DCE6_ERR;
	288		goto unlock_atb;
	289		}
	290
	291		/* encoder and transmitter mode set */
	292		r = atb_trans_link_off(atb, i);
	293		if (r != 0) {
	294		dev_err(dce->ddev.dev, "dce6:dp%u: unable to disable the "
	295		"transmitter link\n", i);
	296		r = -DCE6_ERR;
	297		goto unlock_atb;
	298		}
	299
	300		r = atb_enc_setup(atb, i, dce->dps[i].lanes_n,
	301		dce->dps[i].link_rate, alga_pixel_fmts_bpc[db_fb->pixel_fmt],
	302		db_fb->timing.pixel_clk);
	303		if (r != 0) {
	304		dev_err(dce->ddev.dev, "dce6:dp%u: unable to setup the "
	305		"encoder\n", i);
	306		r = -DCE6_ERR;
	307		goto unlock_atb;
	308		}
	309
	310		r = atb_trans_link_on(atb, i, dce->dps[i].lanes_n,
	311		db_fb->timing.pixel_clk);
	312		if (r != 0) {
	313		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable the "
	314		"transmitter link\n", i);
	315		r = -DCE6_ERR;
	316		goto unlock_atb;
	317		}
	318
	319		/* crtc commit */
	320		r = atb_crtc(atb, i, true);
	321		if (r != 0) {
	322		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable the "
	323		"crtc\n", i);
	324		r = -DCE6_ERR;
	325		goto unlock_atb;
	326		}
	327
	328		r = atb_crtc_mem_req(atb, i, true);
	329		if (r != 0) {
	330		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable the crtc "
	331		"memory requests\n", i);
	332		r = -DCE6_ERR;
	333		goto unlock_atb;
	334		}
	335
	336		r = atb_crtc_blank(atb, i, false);
	337		if (r != 0) {
	338		dev_err(dce->ddev.dev, "dce6:dp%u: unable to unblank the "
	339		"crtc\n", i);
	340		r = -DCE6_ERR;
	341		goto unlock_atb;
	342		}
	343
	344		crtc_lut(dce, i);
	345
	346		r = atb_crtc_lock(atb, i, false);
	347		if (r != 0) {
	348		dev_err(dce->ddev.dev, "dce6:dp%u: unable to unlock the crtc\n",
	349		i);
	350		r = -DCE6_ERR;
	351		goto unlock_atb;
	352		}
	353
	354		/* encoder and transmitter commit */
	355		r = atb_trans_link_output_on(atb, i, dce->dps[i].lanes_n,
	356		db_fb->timing.pixel_clk);
	357		if (r != 0) {
	358		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable the "
	359		"transmitter link output\n", i);
	360		r = -DCE6_ERR;
	361		goto unlock_atb;
	362		}
	363
	364		/* XXX: skipped switching on again power */
	365
	366		r = dp_link_train(dce, i);
	367		if (r < 0) {
	368		dev_err(dce->ddev.dev, "dce6:dp%u: unable to train the link\n",
	369		i);
	370		goto unlock_atb;
	371		}
	372
	373		r = atb_enc_video(atb, i, true);
	374		if (r != 0) {
	375		dev_err(dce->ddev.dev, "dce6:dp%u: unable to enable the video "
	376		"output on encoder\n", i);
	377		r = -DCE6_ERR;
	378		goto unlock_atb;
	379		}
	380		unlock_atb:
	381		atb_lock(atb, false);
	382		return r;
	383		}

File drivers/gpu/alga/amd/dce6/sink.h added (mode: 100644) (index 0000000..812fe94)
	1		#ifndef _ALGA_AMD_DCE6_SINK_H
	2		#define _ALGA_AMD_DCE6_SINK_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		int sink_timings(struct dce6 *dce, unsigned i,
	9		struct alga_timing (*ts)[ALGA_TIMINGS_MAX]);
	10		void sink_pixel_fmts(struct dce6 *dce, unsigned i,
	11		enum alga_pixel_fmt (*fmts)[ALGA_PIXEL_FMTS_MAX]);
	12
	13		int sink_mode_set(struct dce6 *dce, unsigned i, struct db_fb *db_fb);
	14		#endif

File drivers/gpu/alga/amd/si/Kconfig added (mode: 100644) (index 0000000..04c157b)
	1		config ALGA_AMD_SI
	2		tristate "si"
	3		depends on ALGA && ALGA_AMD && PCI
	4		select ALGA_AMD_DCE6
	5		select ALGA_AMD_ATOMBIOS
	6		help
	7		Choose this option if you have an AMD southern island graphics card. You
	8		don't need to choose this to run the Radeon in plain VGA mode.
	9
	10		If M is selected, the module will be called si.

File drivers/gpu/alga/amd/si/Makefile added (mode: 100644) (index 0000000..4b95cd6)
	1		#si-y := ba.o ucode.o ih.o drv.o cp.o fops.o tiling.o
	2		si-y := drv.o
	3		obj-$(CONFIG_ALGA_AMD_SI)+= si.o

File drivers/gpu/alga/amd/si/ba.c added (mode: 100644) (index 0000000..58b620e)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/pci.h>
	7		#include <asm/byteorder.h>
	8		#include <linux/delay.h>
	9		#include <linux/cdev.h>
	10		#include <linux/vmalloc.h>
	11
	12		#include <alga/rng_mng.h>
	13		#include <alga/timing.h>
	14		#include <alga/pixel_fmts.h>
	15		#include <alga/amd/dce4/dce4.h>
	16
	17		#include "regs.h"
	18
	19		#include "ih.h"
	20		#include "ba.h"
	21		#include "ucode.h"
	22		#include "cp.h"
	23		#include "drv.h"
	24
	25		/* pte attributes */
	26		#define PTE_VALID (1 << 0)
	27		#define PTE_SYSTEM (1 << 1) /* page aperture: system (vram+agp), non-system (pcie) */
	28		#define PTE_SNOOPED (1 << 2) /* snoop is cache coherent */
	29		#define PTE_READABLE (1 << 5)
	30		#define PTE_WRITEABLE (1 << 6)
	31
	32		static const size_t ctx0_ba_range_sz = 1024 * 1024 *1024; /* 1 GB */
	33
	34		static void ctx0_tlb_flush(struct pci_dev *dev)
	35		{
	36		unsigned i;
	37		u32 tmp;
	38
	39		/* flush hdp cache */
	40		wr32(dev, 0x1, HDP_MEM_COHERENCY_FLUSH_CTL);
	41
	42		/* bits 0-15 are for the vm contexts 0-15 */
	43		wr32(dev, 1, VM_INVALIDATE_REQ);
	44		}
	45
	46		static void ctx_tlb_flush(struct ctx *ctx)
	47		{
	48		/* only ctx0 in currently supported */
	49		ctx0_tlb_flush(ctx->dev);
	50		}
	51
	52		static int dummy_page(struct pci_dev *dev)
	53		{
	54		struct dev_drv_data *dd;
	55		dd = pci_get_drvdata(dev);
	56
	57		dd->ba.dummy_cpu_addr = dma_zalloc_coherent(&dev->dev, GPU_PAGE_SZ,
	58		&dd->ba.dummy_bus_addr, GFP_KERNEL);
	59		if (!dd->ba.dummy_cpu_addr) {
	60		dev_err(&dev->dev, "ba: unable to allocate dummy page\n");
	61		return -BA_ERR;
	62		}
	63
	64		if (!IS_GPU_PAGE_ALIGNED(dd->ba.dummy_bus_addr)) {
	65		dev_err(&dev->dev,
	66		"ba: dummy page bus addr not aligned on GPU page\n");
	67		dma_free_coherent(&dev->dev, GPU_PAGE_SZ, dd->ba.dummy_cpu_addr,
	68		dd->ba.dummy_bus_addr);
	69		return -BA_ERR;
	70		}
	71		dev_info(&dev->dev, "ba: dummy page mapped cpu_addr=0x%p"
	72		" bus_addr=0x%016llx\n", dd->ba.dummy_cpu_addr,
	73		dd->ba.dummy_bus_addr);
	74		return 0;
	75		}
	76
	77		static int ctx_init(struct pci_dev *dev, struct ctx *ctx, u64 start, u64 sz)
	78		{
	79		struct dev_drv_data *dd;
	80		int r;
	81
	82		ctx->dev = dev;
	83		dd = pci_get_drvdata(ctx->dev);
	84
	85		r = rng_alloc_align(&ctx->pt_start, &dd->vram.mng, (sz / GPU_PAGE_SZ)
	86		* sizeof(u64), GPU_PAGE_SZ);
	87		if (r != 0) {
	88		dev_err(&ctx->dev->dev, "ba:ctx: unable to allocate vram for"
	89		" ctx page table entries\n");
	90		r = -BA_ERR;
	91		return r;
	92		}
	93
	94		rng_mng_init(&ctx->mng, start, sz);
	95		INIT_LIST_HEAD(&dd->ba.ctx0.maps);
	96		return 0;
	97		}
	98
	99		/* only ctx0 */
	100		int ba_init(struct pci_dev *dev)
	101		{
	102		struct dev_drv_data *dd;
	103		unsigned i;
	104		u64 pte;
	105		u32 tmp;
	106		int r;
	107		u64 pt_of;
	108		u64 ctx0_start;
	109		u64 ctx0_end;
	110
	111		dd = pci_get_drvdata(dev);
	112
	113		if (ctx0_ba_range_sz % GPU_PAGE_SZ) {
	114		dev_err(&dev->dev, "ba: bus aperture size is not aligned on gpu"
	115		" page size\n");
	116		return -BA_ERR;
	117		}
	118
	119		/* ctx0 aperture after vram */
	120		ctx0_start = rng_align(dd->vram.mng.s + dd->vram.mng.sz, GPU_PAGE_SZ);
	121		r = ctx_init(dev, &dd->ba.ctx0, ctx0_start, ctx0_ba_range_sz);
	122		if (r != 0)
	123		return r;
	124		ctx0_end = dd->ba.ctx0.mng.s + dd->ba.ctx0.mng.sz - 1;
	125
	126		r = dummy_page(dev);
	127		if (r != 0)
	128		return r;
	129
	130		pt_of = dd->ba.ctx0.pt_start - dd->vram.mng.s;
	131		pte = dd->ba.dummy_bus_addr | PTE_VALID | PTE_SYSTEM
	132		| PTE_SNOOPED | PTE_READABLE | PTE_WRITEABLE;
	133		for (i = 0; i < ctx0_ba_range_sz/GPU_PAGE_SZ; ++i)
	134		writeq(pte, dd->vram.bar0 + pt_of + i * sizeof(pte));
	135
	136		/* make sure the gpu pte updates where sent over the bus */
	137		wmb();
	138
	139		ctx0_tlb_flush(dev);
	140
	141		/* setup tlb control, MX, X is generic for various blocks */
	142		wr32(dev, (0xa << 7)/* ??? */ | ENA_L1_TLB
	143		| SET(SYS_ACCESS_MODE, NOT_IN_SYS)
	144		| ENABLE_ADVANCED_DRIVER_MODEL
	145		| SET(SYS_APER_UNMAPPED_ACCESS, PASS_THRU),
	146		MC_VM_MX_L1_TLB_CTL);
	147
	148		/* setup l2 cache */
	149		wr32(dev, ENA_L2_CACHE | ENA_L2_PTE_CACHE_LRU_UPDATE_BY_WR
	150		| ENA_L2_PDE0_CACHE_LRU_UPDATE_BY_WR
	151		| SET(EFFECTIVE_L2_QUEUE_SZ, 7)
	152		| SET(CTX1_IDENTITY_ACCESS_MODE, 1),
	153		VM_L2_CTL_0);
	154		wr32(dev, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE, VM_L2_CTL_1);
	155		wr32(dev, L2_CACHE_BIGK_ASSOCIATIVITY
	156		| SET(L2_CACHE_BIGK_FRAGMENT_SZ, 0), VM_L2_CTL_2);
	157
	158		/* ctx0 */
	159		wr32(dev, GPU_PAGE_IDX(dd->ba.ctx0.mng.s), VM_CTX_0_PT_START_ADDR);
	160		wr32(dev, GPU_PAGE_IDX(ctx0_end), VM_CTX_0_PT_END_ADDR);
	161		wr32(dev, GPU_PAGE_IDX(dd->ba.ctx0.pt_start), VM_CTX_0_PT_BASE_ADDR);
	162		wr32(dev, GPU_PAGE_IDX(dd->ba.dummy_bus_addr),
	163		VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR);
	164		wr32(dev, ENA_CTX | SET(PT_DEPTH, 0)
	165		| RNG_PROTECTION_FAULT_ENA_DEFAULT, VM_CTX_0_CTL_0);
	166
	167		wr32(dev, 0, VM_CTX_1_CTL_0);
	168
	169		/* ??? */
	170		wr32(dev, 0, 0x15d4);
	171		wr32(dev, 0, 0x15d8);
	172		wr32(dev, 0, 0x15dc);
	173
	174		/* we don't use a hardware vm */
	175		wr32(dev, 0, VM_CTX_1_CTL_1);
	176		wr32(dev, 0, VM_CTX_1_CTL_0);
	177
	178		ctx0_tlb_flush(dev);
	179		return 0;
	180		}
	181
	182		/* only ctx0 */
	183		void ba_shutdown(struct pci_dev *dev)
	184		{
	185		struct dev_drv_data *dd;
	186		u32 tmp;
	187
	188		/* disable all tables */
	189		wr32(dev, 0, VM_CTX_0_CTL_0);
	190		wr32(dev, 0, VM_CTX_1_CTL_0);
	191
	192		/* setup tlb control */
	193		wr32(dev, SET(SYS_ACCESS_MODE, NOT_IN_SYS)
	194		| SET(SYS_APER_UNMAPPED_ACCESS, PASS_THRU),
	195		MC_VM_MX_L1_TLB_CTL);
	196
	197		/* setup l2 cache */
	198		wr32(dev, ENA_L2_PTE_CACHE_LRU_UPDATE_BY_WR
	199		| ENA_L2_PDE0_CACHE_LRU_UPDATE_BY_WR
	200		| SET(EFFECTIVE_L2_QUEUE_SZ, 7)
	201		| SET(CTX1_IDENTITY_ACCESS_MODE, 1),
	202		VM_L2_CTL_0);
	203		wr32(dev, 0, VM_L2_CTL_1);
	204		wr32(dev, L2_CACHE_BIGK_ASSOCIATIVITY
	205		| SET(L2_CACHE_BIGK_FRAGMENT_SZ, 0), VM_L2_CTL_2);
	206
	207		dd = pci_get_drvdata(dev);
	208
	209		dma_free_coherent(&dev->dev, GPU_PAGE_SZ, dd->ba.dummy_cpu_addr,
	210		dd->ba.dummy_bus_addr);
	211		rng_mng_destroy(&dd->ba.ctx0.mng);
	212		}
	213
	214		static void ptes_coherent_contig_restore(struct ba_map *m)
	215		{
	216		struct dev_drv_data *dd;
	217		u64 pte;
	218		unsigned i;
	219
	220		dd = pci_get_drvdata(m->ctx->dev);
	221
	222		pte = dd->ba.dummy_bus_addr | PTE_VALID | PTE_SYSTEM | PTE_SNOOPED
	223		| PTE_READABLE | PTE_WRITEABLE;
	224		for (i = 0; i < m->gpu_ps_n; ++i) {
	225		writeq(pte, dd->vram.bar0 + (m->ptes_start - dd->vram.mng.s)
	226		+ i * sizeof(pte));
	227		}
	228		}
	229
	230		static void ptes_coherent_contig_install(struct ba_map *m)
	231		{
	232		struct dev_drv_data *dd;
	233		unsigned i;
	234		unsigned pages_of;
	235		u64 bar0_pt_of;
	236		u64 __iomem *pte;
	237		u64 bus_addr;
	238
	239		dd = pci_get_drvdata(m->ctx->dev);
	240
	241		pages_of = (m->gpu_addr - m->ctx->mng.s) / GPU_PAGE_SZ;
	242		m->ptes_start = m->ctx->pt_start + pages_of * sizeof(u64);
	243
	244		bar0_pt_of = m->ptes_start - dd->vram.mng.s;
	245		pte = (u64 __iomem *)(dd->vram.bar0 + bar0_pt_of);
	246		bus_addr = m->bus_addr;
	247
	248		for (i = 0; i < m->gpu_ps_n; ++i, ++pte, bus_addr += GPU_PAGE_SZ)
	249		writeq(bus_addr | PTE_VALID | PTE_SYSTEM | PTE_SNOOPED
	250		| PTE_READABLE | PTE_WRITEABLE, pte);
	251		}
	252
	253		static struct ba_map *ctx_map_coherent_contig(struct ctx *ctx, unsigned gpu_ps_n)
	254		{
	255		struct ba_map *m;
	256		size_t sz;
	257		int r;
	258
	259		m = kzalloc(GFP_KERNEL, sizeof(*m));
	260		if (m == NULL) {
	261		dev_err(&ctx->dev->dev, "ba:ctx: unable to allocate ba"
	262		" struct\n");
	263		goto err;
	264		}
	265
	266		m->type = BA_MAP_COHERENT_CONTIG;
	267		m->ctx = ctx;
	268		m->gpu_ps_n = gpu_ps_n;
	269
	270		sz = m->gpu_ps_n * GPU_PAGE_SZ;
	271
	272		/* allocate a range of the aperture */
	273		r = rng_alloc_align(&m->gpu_addr, &m->ctx->mng, GPU_PAGE_SZ
	274		* m->gpu_ps_n, GPU_PAGE_SZ);
	275		if (r != 0) {
	276		dev_err(&ctx->dev->dev, "ba:ctx: unable to allocate gpu address"
	277		" space for mapping\n");
	278		goto err_free_ba_map;
	279		}
	280
	281		/* do the coherent mapping */
	282		m->cpu_addr = dma_zalloc_coherent(&ctx->dev->dev, sz, &m->bus_addr,
	283		GFP_KERNEL);
	284		if (m->cpu_addr == NULL) {
	285		dev_err(&ctx->dev->dev, "ba:ctx: unable to perform coherent dma"
	286		"mapping\n");
	287		goto err_free_rng;
	288		}
	289
	290		/* install the ptes for this mapping in its owning ctx */
	291		ptes_coherent_contig_install(m);
	292
	293		/* account for this new mapping in the ctx */
	294		list_add(&m->n, &ctx->maps);
	295
	296		/* be sure the gpu pte updates were sent over the bus */
	297		wmb();
	298
	299		/* flush ctx tlb to make live the mapping on the gpu */
	300		ctx_tlb_flush(ctx);
	301		return m;
	302
	303		err_free_rng:
	304		rng_free(&m->ctx->mng, m->gpu_addr);
	305
	306		err_free_ba_map:
	307		kfree(m);
	308		err:
	309		return NULL;
	310		}
	311
	312		static void cleanup_coherent_contig(struct ba_map *m)
	313		{
	314		ptes_coherent_contig_restore(m);
	315		rng_free(&m->ctx->mng, m->gpu_addr);
	316		dma_free_coherent(&m->ctx->dev->dev, m->gpu_ps_n * GPU_PAGE_SZ,
	317		m->cpu_addr, m->bus_addr);
	318		kfree(m);
	319		}
	320
	321		static void cleanup(struct ba_map *m)
	322		{
	323		switch (m->type) {
	324		case BA_MAP_COHERENT_CONTIG:
	325		cleanup_coherent_contig(m);
	326		break;
	327		default:
	328		dev_err(&m->ctx->dev->dev, "ba: unable to cleanup unknown type"
	329		" mapping\n");
	330		break;
	331		}
	332		}
	333
	334		static void unmap(struct ba_map *m)
	335		{
	336		struct ba_map *pos;
	337		struct ctx *ctx;
	338
	339		ctx = m->ctx; /* don't use m ctx since we getting rid of it */
	340		list_for_each_entry(pos, &ctx->maps, n) {
	341		if (pos == m) {
	342		list_del(&pos->n);
	343		cleanup(pos);
	344		break;
	345		}
	346		}
	347
	348		/* make sure the gpu pte updates were sent over the bus */
	349		wmb();
	350
	351		/* flush ctx tlb to make live the restored dummy pages */
	352		ctx_tlb_flush(ctx);
	353		}
	354
	355		/* just an helper for the core mappings */
	356		static int generic_map(struct ctx *ctx, u64 sz, struct ba_map **m)
	357		{
	358		if (sz % GPU_PAGE_SZ) {
	359		dev_err(&ctx->dev->dev, "ba: size not aligned on gpu page"
	360		" size\n");
	361		return -BA_ERR;
	362		}
	363
	364		*m = ctx_map_coherent_contig(ctx, sz / GPU_PAGE_SZ);
	365		if (*m == NULL) {
	366		dev_err(&ctx->dev->dev, "ba: unable to dma map the aperture\n");
	367		return -BA_ERR;
	368		}
	369		dev_info(&ctx->dev->dev, "ba: aperture coherently mapped gpu_addr=0x%016llx"
	370		" cpu_addr=0x%p\n", (*m)->gpu_addr, (*m)->cpu_addr);
	371		return 0;
	372		}
	373
	374		/* default in ctx0 */
	375		static int wb_map(struct pci_dev *dev)
	376		{
	377		struct dev_drv_data *dd;
	378
	379		dd = pci_get_drvdata(dev);
	380
	381		dev_info(&dev->dev, "ba: mapping write back page bus aperture\n");
	382		return generic_map(&dd->ba.ctx0, GPU_PAGE_SZ, &dd->ba.wb_map);
	383		}
	384
	385		/* default in ctx0 */
	386		static int ih_ring_map(struct pci_dev *dev)
	387		{
	388		struct dev_drv_data *dd;
	389		u64 ih_ring_sz;
	390
	391		ih_ring_sz = (1 << IH_RING_LOG2_DWS) * 4;
	392
	393		dd = pci_get_drvdata(dev);
	394
	395		dev_info(&dev->dev, "ba: mapping ih ring bus aperture\n");
	396		return generic_map(&dd->ba.ctx0, ih_ring_sz, &dd->ba.ih_ring_map);
	397		}
	398
	399		/* default in ctx0 */
	400		static int cp_ring_map(struct pci_dev *dev)
	401		{
	402		struct dev_drv_data *dd;
	403		u64 cp_ring_sz;
	404
	405		cp_ring_sz = (1 << CP_RING_LOG2_QWS) * 8;
	406
	407		dd = pci_get_drvdata(dev);
	408
	409		dev_info(&dev->dev, "ba: mapping cp ring bus aperture\n");
	410		return generic_map(&dd->ba.ctx0, cp_ring_sz, &dd->ba.cp_ring_map);
	411		}
	412
	413		int ba_map(struct pci_dev *dev)
	414		{
	415		struct dev_drv_data *dd;
	416		int r;
	417
	418		dd = pci_get_drvdata(dev);
	419
	420		r = wb_map(dev);
	421		if (r)
	422		goto err;
	423
	424		r = ih_ring_map(dev);
	425		if (r)
	426		goto err_unmap_wb;
	427
	428		r = cp_ring_map(dev);
	429		if (r)
	430		goto err_unmap_ih_ring;
	431
	432		return 0;
	433
	434		err_unmap_ih_ring:
	435		unmap(dd->ba.ih_ring_map);
	436
	437		err_unmap_wb:
	438		unmap(dd->ba.wb_map);
	439		err:
	440		return -BA_ERR;
	441		}
	442
	443		void ba_unmap(struct pci_dev *dev)
	444		{
	445		struct dev_drv_data *dd;
	446		dd = pci_get_drvdata(dev);
	447
	448		unmap(dd->ba.cp_ring_map);
	449		unmap(dd->ba.ih_ring_map);
	450		unmap(dd->ba.wb_map);
	451		}

File drivers/gpu/alga/amd/si/ba.h added (mode: 100644) (index 0000000..57c451f)
	1		#ifndef _BA_H
	2		#define _BA_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define BA_ERR 950
	9
	10		enum ba_map_type {
	11		BA_MAP_COHERENT_CONTIG
	12		};
	13
	14		struct ba_map {
	15		struct list_head n;
	16		enum ba_map_type type;
	17
	18		struct ctx *ctx;
	19		u64 ptes_start; /* location of the pte table in (v)ram */
	20		unsigned gpu_ps_n;
	21
	22		void *cpu_addr;
	23		dma_addr_t bus_addr;
	24		u64 gpu_addr;
	25		};
	26
	27		struct ctx {
	28		struct pci_dev *dev;
	29
	30		struct rng mng; /* range manager of the aperture */
	31		u64 pt_start; /* location of the page table in (v)ram */
	32
	33		struct list_head maps;
	34		};
	35
	36		struct ba {
	37		dma_addr_t dummy_bus_addr;
	38		void *dummy_cpu_addr;
	39
	40		struct ba_map *wb_map;
	41		struct ba_map *ih_ring_map;
	42		struct ba_map *cp_ring_map;
	43
	44		struct ctx ctx0;
	45		};
	46
	47		/* major bus aperture functions */
	48		int ba_init(struct pci_dev *dev);
	49		int ba_map(struct pci_dev *dev);
	50		void ba_unmap(struct pci_dev *dev);
	51		void ba_shutdown(struct pci_dev *dev);
	52		#endif /* _BA_H */

File drivers/gpu/alga/amd/si/cp.c added (mode: 100644) (index 0000000..6c24567)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/pci.h>
	7		#include <linux/delay.h>
	8		#include <linux/cdev.h>
	9
	10		#include <alga/rng_mng.h>
	11		#include <alga/timing.h>
	12		#include <alga/pixel_fmts.h>
	13		#include <alga/amd/dce4/dce4.h>
	14
	15		#include "regs.h"
	16
	17		#include "ih.h"
	18		#include "ba.h"
	19		#include "ucode.h"
	20		#include "cp.h"
	21		#include "drv.h"
	22
	23		void cp_stop(struct pci_dev *dev)
	24		{
	25		wr32(dev, CP_ME_HALT | CP_PFP_HALT, CP_ME_CTL);
	26		wr32(dev, 0, SCRATCH_UMSK);
	27		}
	28
	29		/* should be at the very beginning of the ring */
	30		void cp_me_init(struct pci_dev *dev)
	31		{
	32		struct dev_drv_data *dd;
	33		dd = pci_get_drvdata(dev);
	34
	35		cp_wr(dev, PKT3(PKT3_ME_INIT, 6));
	36		cp_wr(dev, 0x1);
	37		cp_wr(dev, 0x2);
	38		cp_wr(dev, dd->cfg.gpu_hw_ctxs_n_max - 1);
	39		cp_wr(dev, PKT3_ME_INIT_DEV_ID(1));
	40		cp_wr(dev, 0);
	41		cp_wr(dev, 0);
	42
	43		cp_commit(dev);
	44		wr32(dev, 0xff, CP_ME_CTL); /* XXX: specific to ME init? */
	45		}
	46
	47		/*
	48		* o ring size is 2^CP_RING_LOG2_QWS(17) quadwords (256 * 4096 bytes)
	49		* o block size is gpu page size, namely 2^GPU_PAGE_LOG2_QWS(9) quadwords
	50		* (4096 bytes)
	51		*/
	52		#define WB_SCRATCH_OF 0
	53		#define WB_CP_RPTR_OF 1024
	54		void cp_init(struct pci_dev *dev)
	55		{
	56		u32 cp_rb_ctl;
	57		u64 cp_rb_rptr_addr;
	58		u64 wb_scratch_addr;
	59		struct dev_drv_data *dd;
	60
	61		/* some command processor base settings */
	62		wr32(dev, SET(ROQ_IB_0_START, 0x16) | SET(ROQ_IB_1_START, 0x2b),
	63		CP_QUEUE_THRESHOLDS);
	64		wr32(dev, SET(MEQ_0_START, 0x30) | SET(MEQ_1_START, 0x60),
	65		CP_MEQ_THRESHOLDS);
	66		wr32(dev, 0, CP_PERFMON_CTL);
	67
	68		/* reset cp; if cp is reset, then pa, sh, vgt also need to be reset */
	69		wr32(dev, SOFT_RESET_CP | SOFT_RESET_PA | SOFT_RESET_SH
	70		| SOFT_RESET_VGT | SOFT_RESET_SX, GRBM_SOFT_RESET);
	71		rr32(dev, GRBM_SOFT_RESET);
	72		mdelay(15);
	73		wr32(dev, 0, GRBM_SOFT_RESET);
	74		rr32(dev, GRBM_SOFT_RESET);
	75
	76		/* set ring buffer size */
	77		cp_rb_ctl = SET(RB_BLK_LOG2_QWS, GPU_PAGE_LOG2_QWS)
	78		| SET(RB_BUF_LOG2_QWS, CP_RING_LOG2_QWS);
	79		#ifdef __BIG_ENDIAN
	80		cp_rb_ctl |= BUF_SWAP_32BIT;
	81		#endif
	82		wr32(dev, cp_rb_ctl, CP_RB_CTL);
	83		wr32(dev, 0x4, CP_SEM_WAIT_TIMER);
	84
	85		wr32(dev, 0, CP_RB_WPTR_DELAY);
	86
	87		wr32(dev, cp_rb_ctl | RB_RPTR_WR_ENA, CP_RB_CTL);
	88		wr32(dev, 0, CP_RB_RPTR_WR);
	89		wr32(dev, 0, CP_RB_WPTR);
	90		wr32(dev, 0, CP_RB_RPTR);
	91
	92		dd = pci_get_drvdata(dev);
	93
	94		/* set the wb address, 2 lower bits are for endianness */
	95		cp_rb_rptr_addr = dd->ba.wb_map->gpu_addr + WB_CP_RPTR_OF;
	96
	97		wr32(dev, cp_rb_rptr_addr & 0xfffffffc, CP_RB_RPTR_ADDR);
	98		wr32(dev, upper_32_bits(cp_rb_rptr_addr) & 0xff, CP_RB_RPTR_ADDR_HI);
	99
	100		wb_scratch_addr = dd->ba.wb_map->gpu_addr + WB_SCRATCH_OF;
	101		/*
	102		* 256 bytes block index is ok because gpu address and chosen write back
	103		* page offset fit properly that required aligment
	104		*/
	105		wr32(dev, (wb_scratch_addr >> 8) & 0xffffffff, SCRATCH_ADDR);
	106
	107		wr32(dev, 0xff, SCRATCH_UMSK);
	108
	109		mdelay(1);
	110		wr32(dev, cp_rb_ctl, CP_RB_CTL);
	111
	112		/* 256 bytes aligned ok because it is GPU_PAGE_SZ aligned */
	113		wr32(dev, dd->ba.cp_ring_map->gpu_addr >> 8, CP_RB_BASE);
	114		wr32(dev, (1 << 27) | (1 << 28), CP_DEBUG); /* ??? */
	115
	116		dd->cp0.rptr = 0;
	117		dd->cp0.wptr = 0;
	118		spin_lock_init(&dd->cp0.lock);
	119		}
	120
	121		inline void cp_wr(struct pci_dev *dev, u32 v)
	122		{
	123		struct dev_drv_data *dd;
	124		u32 *r;
	125
	126		dd = pci_get_drvdata(dev);
	127
	128		r = dd->ba.cp_ring_map->cpu_addr;
	129		r[dd->cp0.wptr++] = v;
	130		dd->cp0.wptr &= CP_RING_DW_MASK;
	131		}
	132
	133		inline void cp_commit(struct pci_dev *dev)
	134		{
	135		struct dev_drv_data *dd;
	136		u32 *r;
	137
	138		dd = pci_get_drvdata(dev);
	139
	140		/* match ring fetch size */
	141		r = dd->ba.cp_ring_map->cpu_addr;
	142		while (dd->cp0.wptr & CP_RING_PFP_DW_MASK)
	143		r[dd->cp0.wptr++] = PKT2;
	144
	145		wmb(); /* data write operations emitted before dma */
	146
	147		dd->cp0.wptr &= CP_RING_DW_MASK;
	148		wr32(dev, dd->cp0.wptr, CP_RB_WPTR);
	149		rr32(dev, CP_RB_WPTR);
	150		}

File drivers/gpu/alga/amd/si/cp.h added (mode: 100644) (index 0000000..4ac867a)
	1		#ifndef _CP_H
	2		#define _CP_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define CP_RING_LOG2_QWS 17
	9		#define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1)
	10
	11		#define CP_RING_PFP_DWS 16
	12		#define CP_RING_PFP_DW_MASK (CP_RING_PFP_DWS - 1)
	13
	14		#define PKT_TYPE2 2
	15		#define PKT_TYPE3 3
	16		#define PKT2 (PKT_TYPE2 << 30)
	17		#define PKT3(op,n) ((PKT_TYPE3 << 30) \
	18		| (((op) & 0xff) << 8) \
	19		| ((n - 1) & 0x3fff) << 16)
	20
	21		/* packet 3 operations */
	22		#define PKT3_CLR_STATE 0x12
	23		#define PKT3_MODE_CTL 0x18
	24		#define PKT3_CTX_CTL 0x28
	25		#define PKT3_IB 0x32
	26		#define PKT3_SURF_SYNC 0x43
	27		#define PKT3_DST_BASE_0_ENA BIT(0)
	28		#define PKT3_DST_BASE_1_ENA BIT(1)
	29		#define PKT3_CB0_DST_BASE_ENA BIT(6)
	30		#define PKT3_CB1_DST_BASE_ENA BIT(7)
	31		#define PKT3_CB2_DST_BASE_ENA BIT(8)
	32		#define PKT3_CB3_DST_BASE_ENA BIT(9)
	33		#define PKT3_CB4_DST_BASE_ENA BIT(10)
	34		#define PKT3_CB5_DST_BASE_ENA BIT(11)
	35		#define PKT3_CB6_DST_BASE_ENA BIT(12)
	36		#define PKT3_CB7_DST_BASE_ENA BIT(13)
	37		#define PKT3_DB_DEST_BASE_ENA BIT(14)
	38		#define PKT3_CB8_DST_BASE_ENA BIT(15)
	39		#define PKT3_CB9_DST_BASE_ENA BIT(16)
	40		#define PKT3_CB10_DST_BASE_ENA BIT(17)
	41		#define PKT3_CB11_DST_BASE_ENA BIT(18)
	42		#define PKT3_DST_BASE_2_ENA BIT(19)
	43		#define PKT3_FULL_CACHE_ENA BIT(20)
	44		#define PKT3_DST_BASE_3_ENA BIT(21)
	45		#define PKT3_TCL1_ACTION_ENA BIT(22)
	46		#define PKT3_TC_ACTION_ENA BIT(23)
	47		#define PKT3_VC_ACTION_ENA BIT(24)
	48		#define PKT3_CB_ACTION_ENA BIT(25)
	49		#define PKT3_DB_ACTION_ENA BIT(26)
	50		#define PKT3_SH_ACTION_ENA BIT(27)
	51		#define PKT3_SX_ACTION_ENA BIT(28)
	52		#define PKT3_SH_ICACHE_ACTION_ENA BIT(29)
	53		#define PKT3_ME_INIT 0x44
	54		#define PKT3_ME_INIT_DEV_ID(x) ((x) << 16)
	55		#define PKT3_PREAMBLE_CTL 0x4a
	56		#define PKT3_PREAMBLE_BEGIN_CLR_STATE (2 << 28)
	57		#define PKT3_PREAMBLE_END_CLR_STATE (3 << 28)
	58		#define PKT3_SET_CFG_REG 0x68
	59		#define PKT3_SET_CFG_REG_START 0x00008000
	60		#define PKT3_SET_CFG_REG_END 0x0000b000
	61		#define PKT3_SET_CTX_REG 0x69
	62		#define PKT3_SET_CTX_REG_START 0x00028000
	63		#define PKT3_SET_CTX_REG_END 0x00029000
	64		//TODO:confirm it's gone
	65		//#define PKT3_SET_RES 0x6d
	66		//#define PKT3_SET_RES_START 0x00030000
	67		//#define PKT3_SET_RES_END 0x00038000
	68		//#define PKT3_SET_SAMPLER 0x6e
	69		//#define PKT3_SET_SAMPLER_START 0x0003c000
	70		//#define PKT3_SET_SAMPLER_END 0x0003c600
	71		//#define PKT3_SET_CTL_CONST 0x6f
	72		//#define PKT3_SET_CTL_CONST_START 0x0003cff0
	73		//#define PKT3_SET_CTL_CONST_END 0x0003ff0c
	74
	75		struct cp
	76		{
	77		spinlock_t lock;
	78
	79		unsigned wptr; /* dword index in ring buffer: accounted by CPU */
	80		unsigned rptr; /* dword index in ring buffer: accounted by GPU */
	81		};
	82
	83		void cp_stop(struct pci_dev *dev);
	84		void cp_init(struct pci_dev *dev);
	85		void cp_me_init(struct pci_dev *dev);
	86		void cp_gpu_state_init(struct pci_dev *dev);
	87		void cp_wr(struct pci_dev *dev, u32 v);
	88		void cp_commit(struct pci_dev *dev);
	89		#endif /* CP_H */

File drivers/gpu/alga/amd/si/drv.c added (mode: 100644) (index 0000000..ec8709b)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		#include <linux/pci.h>
	8		#include <asm/byteorder.h>
	9		#include <linux/interrupt.h>
	10		#include <linux/firmware.h>
	11		#include <linux/delay.h>
	12		#include <linux/module.h>
	13		#include <linux/cdev.h>
	14		#include <linux/fs.h>
	15
	16		#include <alga/rng_mng.h>
	17		#include <alga/pixel_fmts.h>
	18		#include <alga/timing.h>
	19		#include <alga/amd/atombios/atb.h>
	20		#include <alga/amd/dce6/dce6.h>
	21
	22		#include "regs.h"
	23
	24		#include "ih.h"
	25		#include "ba.h"
	26		#include "ucode.h"
	27		#include "cp.h"
	28		#include "drv.h"
	29
	30		#include "pcie_ports.h"
	31
	32		#include "fops.h"
	33
	34		static struct class *class;
	35
	36		static struct atb_dev adev;
	37		static struct dce6_dev ddev;
	38
	39		/* those functions exist to deal with regs above regs range */
	40		u32 rr32(struct pci_dev *dev, unsigned of)
	41		{
	42		struct dev_drv_data *dd;
	43		u32 val;
	44
	45		dd = pci_get_drvdata(dev);
	46
	47		if (of <= (dd->regs_sz - sizeof(u32))) {
	48		val = le32_to_cpu(readl(dd->regs + of));
	49		} else {
	50		writel(of, dd->regs + 0);
	51		val = le32_to_cpu(readl(dd->regs + 4));
	52		}
	53		return val;
	54		}
	55
	56		void wr32(struct pci_dev *dev, u32 val, unsigned of)
	57		{
	58		struct dev_drv_data *dd;
	59		dd = pci_get_drvdata(dev);
	60
	61		if (of <= (dd->regs_sz - sizeof(u32))) {
	62		writel(cpu_to_le32(val), dd->regs + of);
	63		} else {
	64		writel(of, dd->regs + 0);
	65		writel(cpu_to_le32(val), dd->regs + 4);
	66		}
	67		}
	68
	69		static u32 extern_rr32(struct device *dev, unsigned of)
	70		{
	71		struct dev_drv_data *dd;
	72		struct pci_dev *pdev;
	73
	74		pdev = container_of(dev, struct pci_dev, dev);
	75		dd = pci_get_drvdata(pdev);
	76
	77		return rr32(pdev, of);
	78		}
	79
	80		static void extern_wr32(struct device *dev, u32 val, unsigned of)
	81		{
	82		struct dev_drv_data *dd;
	83		struct pci_dev *pdev;
	84
	85		pdev = container_of(dev, struct pci_dev, dev);
	86		dd = pci_get_drvdata(pdev);
	87
	88		wr32(pdev, val, of);
	89		}
	90
	91		static void * __devinit rom_copy_get(struct pci_dev *dev)
	92		{
	93		void __iomem *rom;
	94		void *rom_copy;
	95		size_t rom_sz;
	96
	97		rom = pci_map_rom(dev, &rom_sz);
	98		if (IS_ERR_OR_NULL(rom))
	99		return rom;
	100
	101		rom_copy = kzalloc(rom_sz, GFP_KERNEL);
	102		if (!rom_copy) {
	103		pci_unmap_rom(dev, rom);
	104		return ERR_PTR(-ENOMEM);
	105		}
	106
	107		memcpy_fromio(rom_copy, rom, rom_sz);
	108		pci_unmap_rom(dev, rom);
	109		return rom_copy;
	110		}
	111
	112		//static void intrs_reset(struct pci_dev *dev)
	113		//{
	114		// struct dev_drv_data *dd;
	115		// dd = pci_get_drvdata(dev);
	116		//
	117		// /* works even if ucode is not loaded */
	118		// wr32(dev, CNTX_BUSY_INT_ENA | CNTX_EMPTY_INT_ENA, CP_INT_CTL);
	119		//
	120		// wr32(dev, 0, GRBM_INT_CTL);
	121		//
	122		// dce6_intrs_reset(dd->dce);
	123		//}
	124
	125
	126		//static int mc_wait_for_idle(struct pci_dev *dev)
	127		//{
	128		// unsigned i;
	129		//
	130		// /* 100000 us = 100 ms */
	131		// for (i = 0; i < 100000; ++i) {
	132		// if (!(rr32(dev, SRBM_STATUS) & MC_STATUS_MASK))
	133		// return 0;
	134		// udelay(1);
	135		// }
	136		// return -1;
	137		//}
	138
	139		//static int mc_program(struct pci_dev *dev)
	140		//{
	141		// struct dev_drv_data *dd;
	142		// int i;
	143		// int j;
	144		// u32 tmp;
	145		// u64 vram_start;
	146		// u64 vram_end;
	147		// int r;
	148		//
	149		// dd = pci_get_drvdata(dev);
	150		//
	151		// vram_start = dd->vram.mng.s;
	152		// vram_end = vram_start + dd->vram.mng.sz - 1;
	153		//
	154		// /* initialize hdp */
	155		// for (i = 0, j = 0; i < 32; i++, j += 0x18) {
	156		// wr32(dev, 0x00000000, 0x2c14 + j);
	157		// wr32(dev, 0x00000000, 0x2c18 + j);
	158		// wr32(dev, 0x00000000, 0x2c1c + j);
	159		// wr32(dev, 0x00000000, 0x2c20 + j);
	160		// wr32(dev, 0x00000000, 0x2c24 + j);
	161		// }
	162		// wr32(dev, 0, HDP_REG_COHERENCY_FLUSH_CTL);
	163		//
	164		// if (mc_wait_for_idle(dev))
	165		// dev_warn(&dev->dev, "mc_program:stop:"
	166		// " wait for mc idle timed out\n");
	167		//
	168		// wr32(dev, GPU_PAGE_IDX(vram_start), MC_VM_SYS_APER_LOW_ADDR);
	169		// wr32(dev, GPU_PAGE_IDX(vram_end), MC_VM_SYS_APER_HIGH_ADDR);
	170		//
	171		// /* scratch gpu page */
	172		// r = rng_alloc_align(&dd->vram.scratch_page, &dd->vram.mng, GPU_PAGE_SZ,
	173		// GPU_PAGE_SZ);
	174		// if (r != 0) {
	175		// dev_err(&dev->dev, "unable to alloc GPU scratch page\n");
	176		// return r;
	177		// }
	178		// wr32(dev, GPU_PAGE_IDX(dd->vram.scratch_page),
	179		// MC_VM_SYS_APER_DEFAULT_ADDR);
	180		//
	181		// /*
	182		// * MC_VRAM_LOCATION:
	183		// * [15:8] last gpu address 16MB block index
	184		// * [7:0] first gpu address 16MB block index
	185		// */
	186		// tmp = ((vram_end >> 24) & 0xffff) << 16;
	187		// tmp |= ((vram_start >> 24) & 0xffff);
	188		// wr32(dev, tmp, MC_VRAM_LOCATION);
	189		//
	190		// /*
	191		// * maps pci bar 0: use the 256 kB block index of the gpu start
	192		// * address for vram. 1 GB of gpu address space.
	193		// */
	194		// wr32(dev, vram_start >> 8, HDP_NONSURFACE_BASE);
	195		// wr32(dev, (2 << 7) | (1 << 30), HDP_NONSURFACE_INFO);
	196		// wr32(dev, 0x3fffffff, HDP_NONSURFACE_SZ);
	197		//
	198		// /* no agp aperture in physical addresses */
	199		// wr32(dev, 0, MC_AGP_BASE);
	200		// wr32(dev, 0x0fffffff, MC_AGP_TOP);
	201		// wr32(dev, 0x0fffffff, MC_AGP_BOT);
	202		//
	203		// if (mc_wait_for_idle(dev))
	204		// dev_warn(&dev->dev, "mc_program:start:"
	205		// " wait for mc idle timed out\n");
	206		// return 0;
	207		//}
	208
	209		static int __devinit bars_map(struct pci_dev *dev)
	210		{
	211		struct dev_drv_data *dd;
	212		dd = pci_get_drvdata(dev);
	213
	214		dd->regs = ioremap_nocache(pci_resource_start(dev, 2),
	215		pci_resource_len(dev, 2));
	216		if (!dd->regs)
	217		return -ENOMEM;
	218		dd->regs_sz = pci_resource_len(dev, 2);
	219
	220		dev_info(&dev->dev, "regs mmio base: 0x%p\n", dd->regs);
	221		dev_info(&dev->dev, "regs mmio size: %zu\n",
	222		(size_t)pci_resource_len(dev, 2));
	223
	224		dd->vram.bar0 = ioremap_wc(pci_resource_start(dev, 0),
	225		pci_resource_len(dev, 0));
	226		if (!dd->vram.bar0) {
	227		iounmap(dd->regs);
	228		return -ENOMEM;
	229		}
	230		dev_info(&dev->dev, "vram mmio base: 0x%p\n", dd->vram.bar0);
	231		dev_info(&dev->dev, "vram mmio size: %zu\n",
	232		(size_t)pci_resource_len(dev, 0));
	233		return 0;
	234		}
	235
	236		static void bars_unmap(struct pci_dev *dev)
	237		{
	238		struct dev_drv_data *dd;
	239		dd = pci_get_drvdata(dev);
	240
	241		iounmap(dd->vram.bar0);
	242		iounmap(dd->regs);
	243		}
	244
	245		static void cfg_init(struct pci_dev *dev)
	246		{
	247		struct dev_drv_data *dd;
	248
	249		dd = pci_get_drvdata(dev);
	250
	251		switch (dd->family) {
	252		case TAHITI:
	253		dd->cfg.addr_best = 0x12011003;
	254		dd->cfg.dce_crtcs_n = 6;
	255
	256		dd->cfg.gpu_ses_n = 2;
	257		dd->cfg.gpu_se_shs_n = 2;
	258		dd->cfg.gpu_se_rbs_n = 4;
	259		dd->cfg.gpu_sh_cus_n = 8;
	260		dd->cfg.gpu_hw_ctxs_n = 8;
	261
	262		dd->cfg.gpu_sc_prim_fifo_sz_frontend = 0x20;
	263		dd->cfg.gpu_sc_prim_fifo_sz_backend = 0x100;
	264		dd->cfg.gpu_sc_hiz_tile_fifo_sz = 0x30;
	265		dd->cfg.gpu_sc_earlyz_tile_fifo_sz = 0x130;
	266		break;
	267		case PITCAIRN:
	268		dd->cfg.addr_best = 0x12011003;
	269		dd->cfg.dce_crtcs_n = 6;
	270
	271		dd->cfg.gpu_ses_n = 2;
	272		dd->cfg.gpu_se_shs_n = 2;
	273		dd->cfg.gpu_se_rbs_n = 4;
	274		dd->cfg.gpu_sh_cus_n = 5;
	275		dd->cfg.gpu_hw_ctxs_n = 8;
	276
	277		dd->cfg.gpu_sc_prim_fifo_sz_frontend = 0x20;
	278		dd->cfg.gpu_sc_prim_fifo_sz_backend = 0x100;
	279		dd->cfg.gpu_sc_hiz_tile_fifo_sz = 0x30;
	280		dd->cfg.gpu_sc_earlyz_tile_fifo_sz = 0x130;
	281		break;
	282		case VERDE:
	283		dd->cfg.addr_best = 0x12010002;
	284		dd->cfg.dce_crtcs_n = 6;
	285
	286		dd->cfg.gpu_ses_n = 2;
	287		dd->cfg.gpu_se_shs_n = 2;
	288		dd->cfg.gpu_se_rbs_n = 4;
	289		dd->cfg.gpu_sh_cus_n = 2;
	290		dd->cfg.gpu_hw_ctxs_n = 8;
	291
	292		dd->cfg.gpu_sc_prim_fifo_sz_frontend = 0x20;
	293		dd->cfg.gpu_sc_prim_fifo_sz_backend = 0x40;
	294		dd->cfg.gpu_sc_hiz_tile_fifo_sz = 0x30;
	295		dd->cfg.gpu_sc_earlyz_tile_fifo_sz = 0x130;
	296		break;
	297		}
	298		}
	299
	300		//static void hdp_init(struct pci_dev *dev, u32 addr_cfg)
	301		//{
	302		// struct dev_drv_data *dd;
	303		// int i;
	304		// int j;
	305		// u32 hdp_misc_ctl;
	306		// u32 hdp_host_path_ctl;
	307		//
	308		// dd = pci_get_drvdata(dev);
	309		//
	310		// for (i = 0, j = 0; i < 32; i++, j += 0x18) {
	311		// wr32(dev, 0x00000000, 0x2c14 + j);
	312		// wr32(dev, 0x00000000, 0x2c18 + j);
	313		// wr32(dev, 0x00000000, 0x2c1c + j);
	314		// wr32(dev, 0x00000000, 0x2c20 + j);
	315		// wr32(dev, 0x00000000, 0x2c24 + j);
	316		// }
	317		//
	318		// wr32(dev, addr_cfg, HDP_ADDR_CFG);
	319		//
	320		// hdp_misc_ctl = rr32(dev, HDP_MISC_CTL);
	321		// hdp_misc_ctl |= HDP_FLUSH_INVALIDATE_CACHE;
	322		// wr32(dev, hdp_misc_ctl, HDP_MISC_CTL);
	323		//
	324		// hdp_host_path_ctl = rr32(dev, HDP_HOST_PATH_CTL);
	325		// wr32(dev, hdp_host_path_ctl, HDP_HOST_PATH_CTL);
	326		//
	327		// udelay(50);
	328		//}
	329
	330		//static void soft_reset(struct pci_dev *dev)
	331		//{
	332		// u32 grbm_reset;
	333		//
	334		// /* reset all the gfx blocks */
	335		// grbm_reset = (SOFT_RESET_CP |
	336		// SOFT_RESET_CB |
	337		// SOFT_RESET_DB |
	338		// SOFT_RESET_GDS |
	339		// SOFT_RESET_PA |
	340		// SOFT_RESET_SC |
	341		// SOFT_RESET_BCI |
	342		// SOFT_RESET_SPI |
	343		// SOFT_RESET_SX |
	344		// SOFT_RESET_TC |
	345		// SOFT_RESET_TA |
	346		// SOFT_RESET_VGT |
	347		// SOFT_RESET_IA);
	348		//
	349		// wr32(dev, grbm_reset, GRBM_SOFT_RESET);
	350		// rr32(dev, GRBM_SOFT_RESET);
	351		// udelay(50);
	352		// wr32(dev, 0, GRBM_SOFT_RESET);
	353		// rr32(dev, GRBM_SOFT_RESET);
	354		// udelay(50);
	355		//}
	356
	357		//static void se_sh_select(struct pci_dev *dev, u32 se_idx, u32 sh_idx)
	358		//{
	359		// u32 grbm_gfx_idx = INSTANCE_BROADCAST_WRS;
	360		//
	361		// if ((se_idx == 0xffffffff) && (sh_idx == 0xffffffff))
	362		// grbm_gfx_idx = SH_BROADCAST_WRS | SE_BROADCAST_WRS;
	363		// else if (se_idx == 0xffffffff)
	364		// grbm_gfx_idx |= SE_BROADCAST_WRS | SET(SH_IDX, sh_idx);
	365		// else if (sh_idx == 0xffffffff)
	366		// grbm_gfx_idx |= SH_BROADCAST_WRS | SET(SE_IDX, se_idx);
	367		// else
	368		// grbm_gfx_idx |= SET(SH_IDX, sh_idx) | SET(SE_IDX, se_idx);
	369		// wr32(dev, grbm_gfx_idx, GRBM_GFX_IDX);
	370		//}
	371
	372		/*
	373		* bitwidth=0-->mask=0x0
	374		* bitwidth=1-->mask=0x1
	375		* bitwidth=2-->mask=0x3
	376		* ...
	377		*/
	378		//static u32 bitmask_create(u32 bit_width)
	379		//{
	380		// u32 i;
	381		// u32 mask;
	382		//
	383		// mask = 0;
	384		// for (i = 0; i < bit_width; ++i) {
	385		// mask <<= 1;
	386		// mask |= 1;
	387		// }
	388		// return mask;
	389		//}
	390
	391		/* the mask of disabled rbs of the **selected sh** */
	392		//static u32 sh_rbs_dis_get(struct pci_dev *dev)
	393		//{
	394		// struct dev_drv_data *dd;
	395		// u32 rb_backend_dis;
	396		// u32 mask;
	397		//
	398		// dd = pci_get_drvdata(dev);
	399		//
	400		// /* disabling a rb for a sh is done at 2 levels: CC_ and GC_USER_ */
	401		// rbs_disable = rd32(dev, CC_RB_BACKEND_DIS);
	402		// if (tmp & BACKEND_DIS_VALID)
	403		// tmp &= BACKEND_DIS_MASK;
	404		// else
	405		// tmp = 0;
	406		// tmp |= rd32(dev, GC_USER_RB_BACKEND_DIS);
	407		//
	408		// tmp >>= BACKEND_DIS_SHIFT;
	409		//
	410		// /* get a bit mask for the rbs which are disabled for this sh */
	411		// mask = bitmask_create(dd->cfg.gpu_se_rbs_n / dd->cfg.gpu_ses_n
	412		// / dd->cfg.gpu_se_shs_n);
	413		// return tmp & mask;
	414		//}
	415
	416		//static void rbs_setup(struct pci_dev *dev)
	417		//{
	418		// struct dev_drv_data *dd;
	419		// unsigned i;
	420		// unsigned j;
	421		// u32 sh_rbs_dis;
	422		// u32 rbs_dis;
	423		// u32 mask;
	424		// u32 rbs_ena;
	425		// u32 pa_sc_raster_cfg;
	426		//
	427		// dd = pci_get_drvdata(dev);
	428		//
	429		// /* build the mask of disabled rbs from registers*/
	430		// rbs_dis = 0;
	431		// for (i = 0; i < dd->cfg.gpu_ses_n; ++i) {
	432		// for (j = 0; j < dd->cfg.gpu_se_shs_n; ++j) {
	433		// se_sh_select(dev, i, j);
	434		// sh_rbs_dis = sh_rbs_dis_get(dev);
	435		// rbs_dis |= sh_rbs_dis << ((i * dd->cfg.gpu_se_shs_n + j)
	436		// * TAHITI_RB_BITMAP_W_PER_SH);
	437		// }
	438		// }
	439		//
	440		// se_sh_select(dev, 0xffffffff, 0xffffffff);
	441		//
	442		// /* build the mask of enabled rbs from the mask of disabled rbs */
	443		// rbs_ena = 0;
	444		// mask = 1;
	445		// for (i = 0; i < dd->cfg.gpu_se_rbs_n; ++i) {
	446		// if(!(rbs_dis & mask))
	447		// rbs_ena |= mask;
	448		// mask <<= 1;
	449		// }
	450		//
	451		// /* configure the raster block for each sh */
	452		// for (i = 0; i < dd->cfg.gpu_ses_n; ++i) {
	453		// pa_sc_raster_cfg = 0;
	454		// for (j = 0; j < dd->cfg.gpu_se_shs_n; ++j) {
	455		// switch (rbs_ena & 3) {
	456		// case 1:
	457		// pa_sc_raster_cfg |= (RASTER_CFG_RB_MAP_0
	458		// << (i * dd->cfg.gpu_se_shs_n + j) * 2);
	459		// break;
	460		// case 2:
	461		// pa_sc_raster_cfg |= (RASTER_CFG_RB_MAP_3
	462		// << (i * dd->cfg.gpu_se_shs_n + j) * 2);
	463		// break;
	464		// case 3:
	465		// default:
	466		// pa_sc_raster_cfg |= (RASTER_CFG_RB_MAP_2
	467		// << (i * dd->cfg.gpu_se_shs_n + j) * 2);
	468		// break;
	469		// }
	470		// rbs_ena >>= 2;/* enabled rbs of next sh */
	471		// }
	472		// se_sh_select(rdev, i, 0xffffffff);
	473		// wr32(dev, pa_sc_raster_cfg, PA_SC_RASTER_CFG);
	474		// }
	475		// se_sh_select(rdev, 0xffffffff, 0xffffffff);
	476		//}
	477
	478		/* get enabled cus for the **selected sh** */
	479		//static u32 cus_ena_get(struct pci_dev *dev)
	480		//{
	481		// struct dev_drv_data *dd;
	482		// u32 tmp;
	483		// u32 mask;
	484		//
	485		// dd = pci_get_drvdata(dev);
	486		//
	487		// /* disabling a cu for a sh is done at 2 levels: CC_ and GC_USER_ */
	488		// tmp = rd32(dev, CC_GC_SHADER_ARRAY_CFG);
	489		// if (tmp & INACTIVE_CUS_VALID)
	490		// tmp &= INACTIVE_CUS_MASK;
	491		// else
	492		// tmp = 0;
	493		// tmp |= rd32(dev, GC_USER_SHADER_ARRAY_CFG);
	494		//
	495		// tmp >>= INACTIVE_CUS_SHIFT;
	496		//
	497		// mask = bitmask_create(dd->cfg.gpu_sh_cus_n);
	498		// return ~tmp & mask;
	499		//}
	500
	501		//static void spi_setup(struct pci_dev *dev)
	502		//{
	503		// struct dev_drv_data *dd;
	504		// unsigned i;
	505		// unsigned j;
	506		// unsigned k;
	507		// u32 spi_static_thd_mgmt_2;
	508		// u32 cus_ena;
	509		// u32 mask;
	510		//
	511		// dd = pci_get_drvdata(dev);
	512		//
	513		// for (i = 0; i < dd->cfg.gpu_ses_n; ++i) {
	514		// for (j = 0; j < dd->cfg.gpu_se_shs_n; ++j) {
	515		// se_sh_select(dev, i, j);
	516		// spi_static_thd_mgmt_2 = rd32(dev,
	517		// SPI_STATIC_THD_MGMT_2);
	518		// cus_ena = cus_ena_get(dev);
	519		//
	520		// mask = 1;
	521		// for (k = 0; k < SH_CUS_N_MAX; ++k) {
	522		// mask <<= k;
	523		// if (cus_ena & mask) {
	524		// spi_static_thd_mgmt_2 &= ~mask;
	525		// wr32(dev, spi_static_thd_mgmt_2,
	526		// SPI_STATIC_THD_MGMT_2);
	527		// break;
	528		// }
	529		// }
	530		// }
	531		// }
	532		// se_sh_select(rdev, 0xffffffff, 0xffffffff);
	533		//
	534		// wr32(dev, SET(VTX_DONE_DELAY, 4), SPI_CFG_CTL_1);
	535		//}
	536
	537		/* gpu registers which need to be inited only once */
	538		//static void gpu_init(struct pci_dev *dev, u32 addr_cfg, mem_row_sz_kb)
	539		//{
	540		// struct dev_drv_data *dd;
	541		// u32 sx_debug_1;
	542		//
	543		// dd = pci_get_drvdata(dev);
	544		//
	545		// wr32(dev, SET(GRBM_RD_TIMEOUT, 0xff), GRBM_CTL);
	546		// wr32(dev, addr_cfg, GB_ADDR_CFG);
	547		//
	548		// tiling_modes_tbl_init(dev, mem_row_sz_kb);
	549		// rbs_setup(dev);
	550		// spi_setup(dev);
	551		//
	552		// sx_debug_1 = rr32(dev, SX_DEBUG_1);
	553		// wr32(dev, SX_DEBUG_1, sx_debug_1);
	554		//
	555		// wr32(dev, SET(SC_FRONTEND_PRIM_FIFO_SZ,
	556		// dd->cfg.gpu_sc_prim_fifo_sz_frontend)
	557		// | SET(SC_BACKEND_PRIM_FIFO_SZ,
	558		// dd->cfg.gpu_sc_prim_fifo_size_backend)
	559		// | SET(SC_HIZ_TILE_FIFO_SZ(dd->cfg.gpu_sc_hiz_tile_fifo_sz)
	560		// | SET(SC_EARLYZ_TILE_FIFO_SZ(
	561		// dd->cfg.gpu_sc_earlyz_tile_fifo_sz),
	562		// PA_SC_FIFO_SIZE);
	563		// wr32(dev, 1, VGT_INSTS_N);
	564		//
	565		// wr32(dev, 0, SQ_CFG);
	566		//
	567		// wr32(dev, SET(FORCE_EOV_MAX_CLK_CNT, 4095)
	568		// | SET(FORCE_EOV_MAX_REZ_CNT, 255), PA_SC_FORCE_EOV_MAX_CNTS);
	569		//
	570		//
	571		// wr32(dev, SET(CACHE_INVALIDATION, VC_AND_TC)
	572		// | SET(AUTO_INVLD_ENA, ES_AND_GS_AUTO), VGT_CACHE_INVALIDATION);
	573		//
	574		// wr32(dev, 16, VGT_GS_VTX_REUSE);
	575		// wr32(dev, 0, PA_SC_LINE_STIPPLE_STATE);
	576		//
	577		// wr32(dev, 0, CB_PERF_CTR_0_SELECT_0);
	578		// wr32(dev, 0, CB_PERF_CTR_0_SELECT_1);
	579		// wr32(dev, 0, CB_PERF_CTR_1_SELECT_0);
	580		// wr32(dev, 0, CB_PERF_CTR_1_SELECT_1);
	581		// wr32(dev, 0, CB_PERF_CTR_2_SELECT_0);
	582		// wr32(dev, 0, CB_PERF_CTR_2_SELECT_1);
	583		// wr32(dev, 0, CB_PERF_CTR_3_SELECT_0);
	584		// wr32(dev, 0, CB_PERF_CTR_3_SELECT_1);
	585		//
	586		// wr32(dev, CLIP_VTX_REORDER_ENA | SET(CLIP_SEQ_N, 3), PA_CL_ENHANCE);
	587		//
	588		// udelay(50);
	589		//}
	590
	591		//static irqreturn_t irq_thd(int irq, void *dev_id)
	592		//{
	593		// struct pci_dev *dev;
	594		// struct dev_drv_data *dd;
	595		//
	596		// dev = dev_id;
	597		// dd = pci_get_drvdata(dev);
	598		//
	599		// dce6_irqs_thd(dd->dce);
	600		// return IRQ_HANDLED;
	601		//}
	602
	603		//static irqreturn_t irq(int irq, void *dev_id)
	604		//{
	605		// struct pci_dev *dev;
	606		// dev = dev_id;
	607		// /* TODO: should return IRQ_HANDLED in some cases ? */
	608		// if (ih_parse(dev))
	609		// return IRQ_WAKE_THREAD;
	610		// else
	611		// return IRQ_NONE;
	612		//}
	613
	614		/* override the memory configuration */
	615		//static void addr_cfg_compute(struct pci_dev *dev, u32 *addr_cfg,
	616		// unsigned *mem_row_sz_kb)
	617		//{
	618		// struct dev_drv_data *dd;
	619		// u32 arb_ram_cfg;
	620		// unsigned cols_n;
	621		//
	622		// dd = pci_get_drvdata(dev);
	623		//
	624		// arb_ram_cfg = rd32(dev, MC_ARB_RAM_CFG);
	625		// cols_n = GET(MC_COLS_N, arb_ram_cfg);
	626		//
	627		// *mem_row_sz_kb = (4 *(1 << (8 + cols_n))) / 1024;
	628		// if (*mem_row_sz_kb > 4)
	629		// *mem_row_sz_kb = 4;
	630		//
	631		// *addr_cfg = dd->cfg.addr_best;
	632		// *addr_cfg &= ~ROW_SZ_MASK;
	633		// switch (*mem_row_sz_kb) {
	634		// case 1:
	635		// default:
	636		// *addr_cfg |= SET(ROW_SZ, 0);
	637		// break;
	638		// case 2:
	639		// *addr_cfg |= SET(ROW_SZ, 1);
	640		// break;
	641		// case 4:
	642		// *addr_cfg |= SET(ROW_SZ, 2);
	643		// break;
	644		// }
	645		//}
	646
	647		static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id)
	648		{
	649		int err;
	650		struct dev_drv_data *dd;
	651		//u32 addr_cfg;
	652
	653		err = pci_enable_device(dev);
	654		if (err) {
	655		dev_err(&dev->dev, "cannot enable the device\n");
	656		return err;
	657		}
	658
	659		err = pci_enable_msi(dev);
	660		if (err) { dev_err(&dev->dev, "cannot enable MSI\n");
	661		goto err_dis_pdev;
	662		}
	663
	664
	665		err = dma_set_mask(&dev->dev, DMA_BIT_MASK(40));
	666		if (err) {
	667		dev_err(&dev->dev, "cannot set DMA address width to 40 bits\n");
	668		goto err_dis_msi;
	669		}
	670		dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(40));
	671
	672		err = pci_request_regions(dev, pci_name(dev));
	673		if (err != 0) {
	674		goto err_dis_msi;
	675		}
	676
	677		dd = kzalloc(sizeof(*dd), GFP_KERNEL);
	678		if (!dd) {
	679		dev_err(&dev->dev, "cannot allocate driver private data for"
	680		" device\n");
	681		err = -ENOMEM;
	682		goto err_release_pci_regions;
	683		}
	684
	685		pci_set_drvdata(dev, dd);
	686
	687		dd->dev = dev; /* only used for char device node */
	688		dd->family = id->driver_data;
	689
	690		cfg_init(dev);
	691
	692		adev.rom = rom_copy_get(dev);
	693		if (IS_ERR_OR_NULL(adev.rom)) {
	694		if (IS_ERR(adev.rom))
	695		err = PTR_ERR(adev.rom);
	696		else
	697		err = -EIO;
	698		dev_err(&dev->dev, "cannot copy the rom\n");
	699		goto err_free_drv_data;
	700		}
	701
	702		err = bars_map(dev);
	703		if (err)
	704		goto err_free_rom_copy;
	705
	706		adev.dev = &dev->dev;
	707		adev.rr32 = extern_rr32;
	708		adev.wr32 = extern_wr32;
	709
	710		dd->atb = atb_alloc(&adev);
	711		if (!dd->atb) {
	712		dev_err(&dev->dev, "cannot allocate atombios\n");
	713		err = -ENOMEM;
	714		goto err_bars_unmap;
	715		}
	716
	717		err = atb_init(dd->atb);
	718		if (err) {
	719		dev_err(&dev->dev, "cannot init the atombios\n");
	720		goto err_free_atb;
	721		}
	722
	723		ddev.dev = &dev->dev;
	724		ddev.atb = dd->atb;
	725		ddev.crtcs_n = dd->cfg.dce_crtcs_n;
	726		ddev.rr32 = extern_rr32;
	727		ddev.wr32 = extern_wr32;
	728
	729		dd->dce = dce6_alloc(&ddev);
	730
	731		if (!dd->dce) {
	732		dev_err(&dev->dev, "cannot allocate dce\n");
	733		err = -ENOMEM;
	734		goto err_cleanup_atb;
	735		}
	736
	737		if (!rr32(dev, CFG_MEM_SZ)) {
	738		dev_info(&dev->dev, "posting now...\n");
	739		err = atb_asic_init(dd->atb);
	740		if (err) {
	741		dev_err(&dev->dev, "atombios failed to init the "
	742		"asic\n");
	743		goto err_dce_free;
	744		}
	745		} else {
	746		dev_info(&dev->dev, "already posted\n");
	747		}
	748
	749		wr32(dev, FB_RD_ENA | FB_WR_ENA, BIF_FB_ENA);
	750
	751		///* claim back the 256k vga memory at vram beginning */
	752		//dce6_vga_off(dd->dce);
	753
	754		//addr_cfg_compute(dev, &addr_cfg, &mem_row_sz_kb);
	755
	756		///* CFG_MEM_SZ is now valid */
	757		//dev_info(&dev->dev, "vram size is %uMB\n", rr32(dev, CFG_MEM_SZ));
	758
	759		//rng_mng_init(&dd->vram.mng, 0, rr32(dev, CFG_MEM_SZ) * 1024 * 1024);
	760
	761		//cp0_stop(dev);
	762		//cp1_stop(dev);
	763		//cp2_stop(dev);
	764		//ih_stop(dev);
	765		//intrs_reset(dev);
	766
	767		//err = request_threaded_irq(dev->irq, irq, irq_thd, 0, pci_name(dev),
	768		// (void*)dev);
	769		//if (err) {
	770		// dev_err(&dev->dev, "unable to request threaded irq\n");
	771		// goto err_vram_mng_destroy;
	772		//}
	773
	774		//err = ucode_load(dev);
	775		//if (err)
	776		// goto err_free_irq;
	777
	778		///* quiet the memory requests before mc programming: dce then gpu */
	779		///* TODO:dce6 still has mem_req? */
	780		//err = dce6_mem_req(dd->dce, false);
	781		//if (err)
	782		// goto err_release_firmware;
	783
	784		//if (rr32(dev, GRBM_STATUS) & GUI_ACTIVE)
	785		// soft_reset(dev);
	786
	787		//ucode_mc_program(dev);
	788
	789		//err = mc_program(dev);
	790		//if (err)
	791		// goto err_release_firmware;
	792
	793		//hdp_init(dev, addr_cfg);
	794
	795		//err = ba_init(dev);
	796		//if (err)
	797		// goto err_release_firmware;
	798
	799		//err = ba_map(dev); /* map wb page, ih ring, cp rings */
	800		//if (err)
	801		// goto err_ba_shutdown;
	802
	803		//err = dce6_init(dd->dce, addr_cfg);
	804		//if (err)
	805		// goto err_ba_unmap;
	806
	807		//gpu_init(dev, addr_cfg, mem_row_sz_kb);
	808
	809
	810		////KEEP GOING HERE
	811
	812
	813		//ucode_rlc_program(dev);
	814		//ih_init(dev);
	815
	816		//pci_set_master(dev);
	817
	818		//ih_start(dev);
	819
	820		//ucode_cp_program(dev);
	821		//cp_init(dev);
	822		//cp_me_init(dev);
	823
	824		//dce6_hpds_intr_ena(dd->dce);
	825
	826		///* userland interface setup */
	827		//cdev_init(&dd->evergreen_cdev, &fops);
	828		//err = cdev_add(&dd->evergreen_cdev, devt, 1);
	829		//if (err) {
	830		// dev_err(&dev->dev, "cannot add register char device\n");
	831		// goto err_clr_master;
	832		//}
	833
	834		//dd->evergreen_dev = device_create(class, &dev->dev,
	835		// dd->evergreen_cdev.dev, NULL, "evergreen0");
	836		//if (IS_ERR(dd->evergreen_dev)) {
	837		// dev_err(&dev->dev, "cannot create userspace char device\n");
	838		// goto err_cdev_del;
	839		//}
	840
	841		dev_info(&dev->dev, "ready\n");
	842		return 0;
	843
	844		//err_cdev_del:
	845		// cdev_del(&dd->evergreen_cdev);
	846		//
	847		//err_clr_master:
	848		// pci_clear_master(dev);
	849		// cp_stop(dev);
	850		// ih_stop(dev);
	851		// dce6_shutdown(dd->dce);
	852		//
	853		//err_ba_unmap:
	854		// ba_unmap(dev);
	855		//
	856		//err_ba_shutdown:
	857		// ba_shutdown(dev);
	858		//
	859		//err_release_firmware:
	860		// ucode_release(dev);
	861		//
	862		//err_free_irq:
	863		// free_irq(dev->irq, (void*)dev);
	864		//
	865		//err_vram_mng_destroy:
	866		// rng_mng_destroy(&dd->vram.mng);
	867
	868		err_dce_free:
	869		kfree(dd->dce);
	870
	871		err_cleanup_atb:
	872		atb_cleanup(dd->atb);
	873
	874		err_free_atb:
	875		kfree(dd->atb);
	876
	877		err_bars_unmap:
	878		bars_unmap(dev);
	879
	880		err_free_rom_copy:
	881		kfree(adev.rom);
	882
	883		err_free_drv_data:
	884		pci_set_drvdata(dev, NULL);
	885		kfree(dd);
	886
	887		err_release_pci_regions:
	888		pci_release_regions(dev);
	889
	890		err_dis_msi:
	891		pci_disable_msi(dev);
	892
	893		err_dis_pdev:
	894		pci_disable_device(dev);
	895		return err;
	896		}
	897
	898		static void __devexit remove(struct pci_dev *dev)
	899		{
	900		struct dev_drv_data *dd;
	901
	902		dd = pci_get_drvdata(dev);
	903
	904		/* remove userland interface */
	905		//device_destroy(class, dd->evergreen_cdev.dev);
	906		//cdev_del(&dd->evergreen_cdev);
	907
	908		//pci_clear_master(dev);
	909		//cp_stop(dev);
	910		//ih_stop(dev);
	911		//dce6_shutdown(dd->dce);
	912		kfree(dd->dce);
	913		//free_irq(dev->irq, (void*)dev);
	914
	915		//ba_unmap(dev);
	916
	917		//ba_shutdown(dev);
	918
	919		ucode_release(dev);
	920
	921		//rng_mng_destroy(&dd->vram.mng);
	922		atb_cleanup(dd->atb);
	923		kfree(dd->atb);
	924		kfree(adev.rom);
	925
	926		bars_unmap(dev);
	927
	928		pci_release_regions(dev);
	929		pci_disable_msi(dev);
	930		pci_disable_device(dev);
	931
	932		pci_set_drvdata(dev, NULL);
	933		kfree(dd);
	934		}
	935
	936		static const struct dev_pm_ops pm_ops;
	937
	938		/* FIXME: hardcoded for now */
	939		static DEFINE_PCI_DEVICE_TABLE(pci_tbl) =
	940		{
	941		{PCI_VENDOR_ID_ATI, 0x254d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TAHITI},
	942		{}
	943		};
	944		MODULE_DEVICE_TABLE(pci, pci_tbl);
	945
	946		static struct pci_driver pci_driver =
	947		{
	948		.name = "AMD southern island PCI driver",
	949		.id_table = pci_tbl,
	950		.probe = probe,
	951		.remove = __devexit_p(remove),
	952		.driver.pm = NULL
	953		};
	954
	955		static int __init init(void)
	956		{
	957		int r;
	958
	959		class = class_create(THIS_MODULE, "si");
	960		if (IS_ERR(class))
	961		return PTR_ERR(class);
	962
	963		r = alloc_chrdev_region(&devt, 0, 1, pci_driver.name);
	964		if (r < 0) {
	965		printk(KERN_ERR "%s:cannot allocate major/minor range\n",
	966		pci_driver.name);
	967		goto class_destroy;
	968		}
	969
	970		r = pci_register_driver(&pci_driver);
	971		if (r != 0) {
	972		printk(KERN_ERR "%s:cannot register PCI driver\n",
	973		pci_driver.name);
	974		goto chrdev_region_unregister;
	975		}
	976		return 0;
	977
	978		chrdev_region_unregister:
	979		unregister_chrdev_region(devt, 1);
	980
	981		class_destroy:
	982		class_destroy(class);
	983		return r;
	984		}
	985
	986		static void __exit cleanup(void)
	987		{
	988		pci_unregister_driver(&pci_driver);
	989		unregister_chrdev_region(devt, 1);
	990		class_destroy(class);
	991		}
	992
	993		module_init(init);
	994		module_exit(cleanup);
	995
	996		MODULE_AUTHOR("Sylvain Bertrand <digital.ragnarok@gmail.com>");
	997		MODULE_DESCRIPTION("AMD southern island driver");
	998		MODULE_LICENSE("GPL");

File drivers/gpu/alga/amd/si/drv.h added (mode: 100644) (index 0000000..076cf5a)
	1		#ifndef _DRV_H
	2		#define _DRV_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		enum family {
	10		TAHITI,
	11		PITCAIRN,
	12		VERDE
	13		};
	14
	15		#define ERR -900
	16
	17		#define GPU_PAGE_SZ 4096
	18		#define GPU_PAGE_LOG2_QWS 9
	19		#define GPU_PAGE_MASK(gpu_addr) ((gpu_addr) & 0xfffffffffffff000)
	20		#define GPU_PAGE_IDX(addr) ((addr) >> 12)
	21		#define IS_GPU_PAGE_ALIGNED(addr) (!((addr) & 0xfff))
	22
	23		struct vram {
	24		void __iomem *bar0;
	25		struct rng mng;
	26		u64 scratch_page;
	27		};
	28
	29		struct cfg {
	30		u32 addr_best;
	31		unsigned dce_crtcs_n;
	32		unsigned gpu_hw_ctxs_n;
	33		unsigned gpu_ses_n;
	34		unsigned gpu_se_shs_n;
	35		unsigned gpu_se_rbs_n;
	36		unsigned gpu_sh_cus_n;
	37
	38		unsigned gpu_sc_prim_fifo_sz_frontend;
	39		unsigned gpu_sc_prim_fifo_sz_backend;
	40		unsigned gpu_sc_hiz_tile_fifo_sz;
	41		unsigned gpu_sc_earlyz_tile_fifo_sz;
	42		};
	43		struct dev_drv_data {
	44		struct hlist_node node;
	45
	46		enum family family;
	47		struct cfg cfg;
	48
	49		struct atombios *atb;
	50
	51		struct dce6 *dce;
	52
	53		void __iomem *regs;
	54		size_t regs_sz;
	55		struct vram vram;
	56		struct ba ba;
	57		struct ucode ucode;
	58		struct cp cp0;
	59		struct cp cp1;
	60		struct cp cp2;
	61		struct ih ih;
	62
	63		/* userland */
	64		struct cdev si_cdev;
	65		struct device *si_dev;
	66		struct pci_dev *dev;
	67		};
	68
	69		u32 rr32(struct pci_dev *dev, unsigned offset);
	70		void wr32(struct pci_dev *dev, u32 val, unsigned offset);
	71		#endif /* _DRV_H */

File drivers/gpu/alga/amd/si/fops.c added (mode: 100644) (index 0000000..4d1ff6d)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/pci.h>
	8		#include <linux/fs.h>
	9		#include <linux/irq.h>
	10		#include <linux/cdev.h>
	11		#include <linux/slab.h>
	12		#include <asm/uaccess.h>
	13		#include <asm/ioctl.h>
	14		#include <linux/dma-direction.h>
	15
	16		#include <alga/rng_mng.h>
	17		#include <alga/pixel_fmts.h>
	18		#include <alga/timing.h>
	19		#include <alga/amd/dce4/dce4.h>
	20		#include <alga/amd/evergreen/ioctl.h>
	21
	22		#include "regs.h"
	23
	24		#include "ih.h"
	25		#include "ba.h"
	26		#include "ucode.h"
	27		#include "cp.h"
	28		#include "drv.h"
	29
	30		dev_t devt; /* global to the driver */
	31
	32		static int open(struct inode *i, struct file *f)
	33		{
	34		struct dev_drv_data *dd;
	35		//DEBUG
	36		printk(KERN_INFO "EVERGREEN OPEN\n");
	37		dd = container_of(i->i_cdev, struct dev_drv_data, evergreen_cdev);
	38		f->private_data = dd->dev;
	39		return 0;
	40		}
	41
	42		static int dce_dps_info(struct pci_dev *dev, void __user *user)
	43		{
	44		struct dev_drv_data *dd;
	45		int r;
	46		struct evergreen_dce_dps_info *info;
	47
	48
	49		/* too big for a kernel stack */
	50		info = kzalloc(sizeof(*info), GFP_KERNEL);
	51		if (!info)
	52		return -ENOMEM;
	53
	54		dd = pci_get_drvdata(dev);
	55
	56		r = dce4_dps_info(dd->dce, &info->used, &info->connected,
	57		&info->pixel_fmts, &info->timings);
	58		if (r != 0) {
	59		r = -ENODEV;
	60		goto free_info;
	61		}
	62		if(copy_to_user(user, info, sizeof(*info)))
	63		r = -EFAULT;
	64
	65		free_info:
	66		kfree(info);
	67		return r;
	68		}
	69
	70		static int dce_dp_set(struct pci_dev *dev, void __user *user)
	71		{
	72		struct dev_drv_data *dd;
	73		struct evergreen_dce_dp_set dp_set;
	74		struct db_fb db_fb;
	75		int r;
	76
	77		if(copy_from_user(&dp_set, user, sizeof(dp_set)))
	78		return -EFAULT;
	79
	80		db_fb.primary = dp_set.primary;
	81		db_fb.secondary = dp_set.secondary;
	82		db_fb.pixel_fmt = dp_set.pixel_fmt;
	83		db_fb.timing = dp_set.timing;
	84		db_fb.pitch = dp_set.pitch;
	85
	86		dd = pci_get_drvdata(dev);
	87
	88		r = dce4_sink_mode_set(dd->dce, dp_set.i, &db_fb);
	89		if (r != 0)
	90		return -ENODEV;
	91		return 0;
	92		}
	93
	94		static int dce_dp_dpm(struct pci_dev *dev, unsigned __user *user_i)
	95		{
	96		struct dev_drv_data *dd;
	97		unsigned i;
	98		int r;
	99
	100		get_user(i, user_i);
	101
	102		dd = pci_get_drvdata(dev);
	103
	104		r = dce4_dp_dpm(dd->dce, i);
	105		if (r != 0)
	106		return -ENODEV;
	107		return 0;
	108		}
	109
	110		static int dce_pf(struct pci_dev *dev, unsigned __user *user)
	111		{
	112		struct dev_drv_data *dd;
	113		unsigned i;
	114		unsigned vblanks_n;
	115		int r;
	116
	117		get_user(i, user);
	118
	119		dd = pci_get_drvdata(dev);
	120
	121		r = dce4_pf(dd->dce, i, &vblanks_n);
	122		if (r != 0)
	123		return -ENODEV;
	124		put_user(vblanks_n, user);
	125		return 0;
	126		}
	127
	128		static int evergreen_mem_alloc(struct pci_dev *dev,
	129		struct evergreen_mem __user *mem)
	130		{
	131		struct dev_drv_data *dd;
	132		u64 sz;
	133		u64 align;
	134		u64 gpu_addr;
	135		int r;
	136
	137		get_user(sz, &mem->sz);
	138		get_user(align, &mem->align);
	139
	140		dd = pci_get_drvdata(dev);
	141
	142		r = rng_alloc_align(&gpu_addr, &dd->vram.mng, sz, align);
	143		if (r == 0)
	144		put_user(gpu_addr, &mem->gpu_addr);
	145		else
	146		r = -ENODEV;
	147		return r;
	148		}
	149
	150		static void evergreen_mem_free(struct pci_dev *dev, u64 __user *user_gpu_addr)
	151		{
	152		u64 gpu_addr;
	153		struct dev_drv_data *dd;
	154
	155		get_user(gpu_addr, user_gpu_addr);
	156
	157		dd = pci_get_drvdata(dev);
	158
	159		rng_free(&dd->vram.mng, gpu_addr);
	160		}
	161
	162		static long unlocked_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
	163		{
	164		struct pci_dev *dev;
	165		int r;
	166		unsigned nr;
	167
	168		dev = f->private_data;
	169		nr = _IOC_NR(cmd);
	170
	171		r = 0;
	172		switch (nr) {
	173		case EVERGREEN_DCE_DPS_INFO:
	174		//DEBUG
	175		printk(KERN_INFO "IOCTL_EVERGREEN_DCE_DPS_INFO\n");
	176		r = dce_dps_info(dev, (void __user *)arg);
	177		break;
	178		case EVERGREEN_DCE_DP_SET:
	179		//DEBUG
	180		printk(KERN_INFO "EVERGREEN_DCE_DP_SET\n");
	181		r = dce_dp_set(dev, (void __user *)arg);
	182		break;
	183		case EVERGREEN_DCE_DP_DPM:
	184		//DEBUG
	185		printk(KERN_INFO "EVERGREEN_DCE_DP_DPM\n");
	186		r = dce_dp_dpm(dev, (unsigned __user *)arg);
	187		break;
	188		case EVERGREEN_DCE_PF:
	189		//DEBUG
	190		printk(KERN_INFO "EVERGREEN_DCE_PF\n");
	191		r = dce_pf(dev, (unsigned __user *)arg);
	192		break;
	193		case EVERGREEN_MEM_ALLOC:
	194		//DEBUG
	195		printk(KERN_INFO "EVERGREEN_MEM_ALLOC\n");
	196		r = evergreen_mem_alloc(dev,
	197		(struct evergreen_mem __user *)arg);
	198		break;
	199		case EVERGREEN_MEM_FREE:
	200		//DEBUG
	201		printk(KERN_INFO "EVERGREEN_MEM_FREE\n");
	202		evergreen_mem_free(dev, (u64 __user *)arg);
	203		break;
	204		case EVERGREEN_INFO:
	205		//DEBUG
	206		printk(KERN_INFO "EVERGREEN_INFO\n");
	207		break;
	208		default:
	209		r = -EINVAL;
	210		break;
	211		}
	212		return r;
	213		}
	214
	215		static int release(struct inode *i, struct file *f)
	216		{
	217		//DEBUG
	218		printk(KERN_INFO "EVERGREEN RELEASE\n");
	219		return 0;
	220		}
	221
	222		struct file_operations fops = {
	223		.owner = THIS_MODULE,
	224		.unlocked_ioctl = unlocked_ioctl,
	225		.open = open,
	226		.release = release,
	227		};

File drivers/gpu/alga/amd/si/fops.h added (mode: 100644) (index 0000000..736e636)
	1		#ifndef _FOPS_H
	2		#define _FOPS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		extern dev_t devt;
	9		extern struct file_operations fops;
	10		#endif

File drivers/gpu/alga/amd/si/gpu_address_space.layout added (mode: 100644) (index 0000000..5a3a733)
	1		Flexibility of PCIE aperture reprogramming is unknown.
	2		We book early the context 0 page table block (PTEs) in order to be low enough to be in the PCI bar0 aperture.
	3
	4		<---------PCI bar0 (256MB)---------->
	5		<------------VRAM-------------------------------><------------------------------BUS APERTURE----------------------------------------------->
	6		<-256 kB-> <----4 kB----> <------4 kB-----> <-----2^14 dwords-----> <----2^17 quadwords---->
	7		+------------------------------------------------------------------------------------------------------------------------------------------+
	8		| VGA | scratch page | PTEs | rest of VRAM || Write Back page | Interrup Handler ring | Command Processor ring | rest of bus aperture |
	9		+------------------------------------------------------------------------------------------------------------------------------------------+

File drivers/gpu/alga/amd/si/ih.c added (mode: 100644) (index 0000000..e0026d9)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/pci.h>
	7		#include <linux/interrupt.h>
	8		#include <linux/cdev.h>
	9
	10		#include <alga/rng_mng.h>
	11		#include <alga/timing.h>
	12		#include <alga/pixel_fmts.h>
	13		#include <alga/amd/dce4/dce4.h>
	14
	15		#include "regs.h"
	16
	17		#include "ih.h"
	18		#include "ba.h"
	19		#include "ucode.h"
	20		#include "cp.h"
	21		#include "drv.h"
	22
	23		void ih_start(struct pci_dev *dev)
	24		{
	25		u32 ih_ctl;
	26		u32 ih_rb_ctl;
	27
	28		ih_ctl = rr32(dev, IH_CTL);
	29		ih_rb_ctl = rr32(dev, IH_RB_CTL);
	30
	31		ih_ctl |= ENA_INTR;
	32		ih_rb_ctl |= IH_RB_ENA;
	33		wr32(dev, ih_ctl, IH_CTL);
	34		wr32(dev, ih_rb_ctl, IH_RB_CTL);
	35		}
	36
	37		void ih_stop(struct pci_dev *dev)
	38		{
	39		u32 ih_rb_ctl;
	40		u32 ih_ctl;
	41
	42		ih_rb_ctl = rr32(dev, IH_RB_CTL);
	43		ih_ctl = rr32(dev, IH_CTL);
	44
	45		ih_rb_ctl &= ~IH_RB_ENA;
	46		ih_ctl &= ~ENA_INTR;
	47
	48		/* works even if ucode in not loaded */
	49		wr32(dev, ih_rb_ctl, IH_RB_CTL);
	50		wr32(dev, ih_ctl, IH_CTL);
	51		}
	52
	53		/* ih ring size is 2^IH_RING_LOG2_DWS(=14) dwords or 4096 vectors of 16 bytes */
	54		#define WB_IH_WPTR_OF 2048
	55		void ih_init(struct pci_dev *dev)
	56		{
	57		struct dev_drv_data *dd;
	58		u32 intr_ctl;
	59		u32 ih_rb_ctl;
	60		u32 ih_ctl;
	61
	62		dd = pci_get_drvdata(dev);
	63
	64		/*
	65		* setup interrupt control
	66		* set dummy read address to ring address
	67		* 256 bytes block index
	68		*/
	69		wr32(dev, dd->ba.ih_ring_map->gpu_addr >> 8, INTR_CTL2);
	70
	71		intr_ctl = rr32(dev, INTR_CTL);
	72		/*
	73		* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled
	74		* without msi
	75		* IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_ENA
	76		*/
	77		intr_ctl &= ~IH_DUMMY_RD_OVERRIDE; /* GPU should disable dummy read */
	78
	79		/* IH_REQ_NONSNOOP_ENA=1 if ring is in non-cacheable mem, e.g. vram */
	80		intr_ctl &= ~IH_REQ_NONSNOOP_ENA; /* we are in bus aperture */
	81		wr32(dev, intr_ctl, INTR_CTL);
	82
	83		/* 256 bytes block index */
	84		wr32(dev, dd->ba.ih_ring_map->gpu_addr >> 8, IH_RB_BASE);
	85
	86		ih_rb_ctl = (IH_WPTR_OVERFLOW_ENA | IH_WPTR_OVERFLOW_CLR
	87		| SET(IH_IB_LOG2_DWS, IH_RING_LOG2_DWS)
	88		| IH_WPTR_WRITEBACK_ENA);
	89
	90		wr32(dev, (dd->ba.wb_map->gpu_addr + WB_IH_WPTR_OF) & 0xfffffffc,
	91		IH_RB_WPTR_ADDR_LO);
	92		wr32(dev, upper_32_bits(dd->ba.wb_map->gpu_addr + WB_IH_WPTR_OF) & 0xff,
	93		IH_RB_WPTR_ADDR_HI);
	94		wr32(dev, ih_rb_ctl, IH_RB_CTL);
	95
	96		wr32(dev, 0, IH_RB_RPTR);
	97		wr32(dev, 0, IH_RB_WPTR);
	98
	99		/* default settings for IH_CTL (disabled at first) */
	100		ih_ctl = SET(MC_WR_REQ_CREDIT, 0x10) | SET(MC_WR_CLEAN_CNT, 0x10)
	101		| RPTR_REARM;
	102		wr32(dev, ih_ctl, IH_CTL);
	103
	104		dd->ih.rp = 0;
	105		spin_lock_init(&dd->ih.lock);
	106		};
	107
	108		#define VECTOR_SZ 16
	109		#define VECTOR_ID_D0 1
	110		#define VECTOR_ID_D1 2
	111		#define VECTOR_ID_D2 3
	112		#define VECTOR_ID_D3 4
	113		#define VECTOR_ID_D4 5
	114		#define VECTOR_ID_D5 6
	115		#define Dx_VBLANK 0
	116		#define VECTOR_ID_HPD 42
	117
	118		static void vector(struct pci_dev *dev, u32 id, u32 data, bool *irq_thd)
	119		{
	120		struct dev_drv_data *dd;
	121		dd = pci_get_drvdata(dev);
	122
	123		switch (id) {
	124		case VECTOR_ID_HPD:
	125		dce4_hpd_irq(dd->dce, data);
	126		*irq_thd = true;
	127		break;
	128		case VECTOR_ID_D0:
	129		case VECTOR_ID_D1:
	130		case VECTOR_ID_D2:
	131		case VECTOR_ID_D3:
	132		case VECTOR_ID_D4:
	133		case VECTOR_ID_D5:
	134		if (data == Dx_VBLANK) {/* only page flipping in vblank */
	135		dce4_pf_irq(dd->dce, id - 1);
	136		*irq_thd = true;
	137		}
	138		break;
	139		}
	140		}
	141
	142		static u64 wp_overflow(struct pci_dev *dev, u32 wp)
	143		{
	144		struct dev_drv_data *dd;
	145		u32 tmp;
	146
	147		dd = pci_get_drvdata(dev);
	148
	149		if ((wp & RB_OVERFLOW) != 0) {
	150		/*
	151		* When a ring buffer overflow happen start parsing interrupt
	152		* from the last not overwritten vector (wptr + 16). Hopefully
	153		* this should allow us to catchup.
	154		*/
	155		dev_warn(&dev->dev, "ih ring buffer overflow wp=0x%08x"
	156		"rp=0x%08x, trying next vector at 0x%08x\n",
	157		(u32)(wp & (~RB_OVERFLOW)), dd->ih.rp,
	158		(wp + VECTOR_SZ) & IH_RING_MASK);
	159
	160		dd->ih.rp = (wp + VECTOR_SZ) & IH_RING_MASK;
	161
	162		tmp = rr32(dev, IH_RB_CTL);
	163		tmp |= IH_WPTR_OVERFLOW_CLR;
	164		wr32(dev, tmp, IH_RB_CTL);
	165
	166		wp &= ~RB_OVERFLOW;
	167		}
	168		return wp;
	169		}
	170
	171		bool ih_parse(struct pci_dev *dev)
	172		{
	173		struct dev_drv_data *dd;
	174		unsigned long flgs;
	175		u32 wp;
	176		u32 rp;
	177		bool irq_thd;
	178
	179		dd = pci_get_drvdata(dev);
	180		irq_thd = false;
	181
	182		spin_lock_irqsave(&dd->ih.lock, flgs);
	183		while (1) {
	184		rmb();
	185
	186		wp = le32_to_cpup(dd->ba.wb_map->cpu_addr + WB_IH_WPTR_OF);
	187		wp = wp_overflow(dev, wp);
	188		rp = dd->ih.rp;
	189
	190		if (rp == wp)
	191		break;
	192
	193		dce4_irqs_ack(dd->dce); /* must ack dce irqs ourself... */
	194
	195		do {
	196		u32 id;
	197		u32 data;
	198
	199		id = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp)
	200		& 0xff;
	201		data = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp
	202		+ sizeof(id)) & 0xfffffff;
	203
	204		vector(dev, id, data, &irq_thd);
	205
	206		rp += VECTOR_SZ;
	207		rp &= IH_RING_MASK;
	208		} while (rp != wp);
	209		dd->ih.rp = rp;
	210		}
	211		wr32(dev, dd->ih.rp, IH_RB_RPTR);
	212		spin_unlock_irqrestore(&dd->ih.lock, flgs);
	213		return irq_thd;
	214		}

File drivers/gpu/alga/amd/si/ih.h added (mode: 100644) (index 0000000..2f6d72d)
	1		#ifndef _IH_H
	2		#define _IH_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define IH_RING_LOG2_DWS 14
	9		#define IH_RING_MASK (((1 << IH_RING_LOG2_DWS) * 4) - 1)
	10
	11		struct ih {
	12		spinlock_t lock;
	13		u32 rp; /* the index of the next vector to process */
	14		};
	15		void ih_stop(struct pci_dev *dev);
	16		void ih_start(struct pci_dev *dev);
	17		void ih_init(struct pci_dev *dev);
	18		bool ih_parse(struct pci_dev *dev);
	19		#endif /* _IH_H */
	20

File drivers/gpu/alga/amd/si/pcie_ports.h added (mode: 100644) (index 0000000..36fd211)
	1		#ifndef _PCIE_PORTS_H
	2		#define _PCIE_PORTS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		#define PCIE_LC_TRAINING_CTL 0xa1
	10		#define LC_POINT_7_PLUS_EN (1 << 6)
	11		#define PCIE_LC_LINK_WIDTH_CTL 0xa2
	12		#define LC_LINK_WIDTH_SHIFT 0
	13		#define LC_LINK_WIDTH_MASK 0x7
	14		#define LC_LINK_WIDTH_X0 0
	15		#define LC_LINK_WIDTH_X1 1
	16		#define LC_LINK_WIDTH_X2 2
	17		#define LC_LINK_WIDTH_X4 3
	18		#define LC_LINK_WIDTH_X8 4
	19		#define LC_LINK_WIDTH_X16 6
	20		#define LC_LINK_WIDTH_RD_SHIFT 4
	21		#define LC_LINK_WIDTH_RD_MASK 0x70
	22		#define LC_RECFG_ARC_MISSING_ESCAPE (1 << 7)
	23		#define LC_RECFG_NOW (1 << 8)
	24		#define LC_RENEGOTIATION_SUPPORT (1 << 9)
	25		#define LC_RENEGOTIATE_EN (1 << 10)
	26		#define LC_SHORT_RECFG_EN (1 << 11)
	27		#define LC_UPCONFIGURE_SUPPORT (1 << 12)
	28		#define LC_UPCONFIGURE_DIS (1 << 13)
	29		#define PCIE_LC_SPEED_CTL 0xa4
	30		#define LC_GEN2_EN_STRAP (1 << 0)
	31		#define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
	32		#define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
	33		#define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
	34		#define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
	35		#define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
	36		#define LC_CURRENT_DATA_RATE (1 << 11)
	37		#define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
	38		#define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
	39		#define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
	40		#define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
	41		#define LINK_CTL2 0x88 /* F0 */
	42		#define TARGET_LINK_SPEED_MASK (0xf << 0)
	43		#define SELECTABLE_DEEMPHASIS (1 << 6)
	44
	45		#endif /* _PCIE_PORTS_H */

File drivers/gpu/alga/amd/si/regs added (mode: 100644) (index 0000000..26a9d66)
	1		Registers are in the PCI BAR region 2.
	2
	3		Not all registers were published by AMD. Hope those registers are *not*
	4		significant for the efficiency of the GPU operations.
	5
	6		Most graphics/3D regs sit behind a smart fifo (the rbm) because it is complex
	7		to deal with those, while other like display/asic setup/config regs do not.
	8
	9		The indirect access of a target register in done via the first two 32 bits
	10		registers:
	11
	12		o Target register address/index goes in the first 32bits word of the register
	13		address space.
	14
	15		o Target register value goes in/comes from the 2nd 32 bits word of the
	16		register address space.
	17
	18		********************************************************************************
	19		This indirect access works with the gpu address space with setting the bit 31
	20		of the index reg
	21		********************************************************************************
	22
	23		You have also register muliplexing for the GRBM and RLC block among "instances"
	24		and shader engines. You need to select using RLC_GFX_IDX and GRBM_GFX_IDX which
	25		"instances" and shader engines you intend to program.

File drivers/gpu/alga/amd/si/regs.h added (mode: 100644) (index 0000000..44dd7d2)
	1		#ifndef _REGS_H
	2		#define _REGS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		/*
	10		* many masks are 0xfffffff because we need the info from AMD
	11		* or need to deduce from other values in the register
	12		*/
	13
	14		#define SET(n, x) (((x) << n##_SHIFT) & n##_MASK)
	15		#define GET(n, x) (((x) & n##_MASK) >> n##_SHIFT)
	16
	17		#define PCIE_PORT_INDEX 0x38
	18		#define PCIE_PORT_DATA 0x3c
	19
	20		#define RCU_IDX 0x100
	21		#define RCU_DATA 0x104
	22
	23		#define SRBM_STATUS 0xe50
	24		#define MC_STATUS_MASK 0x00001f00
	25		#define MC_STATUS_SHIFT 8
	26
	27		#define CC_SYS_RB_BACKEND_DIS 0xe80
	28		#define GC_USER_SYS_RB_BACKEND_DIS 0xe84
	29
	30		#define VM_L2_CTL_0 0x1400
	31		#define ENA_L2_CACHE BIT(0)
	32		#define ENA_L2_FRAG_PROCESSING BIT(1)
	33		#define L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xffffffff
	34		#define L2_CACHE_PTE_ENDIAN_SWAP_MODE_SHIFT 2
	35		#define L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0xffffffff
	36		#define L2_CACHE_PDE_ENDIAN_SWAP_MODE_SHIFT 4
	37		#define ENA_L2_PTE_CACHE_LRU_UPDATE_BY_WR BIT(9)
	38		#define ENA_L2_PDE0_CACHE_LRU_UPDATE_BY_WR BIT(10)
	39		#define EFFECTIVE_L2_QUEUE_SZ_MASK 0x0001c000
	40		#define EFFECTIVE_L2_QUEUE_SZ_SHIFT 14
	41		#define CTX1_IDENTITY_ACCESS_MODE_MASK 0x00180000
	42		#define CTX1_IDENTITY_ACCESS_MODE_SHIFT 19
	43		#define VM_L2_CTL_1 0x1404
	44		#define INVALIDATE_ALL_L1_TLBS BIT(0)
	45		#define INVALIDATE_L2_CACHE BIT(1)
	46		#define INVALIDATE_CACHE_MODE_MASK 0xffffffff
	47		#define INVALIDATE_CACHE_MODE_SHIFT 26
	48		#define INVALIDATE_PTE_AND_PDE_CACHES 0
	49		#define INVALIDATE_ONLY_PTE_CACHES 1
	50		#define INVALIDATE_ONLY_PDE_CACHES 2
	51		#define VM_L2_CTL_2 0x1408
	52		#define BANK_SELECT_MASK 0xffffffff
	53		#define BANK_SELECT_SHIFT 0
	54		#define L2_CACHE_UPDATE_MODE_MASK 0xffffffff
	55		#define L2_CACHE_UPDATE_MODE_SHIFT 6
	56		#define L2_CACHE_BIGK_FRAGMENT_SZ_MASK 0xffffffff
	57		#define L2_CACHE_BIGK_FRAGMENT_SZ_SHIFT 15
	58		#define L2_CACHE_BIGK_ASSOCIATIVITY BIT(20)
	59
	60		#define VM_L2_STATUS 0x140c
	61		#define L2_BUSY BIT(0)
	62
	63		#define VM_CTX_0_CTL_0 0x1410
	64		#define ENA_CTX BIT(0)
	65		#define PT_DEPTH_MASK 0x00000006
	66		#define PT_DEPTH_SHIFT 1
	67		#define RNG_PROTECTION_FAULT_ENA_DEFAULT BIT(4)
	68		#define VM_CTX_1_CTL_0 0x1414
	69		#define VM_CTX_0_CTL_1 0x1430
	70		#define VM_CTX_1_CTL_1 0x1434
	71		#define VM_CTX_8_PT_BASE_ADDR 0x1438
	72		#define VM_CTX_9_PT_BASE_ADDR 0x143c
	73		#define VM_CTX_A_PT_BASE_ADDR 0x1440
	74		#define VM_CTX_B_PT_BASE_ADDR 0x1444
	75		#define VM_CTX_C_PT_BASE_ADDR 0x1448
	76		#define VM_CTX_D_PT_BASE_ADDR 0x144c
	77		#define VM_CTX_E_PT_BASE_ADDR 0x1450
	78		#define VM_CTX_F_PT_BASE_ADDR 0x1454
	79
	80		//TODO:confirm it's gone
	81		//#define VM_CTX_0_REQ_RESP 0x1470
	82		//#define REQ_TYPE_MASK 0x0000000f
	83		//#define REQ_TYPE_SHIFT 0
	84		//#define TLB_FLUSH 1
	85		//#define RESP_TYPE_MASK 0x000000f0
	86		//#define RESP_TYPE_SHIFT 4
	87		//#define RESP_FAILED 2
	88
	89		#define VM_INVALIDATE_REQ 0x1478
	90		#define VM_INVALIDATE_RESP 0x147c
	91
	92		#define VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
	93		#define VM_CTX_1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
	94		#define VM_CTX_0_PT_BASE_ADDR 0x153c
	95		#define VM_CTX_1_PT_BASE_ADDR 0x1540
	96		#define VM_CTX_2_PT_BASE_ADDR 0x1544
	97		#define VM_CTX_3_PT_BASE_ADDR 0x1548
	98		#define VM_CTX_4_PT_BASE_ADDR 0x154c
	99		#define VM_CTX_5_PT_BASE_ADDR 0x1550
	100		#define VM_CTX_6_PT_BASE_ADDR 0x1554
	101		#define VM_CTX_7_PT_BASE_ADDR 0x1558
	102		#define VM_CTX_0_PT_START_ADDR 0x155c
	103		#define VM_CTX_1_PT_START_ADDR 0x1560
	104		//#define VM_CTX_2_PT_START_ADDR 0x1564
	105		//#define VM_CTX_3_PT_START_ADDR 0x1568
	106		//#define VM_CTX_4_PT_START_ADDR 0x156c
	107		//#define VM_CTX_5_PT_START_ADDR 0x1570
	108		//#define VM_CTX_6_PT_START_ADDR 0x1574
	109		//#define VM_CTX_7_PT_START_ADDR 0x1578
	110		#define VM_CTX_0_PT_END_ADDR 0x157c
	111		#define VM_CTX_1_PT_END_ADDR 0x1580
	112		//#define VM_CTX_2_PT_END_ADDR 0x1584
	113		//#define VM_CTX_3_PT_END_ADDR 0x1588
	114		//#define VM_CTX_4_PT_END_ADDR 0x158c
	115		//#define VM_CTX_5_PT_END_ADDR 0x1590
	116		//#define VM_CTX_6_PT_END_ADDR 0x1594
	117		//#define VM_CTX_7_PT_END_ADDR 0x1598
	118		//#define VM_CTX_8_PT_END_ADDR 0x159c
	119		//#define VM_CTX_9_PT_END_ADDR 0x15a0
	120		//#define VM_CTX_A_PT_END_ADDR 0x15a4
	121		//#define VM_CTX_B_PT_END_ADDR 0x15a8
	122		//#define VM_CTX_C_PT_END_ADDR 0x15ac
	123		//#define VM_CTX_D_PT_END_ADDR 0x15b0
	124		//#define VM_CTX_E_PT_END_ADDR 0x15b4
	125		//#define VM_CTX_F_PT_END_ADDR 0x15b8
	126
	127		// ???
	128		//0x15d4
	129		//0x15d8
	130		//0x15dc
	131
	132		#define MC_SHARED_CHMAP 0x2004
	133		#define CHANS_N_MASK 0x0000f000
	134		#define CHANS_N_SHIFT 12
	135		#define MC_SHARED_CHREMAP 0x2008
	136
	137		#define MC_VRAM_LOCATION 0x2024 /* 16MB aligned */
	138		#define MC_AGP_TOP 0x2028 /* 4MB aligned */
	139		#define MC_AGP_BOT 0x202c /* 4MB aligned */
	140		#define MC_AGP_BASE 0x2030
	141		#define MC_VM_SYS_APER_LOW_ADDR 0x2034
	142		#define MC_VM_SYS_APER_HIGH_ADDR 0x2038
	143		#define MC_VM_SYS_APER_DEFAULT_ADDR 0x203c
	144
	145		/* MX stands probably for MB and MD */
	146		#define MC_VM_MX_L1_TLB_CTL 0x2064
	147		#define ENA_L1_TLB BIT(0)
	148		#define ENA_L1_FRAG_PROCESSING BIT(1)
	149		#define SYS_ACCESS_MODE_MASK 0x00000018
	150		#define SYS_ACCESS_MODE_SHIFT 3
	151		#define PA_ONLY 0
	152		#define USE_SYS_MAY 1
	153		#define IN_SYS 2
	154		#define NOT_IN_SYS 3
	155		#define SYS_APER_UNMAPPED_ACCESS_MASK 0xffffffff
	156		#define SYS_APER_UNMAPPED_ACCESS_SHIFT 5
	157		#define PASS_THRU 0
	158		#define ENA_ADVANCED_DRIVER_MODEL BIT(6)
	159
	160		#define MC_SHARED_BLACKOUT_CTL 0x20ac
	161
	162		//TODO:confirm it's gone
	163		///* MB acronym unknown */
	164		//#define MC_VM_MB_L1_TLB_0_CTL 0x2234
	165		//#define MC_VM_MB_L1_TLB_1_CTL 0x2238
	166		//#define MC_VM_MB_L1_TLB_2_CTL 0x223C
	167		//#define MC_VM_MB_L1_TLB_3_CTL 0x2240
	168		//#define ENA_L1_TLB BIT(0)
	169		//#define ENA_L1_FRAG_PROCESSING BIT(1)
	170		//#define SYS_ACCESS_MODE_MASK 0x00000018
	171		//#define SYS_ACCESS_MODE_SHIFT 3
	172		//#define PA_ONLY 0
	173		//#define USE_SYS_MAY 1
	174		//#define IN_SYS 2
	175		//#define NOT_IN_SYS 3
	176		//#define SYS_APER_UNMAPPED_ACCESS_MASK 0xffffffff
	177		//#define SYS_APER_UNMAPPED_ACCESS_SHIFT 5
	178		//#define PASS_THRU 0
	179		//#define EFFECTIVE_L1_TLB_SZ_MASK 0xffffffff
	180		//#define EFFECTIVE_L1_TLB_SZ_SHIFT 15
	181		//#define EFFECTIVE_L1_QUEUE_SZ_MASK 0xffffffff
	182		//#define EFFECTIVE_L1_QUEUE_SZ_SHIFT 18
	183		//
	184		///* MD acronym unknown, see MC_VM_MB_L1_TLB*_* regs */
	185		//#define MC_VM_MD_L1_TLB_0_CTL 0x2654
	186		//#define MC_VM_MD_L1_TLB_1_CTL 0x2658
	187		//#define MC_VM_MD_L1_TLB_2_CTL 0x265c
	188		//#define MC_VM_MD_L1_TLB_3_CTL 0x2698
	189
	190		#define MC_ARB_RAM_CFG 0x2760
	191		#define MC_BANKS_N_MASK 0x00000003
	192		#define MC_BANKS_N_SHIFT 0
	193		#define MC_RANKS_N_MASK 0x00000004
	194		#define MC_RANKS_N_SHIFT 2
	195		#define MC_ROWS_N_MASK 0x00000038
	196		#define MC_ROWS_N_SHIFT 3
	197		#define MC_COLS_N_MASK 0x000000c0
	198		#define MC_COLS_N_SHIFT 6
	199		#define CHAN_SZ_MASK 0x00000100
	200		#define CHAN_SZ_SHIFT 8 /* 64 or 32 bits */
	201		#define BURST_LEN_MASK 0x00000200
	202		#define BURST_LEN_SHIFT 9
	203		#define CHAN_SZ_OVERRIDE BIT(11)
	204		#define MC_GROUPS_N_MASK 0x00001000
	205		#define MC_GROUPS_N_SHIFT 12
	206
	207		#define MC_SEQ_TRAIN_WAKEUP_CTL 0x2808
	208		#define TRAIN_DONE_D0 BIT(30)
	209		#define TRAIN_DONE_D1 BIT(31)
	210
	211		#define MC_IO_PAD_CTL_D0 0x29d0
	212		#define MEM_FALL_OUT_CMD BIT(8)
	213
	214		#define MC_SEQ_SUP_CTL 0x28c8
	215		#define RUN_MASK BIT(0)
	216		#define MC_SEQ_SUP_PGM 0x28cc
	217
	218		#define MC_SEQ_IO_DBG_IDX 0x2a44
	219		#define MC_SEQ_IO_DBG_DATA 0x2a48
	220
	221		#define HDP_HOST_PATH_CTL 0x2c00
	222		#define HDP_NONSURFACE_BASE 0x2c04
	223		#define HDP_NONSURFACE_INFO 0x2c08
	224		#define HDP_NONSURFACE_SZ 0x2c0c
	225
	226		#define HDP_ADDR_CFG 0x2f48
	227		#define HDP_MISC_CTL 0x2f4c
	228		#define HDP_FLUSH_INVALIDATE_CACHE BIT(0)
	229
	230		/*
	231		* HDP data
	232		* 0x2c14 - 0x2f27 32 blocks of 0x18 bytes
	233		*/
	234
	235		#define IH_RB_CTL 0x3e00
	236		#define IH_RB_ENA BIT(0)
	237		#define IH_IB_LOG2_DWS_MASK 0xffffffff
	238		#define IH_IB_LOG2_DWS_SHIFT 1
	239		#define IH_RB_FULL_DRAIN_ENA BIT(6)
	240		#define IH_WPTR_WRITEBACK_ENA BIT(8)
	241		#define IH_WPTR_WRITEBACK_TIMER_MASK 0xffffffff
	242		#define IH_WPTR_WRITEBACK_TIMER_SHIFT 9
	243		#define IH_WPTR_OVERFLOW_ENA BIT(16)
	244		#define IH_WPTR_OVERFLOW_CLR BIT(31)
	245		#define IH_RB_BASE 0x3e04
	246		#define IH_RB_RPTR 0x3e08
	247		#define IH_RB_WPTR 0x3e0c
	248		#define RB_OVERFLOW BIT(0)
	249		#define WPTR_OF_MASK 0x3fffc
	250		#define IH_RB_WPTR_ADDR_HI 0x3e10
	251		#define IH_RB_WPTR_ADDR_LO 0x3e14
	252		#define IH_CTL 0x3e18
	253		#define ENA_INTR BIT(0)
	254		#define IH_MC_SWAP_MASK 0x00000006
	255		#define IH_MC_SWAP_SHIFT 1
	256		#define IH_MC_SWAP_NONE 0
	257		#define IH_MC_SWAP_16BIT 1
	258		#define IH_MC_SWAP_32BIT 2
	259		#define IH_MC_SWAP_64BIT 3
	260		#define RPTR_REARM BIT(4)
	261		#define MC_WR_REQ_CREDIT_MASK 0xffffffff
	262		#define MC_WR_REQ_CREDIT_SHIFT 15
	263		#define MC_WR_CLEAN_CNT_MASK 0xffffffff
	264		#define MC_WR_CLEAN_CNT_SHIFT 20
	265		#define MC_VM_ID_MASK 0xffffffff
	266		#define MC_VM_ID_SHIFT 25
	267
	268
	269		//TODO:confirm it's gone
	270		//#define CGTS_SYS_TCC_DIS 0x3f90
	271		//#define CGTS_USER_SYS_TCC_DIS 0x3f94
	272		//
	273		//#define RLC_GFX_IDX 0x3fc4 /* see GRDBM_GFX_IDX */
	274
	275		#define CFG_MEM_SZ 0x5428 /* unit is MB */
	276
	277		#define INTR_CTL_0 0x5468
	278		#define IH_DUMMY_RD_OVERRIDE BIT(0)
	279		#define IH_DUMMY_RD_ENA BIT(1)
	280		#define IH_REQ_NONSNOOP_ENA BIT(3)
	281		#define GEN_IH_INT_ENA BIT(8)
	282		#define INTR_CTL_1 0x546c
	283
	284		#define HDP_MEM_COHERENCY_FLUSH_CTL 0x5480
	285		#define BIF_FB_ENA 0x5490
	286		#define FB_RD_ENA BIT(0)
	287		#define FB_WR_ENA BIT(1)
	288		#define HDP_REG_COHERENCY_FLUSH_CTL 0x54a0
	289
	290		/* start of configuration register area: 0x8000-0xac00 */
	291		#define GRBM_CTL 0x8000
	292		#define GRBM_RD_TIMEOUT_MASK 0xffffffff
	293		#define GRBM_RD_TIMEOUT_SHIFT 0
	294		#define GRBM_STATUS_1 0x8008
	295		#define RLC_RQ_PENDING BIT(0)
	296		#define RLC_BUSY BIT(8)
	297		#define TC_BUSY BIT(9)
	298		#define GRBM_STATUS_0 0x8010
	299		#define CMDFIFO_AVAIL_MASK 0x0000000f
	300		#define CMDFIFO_AVAIL_SHIFT 0
	301		#define RING2_RQ_PENDING BIT(4)
	302		#define SRBM_RQ_PENDING BIT(5)
	303		#define RING1_RQ_PENDING BIT(6)
	304		#define CF_RQ_PENDING BIT(7)
	305		#define PF_RQ_PENDING BIT(8)
	306		#define GDS_DMA_RQ_PENDING BIT(9)
	307		#define GRBM_EE_BUSY BIT(10)
	308		#define DB_CLEAN BIT(12)
	309		#define CB_CLEAN BIT(13)
	310		#define TA_BUSY BIT(14)
	311		#define GDS_BUSY BIT(15)
	312		#define VGT_BUSY_NO_DMA BIT(16)
	313		#define VGT_BUSY BIT(17)
	314		#define IA_BUSY_NO_DMA BIT(18)
	315		#define IA_BUSY BIT(19)
	316		#define SX_BUSY BIT(20)
	317		#define SPI_BUSY BIT(22)
	318		#define BCI_BUSY BIT(23)
	319		#define SC_BUSY BIT(24)
	320		#define PA_BUSY BIT(25)
	321		#define DB_BUSY BIT(26)
	322		#define CP_COHERENCY_BUSY BIT(28)
	323		#define CP_BUSY BIT(29)
	324		#define CB_BUSY BIT(30)
	325		#define GUI_ACTIVE BIT(31)
	326
	327		#define GRBM_STATUS_SE0 0x8014
	328		#define GRBM_STATUS_SE1 0x8018
	329		#define SE_DB_CLEAN BIT(1)
	330		#define SE_CB_CLEAN BIT(2)
	331		#define SE_BCI_BUSY BIT(22)
	332		#define SE_VGT_BUSY BIT(23)
	333		#define SE_PA_BUSY BIT(24)
	334		#define SE_TA_BUSY BIT(25)
	335		#define SE_SX_BUSY BIT(26)
	336		#define SE_SPI_BUSY BIT(27)
	337		#define SE_SH_BUSY BIT(28)
	338		#define SE_SC_BUSY BIT(29)
	339		#define SE_DB_BUSY BIT(30)
	340		#define SE_CB_BUSY BIT(31)
	341
	342		#define GRBM_SOFT_RESET 0x8020
	343		#define SOFT_RESET_CP BIT(0)
	344		#define SOFT_RESET_CB BIT(1)
	345		#define SOFT_RESET_RLC BIT(2)
	346		#define SOFT_RESET_DB BIT(3)
	347		#define SOFT_RESET_GDS BIT(4)
	348		#define SOFT_RESET_PA BIT(5)
	349		#define SOFT_RESET_SC BIT(6)
	350		#define SOFT_RESET_BCI BIT(7)
	351		#define SOFT_RESET_SPI BIT(8)
	352		#define SOFT_RESET_SH BIT(9)
	353		#define SOFT_RESET_SX BIT(10)
	354		#define SOFT_RESET_TC BIT(11)
	355		#define SOFT_RESET_TA BIT(12)
	356		#define SOFT_RESET_VC BIT(13)
	357		#define SOFT_RESET_VGT BIT(14)
	358		#define SOFT_RESET_IA BIT(15)
	359
	360		#define GRBM_GFX_IDX 0x802c
	361		#define INST_IDX_MASK 0xffffffff
	362		#define INST_IDX_SHIFT 0
	363		#define SH_IDX_MASK 0xffffffff
	364		#define SH_IDX_SHIFT 8
	365		#define SE_IDX_MASK 0xffffffff
	366		#define SE_IDX_SHIFT 16
	367		#define SH_BROADCAST_WRS BIT(29)
	368		#define INST_BROADCAST_WRS BIT(30)
	369		#define SE_BROADCAST_WRS BIT(31)
	370
	371		#define GRBM_INT_CTL 0x8060
	372		#define RD_ERR_INT_ENA BIT(0)
	373		#define GUI_IDLE_INT_ENA BIT(19)
	374
	375		/* not yet used in the code
	376		#define SCRATCH_REG0 0x8500
	377		#define SCRATCH_REG1 0x8504
	378		#define SCRATCH_REG2 0x8508
	379		#define SCRATCH_REG3 0x850c
	380		#define SCRATCH_REG4 0x8510
	381		#define SCRATCH_REG5 0x8514
	382		#define SCRATCH_REG6 0x8518
	383		#define SCRATCH_REG7 0x851c
	384		*/
	385		#define SCRATCH_UMSK 0x8540
	386		#define SCRATCH_ADDR 0x8544
	387
	388		#define CP_SEM_WAIT_TIMER 0x85bc
	389
	390		#define CP_SEM_INCOMPLETE_TIMER_CTL 0x85c8
	391
	392		#define CP_COHER_CTL_2 0x85e8
	393
	394		#define CP_ME_CTL 0x86d8
	395		#define CP_CE_HALT BIT(24)
	396		#define CP_PFP_HALT BIT(26)
	397		#define CP_ME_HALT BIT(28)
	398
	399
	400		#define CP_RB2_RPT 0x86f8
	401		#define CP_RB1_RPT 0x86fc
	402		#define CP_RB0_RPTR 0x8700
	403		#define CP_RB0_WPTR_DELAY 0x8704
	404
	405		#define CP_QUEUE_THRESHOLDS 0x8760
	406		#define ROQ_IB_0_START_MASK 0xffffffff
	407		#define ROQ_IB_0_START_SHIFT 0
	408		#define ROQ_IB_1_START_MASK 0xffffffff
	409		#define ROQ_IB_1_START_SHIFT 8
	410		#define CP_MEQ_THRESHOLDS 0x8764
	411		#define MEQ_0_START_MASK 0xffffffff
	412		#define MEQ_0_START_SHIFT 0
	413		#define MEQ_1_START_MASK 0xffffffff
	414		#define MEQ_1_START_SHIFT 8
	415
	416		#define CP_PERFMON_CTL 0x87fc
	417
	418		#define VGT_VTX_VECT_EJECT_REG 0x88b0
	419
	420		#define VGT_CACHE_INVALIDATION 0x88c4
	421		#define CACHE_INVALIDATION_MASK 0x00000003
	422		#define CACHE_INVALIDATION_SHIFT 0
	423		#define VC_ONLY 0
	424		#define TC_ONLY 1
	425		#define VC_AND_TC 2
	426		#define AUTO_INVLD_ENA_MASK 0x000000c0
	427		#define AUTO_INVLD_ENA_SHIFT 6
	428		#define NO_AUTO 0
	429		#define ES_AUTO 1
	430		#define GS_AUTO 2
	431		#define ES_AND_GS_AUTO 3
	432		#define VGT_ESGS_RING_SZ 0x88c8
	433		#define VGT_GSVS_RING_SZ 0x88cc
	434
	435		#define VGT_GS_VTX_REUSE 0x88d4
	436
	437		//TODO:confirm it's gone
	438		//#define CC_GC_SHADER_PIPE_CFG 0x8950
	439		//#define WR_DIS BIT(0)
	440		//#define GC_USER_SHADER_PIPE_CFG 0x8954
	441		//#define INACTIVE_QD_PIPES_MASK 0x0000ff00
	442		//#define INACTIVE_QD_PIPES_SHIFT 8
	443		//#define INACTIVE_SIMDS_MASK 0x00ff0000
	444		//#define INACTIVE_SIMDS_SHIFT 16
	445		#define VGT_PRIM_TYPE 0x8958
	446		#define VGT_IDX_TYPE 0x895c
	447
	448		#define VGT_INDICES_N 0x8970
	449		#define VGT_INSTS_N 0x8974
	450
	451		#define VGT_TF_RING_SZ 0x8988
	452
	453		#define VGT_HS_OFFCHIP_PARAM 0x89b0
	454
	455		#define VGT_TF_MEM_BASE 0x89b8
	456
	457		#define CC_GC_SHADER_ARRAY_CFG 0x89bc
	458		#define SH_CUS_N_MAX 16
	459		#define INACTIVE_CUS_VALID BIT(0)
	460		#define INACTIVE_CUS_MASK 0xffff0000
	461		#define INACTIVE_CUS_SHIFT 16
	462		#define GC_USER_SHADER_ARRAY_CFG 0x89c0
	463
	464		#define PA_CL_ENHANCE 0x8a14
	465		#define CLIP_VTX_REORDER_ENA BIT(0)
	466		#define CLIP_SEQ_N_MASK 0xffffffff
	467		#define CLIP_SEQ_N_SHIFT 1
	468
	469		#define PA_SU_LINE_STIPPLE_VALUE 0x8a60
	470
	471		#define PA_SC_LINE_STIPPLE_STATE 0x8b10
	472
	473		#define PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
	474		#define FORCE_EOV_MAX_CLK_CNT_MASK 0xffffffff
	475		#define FORCE_EOV_MAX_CLK_CNT_SHIFT 0
	476		#define FORCE_EOV_MAX_REZ_CNT_MASK 0xffffffff
	477		#define FORCE_EOV_MAX_REZ_CNT_SHIFT 16
	478
	479		#define PA_SC_FIFO_SZ 0x8bcc
	480		#define SC_FRONTEND_PRIM_FIFO_SZ_MASK 0xffffffff
	481		#define SC_FRONTEND_PRIM_FIFO_SZ_SHIFT 0
	482		#define SC_BACKEND_PRIM_FIFO_SZ_MASK 0xffffffff
	483		#define SC_BACKEND_PRIM_FIFO_SZ_SHIFT 6
	484		#define SC_HIZ_TILE_FIFO_SZ_MASK 0xffffffff
	485		#define SC_HIZ_TILE_FIFO_SZ_SHIFT 15
	486		#define SC_EARLYZ_TILE_FIFO_SZ_MASK 0xffffffff
	487		#define SC_EARLYZ_TILE_FIFO_SZ_SHIFT 23
	488
	489		#define PA_SC_ENHANCE 0x8bf0
	490
	491		#define SQ_CFG 0x8c00
	492		//TODO:confirm it's gone (GCN)
	493		//#define VC_ENA BIT(0)
	494		//#define EXPORT_SRC_C BIT(1)
	495		//#define CS_PRIO_MASK 0x000c0000
	496		//#define CS_PRIO_SHIFT 18
	497		//#define LS_PRIO_MASK 0x00300000
	498		//#define LS_PRIO_SHIFT 20
	499		//#define HS_PRIO_MASK 0x00c00000
	500		//#define HS_PRIO_SHIFT 22
	501		//#define PS_PRIO_MASK 0x03000000
	502		//#define PS_PRIO_SHIFT 24
	503		//#define VS_PRIO_MASK 0x0c000000
	504		//#define VS_PRIO_SHIFT 26
	505		//#define GS_PRIO_MASK 0x30000000
	506		//#define GS_PRIO_SHIFT 28
	507		//#define ES_PRIO_MASK 0xc0000000
	508		//#define ES_PRIO_SHIFT 30
	509
	510		//TODO:confirm it's gone (GCN)
	511		//#define SQ_GPR_RES_MGMT_0 0x8c04
	512		//#define PS_GPRS_N_MASK 0xffffffff
	513		//#define PS_GPRS_N_SHIFT 0
	514		//#define VS_GPRS_N_MASK 0xffffffff
	515		//#define VS_GPRS_N_SHIFT 16
	516		//#define CLAUSE_TMP_GPRS_N_MASK 0xffffffff
	517		//#define CLAUSE_TMP_GPRS_N_SHIFT 28
	518
	519		#define SQC_CACHES 0x8c08
	520
	521		//TODO:confirm it's gone (GCN)
	522		//#define SQ_GPR_RES_MGMT_1 0x8c08
	523		//#define GS_GPRS_N_MASK 0xffffffff
	524		//#define GS_GPRS_N_SHIFT 0
	525		//#define ES_GPRS_N_MASK 0xffffffff
	526		//#define ES_GPRS_N_SHIFT 16
	527
	528		//#define SQ_GPR_RES_MGMT_2 0x8c0c
	529		//#define HS_GPRS_N_MASK 0xffffffff
	530		//#define HS_GPRS_N_SHIFT 0
	531		//#define LS_GPRS_N_MASK 0xffffffff
	532		//#define LS_GPRS_N_SHIFT 16
	533		//#define SQ_GLOBAL_GPR_RES_MGMT_0 0x8c10
	534		//#define SQ_GLOBAL_GPR_RES_MGMT_1 0x8c14
	535		//#define SQ_THD_RES_MGMT_0 0x8c18
	536		//#define PS_THDS_N_MASK 0xffffffff
	537		//#define PS_THDS_N_SHIFT 0
	538		//#define VS_THDS_N_MASK 0xffffffff
	539		//#define VS_THDS_N_SHIFT 8
	540		//#define GS_THDS_N_MASK 0xffffffff
	541		//#define GS_THDS_N_SHIFT 16
	542		//#define ES_THDS_N_MASK 0xffffffff
	543		//#define ES_THDS_N_SHIFT 24
	544
	545		//#define SQ_THD_RES_MGMT_1 0x8c1c
	546		//#define HS_THDS_N_MASK 0xffffffff
	547		//#define HS_THDS_N_SHIFT 0
	548		//#define LS_THDS_N_MASK 0xffffffff
	549		//#define LS_THDS_N_SHIFT 8
	550
	551		//#define SQ_STACK_RES_MGMT_0 0x8c20
	552		//#define PS_STACK_ENTRIES_N_MASK 0xffffffff
	553		//#define PS_STACK_ENTRIES_N_SHIFT 0
	554		//#define VS_STACK_ENTRIES_N_MASK 0xffffffff
	555		//#define VS_STACK_ENTRIES_N_SHIFT 16
	556
	557		//#define SQ_STACK_RES_MGMT_1 0x8c24
	558		//#define GS_STACK_ENTRIES_N_MASK 0xffffffff
	559		//#define GS_STACK_ENTRIES_N_SHIFT 0
	560		//#define ES_STACK_ENTRIES_N_MASK 0xffffffff
	561		//#define ES_STACK_ENTRIES_N_SHIFT 16
	562
	563		//#define SQ_STACK_RES_MGMT_2 0x8c28
	564		//#define HS_STACK_ENTRIES_N_MASK 0xffffffff
	565		//#define HS_STACK_ENTRIES_N_SHIFT 0
	566		//#define LS_STACK_ENTRIES_N_MASK 0xffffffff
	567		//#define LS_STACK_ENTRIES_N_SHIFT 16
	568
	569		//#define SQ_MS_FIFO_SZS 0x8cf0
	570		//#define CACHE_FIFO_SZ_MASK 0xffffffff
	571		//#define CACHE_FIFO_SZ_SHIFT 0
	572		//#define FETCH_FIFO_HIWATER_MASK 0xffffffff
	573		//#define FETCH_FIFO_HIWATER_SHIFT 8
	574		//#define DONE_FIFO_HIWATER_MASK 0xffffffff
	575		//#define DONE_FIFO_HIWATER_SHIFT 16
	576		//#define ALU_UPDATE_FIFO_HIWATER_MASK 0xffffffff
	577		//#define ALU_UPDATE_FIFO_HIWATER_SHIFT 24
	578
	579		//#define SQ_DYN_GPR_CTL_PS_FLUSH_REQ 0x8d8c
	580
	581		//#define SQ_LDS_RES_MGMT 0x8e2c
	582
	583		//#define SX_EXPORT_BUF_SZS 0x900c
	584		//#define COLOR_BUF_SZ_MASK 0xffffffff
	585		//#define COLOR_BUF_SZ_SHIFT 0
	586		//#define POS_BUF_SZ_MASK 0xffffffff
	587		//#define POS_BUF_SZ_SHIFT 8
	588		//#define SMX_BUF_SZ_MASK 0xffffffff
	589		//#define SMX_BUF_SZ_SHIFT 16
	590
	591		#define SX_DEBUG_1 0x9060
	592		//#define ENA_NEW_SMX_ADDR BIT(16)
	593
	594		#define SPI_STATIC_THD_MGMT_0 0x90e0
	595		#define SPI_STATIC_THD_MGMT_1 0x90e4
	596		#define SPI_STATIC_THD_MGMT_2 0x90e8
	597		#define SPI_PS_MAX_WAVE_ID 0x90ec
	598
	599		#define SPI_CFG_CTL_0 0x9100
	600		//#define GPR_WR_PRIO_MASK 0xffffffff
	601		//#define GPR_WR_PRIO_SHIFT 0
	602
	603		#define SPI_CFG_CTL_1 0x913c
	604		#define VTX_DONE_DELAY_MASK 0xffffffff
	605		#define VTX_DONE_DELAY_SHIFT 0
	606		#define INTERP_ONE_PRIM_PER_ROW BIT(4)
	607
	608		#define CGTS_TCC_DIS 0x9148
	609		#define CGTS_USER_TCC_DIS 0x914c
	610		#define TCC_DIS_MASK 0xffff0000
	611		#define TCC_DIS_SHIFT 16
	612
	613		#define TA_CTL_AUX 0x9508
	614		//#define DIS_CUBE_WRAP BIT(0)
	615		//#define DIS_CUBE_ANISO BIT(1)
	616		//#define SYNC_GRADIENT BIT(24)
	617		//#define SYNC_WALKER BIT(25)
	618		//#define SYNC_ALIGNER BIT(26)
	619
	620		/* related to GC_USER_RB_BACKEND_DIS */
	621		#define CC_RB_BACKEND_DIS 0x98f4
	622		#define BACKEND_DIS_VALID BIT(0)
	623		#define TAHITI_RB_BITMAP_W_PER_SH 2
	624		#define BACKEND_DIS_MASK 0x00ff0000
	625		#define BACKEND_DIS_SHIFT 16
	626		#define GB_ADDR_CFG 0x98f8
	627		#define PIPES_N_MASK 0x00000007
	628		#define PIPES_N_SHIFT 0
	629		#define PIPE_INTERLEAVE_SZ_MASK 0x00000070
	630		#define PIPE_INTERLEAVE_SZ_SHIFT 4
	631		//#define BANK_INTERLEAVE_SZ_MASK 0xffffffff
	632		//#define BANK_INTERLEAVE_SHIFT 8
	633		#define SES_N_MASK 0x00003000
	634		#define SES_N_SHIFT 12
	635		#define SE_TILE_SZ_MASK 0x00070000
	636		#define SE_TILE_SZ_SHIFT 16
	637		#define GPUS_N_MASK 0x00700000
	638		#define GPUS_N_SHIFT 20
	639		#define MULTI_GPU_TILE_SZ_MASK 0x03000000
	640		#define MULTI_GPU_TILE_SZ_SHIFT 24
	641		#define ROW_SZ_MASK 0x30000000
	642		#define ROW_SZ_SHIFT 28
	643
	644		//TODO:confirm it's gone
	645		//#define GB_BACKEND_MAP 0x98fc
	646
	647		#define GB_TILE_MODE_00 0x9910
	648		#define GB_MICRO_TILE_MODE_MASK 0x00000003
	649		#define GB_MICRO_TILE_MODE_SHIFT 0
	650		#define ADDR_SURF_DISPLAY_MICRO_TILING 0
	651		#define ADDR_SURF_THIN_MICRO_TILING 1
	652		#define ADDR_SURF_DEPTH_MICRO_TILING 2
	653		#define GB_ARRAY_MODE_MASK 0x0000001c
	654		#define GB_ARRAY_MODE_SHIFT 2
	655		#define ARRAY_LINEAR_GENERAL 0
	656		#define ARRAY_LINEAR_ALIGNED 1
	657		#define ARRAY_1D_TILED_THIN1 2
	658		#define ARRAY_2D_TILED_THIN1 4
	659		#define GB_PIPE_CFG_MASK 0x000003c0
	660		#define GB_PIPE_CFG_SHIFT 6
	661		#define ADDR_SURF_P2 0
	662		#define ADDR_SURF_P4_8x16 4
	663		#define ADDR_SURF_P4_16x16 5
	664		#define ADDR_SURF_P4_16x32 6
	665		#define ADDR_SURF_P4_32x32 7
	666		#define ADDR_SURF_P8_16x16_8x16 8
	667		#define ADDR_SURF_P8_16x32_8x16 9
	668		#define ADDR_SURF_P8_32x32_8x16 10
	669		#define ADDR_SURF_P8_16x32_16x16 11
	670		#define ADDR_SURF_P8_32x32_16x16 12
	671		#define ADDR_SURF_P8_32x32_16x32 13
	672		#define ADDR_SURF_P8_32x64_32x32 14
	673		#define GB_TILE_SPLIT_MASK 0x00003800
	674		#define GB_TILE_SPLIT_SHIFT 11
	675		#define ADDR_SURF_TILE_SPLIT_64B 0
	676		#define ADDR_SURF_TILE_SPLIT_128B 1
	677		#define ADDR_SURF_TILE_SPLIT_256B 2
	678		#define ADDR_SURF_TILE_SPLIT_512B 3
	679		#define ADDR_SURF_TILE_SPLIT_1KB 4
	680		#define ADDR_SURF_TILE_SPLIT_2KB 5
	681		#define ADDR_SURF_TILE_SPLIT_4KB 6
	682		#define GB_BANK_W_MASK 0x0000c000
	683		#define GB_BANK_W_SHIFT 14
	684		#define ADDR_SURF_BANK_W_1 0
	685		#define ADDR_SURF_BANK_W_2 1
	686		#define ADDR_SURF_BANK_W_4 2
	687		#define ADDR_SURF_BANK_W_8 3
	688		#define GB_BANK_H_MASK 0x00030000
	689		#define GB_BANK_H_SHIFT 16
	690		#define ADDR_SURF_BANK_H_1 0
	691		#define ADDR_SURF_BANK_H_2 1
	692		#define ADDR_SURF_BANK_H_4 2
	693		#define ADDR_SURF_BANK_H_8 3
	694		#define GB_MACRO_TILE_ASPECT_MASK 0x000c0000
	695		#define GB_MACRO_TILE_ASPECT_SHIFT 18
	696		#define ADDR_SURF_MACRO_ASPECT_1 0
	697		#define ADDR_SURF_MACRO_ASPECT_2 1
	698		#define ADDR_SURF_MACRO_ASPECT_4 2
	699		#define ADDR_SURF_MACRO_ASPECT_8 3
	700		#define GB_BANKS_N_MASK 0x00300000
	701		#define GB_BANKS_N_SHIFT 20
	702		#define ADDR_SURF_02_BANK 0
	703		#define ADDR_SURF_04_BANK 1
	704		#define ADDR_SURF_08_BANK 2
	705		#define ADDR_SURF_16_BANK 3
	706		#define GB_TILE_MODE_01 0x9914
	707		#define GB_TILE_MODE_02 0x9918
	708		#define GB_TILE_MODE_03 0x991c
	709		#define GB_TILE_MODE_04 0x9920
	710		#define GB_TILE_MODE_05 0x9924
	711		#define GB_TILE_MODE_06 0x9928
	712		#define GB_TILE_MODE_07 0x992c
	713		#define GB_TILE_MODE_08 0x9930
	714		#define GB_TILE_MODE_09 0x9934
	715		#define GB_TILE_MODE_0A 0x9938
	716		#define GB_TILE_MODE_0B 0x993c
	717		#define GB_TILE_MODE_0C 0x9940
	718		#define GB_TILE_MODE_0D 0x9944
	719		#define GB_TILE_MODE_0E 0x9948
	720		#define GB_TILE_MODE_0F 0x994c
	721		#define GB_TILE_MODE_10 0x9950
	722		#define GB_TILE_MODE_11 0x9954
	723		#define GB_TILE_MODE_12 0x9958
	724		#define GB_TILE_MODE_13 0x995c
	725		#define GB_TILE_MODE_14 0x9960
	726		#define GB_TILE_MODE_15 0x9964
	727		#define GB_TILE_MODE_16 0x9968
	728		#define GB_TILE_MODE_17 0x996c
	729		#define GB_TILE_MODE_18 0x9970
	730		#define GB_TILE_MODE_19 0x9974
	731		#define GB_TILE_MODE_1A 0x9978
	732		#define GB_TILE_MODE_1B 0x997c
	733		#define GB_TILE_MODE_1C 0x9980
	734		#define GB_TILE_MODE_1D 0x9984
	735		#define GB_TILE_MODE_1E 0x9988
	736		#define GB_TILE_MODE_1F 0x998c
	737
	738		#define CB_PERF_CTR_0_SEL_0 0x9a20
	739		#define CB_PERF_CTR_0_SEL_1 0x9a24
	740		#define CB_PERF_CTR_1_SEL_0 0x9a28
	741		#define CB_PERF_CTR_1_SEL_1 0x9a2c
	742		#define CB_PERF_CTR_2_SEL_0 0x9a30
	743		#define CB_PERF_CTR_2_SEL_1 0x9a34
	744		#define CB_PERF_CTR_3_SEL_0 0x9a38
	745		#define CB_PERF_CTR_3_SEL_1 0x9a3c
	746
	747		/* related to CC_RB_BACKEND_DIS */
	748		#define GC_USER_RB_BACKEND_DIS 0x9b7c
	749
	750		//TODO:confirm it's fone
	751		//#define SMX_SAR_CTL_0 0xa008
	752		//#define SMX_DC_CTL_0 0xa020
	753		//#define USE_HASH_FUNC BIT(0)
	754		//#define SETS_N_MASK 0x000003fe
	755		//#define SETS_N_SHIFT 1
	756		//#define FLUSH_ALL_ON_EVT BIT(10)
	757		//#define STALL_ON_EVT BIT(11)
	758		//
	759		#define TCP_CHAN_STEER_LO 0xac0c
	760		#define TCP_CHAN_STEER_HI 0xac10
	761
	762		#define CP_RB_BASE 0xc100
	763		#define CP_RB_CTL 0xc104
	764		#define RB_BUF_LOG2_QWS_MASK 0xffffffff
	765		#define RB_BUF_LOG2_QWS_SHIFT 0
	766		#define RB_BLK_LOG2_QWS_MASK 0xffffffff
	767		#define RB_BLK_LOG2_QWS_SHIFT 8
	768		#define BUF_SWAP_MASK 0x00030000
	769		#define BUF_SWAP_SHIFT 16
	770		#define BUF_SWAP_32BITS 2
	771		#define RB_NO_UPDATE BIT(27)
	772		#define RB_RPTR_WR_ENA BIT(31)
	773
	774		//#define CP_RB_RPTR_WR 0xc108
	775		#define CP_RB_0_RPTR_ADDR 0xc10c
	776		//#define RB_RPTR_SWAP_MASK 0xffffffff
	777		//#define RB_RPTR_SWAP_SHIFT 0
	778		#define CP_RB_0_RPTR_ADDR_HI 0xc110
	779		#define CP_RB_0_WPTR 0xc114
	780
	781		//TODO:confirm it's gone
	782		//#define CP_INT_CTL 0xc124
	783		//#define CNTX_BUSY_INT_ENA BIT(19)
	784		//#define CNTX_EMPTY_INT_ENA BIT(20)
	785		//#define SCRATCH_INT_ENA BIT(25)
	786		//#define TIME_STAMP_INT_ENA BIT(26)
	787		//#define IB2_INT_ENA BIT(29)
	788		//#define IB1_INT_ENA BIT(30)
	789		//#define RB_INT_ENA BIT(31)
	790		//#define CP_INT_STATUS 0xc128
	791		//#define SCRATCH_INT_STAT BIT(25)
	792		//#define TIME_STAMP_INT_STAT BIT(26)
	793		//#define IB2_INT_STAT BIT(29)
	794		//#define IB1_INT_STAT BIT(30)
	795
	796		#define CP_PFP_UCODE_ADDR 0xc150
	797		#define CP_PFP_UCODE_DATA 0xc154
	798		//#define RB_INT_STAT BIT(31)
	799		#define CP_ME_RAM_RADDR 0xc158
	800		#define CP_ME_RAM_WADDR 0xc15C
	801		#define CP_ME_RAM_DATA 0xc160
	802
	803		#define CP_CE_UCODE_ADDR 0xc168
	804		#define CP_CE_UCODE_DATA 0xc16c
	805
	806		#define CP_RB_1_BASE 0xc180
	807		#define CP_RB_1_CTL 0xc184
	808		#define CP_RB_1_RPTR_ADDR 0xc188
	809		#define CP_RB_1_RPTR_ADDR_HI 0xc18c
	810		#define CP_RB_1_WPTR 0xc190
	811		#define CP_RB_2_BASE 0xc194
	812		#define CP_RB_2_CTL 0xc198
	813		#define CP_RB_2_RPTR_ADDR 0xc19c
	814		#define CP_RB_2_RPTR_ADDR_HI 0xc1a0
	815		#define CP_RB_2_WPTR 0xc1a4
	816		#define CP_INT_CTL_RING_0 0xc1a8
	817		#define CP_INT_CTL_RING_1 0xc1ac
	818		#define CP_INT_CTL_RING_2 0xc1b0
	819		#define CNTX_BUSY_INT_ENA BIT(19)
	820		#define CNTX_EMPTY_INT_ENA BIT(20)
	821		#define WAIT_MEM_SEM_INT_ENA BIT(21)
	822		#define TIME_STAMP_INT_ENA BIT(26)
	823		#define CP_RING_ID_2_INT_ENA BIT(29)
	824		#define CP_RING_ID_1_INT_ENA BIT(30)
	825		#define CP_RING_ID_0_INT_ENA BIT(31)
	826		#define CP_INT_STATUS_RING_0 0xc1b4
	827		#define CP_INT_STATUS_RING_1 0xc1b8
	828		#define CP_INT_STATUS_RING_2 0xc1bc
	829		#define WAIT_MEM_SEM_INT_STAT BIT(21)
	830		#define TIME_STAMP_INT_STAT BIT(26)
	831		#define CP_RING_ID_2_INT_STAT BIT(29)
	832		#define CP_RING_ID_1_INT_STAT BIT(30)
	833		#define CP_RING_ID_0_INT_STAT BIT(31)
	834
	835		#define CP_DEBUG 0xc1fc
	836
	837		#define RLC_CTL 0xc300
	838		#define RLC_ENA BIT(0)
	839		#define RLC_RL_BASE 0xc304
	840		#define RLC_RL_SZ 0xc308
	841		#define RLC_LB_CTL 0xc30c
	842		#define RLC_SAVE_AND_RESTORE_BASE 0xc310
	843		#define RLC_LB_CNTR_MAX 0xc314
	844		#define RLC_LB_CNTR_INT 0xc318
	845
	846		#define RLC_CLR_STATE_RESTORE_BASE 0xc320
	847
	848		#define RLC_UCODE_ADDR 0xc32c
	849		#define RLC_UCODE_DATA 0xc330
	850
	851		#define RLC_MC_CTL 0xc344
	852		#define RLC_UCODE_CTL 0xc348
	853
	854		/* start of context register area: 0x28000-0x29000 */
	855		/* from there we must use indirect MMIO because above reg MMIO size */
	856		#define DB_RENDER_CTL 0x28000
	857		#define DB_CNT_CTL 0x28004
	858		#define DB_DEPTH_VIEW 0x28008
	859		#define SLICE_MAX_MASK 0x00ffe000
	860		#define SLICE_MAX_SHIFT 13
	861		#define DB_RENDER_OVERRIDE_0 0x2800c
	862		#define DB_RENDER_OVERRIDE_1 0x28010
	863		#define DB_HTILE_DATA_BASE 0x28014
	864
	865		#define DB_STENCIL_CLR 0x28028
	866		#define DB_DEPTH_CLR 0x2802c
	867		#define PA_SC_SCR_SCISSOR_TL 0x28030
	868		#define PA_SC_SCR_SCISSOR_BR 0x28034
	869
	870		#define DB_Z_INFO 0x28040
	871		#define DB_Z_ARRAY_MODE_MASK 0xffffffff
	872		#define DB_Z_ARRAY_MODE_SHIFT 4
	873		#define DB_TILE_SPLIT_MASK 0x00000700
	874		#define DB_TILE_SPLIT_SHIFT 8
	875		#define DB_BANKS_N_MASK 0x00007000
	876		#define DB_BANKS_N_SHIFT 12
	877		#define DB_BANK_W_MASK 0x00070000
	878		#define DB_BANK_W_SHIFT 16
	879		#define DB_BANK_H_MASK 0x00700000
	880		#define DB_BANK_H_SHIFT 20
	881		#define DB_MACRO_TILE_ASPECT_MASK 0x07000000
	882		#define DB_MACRO_TILE_ASPECT_SHIFT 24
	883
	884		#define DB_STENCIL_INFO 0x28044
	885		#define DB_FMT BIT(0)
	886		/*
	887		* already defined above
	888		#define DB_TILE_SPLIT_MASK 0x00000700
	889		#define DB_TILE_SPLIT_SHIFT 8
	890		*/
	891
	892		#define SQ_ALU_CONST_BUF_SZ_PS_0 0x28140
	893		#define SQ_ALU_CONST_BUF_SZ_PS_1 0x28144
	894		#define SQ_ALU_CONST_BUF_SZ_PS_2 0x28148
	895		#define SQ_ALU_CONST_BUF_SZ_PS_3 0x2814c
	896		#define SQ_ALU_CONST_BUF_SZ_PS_4 0x28150
	897		#define SQ_ALU_CONST_BUF_SZ_PS_5 0x28154
	898		#define SQ_ALU_CONST_BUF_SZ_PS_6 0x28158
	899		#define SQ_ALU_CONST_BUF_SZ_PS_7 0x2815c
	900		#define SQ_ALU_CONST_BUF_SZ_PS_8 0x28160
	901		#define SQ_ALU_CONST_BUF_SZ_PS_9 0x28164
	902		#define SQ_ALU_CONST_BUF_SZ_PS_A 0x28168
	903		#define SQ_ALU_CONST_BUF_SZ_PS_B 0x2816c
	904		#define SQ_ALU_CONST_BUF_SZ_PS_C 0x28170
	905		#define SQ_ALU_CONST_BUF_SZ_PS_D 0x28174
	906		#define SQ_ALU_CONST_BUF_SZ_PS_E 0x28178
	907		#define SQ_ALU_CONST_BUF_SZ_PS_F 0x2817c
	908		#define SQ_ALU_CONST_BUF_SZ_VS_0 0x28180
	909		#define SQ_ALU_CONST_BUF_SZ_VS_1 0x28184
	910		#define SQ_ALU_CONST_BUF_SZ_VS_2 0x28188
	911		#define SQ_ALU_CONST_BUF_SZ_VS_3 0x2818c
	912		#define SQ_ALU_CONST_BUF_SZ_VS_4 0x28190
	913		#define SQ_ALU_CONST_BUF_SZ_VS_5 0x28194
	914		#define SQ_ALU_CONST_BUF_SZ_VS_6 0x28198
	915		#define SQ_ALU_CONST_BUF_SZ_VS_7 0x2819c
	916		#define SQ_ALU_CONST_BUF_SZ_VS_8 0x281a0
	917		#define SQ_ALU_CONST_BUF_SZ_VS_9 0x281a4
	918		#define SQ_ALU_CONST_BUF_SZ_VS_A 0x281a8
	919		#define SQ_ALU_CONST_BUF_SZ_VS_B 0x281ac
	920		#define SQ_ALU_CONST_BUF_SZ_VS_C 0x281b0
	921		#define SQ_ALU_CONST_BUF_SZ_VS_D 0x281b4
	922		#define SQ_ALU_CONST_BUF_SZ_VS_E 0x281b8
	923		#define SQ_ALU_CONST_BUF_SZ_VS_F 0x281bc
	924		#define SQ_ALU_CONST_BUF_SZ_GS_0 0x281c0
	925		#define SQ_ALU_CONST_BUF_SZ_GS_1 0x281c4
	926		#define SQ_ALU_CONST_BUF_SZ_GS_2 0x281c8
	927		#define SQ_ALU_CONST_BUF_SZ_GS_3 0x281cc
	928		#define SQ_ALU_CONST_BUF_SZ_GS_4 0x281d0
	929		#define SQ_ALU_CONST_BUF_SZ_GS_5 0x281d4
	930		#define SQ_ALU_CONST_BUF_SZ_GS_6 0x281d8
	931		#define SQ_ALU_CONST_BUF_SZ_GS_7 0x281dc
	932		#define SQ_ALU_CONST_BUF_SZ_GS_8 0x281e0
	933		#define SQ_ALU_CONST_BUF_SZ_GS_9 0x281e4
	934		#define SQ_ALU_CONST_BUF_SZ_GS_A 0x281e8
	935		#define SQ_ALU_CONST_BUF_SZ_GS_B 0x281ec
	936		#define SQ_ALU_CONST_BUF_SZ_GS_C 0x281f0
	937		#define SQ_ALU_CONST_BUF_SZ_GS_D 0x281f4
	938		#define SQ_ALU_CONST_BUF_SZ_GS_E 0x281f8
	939		#define SQ_ALU_CONST_BUF_SZ_GS_F 0x281fc
	940		#define PA_SC_WND_OF 0x28200
	941		#define PA_SC_WND_SCISSOR_TL 0x28204
	942		#define PA_SC_WND_SCISSOR_BR 0x28208
	943		#define PA_SC_CLIPRECT_RULE 0x2820c
	944		#define PA_SC_CLIPRECT_0_TL 0x28210
	945		#define PA_SC_CLIPRECT_0_BR 0x28214
	946		#define PA_SC_CLIPRECT_1_TL 0x28218
	947		#define PA_SC_CLIPRECT_1_BR 0x2821c
	948		#define PA_SC_CLIPRECT_2_TL 0x28220
	949		#define PA_SC_CLIPRECT_2_BR 0x28224
	950		#define PA_SC_CLIPRECT_3_TL 0x28228
	951		#define PA_SC_CLIPRECT_3_BR 0x2822c
	952		#define PA_SC_EDGERULE 0x28230
	953		#define PA_SU_HW_SCR_OF 0x28234
	954		#define CB_TGT_MASK 0x28238
	955		#define CB_SHADER_MASK 0x2823c
	956		#define PA_SC_GENERIC_SCISSOR_TL 0x28240
	957		#define PA_SC_GENERIC_SCISSOR_BR 0x28244
	958
	959		#define PA_SC_VPORT_SCISSOR_0_TL 0x28250
	960		#define PA_SC_VPORT_SCISSOR_0_BR 0x28254
	961		#define PA_SC_VPORT_SCISSOR_1_TL 0x28258
	962		#define PA_SC_VPORT_SCISSOR_1_BR 0x2825c
	963		#define PA_SC_VPORT_SCISSOR_2_TL 0x28260
	964		#define PA_SC_VPORT_SCISSOR_2_BR 0x28264
	965		#define PA_SC_VPORT_SCISSOR_3_TL 0x28268
	966		#define PA_SC_VPORT_SCISSOR_3_BR 0x2826c
	967		#define PA_SC_VPORT_SCISSOR_4_TL 0x28270
	968		#define PA_SC_VPORT_SCISSOR_4_BR 0x28274
	969		#define PA_SC_VPORT_SCISSOR_5_TL 0x28278
	970		#define PA_SC_VPORT_SCISSOR_5_BR 0x2827c
	971		#define PA_SC_VPORT_SCISSOR_6_TL 0x28280
	972		#define PA_SC_VPORT_SCISSOR_6_BR 0x28284
	973		#define PA_SC_VPORT_SCISSOR_7_TL 0x28288
	974		#define PA_SC_VPORT_SCISSOR_7_BR 0x2828c
	975		#define PA_SC_VPORT_SCISSOR_8_TL 0x28290
	976		#define PA_SC_VPORT_SCISSOR_8_BR 0x28294
	977		#define PA_SC_VPORT_SCISSOR_9_TL 0x28298
	978		#define PA_SC_VPORT_SCISSOR_9_BR 0x2829c
	979		#define PA_SC_VPORT_SCISSOR_A_TL 0x282a0
	980		#define PA_SC_VPORT_SCISSOR_A_BR 0x282a4
	981		#define PA_SC_VPORT_SCISSOR_B_TL 0x282a8
	982		#define PA_SC_VPORT_SCISSOR_B_BR 0x282ac
	983		#define PA_SC_VPORT_SCISSOR_C_TL 0x282b0
	984		#define PA_SC_VPORT_SCISSOR_C_BR 0x282b4
	985		#define PA_SC_VPORT_SCISSOR_D_TL 0x282b8
	986		#define PA_SC_VPORT_SCISSOR_D_BR 0x282bc
	987		#define PA_SC_VPORT_SCISSOR_E_TL 0x282c0
	988		#define PA_SC_VPORT_SCISSOR_E_BR 0x282c4
	989		#define PA_SC_VPORT_SCISSOR_F_TL 0x282c8
	990		#define PA_SC_VPORT_SCISSOR_F_BR 0x282cc
	991		#define PA_SC_VPORT_ZMIN_0 0x282d0
	992		#define PA_SC_VPORT_ZMAX_0 0x282d4
	993		#define PA_SC_VPORT_ZMIN_1 0x282d8
	994		#define PA_SC_VPORT_ZMAX_1 0x282dc
	995		#define PA_SC_VPORT_ZMIN_2 0x282e0
	996		#define PA_SC_VPORT_ZMAX_2 0x282e4
	997		#define PA_SC_VPORT_ZMIN_3 0x282e8
	998		#define PA_SC_VPORT_ZMAX_3 0x282ec
	999		#define PA_SC_VPORT_ZMIN_4 0x282f0
	1000		#define PA_SC_VPORT_ZMAX_4 0x282f4
	1001		#define PA_SC_VPORT_ZMIN_5 0x282f8
	1002		#define PA_SC_VPORT_ZMAX_5 0x282fc
	1003		#define PA_SC_VPORT_ZMIN_6 0x28300
	1004		#define PA_SC_VPORT_ZMAX_6 0x28304
	1005		#define PA_SC_VPORT_ZMIN_7 0x28308
	1006		#define PA_SC_VPORT_ZMAX_7 0x2830c
	1007		#define PA_SC_VPORT_ZMIN_8 0x28310
	1008		#define PA_SC_VPORT_ZMAX_8 0x28314
	1009		#define PA_SC_VPORT_ZMIN_9 0x28318
	1010		#define PA_SC_VPORT_ZMAX_9 0x2831c
	1011		#define PA_SC_VPORT_ZMIN_A 0x28320
	1012		#define PA_SC_VPORT_ZMAX_A 0x28324
	1013		#define PA_SC_VPORT_ZMIN_B 0x28328
	1014		#define PA_SC_VPORT_ZMAX_B 0x2832c
	1015		#define PA_SC_VPORT_ZMIN_C 0x28330
	1016		#define PA_SC_VPORT_ZMAX_C 0x28334
	1017		#define PA_SC_VPORT_ZMIN_D 0x28338
	1018		#define PA_SC_VPORT_ZMAX_D 0x2833c
	1019		#define PA_SC_VPORT_ZMIN_E 0x28340
	1020		#define PA_SC_VPORT_ZMAX_E 0x28344
	1021		#define PA_SC_VPORT_ZMIN_F 0x28348
	1022		#define PA_SC_VPORT_ZMAX_F 0x2834c
	1023		//TODO:confirm it's gone
	1024		//#define SX_MISC 0x28350
	1025		#define PA_SC_RASTER_CFG 0x28350
	1026		#define RASTER_CFG_RB_MAP_0 0
	1027		#define RASTER_CFG_RB_MAP_1 1
	1028		#define RASTER_CFG_RB_MAP_2 2
	1029		#define RASTER_CFG_RB_MAP_3 3
	1030		#define SX_SURF_SYNC 0x28354
	1031
	1032		#define SQ_VTX_SEMANTIC_00 0x28380
	1033		#define SQ_VTX_SEMANTIC_01 0x28384
	1034		#define SQ_VTX_SEMANTIC_02 0x28388
	1035		#define SQ_VTX_SEMANTIC_03 0x2838c
	1036		#define SQ_VTX_SEMANTIC_04 0x28390
	1037		#define SQ_VTX_SEMANTIC_05 0x28394
	1038		#define SQ_VTX_SEMANTIC_06 0x28398
	1039		#define SQ_VTX_SEMANTIC_07 0x2839c
	1040		#define SQ_VTX_SEMANTIC_08 0x283a0
	1041		#define SQ_VTX_SEMANTIC_09 0x283a4
	1042		#define SQ_VTX_SEMANTIC_0A 0x283a8
	1043		#define SQ_VTX_SEMANTIC_0B 0x283ac
	1044		#define SQ_VTX_SEMANTIC_0C 0x283b0
	1045		#define SQ_VTX_SEMANTIC_0D 0x283b4
	1046		#define SQ_VTX_SEMANTIC_0E 0x283b8
	1047		#define SQ_VTX_SEMANTIC_0F 0x283bc
	1048		#define SQ_VTX_SEMANTIC_10 0x283c0
	1049		#define SQ_VTX_SEMANTIC_11 0x283c4
	1050		#define SQ_VTX_SEMANTIC_12 0x283c8
	1051		#define SQ_VTX_SEMANTIC_13 0x283cc
	1052		#define SQ_VTX_SEMANTIC_14 0x283d0
	1053		#define SQ_VTX_SEMANTIC_15 0x283d4
	1054		#define SQ_VTX_SEMANTIC_16 0x283d8
	1055		#define SQ_VTX_SEMANTIC_17 0x283dc
	1056		#define SQ_VTX_SEMANTIC_18 0x283e0
	1057		#define SQ_VTX_SEMANTIC_19 0x283e4
	1058		#define SQ_VTX_SEMANTIC_1A 0x283e8
	1059		#define SQ_VTX_SEMANTIC_1B 0x283ec
	1060		#define SQ_VTX_SEMANTIC_1C 0x283f0
	1061		#define SQ_VTX_SEMANTIC_1D 0x283f4
	1062		#define SQ_VTX_SEMANTIC_1E 0x283f8
	1063		#define SQ_VTX_SEMANTIC_1F 0x283fc
	1064		#define VGT_MAX_VTX_IDX 0x28400
	1065		#define VGT_MIN_VTX_IDX 0x28404
	1066		#define VGT_IDX_OF 0x28408
	1067		#define VGT_MULTI_PRIM_IB_RESET_IDX 0x2840c
	1068		#define SX_ALPHA_TEST_CTL 0x28410
	1069		#define CB_BLEND_RED 0x28414
	1070		#define CB_BLEND_GREEN 0x28418
	1071		#define CB_BLEND_BLUE 0x2841c
	1072		#define CB_BLEND_ALPHA 0x28420
	1073
	1074		#define DB_STENCILREFMASK 0x28430
	1075		#define DB_STENCILREFMASK_BF 0x28434
	1076		#define SX_ALPHA_REF 0x28438
	1077		#define PA_CL_VPORT_X_SCALE_0 0x2843c
	1078		#define PA_CL_VPORT_X_OF_0 0x28440
	1079		#define PA_CL_VPORT_Y_SCALE_0 0x28444
	1080		#define PA_CL_VPORT_Y_OF_0 0x28448
	1081		#define PA_CL_VPORT_ZSCALE_0 0x2844c
	1082		#define PA_CL_VPORT_Z_OF_0 0x28450
	1083		#define PA_CL_VPORT_X_SCALE_1 0x28454
	1084		#define PA_CL_VPORT_X_OF_1 0x28458
	1085		#define PA_CL_VPORT_Y_SCALE_1 0x2845c
	1086		#define PA_CL_VPORT_Y_OF_1 0x28460
	1087		#define PA_CL_VPORT_Z_SCALE_1 0x28464
	1088		#define PA_CL_VPORT_Z_OF_1 0x28468
	1089		#define PA_CL_VPORT_X_SCALE_2 0x2846c
	1090		#define PA_CL_VPORT_X_OF_2 0x28470
	1091		#define PA_CL_VPORT_Y_SCALE_2 0x28474
	1092		#define PA_CL_VPORT_Y_OF_2 0x28478
	1093		#define PA_CL_VPORT_Z_SCALE_2 0x2847c
	1094		#define PA_CL_VPORT_Z_OF_2 0x28480
	1095		#define PA_CL_VPORT_X_SCALE_3 0x28484
	1096		#define PA_CL_VPORT_X_OF_3 0x28488
	1097		#define PA_CL_VPORT_Y_SCALE_3 0x2848c
	1098		#define PA_CL_VPORT_Y_OF_3 0x28490
	1099		#define PA_CL_VPORT_Z_SCALE_3 0x28494
	1100		#define PA_CL_VPORT_Z_OF_3 0x28498
	1101		#define PA_CL_VPORT_X_SCALE_4 0x2849c
	1102		#define PA_CL_VPORT_X_OF_4 0x284a0
	1103		#define PA_CL_VPORT_Y_SCALE_4 0x284a4
	1104		#define PA_CL_VPORT_Y_OF_4 0x284a8
	1105		#define PA_CL_VPORT_Z_SCALE_4 0x284ac
	1106		#define PA_CL_VPORT_Z_OF_4 0x284b0
	1107		#define PA_CL_VPORT_X_SCALE_5 0x284b4
	1108		#define PA_CL_VPORT_X_OF_5 0x284b8
	1109		#define PA_CL_VPORT_Y_SCALE_5 0x284bc
	1110		#define PA_CL_VPORT_Y_OF_5 0x284c0
	1111		#define PA_CL_VPORT_Z_SCALE_5 0x284c4
	1112		#define PA_CL_VPORT_Z_OF_5 0x284c8
	1113		#define PA_CL_VPORT_X_SCALE_6 0x284cc
	1114		#define PA_CL_VPORT_X_OF_6 0x284d0
	1115		#define PA_CL_VPORT_Y_SCALE_6 0x284d4
	1116		#define PA_CL_VPORT_Y_OF_6 0x284d8
	1117		#define PA_CL_VPORT_Z_SCALE_6 0x284dc
	1118		#define PA_CL_VPORT_Z_OF_6 0x284e0
	1119		#define PA_CL_VPORT_X_SCALE_7 0x284e4
	1120		#define PA_CL_VPORT_X_OF_7 0x284e8
	1121		#define PA_CL_VPORT_Y_SCALE_7 0x284ec
	1122		#define PA_CL_VPORT_Y_OF_7 0x284f0
	1123		#define PA_CL_VPORT_Z_SCALE_7 0x284f4
	1124		#define PA_CL_VPORT_Z_OF_7 0x284f8
	1125		#define PA_CL_VPORT_X_SCALE_8 0x284fc
	1126		#define PA_CL_VPORT_X_OF_8 0x28500
	1127		#define PA_CL_VPORT_Y_SCALE_8 0x28504
	1128		#define PA_CL_VPORT_Y_OF_8 0x28508
	1129		#define PA_CL_VPORT_Z_SCALE_8 0x2850c
	1130		#define PA_CL_VPORT_Z_OF_8 0x28510
	1131		#define PA_CL_VPORT_X_SCALE_9 0x28514
	1132		#define PA_CL_VPORT_X_OF_9 0x28518
	1133		#define PA_CL_VPORT_Y_SCALE_9 0x2851c
	1134		#define PA_CL_VPORT_Y_OF_9 0x28520
	1135		#define PA_CL_VPORT_Z_SCALE_9 0x28524
	1136		#define PA_CL_VPORT_Z_OF_9 0x28528
	1137		#define PA_CL_VPORT_X_SCALE_A 0x2852c
	1138		#define PA_CL_VPORT_X_OF_A 0x28530
	1139		#define PA_CL_VPORT_Y_SCALE_A 0x28534
	1140		#define PA_CL_VPORT_Y_OF_A 0x28538
	1141		#define PA_CL_VPORT_Z_SCALE_A 0x2853c
	1142		#define PA_CL_VPORT_Z_OF_A 0x28540
	1143		#define PA_CL_VPORT_X_SCALE_B 0x28544
	1144		#define PA_CL_VPORT_X_OF_B 0x28548
	1145		#define PA_CL_VPORT_Y_SCALE_B 0x2854c
	1146		#define PA_CL_VPORT_Y_OF_B 0x28550
	1147		#define PA_CL_VPORT_Z_SCALE_B 0x28554
	1148		#define PA_CL_VPORT_Z_OF_B 0x28558
	1149		#define PA_CL_VPORT_X_SCALE_C 0x2855c
	1150		#define PA_CL_VPORT_X_OF_C 0x28560
	1151		#define PA_CL_VPORT_Y_SCALE_C 0x28564
	1152		#define PA_CL_VPORT_Y_OF_C 0x28568
	1153		#define PA_CL_VPORT_Z_SCALE_C 0x2856c
	1154		#define PA_CL_VPORT_Z_OF_C 0x28570
	1155		#define PA_CL_VPORT_X_SCALE_D 0x28574
	1156		#define PA_CL_VPORT_X_OF_D 0x28578
	1157		#define PA_CL_VPORT_Y_SCALE_D 0x2857c
	1158		#define PA_CL_VPORT_Y_OF_D 0x28580
	1159		#define PA_CL_VPORT_Z_SCALE_D 0x28584
	1160		#define PA_CL_VPORT_Z_OF_D 0x28588
	1161		#define PA_CL_VPORT_X_SCALE_E 0x2858c
	1162		#define PA_CL_VPORT_X_OF_E 0x28590
	1163		#define PA_CL_VPORT_Y_SCALE_E 0x28594
	1164		#define PA_CL_VPORT_Y_OF_E 0x28598
	1165		#define PA_CL_VPORT_Z_SCALE_E 0x2859c
	1166		#define PA_CL_VPORT_Z_OF_E 0x285a0
	1167		#define PA_CL_VPORT_X_SCALE_F 0x285a4
	1168		#define PA_CL_VPORT_X_OF_F 0x285a8
	1169		#define PA_CL_VPORT_Y_SCALE_F 0x285ac
	1170		#define PA_CL_VPORT_Y_OF_F 0x285b0
	1171		#define PA_CL_VPORT_Z_SCALE_F 0x285b4
	1172		#define PA_CL_VPORT_Z_OF_F 0x285b8
	1173		#define PA_CL_UCP_0_X 0x285bc
	1174		#define PA_CL_UCP_0_Y 0x285c0
	1175		#define PA_CL_UCP_0_Z 0x285c4
	1176		#define PA_CL_UCP_0_W 0x285c8
	1177		#define PA_CL_UCP_1_X 0x285cc
	1178		#define PA_CL_UCP_1_Y 0x285d0
	1179		#define PA_CL_UCP_1_Z 0x285d4
	1180		#define PA_CL_UCP_1_W 0x285d8
	1181		#define PA_CL_UCP_2_X 0x285dc
	1182		#define PA_CL_UCP_2_Y 0x285e0
	1183		#define PA_CL_UCP_2_Z 0x285e4
	1184		#define PA_CL_UCP_2_W 0x285e8
	1185		#define PA_CL_UCP_3_X 0x285ec
	1186		#define PA_CL_UCP_3_Y 0x285f0
	1187		#define PA_CL_UCP_3_Z 0x285f4
	1188		#define PA_CL_UCP_3_W 0x285f8
	1189		#define PA_CL_UCP_4_X 0x285fc
	1190		#define PA_CL_UCP_4_Y 0x28600
	1191		#define PA_CL_UCP_4_Z 0x28604
	1192		#define PA_CL_UCP_4_W 0x28608
	1193		#define PA_CL_UCP_5_X 0x2860c
	1194		#define PA_CL_UCP_5_Y 0x28610
	1195		#define PA_CL_UCP_5_Z 0x28614
	1196		#define PA_CL_UCP_5_W 0x28618
	1197		#define SPI_VS_OUT_ID_0 0x2861c
	1198		#define SPI_VS_OUT_ID_1 0x28620
	1199		#define SPI_VS_OUT_ID_2 0x28624
	1200		#define SPI_VS_OUT_ID_3 0x28628
	1201		#define SPI_VS_OUT_ID_4 0x2862c
	1202		#define SPI_VS_OUT_ID_5 0x28630
	1203		#define SPI_VS_OUT_ID_6 0x28634
	1204		#define SPI_VS_OUT_ID_7 0x28638
	1205		#define SPI_VS_OUT_ID_8 0x2863c
	1206		#define SPI_VS_OUT_ID_9 0x28640
	1207		#define SPI_PS_INPUT_CTL_00 0x28644
	1208		#define SPI_PS_INPUT_CTL_01 0x28648
	1209		#define SPI_PS_INPUT_CTL_02 0x2864c
	1210		#define SPI_PS_INPUT_CTL_03 0x28650
	1211		#define SPI_PS_INPUT_CTL_04 0x28654
	1212		#define SPI_PS_INPUT_CTL_05 0x28658
	1213		#define SPI_PS_INPUT_CTL_06 0x2865c
	1214		#define SPI_PS_INPUT_CTL_07 0x28660
	1215		#define SPI_PS_INPUT_CTL_08 0x28664
	1216		#define SPI_PS_INPUT_CTL_09 0x28668
	1217		#define SPI_PS_INPUT_CTL_0A 0x2866c
	1218		#define SPI_PS_INPUT_CTL_0B 0x28670
	1219		#define SPI_PS_INPUT_CTL_0C 0x28674
	1220		#define SPI_PS_INPUT_CTL_0D 0x28678
	1221		#define SPI_PS_INPUT_CTL_0E 0x2867c
	1222		#define SPI_PS_INPUT_CTL_0F 0x28680
	1223		#define SPI_PS_INPUT_CTL_10 0x28684
	1224		#define SPI_PS_INPUT_CTL_11 0x28688
	1225		#define SPI_PS_INPUT_CTL_12 0x2868c
	1226		#define SPI_PS_INPUT_CTL_13 0x28690
	1227		#define SPI_PS_INPUT_CTL_14 0x28694
	1228		#define SPI_PS_INPUT_CTL_15 0x28698
	1229		#define SPI_PS_INPUT_CTL_16 0x2869c
	1230		#define SPI_PS_INPUT_CTL_17 0x286a0
	1231		#define SPI_PS_INPUT_CTL_18 0x286a4
	1232		#define SPI_PS_INPUT_CTL_19 0x286a8
	1233		#define SPI_PS_INPUT_CTL_1A 0x286ac
	1234		#define SPI_PS_INPUT_CTL_1B 0x286b0
	1235		#define SPI_PS_INPUT_CTL_1C 0x286b4
	1236		#define SPI_PS_INPUT_CTL_1D 0x286b8
	1237		#define SPI_PS_INPUT_CTL_1E 0x286bc
	1238		#define SPI_PS_INPUT_CTL_1F 0x286c0
	1239		#define SPI_VS_OUT_CFG 0x286c4
	1240		#define SPI_THD_GROUPING 0x286c8
	1241		#define SPI_PS_IN_CTL_0 0x286cc
	1242		#define INTERP_N_MASK 0xffffffff
	1243		#define INTERP_N_SHIFT 0
	1244		#define POS BIT(8)
	1245		#define POS_CENTROID BIT(9)
	1246		#define POS_ADDR_MASK 0xffffffff
	1247		#define POS_ADDR_SHIFT 10
	1248		#define PARAM_GEN_MASK 0xffffffff
	1249		#define PARAM_GEN_SHIFT 15
	1250		#define PARAM_GEN_ADDR_MASK 0xffffffff
	1251		#define PARAM_GEN_ADDR_SHIFT 19
	1252		#define BARYC_SAMPLE_CTL_MASK 0xffffffff
	1253		#define BARYC_SAMPLE_CTL_SHIFT 26
	1254		#define PERSP_GRADIENT_ENA BIT(28)
	1255		#define LINEAR_GRADIENT_ENA BIT(29)
	1256		#define POS_SAMPLE BIT(30)
	1257		#define BARYC_AT_SAMPLE_ENA BIT(31)
	1258		#define SPI_PS_IN_CTL_1 0x286d0
	1259		#define SPI_INTERP_CTL_0 0x286d4
	1260		#define SPI_INPUT_Z 0x286d8
	1261		#define SPI_FOG_CTL 0x286dc
	1262		#define SPI_BARYC_CTL 0x286e0
	1263		#define SPI_PS_IN_CTL_2 0x286e4
	1264		#define SPI_COMPUTE_INPUT_CT 0x286e8
	1265		#define SPI_COMPUTE_THDS_N_X 0x286ec
	1266		#define SPI_COMPUTE_THDS_N_Y 0x286f0
	1267		#define SPI_COMPUTE_THDS_N_Z 0x286f4
	1268
	1269		#define GDS_ADDR_BASE 0x28720
	1270		#define GDS_ADDR_SZ 0x28724
	1271		#define GDS_ORDERED_WAVE_PER_SE 0x28728
	1272
	1273		#define CB_BLEND_0_CTL 0x28780
	1274		#define CB_BLEND_1_CTL 0x28784
	1275		#define CB_BLEND_2_CTL 0x28788
	1276		#define CB_BLEND_3_CTL 0x2878c
	1277		#define CB_BLEND_4_CTL 0x28790
	1278		#define CB_BLEND_5_CTL 0x28794
	1279		#define CB_BLEND_6_CTL 0x28798
	1280		#define CB_BLEND_7_CTL 0x2879c
	1281
	1282		#define CS_COPY_STATE 0x287cc
	1283
	1284		#define GFX_COPY_STATE 0x287d0
	1285		#define PA_CL_POINT_X_RAD 0x287d4
	1286		#define PA_CL_POINT_Y_RAD 0x287d8
	1287		#define PA_CL_POINT_SZ 0x287dc
	1288		#define PA_CL_POINT_CULL_RAD 0x287e0
	1289
	1290		#define DB_DEPTH_CTL 0x28800
	1291		#define STENCIL_ENA BIT(0)
	1292		#define Z_ENA BIT(1)
	1293		#define Z_WRITE_ENA BIT(2)
	1294		#define ZFUNC_MASK 0x00000070
	1295		#define ZFUNC_SHIFT 4
	1296		#define BACKFACE_ENA BIT(7)
	1297		#define STENCILFUNC_MASK 0x00000700
	1298		#define STENCILFUNC_SHIFT 8
	1299		#define STENCILFUNC_NEVER 0
	1300		#define STENCILFUNC_LESS 1
	1301		#define STENCILFUNC_EQUAL 2
	1302		#define STENCILFUNC_LEQUAL 3
	1303		#define STENCILFUNC_GREATER 4
	1304		#define STENCILFUNC_NOTEQUAL 5
	1305		#define STENCILFUNC_GEQUAL 6
	1306		#define STENCILFUNC_ALWAYS 7
	1307		#define STENCILFAIL_MASK 0x00003800
	1308		#define STENCILFAIL_SHIFT 11
	1309		#define STENCILFAIL_KEEP 0
	1310		#define STENCILFAIL_ZERO 1
	1311		#define STENCILFAIL_REPLACE 2
	1312		#define STENCILFAIL_INCR 3
	1313		#define STENCILFAIL_DECR 4
	1314		#define STENCILFAIL_INVERT 5
	1315		#define STENCILFAIL_INCR_WRAP 6
	1316		#define STENCILFAIL_DECR_WRAP 7
	1317		#define STENCILZPASS_MASK 0x001c0000
	1318		#define STENCILZPASS_SHIFT 14
	1319		#define STENCILZFAIL_MASK 0x000e0000
	1320		#define STENCILZFAIL_SHIFT 17
	1321		#define STENCILFUNC_BF_MASK 0x00700000
	1322		#define STENCILFUNC_BF_SHIFT 20
	1323		#define STENCILFAIL_BF_MASK 0x03800000
	1324		#define STENCILFAIL_BF_SHIFT 23
	1325		#define STENCILZPASS_BF_MASK 0x1c000000
	1326		#define STENCILZPASS_BF_SHIFT 26
	1327		#define STENCILZFAIL_BF_MASK 0xe0000000
	1328		#define STENCILZFAIL_BF_SHIFT 29
	1329
	1330		#define CB_COLOR_CTL 0x28808
	1331		#define DB_SHADER_CTL 0x2880c
	1332		#define PA_CL_CLIP_CTL 0x28810
	1333		#define PA_SU_SC_MODE_CTL 0x28814
	1334		#define PA_CL_VTE_CTL 0x28818
	1335		#define PA_CL_VS_OUT_CTL 0x2881c
	1336		#define PA_CL_NANINF_CTL 0x28820
	1337		#define PA_SU_LINE_STIPPLE_CTL 0x28824
	1338		#define PA_SU_LINE_STIPPLE_SCALE 0x28828
	1339		#define PA_SU_PRIM_FILTER_CTL 0x2882c
	1340		#define SQ_LSTMP_RING_ITEM_SZ 0x28830
	1341		#define SQ_HSTMP_RING_ITEM_SZ 0x28834
	1342		#define SQ_DYN_GPR_RES_LIMIT_1 0x28838
	1343
	1344		#define SQ_PGM_START_PS 0x28840
	1345		#define SQ_PGM_RES_PS 0x28844
	1346		#define SQ_PGM_RES_2_PS 0x28848
	1347		#define SQ_PGM_EXPORTS_PS 0x2884c
	1348
	1349		#define SQ_PGM_START_VS 0x2885c
	1350		#define SQ_PGM_RES_VS 0x28860
	1351		#define SQ_PGM_RES_2_VS 0x28864
	1352
	1353		#define SQ_PGM_START_GS 0x28874
	1354		#define SQ_PGM_RES_GS 0x28878
	1355		#define SQ_PGM_RES_2_GS 0x2887c
	1356
	1357		#define SQ_PGM_START_ES 0x2888c
	1358		#define SQ_PGM_RES_ES 0x28890
	1359		#define SQ_PGM_RES_2_ES 0x28894
	1360
	1361		#define SQ_PGM_START_FS 0x288a4
	1362		#define SQ_PGM_START_FS 0x288a4
	1363		#define SQ_PGM_RES_FS 0x288a8
	1364
	1365		#define SQ_PGM_START_HS 0x288b8
	1366		#define SQ_PGM_RES_HS 0x288bc
	1367		#define SQ_PGM_RES_2_HS 0x288c0
	1368
	1369		#define SQ_PGM_START_LS 0x288d0
	1370		#define SQ_PGM_RES_LS 0x288d4
	1371		#define SQ_PGM_RES_2_LS 0x288d8
	1372
	1373		#define SQ_LDS_ALLOC 0x288e8
	1374		#define SQ_LDS_ALLOC_PS 0x288ec
	1375		#define SQ_VTX_SEMANTIC_CLR 0x288f0
	1376
	1377		#define SQ_ESGS_RING_ITEM_SZ 0x28900
	1378		#define SQ_GSVS_RING_ITEM_SZ 0x28904
	1379		#define SQ_ESTMP_RING_ITEM_SZ 0x28908
	1380		#define SQ_GSTMP_RING_ITEM_SZ 0x2890c
	1381		#define SQ_VSTMP_RING_ITEM_SZ 0x28910
	1382		#define SQ_PSTMP_RING_ITEM_SZ 0x28914
	1383
	1384		#define SQ_GS_VERT_ITEM_SZ_0 0x2891c
	1385		#define SQ_GS_VERT_ITEM_SZ_1 0x28920
	1386		#define SQ_GS_VERT_ITEM_SZ_2 0x28924
	1387		#define SQ_GS_VERT_ITEM_SZ_3 0x28928
	1388
	1389		#define PA_SU_POINT_SZ 0x28a00
	1390		#define PA_SU_POINT_MINMAX 0x28a04
	1391		#define PA_SU_LINE_CTL 0x28a08
	1392		#define PA_SC_LINE_STIPPLE 0x28a0c
	1393		#define VGT_OUTPUT_PATH_CTL 0x28a10
	1394		#define VGT_HOS_CTL 0x28a14
	1395		#define VGT_HOS_MAX_TESS_LVL 0x28a18
	1396		#define VGT_HOS_MIN_TESS_LVL 0x28a1c
	1397		#define VGT_HOS_REUSE_DEPTH 0x28a20
	1398		#define VGT_GROUP_PRIM_TYPE 0x28a24
	1399		#define VGT_GROUP_FIRST_DECR 0x28a28
	1400		#define VGT_GROUP_DECR 0x28a2c
	1401		#define VGT_GROUP_VECT_0_CTL 0x28a30
	1402		#define VGT_GROUP_VECT_1_CTL 0x28a34
	1403		#define VGT_GROUP_VECT_0_FMT_CTL 0x28a38
	1404		#define VGT_GROUP_VECT_1_FMT_CTL 0x28a3c
	1405		#define VGT_GS_MODE 0x28a40
	1406
	1407		#define PA_SC_MODE_CTL_0 0x28a48
	1408		#define PA_SC_MODE_CTL_1 0x28a4c
	1409		#define VGT_ENHANCE 0x28a50
	1410		#define VGT_GS_PER_ES 0x28a54
	1411		#define VGT_ES_PER_GS 0x28a58
	1412		#define VGT_GS_PER_VS 0x28a5c
	1413
	1414		#define VGT_GS_OUT_PRIM_TYPE 0x28a6c
	1415
	1416		#define VGT_PRIM_ID_ENA 0x28a84
	1417
	1418		/* ??? */
	1419		#define VGT_EVENT_INITIATOR 0x28a90
	1420		#define SAMPLE_STREAMOUTSTATS1 (1 << 0)
	1421		#define SAMPLE_STREAMOUTSTATS2 (2 << 0)
	1422		#define SAMPLE_STREAMOUTSTATS3 (3 << 0)
	1423		#define CACHE_FLUSH_TS (4 << 0)
	1424		#define CACHE_FLUSH (6 << 0)
	1425		#define CS_PARTIAL_FLUSH (7 << 0)
	1426		#define VGT_STREAMOUT_RESET (10 << 0)
	1427		#define END_OF_PIPE_INCR_DE (11 << 0)
	1428		#define END_OF_PIPE_IB_END (12 << 0)
	1429		#define RST_PIX_CNT (13 << 0)
	1430		#define VS_PARTIAL_FLUSH (15 << 0)
	1431		#define PS_PARTIAL_FLUSH (16 << 0)
	1432		#define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
	1433		#define ZPASS_DONE (21 << 0)
	1434		#define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
	1435		#define PERFCOUNTER_START (23 << 0)
	1436		#define PERFCOUNTER_STOP (24 << 0)
	1437		#define PIPELINESTAT_START (25 << 0)
	1438		#define PIPELINESTAT_STOP (26 << 0)
	1439		#define PERFCOUNTER_SAMPLE (27 << 0)
	1440		#define SAMPLE_PIPELINESTAT (30 << 0)
	1441		#define SAMPLE_STREAMOUTSTATS (32 << 0)
	1442		#define RESET_VTX_CNT (33 << 0)
	1443		#define VGT_FLUSH (36 << 0)
	1444		#define BOTTOM_OF_PIPE_TS (40 << 0)
	1445		#define DB_CACHE_FLUSH_AND_INV (42 << 0)
	1446		#define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
	1447		#define FLUSH_AND_INV_DB_META (44 << 0)
	1448		#define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
	1449		#define FLUSH_AND_INV_CB_META (46 << 0)
	1450		#define CS_DONE (47 << 0)
	1451		#define PS_DONE (48 << 0)
	1452		#define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
	1453		#define THREAD_TRACE_START (51 << 0)
	1454		#define THREAD_TRACE_STOP (52 << 0)
	1455		#define THREAD_TRACE_FLUSH (54 << 0)
	1456		#define THREAD_TRACE_FINISH (55 << 0)
	1457
	1458		//TODO:confirm it's gone
	1459		//#define VGT_MULTI_PRIM_IB_RESET_ENA 0x28a94
	1460
	1461		#define VGT_INST_STEP_RATE_0 0x28aa0
	1462		#define VGT_INST_STEP_RATE_1 0x28aa4
	1463
	1464		#define VGT_REUSE_OFF 0x28ab4
	1465		#define VGT_VTX_CNT_ENA 0x28ab8
	1466
	1467		#define DB_SRESULTS_CMP_STATE_0 0x28ac0
	1468		#define DB_SRESULTS_CMP_STATE_1 0x28ac4
	1469		#define DB_PRELOAD_CTL 0x28ac8
	1470
	1471		#define VGT_STRMOUT_VTX_STRIDE_0 0x28ad4
	1472
	1473		#define VGT_STRMOUT_VTX_STRIDE_1 0x28ae4
	1474
	1475		#define VGT_STRMOUT_VTX_STRIDE_2 0x28af4
	1476
	1477		#define VGT_STRMOUT_VTX_STRIDE_3 0x28b04
	1478
	1479		#define VGT_STRMOUT_DRAW_OPAQUE_OF 0x28b28
	1480		#define VGT_STRMOUT_DRAW_OPAQUE_BUF_FILLED_SZ 0x28b2c
	1481		#define VGT_STRMOUT_DRAW_OPAQUE_VTX_STRIDE 0x28b30
	1482
	1483		#define VGT_GS_MAX_VERT_OUT 0x28b38
	1484
	1485		#define VGT_SHADER_STAGES_ENA 0x28b54
	1486		#define VGT_LS_HS_CFG 0x28b58
	1487		#define VGT_LS_SZ 0x28b5c
	1488		#define VGT_HS_SZ 0x28b60
	1489		#define VGT_LS_HS_ALLOC 0x28b64
	1490		#define VGT_HS_PATCH_CONST 0x28b68
	1491		#define VGT_TF_PARAM 0x28b6c
	1492		#define DB_ALPHA_TO_MASK 0x28b70
	1493		#define VGT_GS_INST_CNT 0x28b74
	1494		#define VGT_DISPATCH_INITIATOR 0x28b74/* 2 names */
	1495		#define PA_SU_POLY_OF_DB_FMT_CTL 0x28b78
	1496		#define PA_SU_POLY_OF_CLAMP 0x28b7c
	1497		#define PA_SU_POLY_OF_FRONT_SCALE 0x28b80
	1498		#define PA_SU_POLY_OF_FRONT_OF 0x28b84
	1499		#define PA_SU_POLY_OF_BACK_SCALE 0x28b88
	1500		#define PA_SU_POLY_OF_BACK_OF 0x28b8c
	1501
	1502		#define VGT_STRMOUT_CFG 0x28b94
	1503		#define VGT_STRMOUT_BUF_CFG 0x28b98
	1504
	1505		#define PA_SC_LINE_CTL 0x28c00
	1506		#define PA_SC_AA_CFG 0x28c04
	1507		#define MSAA_SAMPLES_N_MASK 0x00000003
	1508		#define MSAA_SAMPLES_N_SHIFT 0
	1509		#define PA_SU_VTX_CTL 0x28c08
	1510		#define PA_CL_GB_V_CLIP_ADJ 0x28c0c
	1511		#define PA_CL_GB_V_DISC_ADJ 0x28c10
	1512		#define PA_CL_GB_H_CLIP_ADJ 0x28c14
	1513		#define PA_CL_GB_H_DISC_ADJ 0x28c18
	1514		#define PA_SC_AA_SAMPLE_LOCS_0 0x28c1c
	1515		#define PA_SC_AA_SAMPLE_LOCS_1 0x28c20
	1516		#define PA_SC_AA_SAMPLE_LOCS_2 0x28c24
	1517		#define PA_SC_AA_SAMPLE_LOCS_3 0x28c28
	1518		#define PA_SC_AA_SAMPLE_LOCS_4 0x28c2c
	1519		#define PA_SC_AA_SAMPLE_LOCS_5 0x28c30
	1520		#define PA_SC_AA_SAMPLE_LOCS_6 0x28c34
	1521		#define PA_SC_AA_SAMPLE_LOCS_7 0x28c38
	1522		#define PA_SC_AA_MASK 0x28c3c
	1523
	1524		#define VGT_VTX_REUSE_BLK_CTL 0x28c58
	1525		#define VTX_REUSE_DEPTH_MASK 0x000000ff
	1526		#define VGT_OUT_DEALLOC_CTL 0x28c5c
	1527		#define DEALLOC_DIST_MASK 0x0000007f
	1528		#define CB_COLOR_0_BASE 0x28c60
	1529		#define CB_COLOR_0_PITCH 0x28c64
	1530		#define CB_COLOR_0_SLICE 0x28c68
	1531		#define CB_COLOR_0_VIEW 0x28c6c
	1532		#define SLICE_START_MASK 0x7ff
	1533		#define SLICE_START_SHIFT 0
	1534		#define SLICE_MAX_MASK 0x00ffe000
	1535		#define SLICE_MAX_SHIFT 13
	1536		#define CB_COLOR_0_INFO 0x28c70
	1537		#define CB_ENDIAN_MASK 0x00000003
	1538		#define CB_ENDIAN_SHIFT 0
	1539		#define CB_FMT_MASK 0x000000fc
	1540		#define CB_FMT_SHIFT 2
	1541		#define COLOR_INVALID 0x00
	1542		#define COLOR_8 0x01
	1543		#define COLOR_4_4 0x02
	1544		#define COLOR_3_3_2 0x03
	1545		#define COLOR_16 0x05
	1546		#define COLOR_16_FLOAT 0x06
	1547		#define COLOR_8_8 0x07
	1548		#define COLOR_5_6_5 0x08
	1549		#define COLOR_6_5_5 0x09
	1550		#define COLOR_1_5_5_5 0x0a
	1551		#define COLOR_4_4_4_4 0x0b
	1552		#define COLOR_5_5_5_1 0x0c
	1553		#define COLOR_32 0x0d
	1554		#define COLOR_32_FLOAT 0x0e
	1555		#define COLOR_16_16 0x0f
	1556		#define COLOR_16_16_FLOAT 0x10
	1557		#define COLOR_8_24 0x11
	1558		#define COLOR_8_24_FLOAT 0x12
	1559		#define COLOR_24_8 0x13
	1560		#define COLOR_24_8_FLOAT 0x14
	1561		#define COLOR_10_11_11 0x15
	1562		#define COLOR_10_11_11_FLOAT 0x16
	1563		#define COLOR_11_11_10 0x17
	1564		#define COLOR_11_11_10_FLOAT 0x18
	1565		#define COLOR_2_10_10_10 0x19
	1566		#define COLOR_8_8_8_8 0x1a
	1567		#define COLOR_10_10_10_2 0x1b
	1568		#define COLOR_X24_8_32_FLOAT 0x1c
	1569		#define COLOR_32_32 0x1d
	1570		#define COLOR_32_32_FLOAT 0x1e
	1571		#define COLOR_16_16_16_16 0x1f
	1572		#define COLOR_16_16_16_16_FLOAT 0x20
	1573		#define COLOR_32_32_32_32 0x22
	1574		#define COLOR_32_32_32_32_FLOAT 0x23
	1575		#define COLOR_32_32_32_FLOAT 0x30
	1576		#define CB_ARRAY_MODE_MASK 0x00000f00
	1577		#define CB_ARRAY_MODE_SHIFT 8
	1578		#define ARRAY_LINEAR_GENERAL 0
	1579		#define ARRAY_LINEAR_ALIGNED 1
	1580		#define ARRAY_1D_TILED_THIN1 2
	1581		#define ARRAY_2D_TILED_THIN1 4
	1582		#define CB_NUM_TYPE_MASK 0x00007000
	1583		#define CB_NUM_TYPE_SHIFT 12
	1584		#define NUM_UNNORM 0
	1585		#define NUM_SNORM 1
	1586		#define NUM_USCALED 2
	1587		#define NUM_SSCALED 3
	1588		#define NUM_UINT 4
	1589		#define NUM_SINT 5
	1590		#define NUM_SRGB 6
	1591		#define NUM_FLOAT 7
	1592		#define COMP_SWAP_MASK 0x00018000
	1593		#define COMP_SWAP_SHIFT 15
	1594		#define SWAP_STD 0
	1595		#define SWAP_ALT 1
	1596		#define SWAP_STD_REV 2
	1597		#define SWAP_ALT_REV 3
	1598		#define FAST_CLR BIT(17)
	1599		#define COMP_MASK 0x000c00000
	1600		#define COMP_SHIFT 18
	1601		#define BLEND_CLAMP BIT(19)
	1602		#define BLEND_BYPASS BIT(20)
	1603		#define SIMPLE_FLOAT BIT(21)
	1604		#define ROUND_MODE BIT(22)
	1605		#define TILE_COMPACT BIT(23)
	1606		#define CB_SRC_FMT_MASK 0x03000000
	1607		#define CB_SRC_FMT_SHIFT 24
	1608		#define EXPORT_4C_32BPC 0
	1609		#define EXPORT_FULL 0/* 2 names */
	1610		#define EXPORT_4C_16BPC 1
	1611		#define EXPORT_NORM 1/* 2 names */
	1612		#define EXPORT_2C_32BPC 2/* do not use*/
	1613		#define RAT BIT(26)
	1614		#define RES_TYPE_MASK 0x38000000
	1615		#define RES_TYPE_SHIFT 27
	1616		#define CB_COLOR_0_ATTRIB 0x28c74
	1617		#define NON_DISP_TILING_ORDER BIT(4)
	1618		#define CB_TILE_SPLIT_MASK 0x000001e0
	1619		#define CB_TILE_SPLIT_SHIFT 5
	1620		#define ADDR_SURF_TILE_SPLIT_64B 0
	1621		#define ADDR_SURF_TILE_SPLIT_128B 1
	1622		#define ADDR_SURF_TILE_SPLIT_256B 2
	1623		#define ADDR_SURF_TILE_SPLIT_512B 3
	1624		#define ADDR_SURF_TILE_SPLIT_1KB 4
	1625		#define ADDR_SURF_TILE_SPLIT_2KB 5
	1626		#define ADDR_SURF_TILE_SPLIT_4KB 6
	1627		#define CB_BANKS_N_MASK 0x00000c00
	1628		#define CB_BANKS_N_SHIFT 10
	1629		#define ADDR_SURF_2_BANK 0
	1630		#define ADDR_SURF_4_BANK 1
	1631		#define ADDR_SURF_8_BANK 2
	1632		#define ADDR_SURF_16_BANK 3
	1633		#define CB_BANK_W_MASK 0x00006000
	1634		#define CB_BANK_W_SHIFT 13
	1635		#define ADDR_SURF_BANK_W_1 0
	1636		#define ADDR_SURF_BANK_W_2 1
	1637		#define ADDR_SURF_BANK_W_4 2
	1638		#define ADDR_SURF_BANK_W_8 3
	1639		#define CB_BANK_H_MASK 0x00030000
	1640		#define CB_BANK_H_SHIFT 16
	1641		#define ADDR_SURF_BANK_H_1 0
	1642		#define ADDR_SURF_BANK_H_2 1
	1643		#define ADDR_SURF_BANK_H_4 2
	1644		#define ADDR_SURF_BANK_H_8 3
	1645		#define CB_MACRO_TILE_ASPECT_MASK 0x00180000
	1646		#define CB_MACRO_TILE_ASPECT_SHIFT 19
	1647		#define CB_COLOR_0_DIM 0x28c78
	1648		/* only CB0-7 blocks have the 4 following regs */
	1649		#define CB_COLOR_0_CMASK 0x28c7c
	1650		#define CB_COLOR_0_CMASK_SLICE 0x28c80
	1651		#define CB_COLOR_0_FMASK 0x28c84
	1652		#define CB_COLOR_0_FMASK_SLICE 0x28c88
	1653		#define CB_COLOR_0_CLR_WD_0 0x28c8c
	1654		#define CB_COLOR_0_CLR_WD_1 0x28c90
	1655		#define CB_COLOR_0_CLR_WD_2 0x28c94
	1656		#define CB_COLOR_0_CLR_WD_3 0x28c98
	1657		#define CB_COLOR_1_BASE 0x28c9c
	1658		#define CB_COLOR_1_PITCH 0x28ca0
	1659		#define CB_COLOR_1_SLICE 0x28ca4
	1660		#define CB_COLOR_1_VIEW 0x28ca8
	1661		#define CB_COLOR_1_INFO 0x28cac
	1662		#define CB_COLOR_1_ATTRIB 0x28cb0
	1663		#define CB_COLOR_1_DIM 0x28cb4
	1664		/* only CB0-7 blocks have the 4 following regs */
	1665		#define CB_COLOR_1_CMASK 0x28cb8
	1666		#define CB_COLOR_1_CMASK_SLICE 0x28cbc
	1667		#define CB_COLOR_1_FMASK 0x28cc0
	1668		#define CB_COLOR_1_FMASK_SLICE 0x28cc4
	1669		#define CB_COLOR_1_CLR_WD_0 0x28cc8
	1670		#define CB_COLOR_1_CLR_WD_1 0x28ccc
	1671		#define CB_COLOR_1_CLR_WD_2 0x28cd0
	1672		#define CB_COLOR_1_CLR_WD_3 0x28cd4
	1673		#define CB_COLOR_2_BASE 0x28cd8
	1674		#define CB_COLOR_2_PITCH 0x28cdc
	1675		#define CB_COLOR_2_SLICE 0x28ce0
	1676		#define CB_COLOR_2_VIEW 0x28ce4
	1677		#define CB_COLOR_2_INFO 0x28ce8
	1678		#define CB_COLOR_2_ATTRIB 0x28cec
	1679		#define CB_COLOR_2_DIM 0x28cf0
	1680		/* only CB0-7 blocks have the 4 following regs */
	1681		#define CB_COLOR_2_CMASK 0x28cf4
	1682		#define CB_COLOR_2_CMASK_SLICE 0x28cf8
	1683		#define CB_COLOR_2_FMASK 0x28cfc
	1684		#define CB_COLOR_2_FMASK_SLICE 0x28d00
	1685		#define CB_COLOR_2_CLR_WD_0 0x28d04
	1686		#define CB_COLOR_2_CLR_WD_1 0x28d08
	1687		#define CB_COLOR_2_CLR_WD_2 0x28d0c
	1688		#define CB_COLOR_2_CLR_WD_3 0x28d10
	1689		#define CB_COLOR_3_BASE 0x28d14
	1690		#define CB_COLOR_3_PITCH 0x28d18
	1691		#define CB_COLOR_3_SLICE 0x28d1c
	1692		#define CB_COLOR_3_VIEW 0x28d20
	1693		#define CB_COLOR_3_INFO 0x28d24
	1694		#define CB_COLOR_3_ATTRIB 0x28d28
	1695		#define CB_COLOR_3_DIM 0x28d2c
	1696		/* only CB0-7 blocks have the 4 following regs */
	1697		#define CB_COLOR_3_CMASK 0x28d30
	1698		#define CB_COLOR_3_CMASK_SLICE 0x28d34
	1699		#define CB_COLOR_3_FMASK 0x28d38
	1700		#define CB_COLOR_3_FMASK_SLICE 0x28d3c
	1701		#define CB_COLOR_3_CLR_WD_0 0x28d40
	1702		#define CB_COLOR_3_CLR_WD_1 0x28d44
	1703		#define CB_COLOR_3_CLR_WD_2 0x28d48
	1704		#define CB_COLOR_3_CLR_WD_3 0x28d4c
	1705		#define CB_COLOR_4_BASE 0x28d50
	1706		#define CB_COLOR_4_PITCH 0x28d54
	1707		#define CB_COLOR_4_SLICE 0x28d58
	1708		#define CB_COLOR_4_VIEW 0x28d5c
	1709		#define CB_COLOR_4_INFO 0x28d60
	1710		#define CB_COLOR_4_ATTRIB 0x28d64
	1711		#define CB_COLOR_4_DIM 0x28d68
	1712		/* only CB0-7 blocks have the 4 following regs */
	1713		#define CB_COLOR_4_CMASK 0x28d6c
	1714		#define CB_COLOR_4_CMASK_SLICE 0x28d70
	1715		#define CB_COLOR_4_FMASK 0x28d74
	1716		#define CB_COLOR_4_FMASK_SLICE 0x28d78
	1717		#define CB_COLOR_4_CLR_WD_0 0x28d7c
	1718		#define CB_COLOR_4_CLR_WD_1 0x28d80
	1719		#define CB_COLOR_4_CLR_WD_2 0x28d84
	1720		#define CB_COLOR_4_CLR_WD_3 0x28d88
	1721		#define CB_COLOR_5_BASE 0x28d8c
	1722		#define CB_COLOR_5_PITCH 0x28d90
	1723		#define CB_COLOR_5_SLICE 0x28d94
	1724		#define CB_COLOR_5_VIEW 0x28d98
	1725		#define CB_COLOR_5_INFO 0x28d9c
	1726		#define CB_COLOR_5_ATTRIB 0x28da0
	1727		#define CB_COLOR_5_DIM 0x28da4
	1728		/* only CB0-7 blocks have the 4 following regs */
	1729		#define CB_COLOR_5_CMASK 0x28da8
	1730		#define CB_COLOR_5_CMASK_SLICE 0x28dac
	1731		#define CB_COLOR_5_FMASK 0x28db0
	1732		#define CB_COLOR_5_FMASK_SLICE 0x28db4
	1733		#define CB_COLOR_5_CLR_WD_0 0x28db8
	1734		#define CB_COLOR_5_CLR_WD_1 0x28dbc
	1735		#define CB_COLOR_5_CLR_WD_2 0x28dc0
	1736		#define CB_COLOR_5_CLR_WD_3 0x28dc4
	1737		#define CB_COLOR_6_BASE 0x28dc8
	1738		#define CB_COLOR_6_PITCH 0x28dcc
	1739		#define CB_COLOR_6_SLICE 0x28dd0
	1740		#define CB_COLOR_6_VIEW 0x28dd4
	1741		#define CB_COLOR_6_INFO 0x28dd8
	1742		#define CB_COLOR_6_ATTRIB 0x28ddc
	1743		#define CB_COLOR_6_DIM 0x28de0
	1744		/* only CB0-7 blocks have the 4 following regs */
	1745		#define CB_COLOR_6_CMASK 0x28de4
	1746		#define CB_COLOR_6_CMASK_SLICE 0x28de8
	1747		#define CB_COLOR_6_FMASK 0x28dec
	1748		#define CB_COLOR_6_FMASK_SLICE 0x28df0
	1749		#define CB_COLOR_6_CLR_WD_0 0x28df4
	1750		#define CB_COLOR_6_CLR_WD_1 0x28df8
	1751		#define CB_COLOR_6_CLR_WD_2 0x28dfc
	1752		#define CB_COLOR_6_CLR_WD_3 0x28e00
	1753		#define CB_COLOR_7_BASE 0x28e04
	1754		#define CB_COLOR_7_PITCH 0x28e08
	1755		#define CB_COLOR_7_SLICE 0x28e0c
	1756		#define CB_COLOR_7_VIEW 0x28e10
	1757		#define CB_COLOR_7_INFO 0x28e14
	1758		#define CB_COLOR_7_ATTRIB 0x28e18
	1759		#define CB_COLOR_7_DIM 0x28e1c
	1760		/* only CB0-7 blocks have the 4 following regs */
	1761		#define CB_COLOR_7_CMASK 0x28e20
	1762		#define CB_COLOR_7_CMASK_SLICE 0x28e24
	1763		#define CB_COLOR_7_FMASK 0x28e28
	1764		#define CB_COLOR_7_FMASK_SLICE 0x28e2c
	1765		#define CB_COLOR_7_CLR_WD_0 0x28e30
	1766		#define CB_COLOR_7_CLR_WD_1 0x28e34
	1767		#define CB_COLOR_7_CLR_WD_2 0x28e38
	1768		#define CB_COLOR_7_CLR_WD_3 0x28e3c
	1769		#define CB_COLOR_8_BASE 0x28e40
	1770		#define CB_COLOR_8_PITCH 0x28e44
	1771		#define CB_COLOR_8_SLICE 0x28e48
	1772		#define CB_COLOR_8_VIEW 0x28e4c
	1773		#define CB_COLOR_8_INFO 0x28e50
	1774		#define CB_COLOR_8_ATTRIB 0x28e54
	1775		#define CB_COLOR_8_DIM 0x28e58
	1776		#define CB_COLOR_9_BASE 0x28e5c
	1777		#define CB_COLOR_9_PITCH 0x28e60
	1778		#define CB_COLOR_9_SLICE 0x28e64
	1779		#define CB_COLOR_9_VIEW 0x28e68
	1780		#define CB_COLOR_9_INFO 0x28e6c
	1781		#define CB_COLOR_9_ATTRIB 0x28e70
	1782		#define CB_COLOR_9_DIM 0x29e74
	1783		#define CB_COLOR_A_BASE 0x28e78
	1784		#define CB_COLOR_A_PITCH 0x28e7c
	1785		#define CB_COLOR_A_SLICE 0x28e80
	1786		#define CB_COLOR_A_VIEW 0x28e84
	1787		#define CB_COLOR_A_INFO 0x28e88
	1788		#define CB_COLOR_A_ATTRIB 0x28e8c
	1789		#define CB_COLOR_A_DIM 0x28e90
	1790		#define CB_COLOR_B_BASE 0x28e94
	1791		#define CB_COLOR_B_PITCH 0x28e98
	1792		#define CB_COLOR_B_SLICE 0x28e9c
	1793		#define CB_COLOR_B_VIEW 0x28ea0
	1794		#define CB_COLOR_B_INFO 0x28ea4
	1795		#define CB_COLOR_B_ATTRIB 0x28ea8
	1796		#define CB_COLOR_B_DIM 0x28eac
	1797
	1798		#define SQ_ALU_CONST_BUF_SZ_HS_0 0x28f80
	1799		#define SQ_ALU_CONST_BUF_SZ_HS_1 0x28f84
	1800		#define SQ_ALU_CONST_BUF_SZ_HS_2 0x28f88
	1801		#define SQ_ALU_CONST_BUF_SZ_HS_3 0x28f8c
	1802		#define SQ_ALU_CONST_BUF_SZ_HS_4 0x28f90
	1803		#define SQ_ALU_CONST_BUF_SZ_HS_5 0x28f94
	1804		#define SQ_ALU_CONST_BUF_SZ_HS_6 0x28f98
	1805		#define SQ_ALU_CONST_BUF_SZ_HS_7 0x28f9c
	1806		#define SQ_ALU_CONST_BUF_SZ_HS_8 0x28fa0
	1807		#define SQ_ALU_CONST_BUF_SZ_HS_9 0x28fa4
	1808		#define SQ_ALU_CONST_BUF_SZ_HS_A 0x28fa8
	1809		#define SQ_ALU_CONST_BUF_SZ_HS_B 0x28fac
	1810		#define SQ_ALU_CONST_BUF_SZ_HS_C 0x28fb0
	1811		#define SQ_ALU_CONST_BUF_SZ_HS_D 0x28fb4
	1812		#define SQ_ALU_CONST_BUF_SZ_HS_E 0x28fb8
	1813		#define SQ_ALU_CONST_BUF_SZ_HS_F 0x28fbc
	1814		#define SQ_ALU_CONST_BUF_SZ_LS_0 0x28fc0
	1815		#define SQ_ALU_CONST_BUF_SZ_LS_1 0x28fc4
	1816		#define SQ_ALU_CONST_BUF_SZ_LS_2 0x28fc8
	1817		#define SQ_ALU_CONST_BUF_SZ_LS_3 0x28fcc
	1818		#define SQ_ALU_CONST_BUF_SZ_LS_4 0x28fd0
	1819		#define SQ_ALU_CONST_BUF_SZ_LS_5 0x28fd4
	1820		#define SQ_ALU_CONST_BUF_SZ_LS_6 0x28fd8
	1821		#define SQ_ALU_CONST_BUF_SZ_LS_7 0x28fdc
	1822		#define SQ_ALU_CONST_BUF_SZ_LS_8 0x28fe0
	1823		#define SQ_ALU_CONST_BUF_SZ_LS_9 0x28fe4
	1824		#define SQ_ALU_CONST_BUF_SZ_LS_A 0x28fe8
	1825		#define SQ_ALU_CONST_BUF_SZ_LS_B 0x28fec
	1826		#define SQ_ALU_CONST_BUF_SZ_LS_C 0x28ff0
	1827		#define SQ_ALU_CONST_BUF_SZ_LS_D 0x28ff4
	1828		#define SQ_ALU_CONST_BUF_SZ_LS_E 0x28ff8
	1829		#define SQ_ALU_CONST_BUF_SZ_LS_F 0x28ffc
	1830
	1831		/* start of resource area: 0x30000-0x38000 */
	1832		#define SQ_TEX_RES_WD_0_0 0x30000
	1833		#define TEX_DIM_MASK 0xffffffff
	1834		#define TEX_DIM_SHIFT 0
	1835		#define SQ_TEX_DIM_1D 0
	1836		#define SQ_TEX_DIM_2D 1
	1837		#define SQ_TEX_DIM_3D 2
	1838		#define SQ_TEX_DIM_CUBEMAP 3
	1839		#define SQ_TEX_DIM_1D_ARRAY 4
	1840		#define SQ_TEX_DIM_2D_ARRAY 5
	1841		#define SQ_TEX_DIM_2D_MSAA 6
	1842		#define SQ_TEX_DIM_2D_ARRAY_MSAA 7
	1843		/* aligned on 4 pitch unit - 1 */
	1844		#define TEX_PITCH_MASK 0xffffffff
	1845		#define TEX_PITCH_SHIFT 6
	1846		/* w - 1 */
	1847		#define TEX_W_MASK 0xffffffff
	1848		#define TEX_W_SHIFT 18
	1849		#define SQ_TEX_RES_WD_1_0 0x30004
	1850		/* h - 1 */
	1851		#define TEX_H_MASK 0xffffffff
	1852		#define TEX_H_SHIFT 0
	1853		#define TEX_ARRAY_MODE_MASK 0xffffffff
	1854		#define TEX_ARRAY_MODE_SHIFT 28
	1855		#define SQ_TEX_RES_WD_2_0 0x30008
	1856		#define SQ_TEX_RES_WD_3_0 0x3000c
	1857		#define SQ_TEX_RES_WD_4_0 0x30010
	1858		#define TEX_DST_SEL_X_MASK 0xffffffff
	1859		#define TEX_DST_SEL_X_SHIFT 16
	1860		#define TEX_DST_SEL_Y_MASK 0xffffffff
	1861		#define TEX_DST_SEL_Y_SHIFT 19
	1862		#define TEX_DST_SEL_Z_MASK 0xffffffff
	1863		#define TEX_DST_SEL_Z_SHIFT 22
	1864		#define TEX_DST_SEL_W_MASK 0xffffffff
	1865		#define TEX_DST_SEL_W_SHIFT 25
	1866		#define SQ_SEL_X 0
	1867		#define SQ_SEL_Y 1
	1868		#define SQ_SEL_Z 2
	1869		#define SQ_SEL_W 3
	1870		#define SQ_SEL_0 4
	1871		#define SQ_SEL_1 5
	1872		#define SQ_TEX_RES_WD_5_0 0x30014
	1873		#define SQ_TEX_RES_WD_6_0 0x30018
	1874		#define TEX_TILE_SPLIT_MASK 0xe0000000
	1875		#define TEX_TILE_SPLIT_SHIFT 29
	1876		#define SQ_TEX_RES_WD_7_0 0x3001c
	1877		#define TEX_MACRO_TILE_ASPECT_MASK 0x000000c0
	1878		#define TEX_MACRO_TILE_ASPECT_SHIFT 6
	1879		#define TEX_BANK_W_MASK 0x00000300
	1880		#define TEX_BANK_W_SHIFT 8
	1881		#define TEX_BANK_H_MASK 0x00000c00
	1882		#define TEX_BANK_H_SHIFT 10
	1883		#define TEX_BANKS_N_MASK 0x00030000
	1884		#define TEX_BANKS_N_SHIFT 16
	1885		#define SQ_CONST_TYPE_MASK 0xc0000000
	1886		#define SQ_CONST_TYPE_SHIFT 30
	1887		#define SQ_TEX_VTX_INVALID_TEX 0
	1888		#define SQ_TEX_VTX_INVALID_BUF 1
	1889		#define SQ_TEX_VTX_VALID_TEX 2
	1890		#define SQ_TEX_VTX_VALID_BUF 3
	1891
	1892		/* start of sampler register area: 0x3c000-0x3c600 */
	1893
	1894		/* start of const register area: 0x3cff0-0x3ff0c */
	1895		#define SQ_VTX_BASE_VTX_LOC 0x3cff0
	1896		#define SQ_VTX_START_INST_LOC 0x3cff4
	1897
	1898		#define SQ_TEX_SAMPLER_CLR 0x3ff00
	1899		#define SQ_TEX_RESOURCE_CLR 0x3ff04
	1900		#define SQ_LOOP_BOOL_CLR 0x3ff08
	1901		#endif

File drivers/gpu/alga/amd/si/silicium_blks/README added (mode: 100644) (index 0000000..7c75d77)
	1		When developing drivers for such a complex device, the main driving idea is to
	2		divide like a graph the PCI device. The driver code tries to reflect this
	3		"division" through its exposed programming model (*tries*).
	4
	5		This is a driver for a PCI graphical device. That device has some graphical
	6		chips. In our case, each chip is from a specific family. In that chip we have
	7		hardware blocks related to each other:
	8
	9		- A PCI Express block.
	10		- A memory controller block.
	11		- An interrupt controller block
	12		- A Display controller engine (DCE) block.
	13		- A register backbone manager block.
	14		- Some command processor blocks.
	15		- A GPU block:
	16		- Some 3D pipeline blocks.
	17		- Some shader engine blocks.
	18		- Some render backend blocks.
	19
	20		...
	21
	22		Keep in mind that, the real GPU logic is only a part of one of the chip on that
	23		device. Since shaders machine code expression strengh is getting stronger
	24		everyday, they tend to become generic processors, and the part which is
	25		specific to 3D is then even more restricted.

File drivers/gpu/alga/amd/si/silicium_blks/gpu added (mode: 100644) (index 0000000..82f16ff)
	1		GPU programming model:
	2
	3		The GPU has a pipeline. This pipeline runs several "draw" operations at the
	4		same time (or compute job). It's transparent for the driver software. The latest
	5		submits a "draw" operation using the proper CP command through a circular
	6		buffer (the ring). High-end GPUs have a bigger pipeline. Usually, the pipeline
	7		sizes are 4, 8...
	8
	9		The GPU register space is split in several regions. Some regions are common to
	10		all operations running in the pipeline. Others (for instance the context
	11		registers) are specific to one "draw" operation.
	12
	13		Usually, you configure the registers specific to your "draw" operation, then
	14		your submit it to the pipeline. If you want to modify the pipeline global
	15		registers, then you must flush the pipeline first.

File drivers/gpu/alga/amd/si/silicium_blks/hdp added (mode: 100644) (index 0000000..abb1295)
	1		The HDP is the silicium block dealing with the GPU address space accessed
	2		throught PCI bar 0. You tell the HDP the 256kB block index of the start GPU
	3		address to use in HDP_NONSURFACE_BASE, some "information" in HDP_NONSURFACE_INFO
	4		and the size in HDP_NONSURFACE_SIZE.
	5
	6		HDP_MEM_COHERENCY_FLUSH_CTL register is used to flush HDP cache after PCI bar 0
	7		transactions.
	8		HDP_REG_COHERENCY_FLUSH_CTL register is used to flush HDP cache after HDP
	9		register changes.
	10
	11		HDP_MISC_CTL with the HDP_FLUSH_INVALIDATE_CACHE do what is says. What is the
	12		relationship with the caches above?
	13
	14		There is a set of HDP registers not related to memory bus architecture:
	15		from 0x2c14, 32 blocks of 0x18 bytes in size (FIFOs/TLB)

File drivers/gpu/alga/amd/si/silicium_blks/mc added (mode: 100644) (index 0000000..540c0a4)
	1		MC (Memory Controller), VM (Virtual Memory), ARB (ARBitrer)
	2
	3		Way of operations is based on m56(r5xx). See m56 register reference guide
	4		(docs at http://developer.amd.com), the part dealing with the page unit.
	5
	6		MC_VRAM_LOCATION tells the mc where to map the vram in the GPU address
	7		space. Start and end GPU addresses must be 16MB aligned. Not related to VM.
	8
	9		programming memory model:
	10		The VM uses 2 internal apertures: system and non-system. When a memory request
	11		arrives in the VM, if it is in the system aperture the GPU address is used
	12		directly. If it is outside the system aperture the request is routed to page
	13		table translation block for bus address.
	14
	15		The MC_VM_SYS_APER_LOW_ADDR and MC_VM_SYS_APER_HIGH_ADDR defines
	16		the GPU address range of the internal system aperture.
	17		MC_VM_SYS_APERTURE_DEFAULT_ADDR is the default GPU address for unmapped GPU
	18		address in the system aperture.
	19
	20		The VM (historically page unit 0) has 8 contexts which each maps a GPU address
	21		range to other addresses ranges using a page table (for us, it will be one bus
	22		address range). Only the context 0 is used. The context 0 does more for the VM
	23		than the other 7. Then the start GPU address of the range is written in
	24		VM_CTX_0_PT_START_ADDR register, end GPU address of the range is written
	25		in VM_CTX_0_PT_END_ADDR register. The bus address range is defined by a
	26		table which maps a GPU pages to a bus addresses. This table is stored in VRAM.
	27		The VRAM GPU address of this table is to be written in
	28		VM_CTX_0_PT_BASE_ADDR register. Of course, this GPU address is to be
	29		compatible with the previoulsy chosen addresses for the memory controller.
	30		If there is no page in order to map a GPU address from a request to a bus
	31		address, the bus address stored in VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR
	32		is used. The VM has several read/write clients from the MD block and the MB
	33		block. Those clients are configured using MC_VM_MD_L1_TLB_X_CTL (X from 0 to 3)
	34		and MC_VM_MB_L1_TLB_X_CTL (X from 0 to 3). Those clients uses the CTX0, and the
	35		programming memory model is programmed in those latest register (see
	36		NOT_IN_SYS and SYS_APER_UNMAPPED_ACCESS with PASS_THRU).
	37
	38		o The configuration of the VRAM modules is in ARB_RAMCFG register. There you
	39		have the number of the classic channels/ranks/banks/rows/columns with the
	40		channel size and burst size. The burst size is the capability of the channel
	41		protocol to stream a bigger amount of data than a "normally sized" transaction
	42		to the VRAM modules (tradeoff latency/speed). See internet for RAM
	43		channels/ranks/banks/rows/columns way of operation.
	44
	45		o When a memory request arrives in the mc, if that request through address
	46		translation finally target the VRAM GPU address range, that final GPU
	47		address range will be mapped to channel/rank/bank/row/column uplet.
	48		Interleaving is a sequencial mapping of addresses over several units
	49		(channels, banks and more).
	50
	51		o The arbiter is the silicium block which manages the accesses to the mc from
	52		several clients.
	53
	54		address based interleaving: an address range (row) will be sequentially
	55		distributed over a set of units.
	56		It seems there are address based interleaving on several units:
	57		- pipes
	58		- banks (probably vram module)
	59		The base range is based on VRAM channel burst len.
	60
	61		There are 3 arbiter clients:
	62		- HDP (HDP_ADDR_CFG register)
	63		- DMIF (DMIF_ADDR_CFG register)
	64		- GB (GB_ADDR_CFG register)
	65
	66		o swizzled data is tiled organized data.
	67
	68		o the tiling unit seems to be based on VRAM burst lenght.
	69
	70		o VRAM module configuration:
	71		o MC_SHARED_CHMAP (memory controller shared VRAM channel map):
	72		CHANS_N:
	73		(default) 0 --> 1 channel
	74		1 --> 2 channels
	75		2 --> 4 channels
	76		3 --> 8 channels

File drivers/gpu/alga/amd/si/silicium_blks/others added (mode: 100644) (index 0000000..b1b6a1a)
	1		o SP (Shader Pipe)
	2		seems to have some simd units
	3
	4		o vgt (Vertex Grouper and Tessellator)
	5		o tc (Texture Cache)
	6		o vc (Vertex Cache)
	7		o sx (Shader Export)
	8		o spi (Shader Processor Interpolator)
	9		o db (Depth Block)
	10		o cb (Color Block)
	11		o pa (Primitive Assembler)
	12		o sc (Scan Convertor)
	13		o sh (Sequencer instruction cache)
	14		o ta (Texture Addresser)
	15		see R6xx_R7xx_3D.pdf
	16
	17		crtc/cur/lut/grph/viewport
	18
	19		o RLC
	20
	21		Seems related to interrupts. There is multiplexing among "instances" and
	22		shader engines. You need to select using RLC_GFX_IDX the "instances" and
	23		shader engines which are intended to be programed.
	24
	25		o CP is the Command Processor
	26
	27		It requires a firmware to be loaded and is dealed through a ring buffer.
	28		Nethertheless, its basic control silicium block does not need the firmware to
	29		be loaded in order to work.
	30		GPU side, the ring buffer is in bus aperture. CPU side is backed with RAM.
	31		The GPU fetches CPU side RAM (bus master).
	32		The ring buffer works with blocks of 16 dwords. Each "commit" must have a size
	33		padded on blocks of 16 dwords. 16 dwords is the "fetch size", dealed by the
	34		prefetcher of the cp. A padding dword should be filled with the 2 << 30 value
	35		which is a type 2 packet which is actually a filler packet.
	36
	37		<-----ring size (power of 2)----->
	38		+--------------------------------+
	39		| 16 dws | 16 dws | ... | 16 dws |
	40		+--------------------------------+
	41
	42		The ring size is defined in power of two of quadwords (64 bits). Also the
	43		GPU page size is used as "inner blocks". A GPU page is 4096 bytes then
	44		2^9 quadwords exactly.
	45
	46		<--------------2^17 qws------------->
	47		+-----------------------------------+
	48		| 2^9 qws | 2^9 qws | ... | 2^9 qws |
	49		+-----------------------------------+
	50
	51		Of course, the prefectch size is aligned on 2^9 qws, namely 16 dws is 2^3 qws:
	52
	53		<--------------2^9 qws-------------->
	54		+-----------------------------------+
	55		| 2^3 qws | 2^3 qws | ... | 2^3 qws |
	56		+-----------------------------------+
	57
	58		The write pointer of the ring is managed by the CPU. This pointer is a dword
	59		index. When the write pointer is committed to the GPU, it must point to the
	60		dword right after the last fetch block dword (16 dwords).
	61
	62		The CP has a clear context. Namely a set of GPU register values which defines
	63		the "clear" state. It is programmed using a type 3 packet PKT3_PREAMBLE_CTL
	64		and that state is set using the type 3 packet PKT3_CLEAR_STATE.
	65
	66		o IH is the Interrupt Handler.
	67
	68		Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty the same
	69		as the CP ring buffer, but in reverse. Rather than the CPU writing to the
	70		ring and the GPU consuming, the GPU writes to the ring and host consumes. As
	71		the host irq handler processes interrupts, it increments the rptr. When the
	72		rptr catches up with the wptr, all the current interrupts have been processed.
	73
	74		It requires like the CP a firmware to be loaded and is dealed through a ring
	75		buffer too. It does not need the firmware loaded for basic control like
	76		the CP.
	77
	78		The size of the IH ring buffer is 2^14 dwords.
	79
	80		<-------2^14 dws----->
	81		+--------------------+
	82		| dw | dw | ... | dw |
	83		+--------------------+
	84
	85		o scratch registers
	86
	87		There are 7 scratch 32 bits registers. In the write back page, there is a
	88		section for events associated with scratch registers. Each scratch register
	89		has a 32 bits place holder in this event related section.
	90
	91		offset 3072: start of event related section for scratch registers
	92		/
	93		|
	94		+----------------------------------------------------------------------------+
	95		| +---------------------------------------------------------+ |
	96		| | event for scratch reg 0 | ... | event for scratch reg 7 | |
	97		| +---------------------------------------------------------+ |
	98		| WRITE BACK GPU PAGE |
	99		+----------------------------------------------------------------------------+
	100		<----------------------------------4kB--------------------------------------->
	101
	102		o fences
	103
	104		Fences uses a scratch register. The 32 bits event place holder in the write
	105		back page receive a sequence number, inited to 0 by the CPU.
	106
	107		A fence has 3 states:
	108		- created
	109		- emited
	110		- signaled
	111
	112		At first, a fence is created, but neither emited nor signaled.

File drivers/gpu/alga/amd/si/silicium_blks/xrbm added (mode: 100644) (index 0000000..7d50a1e)
	1		Those blockis manage the registers. The PCI bar 2 decodes bus transactions to be
	2		forwarded to proper Xrbm block.
	3
	4		o Xrbm (X Register Backbone Manager) where X is G or S
	5
	6		The PCI BAR region 2 is used for register access. It is usually 128kB. Most
	7		of those registers are accessed throught a Xrbm, which is a block of
	8		silicium which has smart about writting to the real registers. For instance
	9		timing contraints may be respected and is a kind of fifo.
	10
	11		Most graphics/3D regs sit behind a Xrbm because it is a complex
	12		process , while other like display/asic setup/config regs do not.
	13
	14		o grbm (Graphic Register Backbone Manager)
	15
	16		Xrbm that has smart for graphic/3D regs
	17		There is multiplexing among "instances" and shader engines. You need to select
	18		using RLC_GFX_IDX the "instances" and shader engines which are intended to be
	19		programed.
	20
	21		o srbm (System Register Backbone Manager)
	22
	23		Xrbm that has smart for system(?) regs

File drivers/gpu/alga/amd/si/tiling.c added (mode: 100644) (index 0000000..7536af6)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/pci.h>
	7
	8		#include "ih.h"
	9		#include "ba.h"
	10		#include "ucode.h"
	11		#include "cp.h"
	12		#include "drv.h"
	13
	14		#include "tiling.h"
	15
	16		void tiling_modes_tbl_init(struct pci_dev *dev, unsigned mem_row_sz_kb)
	17		{
	18		struct dev_drv_data *dd;
	19		u32 reg_of;
	20		u32 gb_tile_mode_xx;
	21		u32 split_equal_to_row_sz;
	22
	23		dd = pci_get_drvdata(dev);
	24
	25		switch (mem_row_sz_kb) {
	26		case 1:
	27		split_equal_to_row_sz = ADDR_SURF_TILE_SPLIT_1KB;
	28		break;
	29		case 2:
	30		default:
	31		split_equal_to_row_sz = ADDR_SURF_TILE_SPLIT_2KB;
	32		break;
	33		case 4:
	34		split_equal_to_row_sz = ADDR_SURF_TILE_SPLIT_4KB;
	35		break;
	36		}
	37
	38		if ((dd->family == CHIP_TAHITI) || (dd->family == CHIP_PITCAIRN)) {
	39		for (reg_of = 0; reg_of < TILE_MODE_STATES_N; ++reg_of) {
	40		switch (reg_of) {
	41		/* non-aa compressed depth or any compressed stencil */
	42		case 0:
	43		gb_tile_mode_xx =
	44		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	45		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	46		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	47		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	48		| SET(BANKS_N, ADDR_SURF_16_BANK)
	49		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	50		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	51		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	52		break;
	53		/* 2xaa/4xaa compressed depth only */
	54		case 1:
	55		/*
	56		* 2xaa/4xaa compressed depth with stencil (for depth
	57		* buffer)
	58		*/
	59		case 3:
	60		gb_tile_mode_xx =
	61		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	62		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	63		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	64		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_128B)
	65		| SET(BANKS_N, ADDR_SURF_16_BANK)
	66		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	67		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	68		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	69		break;
	70		/* 8xaa compressed depth only */
	71		case 2:
	72		gb_tile_mode_xx =
	73		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	74		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	75		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	76		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	77		| SET(BANKS_N, ADDR_SURF_16_BANK)
	78		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	79		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	80		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	81		break;
	82		/*
	83		* maps w/ a dimension less than the 2d macro-tile
	84		* dimensions (for mipmapped depth textures)
	85		*/
	86		case 4:
	87		gb_tile_mode_xx =
	88		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	89		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	90		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	91		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	92		| SET(BANKS_N, ADDR_SURF_16_BANK)
	93		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	94		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	95		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	96		break;
	97		/*
	98		* uncompressed 16bpp depth - and stencil buffer
	99		* allocated with it
	100		*/
	101		case 5:
	102		gb_tile_mode_xx =
	103		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	104		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	105		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	106		| SET(TILE_SPLIT, split_equal_to_row_sz)
	107		| SET(BANKS_N, ADDR_SURF_16_BANK)
	108		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	109		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	110		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	111		break;
	112		/*
	113		* uncompressed 32bpp depth - and stencil buffer
	114		* allocated with it
	115		*/
	116		case 6:
	117		gb_tile_mode_xx =
	118		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	119		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	120		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	121		| SET(TILE_SPLIT, split_equal_to_row_sz)
	122		| SET(BANKS_N, ADDR_SURF_16_BANK)
	123		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	124		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	125		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	126		break;
	127		/*
	128		* uncompressed 8bpp stencil without depth (drivers
	129		* typically do not use)
	130		*/
	131		case 7:
	132		gb_tile_mode_xx =
	133		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	134		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	135		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	136		| SET(TILE_SPLIT, split_equal_to_row_sz)
	137		| SET(BANKS_N, ADDR_SURF_16_BANK)
	138		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	139		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	140		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	141		break;
	142		/* 1d and 1d array surfaces */
	143		case 8:
	144		gb_tile_mode_xx =
	145		SET(ARRAY_MODE, ARRAY_LINEAR_ALIGNED)
	146		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	147		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	148		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	149		| SET(BANKS_N, ADDR_SURF_16_BANK)
	150		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	151		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	152		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	153		break;
	154		/* displayable maps */
	155		case 9:
	156		gb_tile_mode_xx =
	157		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	158		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	159		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	160		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	161		| SET(BANKS_N, ADDR_SURF_16_BANK)
	162		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	163		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	164		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	165		break;
	166		/* display 8bpp */
	167		case 10:
	168		gb_tile_mode_xx =
	169		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	170		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	171		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	172		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	173		| SET(BANKS_N, ADDR_SURF_16_BANK)
	174		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	175		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	176		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	177		break;
	178		/* display 16bpp */
	179		case 11:
	180		gb_tile_mode_xx =
	181		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	182		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	183		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	184		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	185		| SET(BANKS_N, ADDR_SURF_16_BANK)
	186		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	187		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	188		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	189		break;
	190		/* display 32bpp */
	191		case 12:
	192		gb_tile_mode_xx =
	193		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	194		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	195		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	196		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	197		| SET(BANKS_N, ADDR_SURF_16_BANK)
	198		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	199		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	200		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	201		break;
	202		/* thin */
	203		case 13:
	204		gb_tile_mode_xx =
	205		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	206		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	207		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	208		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	209		| SET(BANKS_N, ADDR_SURF_16_BANK)
	210		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	211		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	212		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	213		break;
	214		/* thin 8 bpp */
	215		case 14:
	216		gb_tile_mode_xx =
	217		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	218		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	219		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	220		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	221		| SET(BANKS_N, ADDR_SURF_16_BANK)
	222		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	223		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	224		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	225		break;
	226		/* thin 16 bpp */
	227		case 15:
	228		gb_tile_mode_xx =
	229		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	230		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	231		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	232		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	233		| SET(BANKS_N, ADDR_SURF_16_BANK)
	234		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	235		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	236		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	237		break;
	238		/* thin 32 bpp */
	239		case 16:
	240		gb_tile_mode_xx =
	241		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	242		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	243		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	244		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	245		| SET(BANKS_N, ADDR_SURF_16_BANK)
	246		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	247		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	248		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	249		break;
	250		/* thin 64 bpp */
	251		case 17:
	252		gb_tile_mode_xx =
	253		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	254		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	255		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	256		| SET(TILE_SPLIT, split_equal_to_row_sz)
	257		| SET(BANKS_N, ADDR_SURF_16_BANK)
	258		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	259		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	260		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	261		break;
	262		/* 8 bpp prt */
	263		case 21:
	264		gb_tile_mode_xx =
	265		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	266		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	267		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	268		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	269		| SET(BANKS_N, ADDR_SURF_16_BANK)
	270		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_2)
	271		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	272		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	273		break;
	274		/* 16 bpp prt */
	275		case 22:
	276		gb_tile_mode_xx =
	277		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	278		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	279		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	280		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	281		| SET(BANKS_N, ADDR_SURF_16_BANK)
	282		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	283		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	284		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	285		break;
	286		/* 32 bpp prt */
	287		case 23:
	288		gb_tile_mode_xx =
	289		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	290		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	291		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	292		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	293		| SET(BANKS_N, ADDR_SURF_16_BANK)
	294		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	295		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	296		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	297		break;
	298		/* 64 bpp prt */
	299		case 24:
	300		gb_tile_mode_xx =
	301		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	302		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	303		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	304		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	305		| SET(BANKS_N, ADDR_SURF_16_BANK)
	306		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	307		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	308		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	309		break;
	310		/* 128 bpp prt */
	311		case 25:
	312		gb_tile_mode_xx =
	313		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	314		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	315		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	316		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_1KB)
	317		| SET(BANKS_N, ADDR_SURF_08_BANK)
	318		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	319		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	320		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	321		break;
	322		default:
	323		gb_tile_mode_xx = 0;
	324		break;
	325		}
	326		wr32(dev, gb_tile_mode_xx, GB_TILE_MODE_00
	327		+ reg_offset * 4);
	328		}
	329		} else if (dd->family == CHIP_VERDE) {
	330		for (reg_of = 0; reg_of < TILE_MODE_STATES_N; ++reg_of) {
	331		switch (reg_of) {
	332		/* non-aa compressed depth or any compressed stencil */
	333		case 0:
	334		gb_tile_mode_xx =
	335		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	336		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	337		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	338		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	339		| SET(BANKS_N, ADDR_SURF_16_BANK)
	340		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	341		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	342		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	343		break;
	344		/* 2xaa/4xaa compressed depth only */
	345		case 1:
	346		/*
	347		* 2xaa/4xaa compressed depth with stencil (for depth
	348		* buffer)
	349		*/
	350		case 3:
	351		gb_tile_mode_xx =
	352		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	353		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	354		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	355		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_128B)
	356		| SET(BANKS_N, ADDR_SURF_16_BANK)
	357		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	358		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	359		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	360		break;
	361		/* 8xaa compressed depth only */
	362		case 2:
	363		gb_tile_mode_xx =
	364		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	365		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	366		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	367		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	368		| SET(BANKS_N, ADDR_SURF_16_BANK)
	369		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	370		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	371		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	372		break;
	373		/*
	374		* maps w/ a dimension less than the 2D macro-tile
	375		* dimensions (for mipmapped depth textures)
	376		*/
	377		case 4:
	378		gb_tile_mode_xx =
	379		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	380		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	381		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	382		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	383		| SET(BANKS_N, ADDR_SURF_16_BANK)
	384		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	385		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	386		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	387		break;
	388		/*
	389		* uncompressed 16bpp depth - and stencil bufferxi
	390		* allocated with it
	391		*/
	392		case 5:
	393		gb_tile_mode_xx =
	394		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	395		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	396		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	397		| SET(TILE_SPLIT, split_equal_to_row_sz)
	398		| SET(BANKS_N, ADDR_SURF_16_BANK)
	399		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	400		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	401		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	402		break;
	403		/*
	404		* uncompressed 32bpp depth - and stencil buffer
	405		* allocated with it
	406		*/
	407		case 6:
	408		gb_tile_mode_xx =
	409		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	410		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	411		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	412		| SET(TILE_SPLIT, split_equal_to_row_sz)
	413		| SET(BANKS_N, ADDR_SURF_16_BANK)
	414		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	415		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	416		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	417		break;
	418		/*
	419		* uncompressed 8bpp stencil without depth (drivers
	420		* typically do not use)
	421		*/
	422		case 7:
	423		gb_tile_mode_xx =
	424		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	425		| SET(MICRO_TILE_MODE, ADDR_SURF_DEPTH_MICRO_TILING)
	426		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	427		| SET(TILE_SPLIT, split_equal_to_row_sz)
	428		| SET(BANKS_N, ADDR_SURF_16_BANK)
	429		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	430		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	431		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	432		break;
	433		/* 1d and 1d array surfaces */
	434		case 8:
	435		gb_tile_mode_xx =
	436		SET(ARRAY_MODE, ARRAY_LINEAR_ALIGNED)
	437		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	438		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	439		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	440		| SET(BANKS_N, ADDR_SURF_16_BANK)
	441		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	442		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	443		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	444		break;
	445		/* displayable maps */
	446		case 9:
	447		gb_tile_mode_xx =
	448		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	449		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	450		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	451		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	452		| SET(BANKS_N, ADDR_SURF_16_BANK)
	453		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	454		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	455		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	456		break;
	457		/* display 8bpp */
	458		case 10:
	459		gb_tile_mode_xx =
	460		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	461		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	462		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	463		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	464		| SET(BANKS_N, ADDR_SURF_16_BANK)
	465		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	466		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	467		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	468		break;
	469		/* display 16bpp */
	470		case 11:
	471		gb_tile_mode_xx =
	472		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	473		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	474		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	475		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	476		| SET(BANKS_N, ADDR_SURF_16_BANK)
	477		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	478		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	479		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	480		break;
	481		/* display 32bpp */
	482		case 12:
	483		gb_tile_mode_xx =
	484		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	485		| SET(MICRO_TILE_MODE, ADDR_SURF_DISPLAY_MICRO_TILING)
	486		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	487		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	488		| SET(BANKS_N, ADDR_SURF_16_BANK)
	489		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	490		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	491		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	492		break;
	493		/* thin */
	494		case 13:
	495		gb_tile_mode_xx =
	496		SET(ARRAY_MODE, ARRAY_1D_TILED_THIN1)
	497		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	498		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	499		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_64B)
	500		| SET(BANKS_N, ADDR_SURF_16_BANK)
	501		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	502		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	503		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	504		break;
	505		/* thin 8 bpp */
	506		case 14:
	507		gb_tile_mode_xx =
	508		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	509		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	510		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	511		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	512		| SET(BANKS_N, ADDR_SURF_16_BANK)
	513		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	514		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	515		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	516		break;
	517		/* thin 16 bpp */
	518		case 15:
	519		gb_tile_mode_xx =
	520		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	521		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	522		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	523		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	524		| SET(BANKS_N, ADDR_SURF_16_BANK)
	525		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	526		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	527		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	528		break;
	529		/* thin 32 bpp */
	530		case 16:
	531		gb_tile_mode_xx =
	532		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	533		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	534		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	535		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	536		| SET(BANKS_N, ADDR_SURF_16_BANK)
	537		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	538		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	539		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	540		break;
	541		/* thin 64 bpp */
	542		case 17:
	543		gb_tile_mode_xx =
	544		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	545		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	546		| SET(PIPE_CFG, ADDR_SURF_P4_8x16)
	547		| SET(TILE_SPLIT, split_equal_to_row_sz)
	548		| SET(BANKS_N, ADDR_SURF_16_BANK)
	549		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	550		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	551		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	552		break;
	553		/* 8 bpp prt */
	554		case 21:
	555		gb_tile_mode_xx =
	556		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	557		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	558		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	559		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	560		| SET(BANKS_N, ADDR_SURF_16_BANK)
	561		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_2)
	562		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	563		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	564		break;
	565		/* 16 bpp prt */
	566		case 22:
	567		gb_tile_mode_xx =
	568		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	569		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	570		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	571		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	572		| SET(BANKS_N, ADDR_SURF_16_BANK)
	573		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	574		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_4)
	575		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_4);
	576		break;
	577		/* 32 bpp prt */
	578		case 23:
	579		gb_tile_mode_xx =
	580		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	581		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	582		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	583		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_256B)
	584		| SET(BANKS_N, ADDR_SURF_16_BANK)
	585		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	586		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_2)
	587		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	588		break;
	589		/* 64 bpp prt */
	590		case 24:
	591		gb_tile_mode_xx =
	592		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	593		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	594		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	595		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_512B)
	596		| SET(BANKS_N, ADDR_SURF_16_BANK)
	597		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	598		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	599		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_2);
	600		break;
	601		/* 128 bpp prt */
	602		case 25:
	603		gb_tile_mode_xx =
	604		SET(ARRAY_MODE, ARRAY_2D_TILED_THIN1)
	605		| SET(MICRO_TILE_MODE, ADDR_SURF_THIN_MICRO_TILING)
	606		| SET(PIPE_CFG, ADDR_SURF_P8_32x32_8x16)
	607		| SET(TILE_SPLIT, ADDR_SURF_TILE_SPLIT_1KB)
	608		| SET(BANKS_N, ADDR_SURF_08_BANK)
	609		| SET(BANK_WIDTH, ADDR_SURF_BANK_WIDTH_1)
	610		| SET(BANK_HEIGHT, ADDR_SURF_BANK_HEIGHT_1)
	611		| SET(MACRO_TILE_ASPECT, ADDR_SURF_MACRO_ASPECT_1);
	612		break;
	613		default:
	614		gb_tile_mode_xx = 0;
	615		break;
	616		}
	617		wr32(dev, gb_tile_mode_xx, GB_TILE_MODE_00
	618		+ reg_offset * 4);
	619		}
	620		}
	621		}

File drivers/gpu/alga/amd/si/tiling.h added (mode: 100644) (index 0000000..86b0761)
	1		#ifndef _TILING_H
	2		#define _TILING_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define TILE_MODE_STATES_N 32
	9		void tiling_modes_tbl_init(struct pci_dev *dev, unsigned mem_row_sz_kb);
	10		#endif

File drivers/gpu/alga/amd/si/ucode.c added (mode: 100644) (index 0000000..0b67076)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/pci.h>
	7		#include <linux/firmware.h>
	8		#include <linux/cdev.h>
	9
	10		#include <alga/rng_mng.h>
	11		#include <alga/timing.h>
	12		#include <alga/pixel_fmts.h>
	13		#include <alga/amd/dce4/dce4.h>
	14
	15		#include "regs.h"
	16
	17		#include "ih.h"
	18		#include "ba.h"
	19		#include "ucode.h"
	20		#include "cp.h"
	21		#include "drv.h"
	22
	23		#define PFP_DWS 2144
	24		#define ME_DWS 2144
	25		#define CE_DWS 2144
	26		#define RLC_DWS 2048
	27		#define MC_DWS 7769
	28
	29		MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
	30		MODULE_FIRMWARE("radeon/TAHITI_me.bin");
	31		MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
	32		MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
	33		MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
	34		MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
	35		MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
	36		MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
	37		MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
	38		MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
	39		MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
	40		MODULE_FIRMWARE("radeon/VERDE_me.bin");
	41		MODULE_FIRMWARE("radeon/VERDE_ce.bin");
	42		MODULE_FIRMWARE("radeon/VERDE_mc.bin");
	43		MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
	44
	45		void ucode_release(struct pci_dev *dev)
	46		{
	47		struct dev_drv_data *dd;
	48		dd = pci_get_drvdata(dev);
	49
	50		release_firmware(dd->ucode.pfp);
	51		release_firmware(dd->ucode.me);
	52		release_firmware(dd->ucode.ce);
	53		release_firmware(dd->ucode.rlc);
	54		release_firmware(dd->ucode.mc);
	55		}
	56
	57		int ucode_load(struct pci_dev *dev)
	58		{
	59		struct dev_drv_data *dd;
	60		const char *chip_name;
	61		size_t pfp_req_sz;
	62		size_t me_req_sz;
	63		size_t ce_req_sz;
	64		size_t rlc_req_sz;
	65		size_t mc_req_sz;
	66		char fw_name[30];
	67		int err;
	68
	69		chip_name = NULL;
	70
	71		dd = pci_get_drvdata(dev);
	72
	73		switch (dd->family) {
	74		case TAHITI:
	75		chip_name = "TAHITI";
	76		break;
	77		case PITCAIRN:
	78		chip_name = "PITCAIRN";
	79		break;
	80		case VERDE:
	81		chip_name = "VERDE";
	82		break;
	83		}
	84
	85		pfp_req_sz = PFP_DWS * 4;
	86		me_req_sz = ME_DWS * 4;
	87		ce_req_sz = CE_DWS * 4;
	88		rlc_req_sz = RLC_DWS * 4;
	89		mc_req_sz = MC_DWS * 4;
	90
	91		dev_info(&dev->dev, "loading %s ucode\n", chip_name);
	92
	93		dd = pci_get_drvdata(dev);
	94
	95		dd->ucode.pfp = NULL;
	96		dd->ucode.me = NULL;
	97		dd->ucode.ce = NULL;
	98		dd->ucode.rlc = NULL;
	99		dd->ucode.mc = NULL;
	100
	101		snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
	102		err = request_firmware(&dd->ucode.pfp, fw_name, &dev->dev);
	103		if (err) {
	104		dev_err(&dev->dev, "unable to load pfp ucode:%s\n", fw_name);
	105		goto out;
	106		}
	107		if (dd->ucode.pfp->size != pfp_req_sz) {
	108		dev_err(&dev->dev, "bogus length %zu in pfp firmware \"%s\"\n",
	109		dd->ucode.pfp->size, fw_name);
	110		err = -EINVAL;
	111		goto out;
	112		}
	113
	114		snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
	115		err = request_firmware(&dd->ucode.me, fw_name, &dev->dev);
	116		if (err) {
	117		dev_err(&dev->dev, "unable to load me ucode:%s\n", fw_name);
	118		goto out;
	119		}
	120		if (dd->ucode.me->size != me_req_sz) {
	121		dev_err(&dev->dev, "bogus length %zu in me firmware \"%s\"\n",
	122		dd->ucode.me->size, fw_name);
	123		err = -EINVAL;
	124		goto out;
	125		}
	126
	127		snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
	128		err = request_firmware(&dd->ucode.ce, fw_name, &dev->dev);
	129		if (err) {
	130		dev_err(&dev->dev, "unable to load ce ucode:%s\n", fw_name);
	131		goto out;
	132		}
	133		if (dd->ucode.ce->size != ce_req_sz) {
	134		dev_err(&dev->dev, "bogus length %zu in ce firmware \"%s\"\n",
	135		dd->ucode.ce->size, fw_name);
	136		err = -EINVAL;
	137		goto out;
	138		}
	139
	140		snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
	141		err = request_firmware(&dd->ucode.rlc, fw_name, &dev->dev);
	142		if (err) {
	143		dev_err(&dev->dev, "unable to load rlc ucode:%s\n", fw_name);
	144		goto out;
	145		}
	146		if (dd->ucode.rlc->size != rlc_req_sz) {
	147		dev_err(&dev->dev, "bogus length %zu in rlc firmware \"%s\"\n",
	148		dd->ucode.rlc->size, fw_name);
	149		err = -EINVAL;
	150		}
	151
	152		snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
	153		err = request_firmware(&dd->ucode.mc, fw_name, &dev->dev);
	154		if (err) {
	155		dev_err(&dev->dev, "unable to load mc ucode:%s\n", fw_name);
	156		goto out;
	157		}
	158		if (dd->ucode.rlc->size != mc_req_sz) {
	159		dev_err(&dev->dev, "bogus length %zu in mc firmware \"%s\"\n",
	160		dd->ucode.mc->size, fw_name);
	161		err = -EINVAL;
	162		}
	163
	164		out:
	165		if (err) {
	166		release_firmware(dd->ucode.pfp);
	167		dd->ucode.pfp = NULL;
	168		release_firmware(dd->ucode.me);
	169		dd->ucode.me = NULL;
	170		release_firmware(dd->ucode.ce);
	171		dd->ucode.ce = NULL;
	172		release_firmware(dd->ucode.rlc);
	173		dd->ucode.rlc = NULL;
	174		release_firmware(dd->ucode.mc);
	175		dd->ucode.mc = NULL;
	176		}
	177		return err;
	178		}
	179
	180		void ucode_rlc_program(struct pci_dev *dev)
	181		{
	182		u32 i;
	183		const __be32 *fw_data;
	184		struct dev_drv_data *dd;
	185
	186		dd = pci_get_drvdata(dev);
	187
	188		wr32(dev, 0, RLC_CTL);
	189
	190		wr32(dev, 0, RLC_HB_BASE);
	191		wr32(dev, 0, RLC_HB_CTL);
	192		wr32(dev, 0, RLC_HB_RPTR);
	193		wr32(dev, 0, RLC_HB_WPTR);
	194		wr32(dev, 0, RLC_HB_WPTR_LSB_ADDR);
	195		wr32(dev, 0, RLC_HB_WPTR_MSB_ADDR);
	196		wr32(dev, 0, RLC_MC_CTL);
	197		wr32(dev, 0, RLC_UCODE_CTL);
	198
	199		fw_data = (const __be32 *)dd->ucode.rlc->data;
	200		for (i = 0; i < RLC_DWS; ++i) {
	201		wr32(dev, i, RLC_UCODE_ADDR);
	202		wr32(dev, be32_to_cpup(fw_data++), RLC_UCODE_DATA);
	203		}
	204		wr32(dev, 0, RLC_UCODE_ADDR);
	205
	206		wr32(dev, RLC_ENA, RLC_CTL);
	207		}
	208
	209		void ucode_cp_program(struct pci_dev *dev)
	210		{
	211		struct dev_drv_data *dd;
	212		u32 cp_rb_ctl;
	213		const __be32 *fw_data;
	214		int i;
	215
	216		dd = pci_get_drvdata(dev);
	217
	218		/* XXX: rb size values for ucode programming */
	219		cp_rb_ctl = RB_NO_UPDATE | SET(RB_BLK_LOG2_QWS, 15)
	220		| SET(RB_BUF_LOG2_QWS, 3);
	221		#ifdef __BIG_ENDIAN
	222		cp_rb_ctl |= BUF_SWAP_32BIT;
	223		#endif
	224		wr32(dev, cp_rb_ctl, CP_RB_CTL);
	225
	226		fw_data = (const __be32 *)dd->ucode.pfp->data;
	227		wr32(dev, 0,CP_PFP_UCODE_ADDR);
	228		for (i = 0; i < PFP_DWS; ++i)
	229		wr32(dev, be32_to_cpup(fw_data++), CP_PFP_UCODE_DATA);
	230		wr32(dev, 0, CP_PFP_UCODE_ADDR);
	231
	232		fw_data = (const __be32 *)dd->ucode.me->data;
	233		wr32(dev, 0, CP_ME_RAM_WADDR);
	234		for (i = 0; i < ME_DWS; ++i)
	235		wr32(dev, be32_to_cpup(fw_data++), CP_ME_RAM_DATA);
	236		wr32(dev, 0, CP_PFP_UCODE_ADDR);
	237		wr32(dev, 0, CP_ME_RAM_WADDR);
	238		wr32(dev, 0, CP_ME_RAM_RADDR);
	239		}
	240
	241		#define TAHITI_IO_MC_REGS_SZ 36
	242
	243		static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SZ][2] = {
	244		{0x0000006f, 0x03044000},
	245		{0x00000070, 0x0480c018},
	246		{0x00000071, 0x00000040},
	247		{0x00000072, 0x01000000},
	248		{0x00000074, 0x000000ff},
	249		{0x00000075, 0x00143400},
	250		{0x00000076, 0x08ec0800},
	251		{0x00000077, 0x040000cc},
	252		{0x00000079, 0x00000000},
	253		{0x0000007a, 0x21000409},
	254		{0x0000007c, 0x00000000},
	255		{0x0000007d, 0xe8000000},
	256		{0x0000007e, 0x044408a8},
	257		{0x0000007f, 0x00000003},
	258		{0x00000080, 0x00000000},
	259		{0x00000081, 0x01000000},
	260		{0x00000082, 0x02000000},
	261		{0x00000083, 0x00000000},
	262		{0x00000084, 0xe3f3e4f4},
	263		{0x00000085, 0x00052024},
	264		{0x00000087, 0x00000000},
	265		{0x00000088, 0x66036603},
	266		{0x00000089, 0x01000000},
	267		{0x0000008b, 0x1c0a0000},
	268		{0x0000008c, 0xff010000},
	269		{0x0000008e, 0xffffefff},
	270		{0x0000008f, 0xfff3efff},
	271		{0x00000090, 0xfff3efbf},
	272		{0x00000094, 0x00101101},
	273		{0x00000095, 0x00000fff},
	274		{0x00000096, 0x00116fff},
	275		{0x00000097, 0x60010000},
	276		{0x00000098, 0x10010000},
	277		{0x00000099, 0x00006000},
	278		{0x0000009a, 0x00001000},
	279		{0x0000009f, 0x00a77400}
	280		};
	281
	282		static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SZ][2] = {
	283		{0x0000006f, 0x03044000},
	284		{0x00000070, 0x0480c018},
	285		{0x00000071, 0x00000040},
	286		{0x00000072, 0x01000000},
	287		{0x00000074, 0x000000ff},
	288		{0x00000075, 0x00143400},
	289		{0x00000076, 0x08ec0800},
	290		{0x00000077, 0x040000cc},
	291		{0x00000079, 0x00000000},
	292		{0x0000007a, 0x21000409},
	293		{0x0000007c, 0x00000000},
	294		{0x0000007d, 0xe8000000},
	295		{0x0000007e, 0x044408a8},
	296		{0x0000007f, 0x00000003},
	297		{0x00000080, 0x00000000},
	298		{0x00000081, 0x01000000},
	299		{0x00000082, 0x02000000},
	300		{0x00000083, 0x00000000},
	301		{0x00000084, 0xe3f3e4f4},
	302		{0x00000085, 0x00052024},
	303		{0x00000087, 0x00000000},
	304		{0x00000088, 0x66036603},
	305		{0x00000089, 0x01000000},
	306		{0x0000008b, 0x1c0a0000},
	307		{0x0000008c, 0xff010000},
	308		{0x0000008e, 0xffffefff},
	309		{0x0000008f, 0xfff3efff},
	310		{0x00000090, 0xfff3efbf},
	311		{0x00000094, 0x00101101},
	312		{0x00000095, 0x00000fff},
	313		{0x00000096, 0x00116fff},
	314		{0x00000097, 0x60010000},
	315		{0x00000098, 0x10010000},
	316		{0x00000099, 0x00006000},
	317		{0x0000009a, 0x00001000},
	318		{0x0000009f, 0x00a47400}
	319		};
	320
	321		static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SZ][2] = {
	322		{0x0000006f, 0x03044000},
	323		{0x00000070, 0x0480c018},
	324		{0x00000071, 0x00000040},
	325		{0x00000072, 0x01000000},
	326		{0x00000074, 0x000000ff},
	327		{0x00000075, 0x00143400},
	328		{0x00000076, 0x08ec0800},
	329		{0x00000077, 0x040000cc},
	330		{0x00000079, 0x00000000},
	331		{0x0000007a, 0x21000409},
	332		{0x0000007c, 0x00000000},
	333		{0x0000007d, 0xe8000000},
	334		{0x0000007e, 0x044408a8},
	335		{0x0000007f, 0x00000003},
	336		{0x00000080, 0x00000000},
	337		{0x00000081, 0x01000000},
	338		{0x00000082, 0x02000000},
	339		{0x00000083, 0x00000000},
	340		{0x00000084, 0xe3f3e4f4},
	341		{0x00000085, 0x00052024},
	342		{0x00000087, 0x00000000},
	343		{0x00000088, 0x66036603},
	344		{0x00000089, 0x01000000},
	345		{0x0000008b, 0x1c0a0000},
	346		{0x0000008c, 0xff010000},
	347		{0x0000008e, 0xffffefff},
	348		{0x0000008f, 0xfff3efff},
	349		{0x00000090, 0xfff3efbf},
	350		{0x00000094, 0x00101101},
	351		{0x00000095, 0x00000fff},
	352		{0x00000096, 0x00116fff},
	353		{0x00000097, 0x60010000},
	354		{0x00000098, 0x10010000},
	355		{0x00000099, 0x00006000},
	356		{0x0000009a, 0x00001000},
	357		{0x0000009f, 0x00a37400}
	358		};
	359
	360		void ucode_mc_program(struct pci_dev *dev)
	361		{
	362		const __be32 *fw_data;
	363		u32 running;
	364		u32 blackout;
	365		u32 *io_mc_regs;
	366		unsigned i;
	367		unsigned ucode_dws;
	368		unsigned regs_sz;
	369		struct dev_drv_data *dd;
	370
	371		dd = pci_get_drvdata(dev);
	372
	373		switch (dd->family) {
	374		case CHIP_TAHITI:
	375		io_mc_regs = (u32 *)&tahiti_io_mc_regs[0][0];
	376		regs_sz = ARRAY_SIZE(tahiti_io_mc_regs) / 2;
	377		ucode_dws = MC_DWS;
	378		break;
	379		case CHIP_PITCAIRN:
	380		io_mc_regs = (u32 *)&pitcairn_io_mc_regs[0][0];
	381		regs_sz = ARRAY_SIZE(pitcairn_io_mc_regs) / 2;
	382		ucode_dws = MC_DWS;
	383		break;
	384		case CHIP_VERDE:
	385		io_mc_regs = (u32 *)&verde_io_mc_regs[0][0];
	386		regs_sz = ARRAY_SIZE(verde_io_mc_regs) / 2;
	387		ucode_dws = MC_DWS;
	388		break;
	389		}
	390
	391		running = rr32(dev, MC_SEQ_SUP_CTL) & RUN_MASK;
	392		blackout = 0;
	393
	394		if (running == 0) {
	395		/* this is a reminder */
	396		if (running) {
	397		blackout = rr32(dev, MC_SHARED_BLACKOUT_CTL);
	398		wr32(dev, blackout | 1, MC_SHARED_BLACKOUT_CTL);
	399		}
	400
	401		/* reset the engine and set to writable */
	402		wr32(dev, 0x00000008, MC_SEQ_SUP_CTL);
	403		wr32(dev, 0x00000010, MC_SEQ_SUP_CTL);
	404
	405		/* load mc io regs */
	406		for (i = 0; i < regs_sz; ++i) {
	407		wr32(dev, io_mc_regs[i * 2], MC_SEQ_IO_DBG_IDX);
	408		wr32(dev, io_mc_regs[i * 2 + 1], MC_SEQ_IO_DBG_DATA);
	409		}
	410		/* load the mc ucode */
	411		fw_data = (const __be32 *)dd->ucode.mc->data;
	412		for (i = 0; i < ucode_dws; ++i)
	413		wr32(dev, be32_to_cpup(fw_data++), MC_SEQ_SUP_PGM);
	414
	415		/* put the engine back into the active state */
	416		wr32(dev, 0x00000008, MC_SEQ_SUP_CTL);
	417		wr32(dev, 0x00000004, MC_SEQ_SUP_CTL);
	418		wr32(dev, 0x00000001, MC_SEQ_SUP_CTL);
	419
	420		/* wait for memory training to complete (100 ms timeout) */
	421		for (i = 0; i < 100000; ++i) {/* memory pattern D0 */
	422		if (rr32(dev, MC_SEQ_TRAIN_WAKEUP_CTL) & TRAIN_DONE_D0)
	423		break;
	424		udelay(1);
	425		}
	426		for (i = 0; i < 10000; ++i) {/* memory pattern D1 */
	427		if (rr32(dev, MC_SEQ_TRAIN_WAKEUP_CTL) & TRAIN_DONE_D1)
	428		break;
	429		udelay(1);
	430		}
	431
	432		/* this is a reminder */
	433		if (running)
	434		wr32(dev, blackout, MC_SHARED_BLACKOUT_CTL);
	435		}
	436		}

File drivers/gpu/alga/amd/si/ucode.h added (mode: 100644) (index 0000000..a7e5d10)
	1		#ifndef _UCODE_H
	2		#define _UCODE_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		struct ucode
	9		{
	10		const struct firmware *pfp;
	11		const struct firmware *me;
	12		const struct firmware *ce;
	13		const struct firmware *rlc;
	14		const struct firmware *mc;
	15		};
	16
	17		int ucode_load(struct pci_dev *dev);
	18		void ucode_release(struct pci_dev *dev);
	19		void ucode_rlc_program(struct pci_dev *dev);
	20		void ucode_cp_program(struct pci_dev *dev);
	21		void ucode_mc_program(struct pci_dev *dev);
	22		#endif /* _UCODE_H */

File drivers/gpu/alga/helpers/ABBREVIATIONS added (mode: 100644) (index 0000000..49a5a6a)
	1		bpp bits per pixels
	2		clk clock
	3		dmt(s) detailed mode timing(s)
	4		dtd(s) detailed timing descriptor(s)
	5		h horizontal
	6		h_bl horizontal blanking
	7		h_so horizontal sync offset
	8		h_spw horizontal sync pulse width
	9		h_b horizontal border
	10		h_sp horizontal sync polarity
	11		mng manager
	12		r refresh rate
	13		rng range
	14		v vertical
	15		v_bl vertical blanking
	16		v_so vertical sync offset
	17		v_spw vertical sync pulse width
	18		v_b vertical border
	19		v_sp vertical polarity

File drivers/gpu/alga/helpers/Makefile added (mode: 100644) (index 0000000..984b907)
	1		alga_helpers-y := mod.o edid.o dp.o rng_mng.o
	2		obj-$(CONFIG_ALGA)+= alga_helpers.o

File drivers/gpu/alga/helpers/dp.c added (mode: 100644) (index 0000000..1a47cd5)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/slab.h>
	8
	9		#include <alga/alga.h>
	10		#include <alga/timing.h>
	11		void alga_dp_safe_timing(struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	12		{
	13		/* init the array, namely one mode and one terminator */
	14		memset(ts, 0, sizeof(*ts));
	15
	16		/* timings from the VESA safe mode standard */
	17		(*ts)[0].h = 640;
	18		(*ts)[0].h_bl = 160;
	19		(*ts)[0].h_so = 656;
	20		(*ts)[0].h_spw = 96;
	21		(*ts)[0].h_sp = 1;
	22
	23		(*ts)[0].v = 480;
	24		(*ts)[0].v_bl = 45;
	25		(*ts)[0].v_so = 490;
	26		(*ts)[0].v_spw = 2;
	27		(*ts)[0].v_sp = 1;
	28
	29		(*ts)[0].pixel_clk = 25175;
	30		}
	31		EXPORT_SYMBOL_GPL(alga_dp_safe_timing);

File drivers/gpu/alga/helpers/edid.c added (mode: 100644) (index 0000000..b964390)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		#include <linux/device.h>
	8		#include <linux/i2c.h>
	9		#include <linux/slab.h>
	10		#include <asm/unaligned.h>
	11		#include <asm/uaccess.h>
	12
	13		#include <alga/alga.h>
	14		#include <alga/timing.h>
	15		#include <alga/edid.h>
	16
	17		#include "vesa_dmts.h"
	18
	19		/* NOTE: do not even try to understand the code without the EDID specs */
	20
	21		#define I2C_FETCH_RETRIES 4
	22
	23		static bool has_valid_hdr(void *edid)
	24		{
	25		static u8 valid_hdr[8] = {
	26		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
	27		if (memcmp(edid, valid_hdr, sizeof(valid_hdr)) != 0)
	28		return false;
	29		return true;
	30		}
	31
	32		static bool is_v1_4(void *edid)
	33		{
	34		u8 version;
	35		u8 revision;
	36
	37		version = *(u8*)(edid + 0x12);
	38		if (version != 1)
	39		return false;
	40
	41		revision = *(u8*)(edid + 0x13);
	42		if (revision != 4)
	43		return false;
	44		return true;
	45		}
	46
	47		static void dtd_collect(void *dtd, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	48		{
	49		struct alga_timing *t;
	50		u8 *p;
	51		unsigned tmp;
	52		unsigned i;
	53
	54		/* get to the first available slot of timings */
	55		for (i = 0; i < ALGA_TIMINGS_MAX; ++i)
	56		if ((*ts)[i].pixel_clk == 0)
	57		break;
	58
	59		if (i < ALGA_TIMINGS_MAX)
	60		t = &(*ts)[i];
	61		else
	62		return; /* no room */
	63
	64		p = (u8*)dtd;
	65
	66		if ((p[17] & 0x80) != 0) /* do not support interlaced modes */
	67		return;
	68
	69		t->pixel_clk = get_unaligned_le16(dtd) * 10;
	70
	71		tmp = p[2];
	72		tmp |= (p[4] & 0xf0) << 4;
	73		t->h = tmp;
	74
	75		tmp = p[3];
	76		tmp |= (p[4] & 0x0f) << 8;
	77		t->h_bl = tmp;
	78
	79		tmp = p[5];
	80		tmp |= (p[7] & 0xf0) << 4;
	81		t->v = tmp;
	82
	83		tmp = p[6];
	84		tmp |= (p[7] & 0x0f) << 8;
	85		t->v_bl = tmp;
	86
	87		/* tmp is front porch from blanking */
	88		tmp = p[8];
	89		tmp |= (p[11] & 0xc0) << 2;
	90		t->h_so = t->h + tmp;
	91
	92		tmp = p[9];
	93		tmp |= (p[11] & 0x30) << 4;
	94		t->h_spw = tmp;
	95
	96		/* tmp is front porch from blanking */
	97		tmp = (p[10] & 0xf0) >> 4;
	98		tmp |= (p[11] & 0x0c) << 2;
	99		t->v_so = t->v + tmp;
	100
	101		tmp = p[10] & 0x0f;
	102		tmp |= (p[11] & 0x03) << 4;
	103		t->v_spw = tmp;
	104
	105		/* only digital separated sync supported */
	106		t->h_sp = 0;
	107		t->v_sp = 0;
	108		if ((p[17] & 0x0e) == 0x0c)
	109		t->v_sp = 1;
	110		if ((p[17] & 0x09) == 0x08)
	111		t->h_sp = 1;
	112		}
	113
	114		static void dtds_collect(void *edid, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	115		{
	116		unsigned i;
	117		void *dtd;
	118
	119		for (i = 0, dtd = edid + 0x36; i < 4; ++i, dtd += 18) {
	120		u16 pixel_clk;
	121
	122		pixel_clk = get_unaligned_le16(dtd);
	123		if (pixel_clk != 0)
	124		dtd_collect(dtd, ts);
	125		}
	126		}
	127
	128		static void timings(void *edid, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	129		{
	130		dtds_collect(edid, ts);
	131		/* TODO: collect the timings defined in other ways */
	132		}
	133
	134		int alga_edid_timings(struct device *dev, void *edid,
	135		struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
	136		{
	137		if (!is_v1_4(edid)) {
	138		dev_err(dev, "alga: edid version not supported\n");
	139		return -ALGA_ERR;
	140		}
	141
	142		memset(ts, 0, sizeof(*ts));
	143		timings(edid, ts);
	144		return 0;
	145		}
	146		EXPORT_SYMBOL_GPL(alga_edid_timings);
	147
	148		int alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a, void **edid)
	149		{
	150		u8 out;
	151		int r;
	152		int retry;
	153		struct i2c_msg msgs[] = {
	154		{
	155		.addr = 0x50,
	156		.flags = 0,
	157		.len = 1,
	158		.buf = &out
	159		},
	160		{
	161		.addr = 0x50,
	162		.flags = I2C_M_RD,
	163		.len = EDID_BLK_SZ,
	164		.buf = NULL
	165		}
	166		};
	167
	168		*edid = kzalloc(EDID_BLK_SZ, GFP_KERNEL);
	169		if (*edid == NULL) {
	170		dev_err(dev, "alga: unable to allocate memory for EDID\n");
	171		return -ALGA_ERR;
	172		}
	173
	174		msgs[1].buf = *edid;
	175		out = 0; /* block 0 */
	176
	177		for (retry = 0; retry < I2C_FETCH_RETRIES; ++retry) {
	178		r = i2c_transfer(a, msgs, 2);
	179		if (r == 2)
	180		break;
	181		}
	182		if (r != 2) {
	183		dev_err(dev, "alga: unable to fetch the edid over i2c\n");
	184		r = -ALGA_ERR;
	185		goto free_edid;
	186		}
	187
	188		if (!has_valid_hdr(*edid)) {
	189		dev_err(dev, "alga: invalid edid header\n");
	190		r = -ALGA_ERR;
	191		goto free_edid;
	192		}
	193		return 0;
	194
	195		free_edid:
	196		kfree(*edid);
	197		*edid = NULL;
	198		return r;
	199		}
	200		EXPORT_SYMBOL_GPL(alga_i2c_edid_fetch);
	201
	202		int alga_edid_bpc(struct device *dev, void *edid)
	203		{
	204		u8 def;
	205
	206		def = *(u8*)(edid + 0x14);
	207
	208		if ((def & BIT(7)) == 0) {
	209		dev_warn(dev, "alga: edid video input definition is not "
	210		"digital\n");
	211		return 0;
	212		}
	213
	214		def &= 0x70;
	215
	216		switch (def) {
	217		case 0x10:
	218		return 6;
	219		case 0x20:
	220		return 8;
	221		case 0x30:
	222		return 10;
	223		case 0x40:
	224		return 12;
	225		case 0x50:
	226		return 14;
	227		case 0x60:
	228		return 16;
	229		case 0x70:
	230		case 0x00:
	231		default:
	232		return 0;
	233		}
	234		}
	235		EXPORT_SYMBOL_GPL(alga_edid_bpc);

File drivers/gpu/alga/helpers/mod.c added (mode: 100644) (index 0000000..d5b9a28)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6		#include <linux/module.h>
	7		static int __init init(void)
	8		{
	9		return 0;
	10		}
	11
	12		static void __exit cleanup(void)
	13		{
	14		}
	15
	16		module_init(init);
	17		module_exit(cleanup);
	18
	19		MODULE_AUTHOR("Sylvain Bertrand <digital.ragnarok@gmail.com>");
	20		MODULE_DESCRIPTION("ALGA helpers");
	21		MODULE_LICENSE("GPL");

File drivers/gpu/alga/helpers/rng_mng.c added (mode: 100644) (index 0000000..9e9694d)
	1		/*
	2		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	3		Protected by GNU Affero GPL v3 with some exceptions.
	4		See README at root of alga tree.
	5		*/
	6
	7		/* Very simple range manager */
	8		#include <linux/module.h>
	9		#include <linux/list.h>
	10		#include <linux/slab.h>
	11
	12		#include <alga/alga.h>
	13		#include <alga/rng_mng.h>
	14
	15		static bool have_room_align(u64 *s_aligned, struct rng *mng, struct rng *r,
	16		struct rng *next_r, u64 sz, u64 align)
	17		{
	18		u64 gap_start;
	19		u64 gap_end;
	20
	21		gap_start = r->s + r->sz;
	22
	23		if (&next_r->n == &mng->n)
	24		gap_end = mng->s + mng->sz - 1; /* r is the list tail */
	25		else
	26		gap_end = next_r->s - 1;
	27
	28		*s_aligned = rng_align(gap_start, align);
	29
	30		if ((*s_aligned + sz - 1) <= gap_end)
	31		return true;
	32		return false;
	33		}
	34
	35		static bool first_range(u64 *s_aligned, struct rng *mng, u64 sz, u64 align)
	36		{
	37		*s_aligned = rng_align(mng->s, align);
	38
	39		if ((*s_aligned + sz - 1) <= (mng->s + mng->sz - 1))
	40		return true;
	41		return false;
	42		}
	43
	44		void rng_mng_init(struct rng *mng, u64 s, u64 sz)
	45		{
	46		mng->s = s;
	47		mng->sz = sz;
	48		INIT_LIST_HEAD(&mng->n);
	49		}
	50		EXPORT_SYMBOL_GPL(rng_mng_init);
	51
	52		void rng_mng_destroy(struct rng *mng)
	53		{
	54		struct rng *pos;
	55		struct rng *n;
	56
	57		list_for_each_entry_safe(pos, n, &mng->n, n) {
	58		list_del(&pos->n);
	59		kfree(pos);
	60		}
	61		}
	62		EXPORT_SYMBOL_GPL(rng_mng_destroy);
	63
	64		int rng_alloc_align(u64 *s_aligned, struct rng *mng, u64 sz, u64 align)
	65		{
	66		struct rng *new_r;
	67		struct rng *pos;
	68
	69		if ((s_aligned == NULL) || (mng == NULL) || (align == 0))
	70		return -ALGA_ERR;
	71
	72		if (sz % align != 0)
	73		return -ALGA_ERR;
	74
	75		new_r = kzalloc(GFP_KERNEL, sizeof(*new_r));
	76		if (new_r == NULL)
	77		return -ALGA_ERR;
	78		INIT_LIST_HEAD(&new_r->n);
	79
	80		if (list_empty(&mng->n)) {
	81		if (!first_range(s_aligned, mng, sz, align)) {
	82		kfree(new_r);
	83		return -ALGA_ERR;
	84		}
	85
	86		new_r->s = *s_aligned;
	87		new_r->sz = sz;
	88		list_add(&new_r->n, &mng->n);
	89		return 0;
	90		}
	91
	92		/* look for aligned room */
	93		list_for_each_entry(pos, &mng->n, n) {
	94		struct rng *next;
	95
	96		next = list_entry(pos->n.next, struct rng, n);
	97		if (have_room_align(&new_r->s, mng, pos, next, sz, align)) {
	98		__list_add(&new_r->n, &pos->n, &next->n);
	99		new_r->sz = sz;
	100		*s_aligned = new_r->s;
	101		return 0;
	102		}
	103		}
	104		kfree(new_r);
	105		return -ALGA_ERR;
	106		}
	107		EXPORT_SYMBOL_GPL(rng_alloc_align);
	108
	109		void rng_free(struct rng *mng, u64 s)
	110		{
	111		struct rng *pos;
	112
	113		list_for_each_entry(pos, &mng->n, n) {
	114		if (pos->s == s) {
	115		list_del(&pos->n);
	116		kfree(pos);
	117		break;
	118		}
	119		}
	120		}
	121		EXPORT_SYMBOL_GPL(rng_free);

File drivers/gpu/alga/helpers/vesa_dmts.h added (mode: 100644) (index 0000000..62b83b7)
	1		#ifndef _ALGA_HELPERS_VESA_DMTS_H
	2		#define _ALGA_HELPERS_VESA_DMTS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define VESA_DMTS_COUNT 0x51
	9		struct dmt {
	10		/* pixels */
	11		unsigned h;
	12		unsigned h_bl;
	13		unsigned h_so;
	14		unsigned h_spw;
	15		unsigned h_b;
	16		unsigned h_sp; /* 0: high/positive, 1: low/negative */
	17
	18		/* lines */
	19		unsigned v;
	20		unsigned v_bl;
	21		unsigned v_so;
	22		unsigned v_spw;
	23		unsigned v_b;
	24		unsigned v_sp; /* 0: high/positive, 1: low/negative */
	25
	26		unsigned pixel_clk; /* kHz */
	27		unsigned r; /* Hz for timing name only */
	28
	29		bool interlaced;
	30		bool reduced_blanking;
	31		};
	32
	33		static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
	34		{
	35		.h = 0,
	36		.h_bl = 0,
	37		.h_so = 0,
	38		.h_spw = 0,
	39		.h_b = 0,
	40		.h_sp = 0,
	41		.v = 0,
	42		.v_bl = 0,
	43		.v_so = 0,
	44		.v_spw = 0,
	45		.v_b = 0,
	46		.v_sp = 0,
	47		.pixel_clk = 0,
	48		.r = 0,
	49		.interlaced = false,
	50		.reduced_blanking = false
	51		},
	52		{/* DMT ID 0x01 */
	53		.h = 640,
	54		.h_bl = 192,
	55		.h_so = 672,
	56		.h_spw = 64,
	57		.h_b = 0,
	58		.h_sp = 0,
	59		.v = 350,
	60		.v_bl = 95,
	61		.v_so = 382,
	62		.v_spw = 3,
	63		.v_b = 0,
	64		.v_sp = 1,
	65		.pixel_clk = 31500,
	66		.r = 85,
	67		.interlaced = false,
	68		.reduced_blanking = false
	69		},
	70		{/* DMT ID 0x02 */
	71		.h = 640,
	72		.h_bl = 192,
	73		.h_so = 672,
	74		.h_spw = 64,
	75		.h_b = 0,
	76		.h_sp = 1,
	77		.v = 400,
	78		.v_bl = 45,
	79		.v_so = 401,
	80		.v_spw = 3,
	81		.v_b = 0,
	82		.v_sp = 0,
	83		.pixel_clk = 31500,
	84		.r = 85,
	85		.interlaced = false,
	86		.reduced_blanking = false
	87		},
	88		{/* DMT ID 0x03 */
	89		.h = 720,
	90		.h_bl = 216,
	91		.h_so = 756,
	92		.h_spw = 72,
	93		.h_b = 0,
	94		.h_sp = 1,
	95		.v = 400,
	96		.v_bl = 46,
	97		.v_so = 401,
	98		.v_spw = 3,
	99		.v_b = 0,
	100		.v_sp = 0,
	101		.pixel_clk = 35500,
	102		.r = 85,
	103		.interlaced = false,
	104		.reduced_blanking = false
	105		},
	106		{/* DMT ID 0x04 */
	107		.h = 640,
	108		.h_bl = 144,
	109		.h_so = 656,
	110		.h_spw = 96,
	111		.h_b = 8,
	112		.h_sp = 1,
	113		.v = 480,
	114		.v_bl = 29,
	115		.v_so = 490,
	116		.v_spw = 2,
	117		.v_b = 8,
	118		.v_sp = 1,
	119		.pixel_clk = 25175,
	120		.r = 60,
	121		.interlaced = false,
	122		.reduced_blanking = false
	123		},
	124		{/* DMT ID 0x05 */
	125		.h = 640,
	126		.h_bl = 176,
	127		.h_so = 664,
	128		.h_spw = 40,
	129		.h_b = 8,
	130		.h_sp = 1,
	131		.v = 480,
	132		.v_bl = 24,
	133		.v_so = 489,
	134		.v_spw = 3,
	135		.v_b = 8,
	136		.v_sp = 1,
	137		.pixel_clk = 31500,
	138		.r = 72,
	139		.interlaced = false,
	140		.reduced_blanking = false
	141		},
	142		{/* DMT ID 0x06 */
	143		.h = 640,
	144		.h_bl = 200,
	145		.h_so = 656,
	146		.h_spw = 64,
	147		.h_b = 0,
	148		.h_sp = 1,
	149		.v = 480,
	150		.v_bl = 20,
	151		.v_so = 481,
	152		.v_spw = 3,
	153		.v_b = 0,
	154		.v_sp = 1,
	155		.pixel_clk = 31500,
	156		.r = 75,
	157		.interlaced = false,
	158		.reduced_blanking = false
	159		},
	160		{/* DMT ID 0x07 */
	161		.h = 640,
	162		.h_bl = 192,
	163		.h_so = 696,
	164		.h_spw = 56,
	165		.h_b = 0,
	166		.h_sp = 1,
	167		.v = 480,
	168		.v_bl = 29,
	169		.v_so = 481,
	170		.v_spw = 3,
	171		.v_b = 0,
	172		.v_sp = 1,
	173		.pixel_clk = 36000,
	174		.r = 85,
	175		.interlaced = false,
	176		.reduced_blanking = false
	177		},
	178		{/* DMT ID 0x08 */
	179		.h = 800,
	180		.h_bl = 224,
	181		.h_so = 824,
	182		.h_spw = 72,
	183		.h_b = 0,
	184		.h_sp = 0,
	185		.v = 600,
	186		.v_bl = 25,
	187		.v_so = 601,
	188		.v_spw = 2,
	189		.v_b = 0,
	190		.v_sp = 0,
	191		.pixel_clk = 36000,
	192		.r = 56,
	193		.interlaced = false,
	194		.reduced_blanking = false
	195		},
	196		{/* DMT ID 0x09 */
	197		.h = 800,
	198		.h_bl = 256,
	199		.h_so = 840,
	200		.h_spw = 128,
	201		.h_b = 0,
	202		.h_sp = 0,
	203		.v = 600,
	204		.v_bl = 28,
	205		.v_so = 601,
	206		.v_spw = 4,
	207		.v_b = 0,
	208		.v_sp = 0,
	209		.pixel_clk = 40000,
	210		.r = 60,
	211		.interlaced = false,
	212		.reduced_blanking = false
	213		},
	214		{/* DMT ID 0x0a */
	215		.h = 800,
	216		.h_bl = 240,
	217		.h_so = 856,
	218		.h_spw = 120,
	219		.h_b = 0,
	220		.h_sp = 0,
	221		.v = 600,
	222		.v_bl = 66,
	223		.v_so = 637,
	224		.v_spw = 6,
	225		.v_b = 0,
	226		.v_sp = 0,
	227		.pixel_clk = 50000,
	228		.r = 72,
	229		.interlaced = false,
	230		.reduced_blanking = false
	231		},
	232		{/* DMT ID 0x0b */
	233		.h = 800,
	234		.h_bl = 256,
	235		.h_so = 816,
	236		.h_spw = 80,
	237		.h_b = 0,
	238		.h_sp = 0,
	239		.v = 600,
	240		.v_bl = 25,
	241		.v_so = 601,
	242		.v_spw = 3,
	243		.v_b = 0,
	244		.v_sp = 0,
	245		.pixel_clk = 49500,
	246		.r = 75,
	247		.interlaced = false,
	248		.reduced_blanking = false
	249		},
	250		{/* DMT ID 0x0c */
	251		.h = 800,
	252		.h_bl = 248,
	253		.h_so = 832,
	254		.h_spw = 64,
	255		.h_b = 0,
	256		.h_sp = 0,
	257		.v = 600,
	258		.v_bl = 31,
	259		.v_so = 601,
	260		.v_spw = 3,
	261		.v_b = 0,
	262		.v_sp = 0,
	263		.pixel_clk = 56250,
	264		.r = 85,
	265		.interlaced = false,
	266		.reduced_blanking = false
	267		},
	268		{/* DMT ID 0x0d */
	269		.h = 800,
	270		.h_bl = 160,
	271		.h_so = 848,
	272		.h_spw = 32,
	273		.h_b = 0,
	274		.h_sp = 0,
	275		.v = 600,
	276		.v_bl = 36,
	277		.v_so = 603,
	278		.v_spw = 4,
	279		.v_b = 0,
	280		.v_sp = 1,
	281		.pixel_clk = 73250,
	282		.r = 120,
	283		.interlaced = false,
	284		.reduced_blanking = true
	285		},
	286		{/* DMT ID 0x0e */
	287		.h = 848,
	288		.h_bl = 240,
	289		.h_so = 864,
	290		.h_spw = 112,
	291		.h_b = 0,
	292		.h_sp = 0,
	293		.v = 480,
	294		.v_bl = 37,
	295		.v_so = 486,
	296		.v_spw = 8,
	297		.v_b = 0,
	298		.v_sp = 0,
	299		.pixel_clk = 33750,
	300		.r = 60,
	301		.interlaced = false,
	302		.reduced_blanking = false
	303		},
	304		{/* DMT ID 0x0f */
	305		.h = 1024,
	306		.h_bl = 240,
	307		.h_so = 1032,
	308		.h_spw = 176,
	309		.h_b = 0,
	310		.h_sp = 0,
	311		.v = 768,
	312		.v_bl = 24,
	313		.v_so = 768,
	314		.v_spw = 4,
	315		.v_b = 0,
	316		.v_sp = 0,
	317		.pixel_clk = 44900,
	318		.r = 43,
	319		.interlaced = true,
	320		.reduced_blanking = false
	321		},
	322		{/* DMT ID 0x10 */
	323		.h = 1024,
	324		.h_bl = 320,
	325		.h_so = 1048,
	326		.h_spw = 136,
	327		.h_b = 0,
	328		.h_sp = 1,
	329		.v = 768,
	330		.v_bl = 38,
	331		.v_so = 771,
	332		.v_spw = 6,
	333		.v_b = 0,
	334		.v_sp = 1,
	335		.pixel_clk = 65000,
	336		.r = 60,
	337		.interlaced = false,
	338		.reduced_blanking = false
	339		},
	340		{/* DMT ID 0x11 */
	341		.h = 1024,
	342		.h_bl = 304,
	343		.h_so = 1048,
	344		.h_spw = 136,
	345		.h_b = 0,
	346		.h_sp = 1,
	347		.v = 768,
	348		.v_bl = 38,
	349		.v_so = 771,
	350		.v_spw = 6,
	351		.v_b = 0,
	352		.v_sp = 1,
	353		.pixel_clk = 75000,
	354		.r = 70,
	355		.interlaced = false,
	356		.reduced_blanking = false
	357		},
	358		{/* DMT ID 0x12 */
	359		.h = 1024,
	360		.h_bl = 288,
	361		.h_so = 1040,
	362		.h_spw = 96,
	363		.h_b = 0,
	364		.h_sp = 0,
	365		.v = 768,
	366		.v_bl = 32,
	367		.v_so = 769,
	368		.v_spw = 3,
	369		.v_b = 0,
	370		.v_sp = 0,
	371		.pixel_clk = 78750,
	372		.r = 75,
	373		.interlaced = false,
	374		.reduced_blanking = false
	375		},
	376		{/* DMT ID 0x13 */
	377		.h = 1024,
	378		.h_bl = 352,
	379		.h_so = 1072,
	380		.h_spw = 96,
	381		.h_b = 0,
	382		.h_sp = 0,
	383		.v = 768,
	384		.v_bl = 40,
	385		.v_so = 769,
	386		.v_spw = 3,
	387		.v_b = 0,
	388		.v_sp = 0,
	389		.pixel_clk = 94500,
	390		.r = 85,
	391		.interlaced = false,
	392		.reduced_blanking = false
	393		},
	394		{/* DMT ID 0x14 */
	395		.h = 1024,
	396		.h_bl = 160,
	397		.h_so = 1072,
	398		.h_spw = 32,
	399		.h_b = 0,
	400		.h_sp = 0,
	401		.v = 768,
	402		.v_bl = 45,
	403		.v_so = 771,
	404		.v_spw = 4,
	405		.v_b = 0,
	406		.v_sp = 1,
	407		.pixel_clk = 115500,
	408		.r = 120,
	409		.interlaced = false,
	410		.reduced_blanking = true
	411		},
	412		{/* DMT ID 0x15 */
	413		.h = 1152,
	414		.h_bl = 448,
	415		.h_so = 1216,
	416		.h_spw = 128,
	417		.h_b = 0,
	418		.h_sp = 0,
	419		.v = 864,
	420		.v_bl = 36,
	421		.v_so = 865,
	422		.v_spw = 3,
	423		.v_b = 0,
	424		.v_sp = 0,
	425		.pixel_clk = 108000,
	426		.r = 75,
	427		.interlaced = false,
	428		.reduced_blanking = false
	429		},
	430		{/* DMT ID 0x16 */
	431		.h = 1280,
	432		.h_bl = 160,
	433		.h_so = 1328,
	434		.h_spw = 32,
	435		.h_b = 0,
	436		.h_sp = 0,
	437		.v = 768,
	438		.v_bl = 22,
	439		.v_so = 771,
	440		.v_spw = 7,
	441		.v_b = 0,
	442		.v_sp = 1,
	443		.pixel_clk = 68250,
	444		.r = 60,
	445		.interlaced = false,
	446		.reduced_blanking = true
	447		},
	448		{/* DMT ID 0x17 */
	449		.h = 1280,
	450		.h_bl = 384,
	451		.h_so = 1344,
	452		.h_spw = 128,
	453		.h_b = 0,
	454		.h_sp = 1,
	455		.v = 768,
	456		.v_bl = 30,
	457		.v_so = 771,
	458		.v_spw = 7,
	459		.v_b = 0,
	460		.v_sp = 0,
	461		.pixel_clk = 79500,
	462		.r = 60,
	463		.interlaced = false,
	464		.reduced_blanking = true
	465		},
	466		{/* DMT ID 0x18 */
	467		.h = 1280,
	468		.h_bl = 416,
	469		.h_so = 1360,
	470		.h_spw = 128,
	471		.h_b = 0,
	472		.h_sp = 1,
	473		.v = 768,
	474		.v_bl = 37,
	475		.v_so = 771,
	476		.v_spw = 7,
	477		.v_b = 0,
	478		.v_sp = 0,
	479		.pixel_clk = 102250,
	480		.r = 75,
	481		.interlaced = false,
	482		.reduced_blanking = false
	483		},
	484		{/* DMT ID 0x19 */
	485		.h = 1280,
	486		.h_bl = 432,
	487		.h_so = 1360,
	488		.h_spw = 136,
	489		.h_b = 0,
	490		.h_sp = 1,
	491		.v = 768,
	492		.v_bl = 41,
	493		.v_so = 771,
	494		.v_spw = 7,
	495		.v_b = 0,
	496		.v_sp = 0,
	497		.pixel_clk = 117500,
	498		.r = 85,
	499		.interlaced = false,
	500		.reduced_blanking = false
	501		},
	502		{/* DMT ID 0x1a */
	503		.h = 1280,
	504		.h_bl = 160,
	505		.h_so = 1328,
	506		.h_spw = 32,
	507		.h_b = 0,
	508		.h_sp = 0,
	509		.v = 768,
	510		.v_bl = 45,
	511		.v_so = 771,
	512		.v_spw = 7,
	513		.v_b = 0,
	514		.v_sp = 1,
	515		.pixel_clk = 140250,
	516		.r = 120,
	517		.interlaced = false,
	518		.reduced_blanking = true
	519		},
	520		{/* DMT ID 0x1b */
	521		.h = 1280,
	522		.h_bl = 160,
	523		.h_so = 1328,
	524		.h_spw = 32,
	525		.h_b = 0,
	526		.h_sp = 0,
	527		.v = 800,
	528		.v_bl = 23,
	529		.v_so = 803,
	530		.v_spw = 6,
	531		.v_b = 0,
	532		.v_sp = 1,
	533		.pixel_clk = 71000,
	534		.r = 60,
	535		.interlaced = false,
	536		.reduced_blanking = true
	537		},
	538		{/* DMT ID 0x1c */
	539		.h = 1280,
	540		.h_bl = 400,
	541		.h_so = 1352,
	542		.h_spw = 128,
	543		.h_b = 0,
	544		.h_sp = 1,
	545		.v = 800,
	546		.v_bl = 31,
	547		.v_so = 803,
	548		.v_spw = 6,
	549		.v_b = 0,
	550		.v_sp = 0,
	551		.pixel_clk = 83500,
	552		.r = 60,
	553		.interlaced = false,
	554		.reduced_blanking = false
	555		},
	556		{/* DMT ID 0x1d */
	557		.h = 1280,
	558		.h_bl = 416,
	559		.h_so = 1360,
	560		.h_spw = 128,
	561		.h_b = 0,
	562		.h_sp = 1,
	563		.v = 800,
	564		.v_bl = 38,
	565		.v_so = 803,
	566		.v_spw = 6,
	567		.v_b = 0,
	568		.v_sp = 0,
	569		.pixel_clk = 106500,
	570		.r = 75,
	571		.interlaced = false,
	572		.reduced_blanking = false
	573		},
	574		{/* DMT ID 0x1e */
	575		.h = 1280,
	576		.h_bl = 432,
	577		.h_so = 1360,
	578		.h_spw = 136,
	579		.h_b = 0,
	580		.h_sp = 1,
	581		.v = 800,
	582		.v_bl = 43,
	583		.v_so = 803,
	584		.v_spw = 6,
	585		.v_b = 0,
	586		.v_sp = 0,
	587		.pixel_clk = 122500,
	588		.r = 85,
	589		.interlaced = false,
	590		.reduced_blanking = false
	591		},
	592		{/* DMT ID 0x1f */
	593		.h = 1280,
	594		.h_bl = 160,
	595		.h_so = 1328,
	596		.h_spw = 32,
	597		.h_b = 0,
	598		.h_sp = 0,
	599		.v = 800,
	600		.v_bl = 47,
	601		.v_so = 803,
	602		.v_spw = 6,
	603		.v_b = 0,
	604		.v_sp = 1,
	605		.pixel_clk = 146250,
	606		.r = 120,
	607		.interlaced = false,
	608		.reduced_blanking = true
	609		},
	610		{/* DMT ID 0x20 */
	611		.h = 1280,
	612		.h_bl = 520,
	613		.h_so = 1376,
	614		.h_spw = 112,
	615		.h_b = 0,
	616		.h_sp = 0,
	617		.v = 960,
	618		.v_bl = 40,
	619		.v_so = 961,
	620		.v_spw = 3,
	621		.v_b = 0,
	622		.v_sp = 0,
	623		.pixel_clk = 108000,
	624		.r = 60,
	625		.interlaced = false,
	626		.reduced_blanking = false
	627		},
	628		{/* DMT ID 0x21 */
	629		.h = 1280,
	630		.h_bl = 448,
	631		.h_so = 1344,
	632		.h_spw = 160,
	633		.h_b = 0,
	634		.h_sp = 0,
	635		.v = 960,
	636		.v_bl = 51,
	637		.v_so = 961,
	638		.v_spw = 3,
	639		.v_b = 0,
	640		.v_sp = 0,
	641		.pixel_clk = 148500,
	642		.r = 85,
	643		.interlaced = false,
	644		.reduced_blanking = false
	645		},
	646		{/* DMT ID 0x22 */
	647		.h = 1280,
	648		.h_bl = 160,
	649		.h_so = 1328,
	650		.h_spw = 32,
	651		.h_b = 0,
	652		.h_sp = 0,
	653		.v = 960,
	654		.v_bl = 57,
	655		.v_so = 963,
	656		.v_spw = 4,
	657		.v_b = 0,
	658		.v_sp = 1,
	659		.pixel_clk = 175500,
	660		.r = 120,
	661		.interlaced = false,
	662		.reduced_blanking = true
	663		},
	664		{/* DMT ID 0x23 */
	665		.h = 1280,
	666		.h_bl = 408,
	667		.h_so = 1328,
	668		.h_spw = 112,
	669		.h_b = 0,
	670		.h_sp = 0,
	671		.v = 1024,
	672		.v_bl = 42,
	673		.v_so = 1025,
	674		.v_spw = 3,
	675		.v_b = 0,
	676		.v_sp = 0,
	677		.pixel_clk = 108000,
	678		.r = 60,
	679		.interlaced = false,
	680		.reduced_blanking = false
	681		},
	682		{/* DMT ID 0x24 */
	683		.h = 1280,
	684		.h_bl = 408,
	685		.h_so = 1296,
	686		.h_spw = 144,
	687		.h_b = 0,
	688		.h_sp = 0,
	689		.v = 1024,
	690		.v_bl = 42,
	691		.v_so = 1025,
	692		.v_spw = 3,
	693		.v_b = 0,
	694		.v_sp = 0,
	695		.pixel_clk = 135000,
	696		.r = 75,
	697		.interlaced = false,
	698		.reduced_blanking = false
	699		},
	700		{/* DMT ID 0x25 */
	701		.h = 1280,
	702		.h_bl = 448,
	703		.h_so = 1344,
	704		.h_spw = 160,
	705		.h_b = 0,
	706		.h_sp = 0,
	707		.v = 1024,
	708		.v_bl = 48,
	709		.v_so = 1025,
	710		.v_spw = 3,
	711		.v_b = 0,
	712		.v_sp = 0,
	713		.pixel_clk = 157500,
	714		.r = 85,
	715		.interlaced = false,
	716		.reduced_blanking = false
	717		},
	718		{/* DMT ID 0x26 */
	719		.h = 1280,
	720		.h_bl = 160,
	721		.h_so = 1328,
	722		.h_spw = 32,
	723		.h_b = 0,
	724		.h_sp = 0,
	725		.v = 1024,
	726		.v_bl = 60,
	727		.v_so = 1027,
	728		.v_spw = 7,
	729		.v_b = 0,
	730		.v_sp = 1,
	731		.pixel_clk = 187250,
	732		.r = 120,
	733		.interlaced = false,
	734		.reduced_blanking = true
	735		},
	736		{/* DMT ID 0x27 */
	737		.h = 1360,
	738		.h_bl = 432,
	739		.h_so = 1424,
	740		.h_spw = 112,
	741		.h_b = 0,
	742		.h_sp = 0,
	743		.v = 768,
	744		.v_bl = 27,
	745		.v_so = 771,
	746		.v_spw = 6,
	747		.v_b = 0,
	748		.v_sp = 0,
	749		.pixel_clk = 85500,
	750		.r = 60,
	751		.interlaced = false,
	752		.reduced_blanking = false
	753		},
	754		{/* DMT ID 0x28 */
	755		.h = 1360,
	756		.h_bl = 160,
	757		.h_so = 1408,
	758		.h_spw = 32,
	759		.h_b = 0,
	760		.h_sp = 0,
	761		.v = 768,
	762		.v_bl = 45,
	763		.v_so = 771,
	764		.v_spw = 5,
	765		.v_b = 0,
	766		.v_sp = 1,
	767		.pixel_clk = 148250,
	768		.r = 120,
	769		.interlaced = false,
	770		.reduced_blanking = true
	771		},
	772		{/* DMT ID 0x29 */
	773		.h = 1400,
	774		.h_bl = 160,
	775		.h_so = 1448,
	776		.h_spw = 32,
	777		.h_b = 0,
	778		.h_sp = 0,
	779		.v = 1050,
	780		.v_bl = 30,
	781		.v_so = 1053,
	782		.v_spw = 4,
	783		.v_b = 0,
	784		.v_sp = 1,
	785		.pixel_clk = 101000,
	786		.r = 60,
	787		.interlaced = false,
	788		.reduced_blanking = true
	789		},
	790		{/* DMT ID 0x2a */
	791		.h = 1400,
	792		.h_bl = 464,
	793		.h_so = 1488,
	794		.h_spw = 144,
	795		.h_b = 0,
	796		.h_sp = 1,
	797		.v = 1050,
	798		.v_bl = 39,
	799		.v_so = 1053,
	800		.v_spw = 4,
	801		.v_b = 0,
	802		.v_sp = 0,
	803		.pixel_clk = 121750,
	804		.r = 60,
	805		.interlaced = false,
	806		.reduced_blanking = false
	807		},
	808		{/* DMT ID 0x2b */
	809		.h = 1400,
	810		.h_bl = 496,
	811		.h_so = 1504,
	812		.h_spw = 144,
	813		.h_b = 0,
	814		.h_sp = 1,
	815		.v = 1050,
	816		.v_bl = 49,
	817		.v_so = 1053,
	818		.v_spw = 4,
	819		.v_b = 0,
	820		.v_sp = 0,
	821		.pixel_clk = 156000,
	822		.r = 75,
	823		.interlaced = false,
	824		.reduced_blanking = false
	825		},
	826		{/* DMT ID 0x2c */
	827		.h = 1400,
	828		.h_bl = 512,
	829		.h_so = 1504,
	830		.h_spw = 152,
	831		.h_b = 0,
	832		.h_sp = 1,
	833		.v = 1050,
	834		.v_bl = 55,
	835		.v_so = 1053,
	836		.v_spw = 4,
	837		.v_b = 0,
	838		.v_sp = 0,
	839		.pixel_clk = 179500,
	840		.r = 85,
	841		.interlaced = false,
	842		.reduced_blanking = false
	843		},
	844		{/* DMT ID 0x2d */
	845		.h = 1400,
	846		.h_bl = 160,
	847		.h_so = 1448,
	848		.h_spw = 32,
	849		.h_b = 0,
	850		.h_sp = 0,
	851		.v = 1050,
	852		.v_bl = 62,
	853		.v_so = 1053,
	854		.v_spw = 4,
	855		.v_b = 0,
	856		.v_sp = 1,
	857		.pixel_clk = 208000,
	858		.r = 120,
	859		.interlaced = false,
	860		.reduced_blanking = true
	861		},
	862		{/* DMT ID 0x2e */
	863		.h = 1440,
	864		.h_bl = 160,
	865		.h_so = 1488,
	866		.h_spw = 32,
	867		.h_b = 0,
	868		.h_sp = 0,
	869		.v = 900,
	870		.v_bl = 26,
	871		.v_so = 903,
	872		.v_spw = 6,
	873		.v_b = 0,
	874		.v_sp = 1,
	875		.pixel_clk = 88750,
	876		.r = 60,
	877		.interlaced = false,
	878		.reduced_blanking = true
	879		},
	880		{/* DMT ID 0x2f */
	881		.h = 1440,
	882		.h_bl = 464,
	883		.h_so = 1520,
	884		.h_spw = 152,
	885		.h_b = 0,
	886		.h_sp = 1,
	887		.v = 900,
	888		.v_bl = 34,
	889		.v_so = 903,
	890		.v_spw = 6,
	891		.v_b = 0,
	892		.v_sp = 0,
	893		.pixel_clk = 106500,
	894		.r = 60,
	895		.interlaced = false,
	896		.reduced_blanking = false
	897		},
	898		{/* DMT ID 0x30 */
	899		.h = 1440,
	900		.h_bl = 496,
	901		.h_so = 1536,
	902		.h_spw = 152,
	903		.h_b = 0,
	904		.h_sp = 1,
	905		.v = 900,
	906		.v_bl = 42,
	907		.v_so = 903,
	908		.v_spw = 6,
	909		.v_b = 0,
	910		.v_sp = 0,
	911		.pixel_clk = 136750,
	912		.r = 75,
	913		.interlaced = false,
	914		.reduced_blanking = false
	915		},
	916		{/* DMT ID 0x31 */
	917		.h = 1440,
	918		.h_bl = 512,
	919		.h_so = 1544,
	920		.h_spw = 152,
	921		.h_b = 0,
	922		.h_sp = 1,
	923		.v = 900,
	924		.v_bl = 48,
	925		.v_so = 903,
	926		.v_spw = 6,
	927		.v_b = 0,
	928		.v_sp = 0,
	929		.pixel_clk = 157000,
	930		.r = 85,
	931		.interlaced = false,
	932		.reduced_blanking = false
	933		},
	934		{/* DMT ID 0x32 */
	935		.h = 1440,
	936		.h_bl = 160,
	937		.h_so = 1488,
	938		.h_spw = 32,
	939		.h_b = 0,
	940		.h_sp = 0,
	941		.v = 900,
	942		.v_bl = 53,
	943		.v_so = 903,
	944		.v_spw = 6,
	945		.v_b = 0,
	946		.v_sp = 1,
	947		.pixel_clk = 182750,
	948		.r = 120,
	949		.interlaced = false,
	950		.reduced_blanking = true
	951		},
	952		{/* DMT ID 0x33 */
	953		.h = 1600,
	954		.h_bl = 560,
	955		.h_so = 1664,
	956		.h_spw = 192,
	957		.h_b = 0,
	958		.h_sp = 0,
	959		.v = 1200,
	960		.v_bl = 50,
	961		.v_so = 1201,
	962		.v_spw = 3,
	963		.v_b = 0,
	964		.v_sp = 0,
	965		.pixel_clk = 162000,
	966		.r = 60,
	967		.interlaced = false,
	968		.reduced_blanking = false
	969		},
	970		{/* DMT ID 0x34 */
	971		.h = 1600,
	972		.h_bl = 560,
	973		.h_so = 1664,
	974		.h_spw = 192,
	975		.h_b = 0,
	976		.h_sp = 0,
	977		.v = 1200,
	978		.v_bl = 50,
	979		.v_so = 1201,
	980		.v_spw = 3,
	981		.v_b = 0,
	982		.v_sp = 0,
	983		.pixel_clk = 175500,
	984		.r = 65,
	985		.interlaced = false,
	986		.reduced_blanking = false
	987		},
	988		{/* DMT ID 0x35 */
	989		.h = 1600,
	990		.h_bl = 560,
	991		.h_so = 1664,
	992		.h_spw = 192,
	993		.h_b = 0,
	994		.h_sp = 0,
	995		.v = 1200,
	996		.v_bl = 50,
	997		.v_so = 1201,
	998		.v_spw = 3,
	999		.v_b = 0,
	1000		.v_sp = 0,
	1001		.pixel_clk = 189000,
	1002		.r = 70,
	1003		.interlaced = false,
	1004		.reduced_blanking = false
	1005		},
	1006		{/* DMT ID 0x36 */
	1007		.h = 1600,
	1008		.h_bl = 560,
	1009		.h_so = 1664,
	1010		.h_spw = 192,
	1011		.h_b = 0,
	1012		.h_sp = 0,
	1013		.v = 1200,
	1014		.v_bl = 50,
	1015		.v_so = 1201,
	1016		.v_spw = 3,
	1017		.v_b = 0,
	1018		.v_sp = 0,
	1019		.pixel_clk = 202500,
	1020		.r = 75,
	1021		.interlaced = false,
	1022		.reduced_blanking = false
	1023		},
	1024		{/* DMT ID 0x37 */
	1025		.h = 1600,
	1026		.h_bl = 560,
	1027		.h_so = 1664,
	1028		.h_spw = 192,
	1029		.h_b = 0,
	1030		.h_sp = 0,
	1031		.v = 1200,
	1032		.v_bl = 50,
	1033		.v_so = 1201,
	1034		.v_spw = 3,
	1035		.v_b = 0,
	1036		.v_sp = 0,
	1037		.pixel_clk = 229500,
	1038		.r = 85,
	1039		.interlaced = false,
	1040		.reduced_blanking = false
	1041		},
	1042		{/* DMT ID 0x38 */
	1043		.h = 1600,
	1044		.h_bl = 160,
	1045		.h_so = 1648,
	1046		.h_spw = 32,
	1047		.h_b = 0,
	1048		.h_sp = 0,
	1049		.v = 1200,
	1050		.v_bl = 71,
	1051		.v_so = 1203,
	1052		.v_spw = 4,
	1053		.v_b = 0,
	1054		.v_sp = 1,
	1055		.pixel_clk = 268250,
	1056		.r = 120,
	1057		.interlaced = false,
	1058		.reduced_blanking = true
	1059		},
	1060		{/* DMT ID 0x39 */
	1061		.h = 1680,
	1062		.h_bl = 160,
	1063		.h_so = 1728,
	1064		.h_spw = 32,
	1065		.h_b = 0,
	1066		.h_sp = 0,
	1067		.v = 1050,
	1068		.v_bl = 30,
	1069		.v_so = 1053,
	1070		.v_spw = 6,
	1071		.v_b = 0,
	1072		.v_sp = 1,
	1073		.pixel_clk = 119000,
	1074		.r = 120,
	1075		.interlaced = false,
	1076		.reduced_blanking = true
	1077		},
	1078		{/* DMT ID 0x3a */
	1079		.h = 1680,
	1080		.h_bl = 560,
	1081		.h_so = 1784,
	1082		.h_spw = 176,
	1083		.h_b = 0,
	1084		.h_sp = 1,
	1085		.v = 1050,
	1086		.v_bl = 39,
	1087		.v_so = 1053,
	1088		.v_spw = 6,
	1089		.v_b = 0,
	1090		.v_sp = 0,
	1091		.pixel_clk = 146250,
	1092		.r = 60,
	1093		.interlaced = false,
	1094		.reduced_blanking = false
	1095		},
	1096		{/* DMT ID 0x3b */
	1097		.h = 1680,
	1098		.h_bl = 592,
	1099		.h_so = 1800,
	1100		.h_spw = 176,
	1101		.h_b = 0,
	1102		.h_sp = 1,
	1103		.v = 1050,
	1104		.v_bl = 49,
	1105		.v_so = 1053,
	1106		.v_spw = 6,
	1107		.v_b = 0,
	1108		.v_sp = 0,
	1109		.pixel_clk = 187000,
	1110		.r = 75,
	1111		.interlaced = false,
	1112		.reduced_blanking = false
	1113		},
	1114		{/* DMT ID 0x3c */
	1115		.h = 1680,
	1116		.h_bl = 608,
	1117		.h_so = 1808,
	1118		.h_spw = 176,
	1119		.h_b = 0,
	1120		.h_sp = 1,
	1121		.v = 1050,
	1122		.v_bl = 55,
	1123		.v_so = 1053,
	1124		.v_spw = 6,
	1125		.v_b = 0,
	1126		.v_sp = 0,
	1127		.pixel_clk = 214750,
	1128		.r = 85,
	1129		.interlaced = false,
	1130		.reduced_blanking = false
	1131		},
	1132		{/* DMT ID 0x3d */
	1133		.h = 1680,
	1134		.h_bl = 160,
	1135		.h_so = 1728,
	1136		.h_spw = 32,
	1137		.h_b = 0,
	1138		.h_sp = 0,
	1139		.v = 1050,
	1140		.v_bl = 62,
	1141		.v_so = 1053,
	1142		.v_spw = 6,
	1143		.v_b = 0,
	1144		.v_sp = 1,
	1145		.pixel_clk = 245500,
	1146		.r = 120,
	1147		.interlaced = false,
	1148		.reduced_blanking = true
	1149		},
	1150		{/* DMT ID 0x3e */
	1151		.h = 1792,
	1152		.h_bl = 656,
	1153		.h_so = 1920,
	1154		.h_spw = 200,
	1155		.h_b = 0,
	1156		.h_sp = 1,
	1157		.v = 1344,
	1158		.v_bl = 50,
	1159		.v_so = 1345,
	1160		.v_spw = 3,
	1161		.v_b = 0,
	1162		.v_sp = 0,
	1163		.pixel_clk = 204750,
	1164		.r = 60,
	1165		.interlaced = false,
	1166		.reduced_blanking = false
	1167		},
	1168		{/* DMT ID 0x3f */
	1169		.h = 1792,
	1170		.h_bl = 664,
	1171		.h_so = 1888,
	1172		.h_spw = 216,
	1173		.h_b = 0,
	1174		.h_sp = 1,
	1175		.v = 1344,
	1176		.v_bl = 73,
	1177		.v_so = 1345,
	1178		.v_spw = 3,
	1179		.v_b = 0,
	1180		.v_sp = 0,
	1181		.pixel_clk = 261000,
	1182		.r = 75,
	1183		.interlaced = false,
	1184		.reduced_blanking = false
	1185		},
	1186		{/* DMT ID 0x40 */
	1187		.h = 1792,
	1188		.h_bl = 160,
	1189		.h_so = 1840,
	1190		.h_spw = 32,
	1191		.h_b = 0,
	1192		.h_sp = 0,
	1193		.v = 1344,
	1194		.v_bl = 79,
	1195		.v_so = 1347,
	1196		.v_spw = 4,
	1197		.v_b = 0,
	1198		.v_sp = 1,
	1199		.pixel_clk = 333250,
	1200		.r = 120,
	1201		.interlaced = false,
	1202		.reduced_blanking = true
	1203		},
	1204		{/* DMT ID 0x41 */
	1205		.h = 1856,
	1206		.h_bl = 672,
	1207		.h_so = 1952,
	1208		.h_spw = 224,
	1209		.h_b = 0,
	1210		.h_sp = 1,
	1211		.v = 1392,
	1212		.v_bl = 47,
	1213		.v_so = 1393,
	1214		.v_spw = 3,
	1215		.v_b = 0,
	1216		.v_sp = 0,
	1217		.pixel_clk = 218250,
	1218		.r = 60,
	1219		.interlaced = false,
	1220		.reduced_blanking = false
	1221		},
	1222		{/* DMT ID 0x42 */
	1223		.h = 1856,
	1224		.h_bl = 704,
	1225		.h_so = 1984,
	1226		.h_spw = 224,
	1227		.h_b = 0,
	1228		.h_sp = 1,
	1229		.v = 1392,
	1230		.v_bl = 108,
	1231		.v_so = 1393,
	1232		.v_spw = 3,
	1233		.v_b = 0,
	1234		.v_sp = 0,
	1235		.pixel_clk = 288000,
	1236		.r = 75,
	1237		.interlaced = false,
	1238		.reduced_blanking = false
	1239		},
	1240		{/* DMT ID 0x43 */
	1241		.h = 1856,
	1242		.h_bl = 160,
	1243		.h_so = 1904,
	1244		.h_spw = 32,
	1245		.h_b = 0,
	1246		.h_sp = 0,
	1247		.v = 1392,
	1248		.v_bl = 82,
	1249		.v_so = 1395,
	1250		.v_spw = 4,
	1251		.v_b = 0,
	1252		.v_sp = 1,
	1253		.pixel_clk = 356500,
	1254		.r = 120,
	1255		.interlaced = false,
	1256		.reduced_blanking = true
	1257		},
	1258		{/* DMT ID 0x44 */
	1259		.h = 1920,
	1260		.h_bl = 160,
	1261		.h_so = 1968,
	1262		.h_spw = 32,
	1263		.h_b = 0,
	1264		.h_sp = 0,
	1265		.v = 1200,
	1266		.v_bl = 35,
	1267		.v_so = 1203,
	1268		.v_spw = 6,
	1269		.v_b = 0,
	1270		.v_sp = 1,
	1271		.pixel_clk = 154000,
	1272		.r = 60,
	1273		.interlaced = false,
	1274		.reduced_blanking = true
	1275		},
	1276		{/* DMT ID 0x45 */
	1277		.h = 1920,
	1278		.h_bl = 672,
	1279		.h_so = 2056,
	1280		.h_spw = 200,
	1281		.h_b = 0,
	1282		.h_sp = 1,
	1283		.v = 1200,
	1284		.v_bl = 45,
	1285		.v_so = 1203,
	1286		.v_spw = 6,
	1287		.v_b = 0,
	1288		.v_sp = 0,
	1289		.pixel_clk = 193250,
	1290		.r = 60,
	1291		.interlaced = false,
	1292		.reduced_blanking = false
	1293		},
	1294		{/* DMT ID 0x46 */
	1295		.h = 1920,
	1296		.h_bl = 688,
	1297		.h_so = 2056,
	1298		.h_spw = 208,
	1299		.h_b = 0,
	1300		.h_sp = 1,
	1301		.v = 1200,
	1302		.v_bl = 55,
	1303		.v_so = 1203,
	1304		.v_spw = 6,
	1305		.v_b = 0,
	1306		.v_sp = 0,
	1307		.pixel_clk = 245250,
	1308		.r = 75,
	1309		.interlaced = false,
	1310		.reduced_blanking = false
	1311		},
	1312		{/* DMT ID 0x47 */
	1313		.h = 1920,
	1314		.h_bl = 704,
	1315		.h_so = 2064,
	1316		.h_spw = 208,
	1317		.h_b = 0,
	1318		.h_sp = 1,
	1319		.v = 1200,
	1320		.v_bl = 62,
	1321		.v_so = 1203,
	1322		.v_spw = 6,
	1323		.v_b = 0,
	1324		.v_sp = 0,
	1325		.pixel_clk = 281250,
	1326		.r = 85,
	1327		.interlaced = false,
	1328		.reduced_blanking = false
	1329		},
	1330		{/* DMT ID 0x48 */
	1331		.h = 1920,
	1332		.h_bl = 160,
	1333		.h_so = 1968,
	1334		.h_spw = 32,
	1335		.h_b = 0,
	1336		.h_sp = 0,
	1337		.v = 1200,
	1338		.v_bl = 71,
	1339		.v_so = 1203,
	1340		.v_spw = 6,
	1341		.v_b = 0,
	1342		.v_sp = 1,
	1343		.pixel_clk = 317000,
	1344		.r = 120,
	1345		.interlaced = false,
	1346		.reduced_blanking = true
	1347		},
	1348		{/* DMT ID 0x49 */
	1349		.h = 1920,
	1350		.h_bl = 680,
	1351		.h_so = 2048,
	1352		.h_spw = 208,
	1353		.h_b = 0,
	1354		.h_sp = 1,
	1355		.v = 1440,
	1356		.v_bl = 60,
	1357		.v_so = 1441,
	1358		.v_spw = 3,
	1359		.v_b = 0,
	1360		.v_sp = 0,
	1361		.pixel_clk = 234000,
	1362		.r = 60,
	1363		.interlaced = false,
	1364		.reduced_blanking = false
	1365		},
	1366		{/* DMT ID 0x4a */
	1367		.h = 1920,
	1368		.h_bl = 720,
	1369		.h_so = 2064,
	1370		.h_spw = 224,
	1371		.h_b = 0,
	1372		.h_sp = 1,
	1373		.v = 1440,
	1374		.v_bl = 60,
	1375		.v_so = 1441,
	1376		.v_spw = 3,
	1377		.v_b = 0,
	1378		.v_sp = 0,
	1379		.pixel_clk = 297000,
	1380		.r = 75,
	1381		.interlaced = false,
	1382		.reduced_blanking = false
	1383		},
	1384		{/* DMT ID 0x4b */
	1385		.h = 1920,
	1386		.h_bl = 160,
	1387		.h_so = 1968,
	1388		.h_spw = 32,
	1389		.h_b = 0,
	1390		.h_sp = 0,
	1391		.v = 1440,
	1392		.v_bl = 85,
	1393		.v_so = 1443,
	1394		.v_spw = 4,
	1395		.v_b = 0,
	1396		.v_sp = 1,
	1397		.pixel_clk = 380500,
	1398		.r = 120,
	1399		.interlaced = false,
	1400		.reduced_blanking = true
	1401		},
	1402		{/* DMT ID 0x4c */
	1403		.h = 2560,
	1404		.h_bl = 160,
	1405		.h_so = 2608,
	1406		.h_spw = 32,
	1407		.h_b = 0,
	1408		.h_sp = 0,
	1409		.v = 1600,
	1410		.v_bl = 46,
	1411		.v_so = 1603,
	1412		.v_spw = 6,
	1413		.v_b = 0,
	1414		.v_sp = 1,
	1415		.pixel_clk = 268500,
	1416		.r = 120,
	1417		.interlaced = false,
	1418		.reduced_blanking = true
	1419		},
	1420		{/* DMT ID 0x4d */
	1421		.h = 2560,
	1422		.h_bl = 944,
	1423		.h_so = 2752,
	1424		.h_spw = 280,
	1425		.h_b = 0,
	1426		.h_sp = 1,
	1427		.v = 1600,
	1428		.v_bl = 58,
	1429		.v_so = 1603,
	1430		.v_spw = 6,
	1431		.v_b = 0,
	1432		.v_sp = 0,
	1433		.pixel_clk = 348500,
	1434		.r = 120,
	1435		.interlaced = false,
	1436		.reduced_blanking = false
	1437		},
	1438		{/* DMT ID 0x4e */
	1439		.h = 2560,
	1440		.h_bl = 976,
	1441		.h_so = 2768,
	1442		.h_spw = 280,
	1443		.h_b = 0,
	1444		.h_sp = 1,
	1445		.v = 1600,
	1446		.v_bl = 72,
	1447		.v_so = 1603,
	1448		.v_spw = 6,
	1449		.v_b = 0,
	1450		.v_sp = 0,
	1451		.pixel_clk = 443250,
	1452		.r = 75,
	1453		.interlaced = false,
	1454		.reduced_blanking = false
	1455		},
	1456		{/* DMT ID 0x4f */
	1457		.h = 2560,
	1458		.h_bl = 976,
	1459		.h_so = 2768,
	1460		.h_spw = 280,
	1461		.h_b = 0,
	1462		.h_sp = 1,
	1463		.v = 1600,
	1464		.v_bl = 82,
	1465		.v_so = 1603,
	1466		.v_spw = 6,
	1467		.v_b = 0,
	1468		.v_sp = 0,
	1469		.pixel_clk = 505250,
	1470		.r = 85,
	1471		.interlaced = false,
	1472		.reduced_blanking = false
	1473		},
	1474		{/* DMT ID 0x50 */
	1475		.h = 2560,
	1476		.h_bl = 160,
	1477		.h_so = 2608,
	1478		.h_spw = 32,
	1479		.h_b = 0,
	1480		.h_sp = 0,
	1481		.v = 1600,
	1482		.v_bl = 94,
	1483		.v_so = 1603,
	1484		.v_spw = 6,
	1485		.v_b = 0,
	1486		.v_sp = 1,
	1487		.pixel_clk = 552750,
	1488		.r = 120,
	1489		.interlaced = false,
	1490		.reduced_blanking = true
	1491		}
	1492		};
	1493		#endif

File drivers/video/Kconfig-3.2.7 added (mode: 100644) (index 0000000..6796f15)
	1		#
	2		# Video configuration
	3		#
	4
	5		menu "Graphics support"
	6		depends on HAS_IOMEM
	7
	8		config HAVE_FB_ATMEL
	9		bool
	10
	11		config SH_MIPI_DSI
	12		tristate
	13		depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	14
	15		config SH_LCD_MIPI_DSI
	16		bool
	17
	18		source "drivers/char/agp/Kconfig"
	19
	20		source "drivers/gpu/vga/Kconfig"
	21
	22		source "drivers/gpu/alga/Kconfig"
	23
	24		source "drivers/gpu/drm/Kconfig"
	25
	26		source "drivers/gpu/stub/Kconfig"
	27
	28		config VGASTATE
	29		tristate
	30		default n
	31
	32		config VIDEO_OUTPUT_CONTROL
	33		tristate "Lowlevel video output switch controls"
	34		help
	35		This framework adds support for low-level control of the video
	36		output switch.
	37
	38		menuconfig FB
	39		tristate "Support for frame buffer devices"
	40		---help---
	41		The frame buffer device provides an abstraction for the graphics
	42		hardware. It represents the frame buffer of some video hardware and
	43		allows application software to access the graphics hardware through
	44		a well-defined interface, so the software doesn't need to know
	45		anything about the low-level (hardware register) stuff.
	46
	47		Frame buffer devices work identically across the different
	48		architectures supported by Linux and make the implementation of
	49		application programs easier and more portable; at this point, an X
	50		server exists which uses the frame buffer device exclusively.
	51		On several non-X86 architectures, the frame buffer device is the
	52		only way to use the graphics hardware.
	53
	54		The device is accessed through special device nodes, usually located
	55		in the /dev directory, i.e. /dev/fb*.
	56
	57		You need an utility program called fbset to make full use of frame
	58		buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
	59		and the Framebuffer-HOWTO at
	60		<http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
	61		information.
	62
	63		Say Y here and to the driver for your graphics board below if you
	64		are compiling a kernel for a non-x86 architecture.
	65
	66		If you are compiling for the x86 architecture, you can say Y if you
	67		want to play with it, but it is not essential. Please note that
	68		running graphical applications that directly touch the hardware
	69		(e.g. an accelerated X server) and that are not frame buffer
	70		device-aware may cause unexpected results. If unsure, say N.
	71
	72		config FIRMWARE_EDID
	73		bool "Enable firmware EDID"
	74		depends on FB
	75		default n
	76		---help---
	77		This enables access to the EDID transferred from the firmware.
	78		On the i386, this is from the Video BIOS. Enable this if DDC/I2C
	79		transfers do not work for your driver and if you are using
	80		nvidiafb, i810fb or savagefb.
	81
	82		In general, choosing Y for this option is safe. If you
	83		experience extremely long delays while booting before you get
	84		something on your display, try setting this to N. Matrox cards in
	85		combination with certain motherboards and monitors are known to
	86		suffer from this problem.
	87
	88		config FB_DDC
	89		tristate
	90		depends on FB
	91		select I2C_ALGOBIT
	92		select I2C
	93		default n
	94
	95		config FB_BOOT_VESA_SUPPORT
	96		bool
	97		depends on FB
	98		default n
	99		---help---
	100		If true, at least one selected framebuffer driver can take advantage
	101		of VESA video modes set at an early boot stage via the vga= parameter.
	102
	103		config FB_CFB_FILLRECT
	104		tristate
	105		depends on FB
	106		default n
	107		---help---
	108		Include the cfb_fillrect function for generic software rectangle
	109		filling. This is used by drivers that don't provide their own
	110		(accelerated) version.
	111
	112		config FB_CFB_COPYAREA
	113		tristate
	114		depends on FB
	115		default n
	116		---help---
	117		Include the cfb_copyarea function for generic software area copying.
	118		This is used by drivers that don't provide their own (accelerated)
	119		version.
	120
	121		config FB_CFB_IMAGEBLIT
	122		tristate
	123		depends on FB
	124		default n
	125		---help---
	126		Include the cfb_imageblit function for generic software image
	127		blitting. This is used by drivers that don't provide their own
	128		(accelerated) version.
	129
	130		config FB_CFB_REV_PIXELS_IN_BYTE
	131		bool
	132		depends on FB
	133		default n
	134		---help---
	135		Allow generic frame-buffer functions to work on displays with 1, 2
	136		and 4 bits per pixel depths which has opposite order of pixels in
	137		byte order to bytes in long order.
	138
	139		config FB_SYS_FILLRECT
	140		tristate
	141		depends on FB
	142		default n
	143		---help---
	144		Include the sys_fillrect function for generic software rectangle
	145		filling. This is used by drivers that don't provide their own
	146		(accelerated) version and the framebuffer is in system RAM.
	147
	148		config FB_SYS_COPYAREA
	149		tristate
	150		depends on FB
	151		default n
	152		---help---
	153		Include the sys_copyarea function for generic software area copying.
	154		This is used by drivers that don't provide their own (accelerated)
	155		version and the framebuffer is in system RAM.
	156
	157		config FB_SYS_IMAGEBLIT
	158		tristate
	159		depends on FB
	160		default n
	161		---help---
	162		Include the sys_imageblit function for generic software image
	163		blitting. This is used by drivers that don't provide their own
	164		(accelerated) version and the framebuffer is in system RAM.
	165
	166		menuconfig FB_FOREIGN_ENDIAN
	167		bool "Framebuffer foreign endianness support"
	168		depends on FB
	169		---help---
	170		This menu will let you enable support for the framebuffers with
	171		non-native endianness (e.g. Little-Endian framebuffer on a
	172		Big-Endian machine). Most probably you don't have such hardware,
	173		so it's safe to say "n" here.
	174
	175		choice
	176		prompt "Choice endianness support"
	177		depends on FB_FOREIGN_ENDIAN
	178
	179		config FB_BOTH_ENDIAN
	180		bool "Support for Big- and Little-Endian framebuffers"
	181
	182		config FB_BIG_ENDIAN
	183		bool "Support for Big-Endian framebuffers only"
	184
	185		config FB_LITTLE_ENDIAN
	186		bool "Support for Little-Endian framebuffers only"
	187
	188		endchoice
	189
	190		config FB_SYS_FOPS
	191		tristate
	192		depends on FB
	193		default n
	194
	195		config FB_WMT_GE_ROPS
	196		tristate
	197		depends on FB
	198		default n
	199		---help---
	200		Include functions for accelerated rectangle filling and area
	201		copying using WonderMedia Graphics Engine operations.
	202
	203		config FB_DEFERRED_IO
	204		bool
	205		depends on FB
	206
	207		config FB_HECUBA
	208		tristate
	209		depends on FB
	210		depends on FB_DEFERRED_IO
	211
	212		config FB_SVGALIB
	213		tristate
	214		depends on FB
	215		default n
	216		---help---
	217		Common utility functions useful to fbdev drivers of VGA-based
	218		cards.
	219
	220		config FB_MACMODES
	221		tristate
	222		depends on FB
	223		default n
	224
	225		config FB_BACKLIGHT
	226		bool
	227		depends on FB
	228		select BACKLIGHT_LCD_SUPPORT
	229		select BACKLIGHT_CLASS_DEVICE
	230		default n
	231
	232		config FB_MODE_HELPERS
	233		bool "Enable Video Mode Handling Helpers"
	234		depends on FB
	235		default n
	236		---help---
	237		This enables functions for handling video modes using the
	238		Generalized Timing Formula and the EDID parser. A few drivers rely
	239		on this feature such as the radeonfb, rivafb, and the i810fb. If
	240		your driver does not take advantage of this feature, choosing Y will
	241		just increase the kernel size by about 5K.
	242
	243		config FB_TILEBLITTING
	244		bool "Enable Tile Blitting Support"
	245		depends on FB
	246		default n
	247		---help---
	248		This enables tile blitting. Tile blitting is a drawing technique
	249		where the screen is divided into rectangular sections (tiles), whereas
	250		the standard blitting divides the screen into pixels. Because the
	251		default drawing element is a tile, drawing functions will be passed
	252		parameters in terms of number of tiles instead of number of pixels.
	253		For example, to draw a single character, instead of using bitmaps,
	254		an index to an array of bitmaps will be used. To clear or move a
	255		rectangular section of a screen, the rectangle will be described in
	256		terms of number of tiles in the x- and y-axis.
	257
	258		This is particularly important to one driver, matroxfb. If
	259		unsure, say N.
	260
	261		comment "Frame buffer hardware drivers"
	262		depends on FB
	263
	264		config FB_GRVGA
	265		tristate "Aeroflex Gaisler framebuffer support"
	266		depends on FB && SPARC
	267		select FB_CFB_FILLRECT
	268		select FB_CFB_COPYAREA
	269		select FB_CFB_IMAGEBLIT
	270		---help---
	271		This enables support for the SVGACTRL framebuffer in the GRLIB IP library from Aeroflex Gaisler.
	272
	273		config FB_CIRRUS
	274		tristate "Cirrus Logic support"
	275		depends on FB && (ZORRO || PCI)
	276		select FB_CFB_FILLRECT
	277		select FB_CFB_COPYAREA
	278		select FB_CFB_IMAGEBLIT
	279		---help---
	280		This enables support for Cirrus Logic GD542x/543x based boards on
	281		Amiga: SD64, Piccolo, Picasso II/II+, Picasso IV, or EGS Spectrum.
	282
	283		If you have a PCI-based system, this enables support for these
	284		chips: GD-543x, GD-544x, GD-5480.
	285
	286		Please read the file <file:Documentation/fb/cirrusfb.txt>.
	287
	288		Say N unless you have such a graphics board or plan to get one
	289		before you next recompile the kernel.
	290
	291		config FB_PM2
	292		tristate "Permedia2 support"
	293		depends on FB && ((AMIGA && BROKEN) || PCI)
	294		select FB_CFB_FILLRECT
	295		select FB_CFB_COPYAREA
	296		select FB_CFB_IMAGEBLIT
	297		help
	298		This is the frame buffer device driver for cards based on
	299		the 3D Labs Permedia, Permedia 2 and Permedia 2V chips.
	300		The driver was tested on the following cards:
	301		Diamond FireGL 1000 PRO AGP
	302		ELSA Gloria Synergy PCI
	303		Appian Jeronimo PRO (both heads) PCI
	304		3DLabs Oxygen ACX aka EONtronics Picasso P2 PCI
	305		Techsource Raptor GFX-8P (aka Sun PGX-32) on SPARC
	306		ASK Graphic Blaster Exxtreme AGP
	307
	308		To compile this driver as a module, choose M here: the
	309		module will be called pm2fb.
	310
	311		config FB_PM2_FIFO_DISCONNECT
	312		bool "enable FIFO disconnect feature"
	313		depends on FB_PM2 && PCI
	314		help
	315		Support the Permedia2 FIFO disconnect feature.
	316
	317		config FB_ARMCLCD
	318		tristate "ARM PrimeCell PL110 support"
	319		depends on FB && ARM && ARM_AMBA
	320		select FB_CFB_FILLRECT
	321		select FB_CFB_COPYAREA
	322		select FB_CFB_IMAGEBLIT
	323		help
	324		This framebuffer device driver is for the ARM PrimeCell PL110
	325		Colour LCD controller. ARM PrimeCells provide the building
	326		blocks for System on a Chip devices.
	327
	328		If you want to compile this as a module (=code which can be
	329		inserted into and removed from the running kernel), say M
	330		here and read <file:Documentation/kbuild/modules.txt>. The module
	331		will be called amba-clcd.
	332
	333		config FB_ACORN
	334		bool "Acorn VIDC support"
	335		depends on (FB = y) && ARM && ARCH_ACORN
	336		select FB_CFB_FILLRECT
	337		select FB_CFB_COPYAREA
	338		select FB_CFB_IMAGEBLIT
	339		help
	340		This is the frame buffer device driver for the Acorn VIDC graphics
	341		hardware found in Acorn RISC PCs and other ARM-based machines. If
	342		unsure, say N.
	343
	344		config FB_CLPS711X
	345		bool "CLPS711X LCD support"
	346		depends on (FB = y) && ARM && ARCH_CLPS711X
	347		select FB_CFB_FILLRECT
	348		select FB_CFB_COPYAREA
	349		select FB_CFB_IMAGEBLIT
	350		help
	351		Say Y to enable the Framebuffer driver for the CLPS7111 and
	352		EP7212 processors.
	353
	354		config FB_SA1100
	355		bool "SA-1100 LCD support"
	356		depends on (FB = y) && ARM && ARCH_SA1100
	357		select FB_CFB_FILLRECT
	358		select FB_CFB_COPYAREA
	359		select FB_CFB_IMAGEBLIT
	360		help
	361		This is a framebuffer device for the SA-1100 LCD Controller.
	362		See <http://www.linux-fbdev.org/> for information on framebuffer
	363		devices.
	364
	365		If you plan to use the LCD display with your SA-1100 system, say
	366		Y here.
	367
	368		config FB_IMX
	369		tristate "Freescale i.MX LCD support"
	370		depends on FB && IMX_HAVE_PLATFORM_IMX_FB
	371		select FB_CFB_FILLRECT
	372		select FB_CFB_COPYAREA
	373		select FB_CFB_IMAGEBLIT
	374
	375		config FB_CYBER2000
	376		tristate "CyberPro 2000/2010/5000 support"
	377		depends on FB && PCI && (BROKEN || !SPARC64)
	378		select FB_CFB_FILLRECT
	379		select FB_CFB_COPYAREA
	380		select FB_CFB_IMAGEBLIT
	381		help
	382		This enables support for the Integraphics CyberPro 20x0 and 5000
	383		VGA chips used in the Rebel.com Netwinder and other machines.
	384		Say Y if you have a NetWinder or a graphics card containing this
	385		device, otherwise say N.
	386
	387		config FB_CYBER2000_DDC
	388		bool "DDC for CyberPro support"
	389		depends on FB_CYBER2000
	390		select FB_DDC
	391		default y
	392		help
	393		Say Y here if you want DDC support for your CyberPro graphics
	394		card. This is only I2C bus support, driver does not use EDID.
	395
	396		config FB_CYBER2000_I2C
	397		bool "CyberPro 2000/2010/5000 I2C support"
	398		depends on FB_CYBER2000 && I2C && ARCH_NETWINDER
	399		select I2C_ALGOBIT
	400		help
	401		Enable support for the I2C video decoder interface on the
	402		Integraphics CyberPro 20x0 and 5000 VGA chips. This is used
	403		on the Netwinder machines for the SAA7111 video capture.
	404
	405		config FB_APOLLO
	406		bool
	407		depends on (FB = y) && APOLLO
	408		default y
	409		select FB_CFB_FILLRECT
	410		select FB_CFB_IMAGEBLIT
	411
	412		config FB_Q40
	413		bool
	414		depends on (FB = y) && Q40
	415		default y
	416		select FB_CFB_FILLRECT
	417		select FB_CFB_COPYAREA
	418		select FB_CFB_IMAGEBLIT
	419
	420		config FB_AMIGA
	421		tristate "Amiga native chipset support"
	422		depends on FB && AMIGA
	423		help
	424		This is the frame buffer device driver for the builtin graphics
	425		chipset found in Amigas.
	426
	427		To compile this driver as a module, choose M here: the
	428		module will be called amifb.
	429
	430		config FB_AMIGA_OCS
	431		bool "Amiga OCS chipset support"
	432		depends on FB_AMIGA
	433		help
	434		This enables support for the original Agnus and Denise video chips,
	435		found in the Amiga 1000 and most A500's and A2000's. If you intend
	436		to run Linux on any of these systems, say Y; otherwise say N.
	437
	438		config FB_AMIGA_ECS
	439		bool "Amiga ECS chipset support"
	440		depends on FB_AMIGA
	441		help
	442		This enables support for the Enhanced Chip Set, found in later
	443		A500's, later A2000's, the A600, the A3000, the A3000T and CDTV. If
	444		you intend to run Linux on any of these systems, say Y; otherwise
	445		say N.
	446
	447		config FB_AMIGA_AGA
	448		bool "Amiga AGA chipset support"
	449		depends on FB_AMIGA
	450		help
	451		This enables support for the Advanced Graphics Architecture (also
	452		known as the AGA or AA) Chip Set, found in the A1200, A4000, A4000T
	453		and CD32. If you intend to run Linux on any of these systems, say Y;
	454		otherwise say N.
	455
	456		config FB_FM2
	457		bool "Amiga FrameMaster II/Rainbow II support"
	458		depends on (FB = y) && ZORRO
	459		select FB_CFB_FILLRECT
	460		select FB_CFB_COPYAREA
	461		select FB_CFB_IMAGEBLIT
	462		help
	463		This is the frame buffer device driver for the Amiga FrameMaster
	464		card from BSC (exhibited 1992 but not shipped as a CBM product).
	465
	466		config FB_ARC
	467		tristate "Arc Monochrome LCD board support"
	468		depends on FB && X86
	469		select FB_SYS_FILLRECT
	470		select FB_SYS_COPYAREA
	471		select FB_SYS_IMAGEBLIT
	472		select FB_SYS_FOPS
	473		help
	474		This enables support for the Arc Monochrome LCD board. The board
	475		is based on the KS-108 lcd controller and is typically a matrix
	476		of 2*n chips. This driver was tested with a 128x64 panel. This
	477		driver supports it for use with x86 SBCs through a 16 bit GPIO
	478		interface (8 bit data, 8 bit control). If you anticipate using
	479		this driver, say Y or M; otherwise say N. You must specify the
	480		GPIO IO address to be used for setting control and data.
	481
	482		config FB_ATARI
	483		bool "Atari native chipset support"
	484		depends on (FB = y) && ATARI
	485		select FB_CFB_FILLRECT
	486		select FB_CFB_COPYAREA
	487		select FB_CFB_IMAGEBLIT
	488		help
	489		This is the frame buffer device driver for the builtin graphics
	490		chipset found in Ataris.
	491
	492		config FB_OF
	493		bool "Open Firmware frame buffer device support"
	494		depends on (FB = y) && (PPC64 || PPC_OF) && (!PPC_PSERIES || PCI)
	495		select FB_CFB_FILLRECT
	496		select FB_CFB_COPYAREA
	497		select FB_CFB_IMAGEBLIT
	498		select FB_MACMODES
	499		help
	500		Say Y if you want support with Open Firmware for your graphics
	501		board.
	502
	503		config FB_CONTROL
	504		bool "Apple \"control\" display support"
	505		depends on (FB = y) && PPC_PMAC && PPC32
	506		select FB_CFB_FILLRECT
	507		select FB_CFB_COPYAREA
	508		select FB_CFB_IMAGEBLIT
	509		select FB_MACMODES
	510		help
	511		This driver supports a frame buffer for the graphics adapter in the
	512		Power Macintosh 7300 and others.
	513
	514		config FB_PLATINUM
	515		bool "Apple \"platinum\" display support"
	516		depends on (FB = y) && PPC_PMAC && PPC32
	517		select FB_CFB_FILLRECT
	518		select FB_CFB_COPYAREA
	519		select FB_CFB_IMAGEBLIT
	520		select FB_MACMODES
	521		help
	522		This driver supports a frame buffer for the "platinum" graphics
	523		adapter in some Power Macintoshes.
	524
	525		config FB_VALKYRIE
	526		bool "Apple \"valkyrie\" display support"
	527		depends on (FB = y) && (MAC || (PPC_PMAC && PPC32))
	528		select FB_CFB_FILLRECT
	529		select FB_CFB_COPYAREA
	530		select FB_CFB_IMAGEBLIT
	531		select FB_MACMODES
	532		help
	533		This driver supports a frame buffer for the "valkyrie" graphics
	534		adapter in some Power Macintoshes.
	535
	536		config FB_CT65550
	537		bool "Chips 65550 display support"
	538		depends on (FB = y) && PPC32 && PCI
	539		select FB_CFB_FILLRECT
	540		select FB_CFB_COPYAREA
	541		select FB_CFB_IMAGEBLIT
	542		help
	543		This is the frame buffer device driver for the Chips & Technologies
	544		65550 graphics chip in PowerBooks.
	545
	546		config FB_ASILIANT
	547		bool "Asiliant (Chips) 69000 display support"
	548		depends on (FB = y) && PCI
	549		select FB_CFB_FILLRECT
	550		select FB_CFB_COPYAREA
	551		select FB_CFB_IMAGEBLIT
	552		help
	553		This is the frame buffer device driver for the Asiliant 69030 chipset
	554
	555		config FB_IMSTT
	556		bool "IMS Twin Turbo display support"
	557		depends on (FB = y) && PCI
	558		select FB_CFB_IMAGEBLIT
	559		select FB_MACMODES if PPC
	560		help
	561		The IMS Twin Turbo is a PCI-based frame buffer card bundled with
	562		many Macintosh and compatible computers.
	563
	564		config FB_VGA16
	565		tristate "VGA 16-color graphics support"
	566		depends on FB && (X86 || PPC)
	567		select FB_CFB_FILLRECT
	568		select FB_CFB_COPYAREA
	569		select FB_CFB_IMAGEBLIT
	570		select VGASTATE
	571		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	572		help
	573		This is the frame buffer device driver for VGA 16 color graphic
	574		cards. Say Y if you have such a card.
	575
	576		To compile this driver as a module, choose M here: the
	577		module will be called vga16fb.
	578
	579		config FB_BF54X_LQ043
	580		tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)"
	581		depends on FB && (BF54x) && !BF542
	582		select FB_CFB_FILLRECT
	583		select FB_CFB_COPYAREA
	584		select FB_CFB_IMAGEBLIT
	585		help
	586		This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD
	587
	588		config FB_BFIN_T350MCQB
	589		tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)"
	590		depends on FB && BLACKFIN
	591		select BFIN_GPTIMERS
	592		select FB_CFB_FILLRECT
	593		select FB_CFB_COPYAREA
	594		select FB_CFB_IMAGEBLIT
	595		help
	596		This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD
	597		This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
	598		It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
	599
	600		config FB_BFIN_LQ035Q1
	601		tristate "SHARP LQ035Q1DH02 TFT LCD"
	602		depends on FB && BLACKFIN && SPI
	603		select FB_CFB_FILLRECT
	604		select FB_CFB_COPYAREA
	605		select FB_CFB_IMAGEBLIT
	606		select BFIN_GPTIMERS
	607		help
	608		This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
	609		the Blackfin Landscape LCD EZ-Extender Card.
	610		This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
	611		It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
	612
	613		To compile this driver as a module, choose M here: the
	614		module will be called bfin-lq035q1-fb.
	615
	616		config FB_BF537_LQ035
	617		tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
	618		depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
	619		select FB_CFB_FILLRECT
	620		select FB_CFB_COPYAREA
	621		select FB_CFB_IMAGEBLIT
	622		select BFIN_GPTIMERS
	623		help
	624		This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
	625		attached to a BF537.
	626
	627		To compile this driver as a module, choose M here: the
	628		module will be called bf537-lq035.
	629
	630		config FB_BFIN_7393
	631		tristate "Blackfin ADV7393 Video encoder"
	632		depends on FB && BLACKFIN
	633		select I2C
	634		select FB_CFB_FILLRECT
	635		select FB_CFB_COPYAREA
	636		select FB_CFB_IMAGEBLIT
	637		help
	638		This is the framebuffer device for a ADV7393 video encoder
	639		attached to a Blackfin on the PPI port.
	640		If your Blackfin board has a ADV7393 select Y.
	641
	642		To compile this driver as a module, choose M here: the
	643		module will be called bfin_adv7393fb.
	644
	645		choice
	646		prompt "Video mode support"
	647		depends on FB_BFIN_7393
	648		default NTSC
	649
	650		config NTSC
	651		bool 'NTSC 720x480'
	652
	653		config PAL
	654		bool 'PAL 720x576'
	655
	656		config NTSC_640x480
	657		bool 'NTSC 640x480 (Experimental)'
	658
	659		config PAL_640x480
	660		bool 'PAL 640x480 (Experimental)'
	661
	662		config NTSC_YCBCR
	663		bool 'NTSC 720x480 YCbCR input'
	664
	665		config PAL_YCBCR
	666		bool 'PAL 720x576 YCbCR input'
	667
	668		endchoice
	669
	670		choice
	671		prompt "Size of ADV7393 frame buffer memory Single/Double Size"
	672		depends on (FB_BFIN_7393)
	673		default ADV7393_1XMEM
	674
	675		config ADV7393_1XMEM
	676		bool 'Single'
	677
	678		config ADV7393_2XMEM
	679		bool 'Double'
	680		endchoice
	681
	682		config FB_STI
	683		tristate "HP STI frame buffer device support"
	684		depends on FB && PARISC
	685		select FB_CFB_FILLRECT
	686		select FB_CFB_COPYAREA
	687		select FB_CFB_IMAGEBLIT
	688		select STI_CONSOLE
	689		select VT
	690		default y
	691		---help---
	692		STI refers to the HP "Standard Text Interface" which is a set of
	693		BIOS routines contained in a ROM chip in HP PA-RISC based machines.
	694		Enabling this option will implement the linux framebuffer device
	695		using calls to the STI BIOS routines for initialisation.
	696
	697		If you enable this option, you will get a planar framebuffer device
	698		/dev/fb which will work on the most common HP graphic cards of the
	699		NGLE family, including the artist chips (in the 7xx and Bxxx series),
	700		HCRX, HCRX24, CRX, CRX24 and VisEG series.
	701
	702		It is safe to enable this option, so you should probably say "Y".
	703
	704		config FB_MAC
	705		bool "Generic Macintosh display support"
	706		depends on (FB = y) && MAC
	707		select FB_CFB_FILLRECT
	708		select FB_CFB_COPYAREA
	709		select FB_CFB_IMAGEBLIT
	710		select FB_MACMODES
	711
	712		config FB_HP300
	713		bool
	714		depends on (FB = y) && DIO
	715		select FB_CFB_IMAGEBLIT
	716		default y
	717
	718		config FB_TGA
	719		tristate "TGA/SFB+ framebuffer support"
	720		depends on FB && (ALPHA || TC)
	721		select FB_CFB_FILLRECT
	722		select FB_CFB_COPYAREA
	723		select FB_CFB_IMAGEBLIT
	724		select BITREVERSE
	725		---help---
	726		This is the frame buffer device driver for generic TGA and SFB+
	727		graphic cards. These include DEC ZLXp-E1, -E2 and -E3 PCI cards,
	728		also known as PBXGA-A, -B and -C, and DEC ZLX-E1, -E2 and -E3
	729		TURBOchannel cards, also known as PMAGD-A, -B and -C.
	730
	731		Due to hardware limitations ZLX-E2 and E3 cards are not supported
	732		for DECstation 5000/200 systems. Additionally due to firmware
	733		limitations these cards may cause troubles with booting DECstation
	734		5000/240 and /260 systems, but are fully supported under Linux if
	735		you manage to get it going. ;-)
	736
	737		Say Y if you have one of those.
	738
	739		config FB_UVESA
	740		tristate "Userspace VESA VGA graphics support"
	741		depends on FB && CONNECTOR
	742		select FB_CFB_FILLRECT
	743		select FB_CFB_COPYAREA
	744		select FB_CFB_IMAGEBLIT
	745		select FB_MODE_HELPERS
	746		help
	747		This is the frame buffer driver for generic VBE 2.0 compliant
	748		graphic cards. It can also take advantage of VBE 3.0 features,
	749		such as refresh rate adjustment.
	750
	751		This driver generally provides more features than vesafb but
	752		requires a userspace helper application called 'v86d'. See
	753		<file:Documentation/fb/uvesafb.txt> for more information.
	754
	755		If unsure, say N.
	756
	757		config FB_VESA
	758		bool "VESA VGA graphics support"
	759		depends on (FB = y) && X86
	760		select FB_CFB_FILLRECT
	761		select FB_CFB_COPYAREA
	762		select FB_CFB_IMAGEBLIT
	763		select FB_BOOT_VESA_SUPPORT
	764		help
	765		This is the frame buffer device driver for generic VESA 2.0
	766		compliant graphic cards. The older VESA 1.2 cards are not supported.
	767		You will get a boot time penguin logo at no additional cost. Please
	768		read <file:Documentation/fb/vesafb.txt>. If unsure, say Y.
	769
	770		config FB_EFI
	771		bool "EFI-based Framebuffer Support"
	772		depends on (FB = y) && X86 && EFI
	773		select FB_CFB_FILLRECT
	774		select FB_CFB_COPYAREA
	775		select FB_CFB_IMAGEBLIT
	776		help
	777		This is the EFI frame buffer device driver. If the firmware on
	778		your platform is EFI 1.10 or UEFI 2.0, select Y to add support for
	779		using the EFI framebuffer as your console.
	780
	781		config FB_N411
	782		tristate "N411 Apollo/Hecuba devkit support"
	783		depends on FB && X86 && MMU
	784		select FB_SYS_FILLRECT
	785		select FB_SYS_COPYAREA
	786		select FB_SYS_IMAGEBLIT
	787		select FB_SYS_FOPS
	788		select FB_DEFERRED_IO
	789		select FB_HECUBA
	790		help
	791		This enables support for the Apollo display controller in its
	792		Hecuba form using the n411 devkit.
	793
	794		config FB_HGA
	795		tristate "Hercules mono graphics support"
	796		depends on FB && X86
	797		help
	798		Say Y here if you have a Hercules mono graphics card.
	799
	800		To compile this driver as a module, choose M here: the
	801		module will be called hgafb.
	802
	803		As this card technology is at least 25 years old,
	804		most people will answer N here.
	805
	806		config FB_SGIVW
	807		tristate "SGI Visual Workstation framebuffer support"
	808		depends on FB && X86_VISWS
	809		select FB_CFB_FILLRECT
	810		select FB_CFB_COPYAREA
	811		select FB_CFB_IMAGEBLIT
	812		help
	813		SGI Visual Workstation support for framebuffer graphics.
	814
	815		config FB_GBE
	816		bool "SGI Graphics Backend frame buffer support"
	817		depends on (FB = y) && (SGI_IP32 || X86_VISWS)
	818		select FB_CFB_FILLRECT
	819		select FB_CFB_COPYAREA
	820		select FB_CFB_IMAGEBLIT
	821		help
	822		This is the frame buffer device driver for SGI Graphics Backend.
	823		This chip is used in SGI O2 and Visual Workstation 320/540.
	824
	825		config FB_GBE_MEM
	826		int "Video memory size in MB"
	827		depends on FB_GBE
	828		default 4
	829		help
	830		This is the amount of memory reserved for the framebuffer,
	831		which can be any value between 1MB and 8MB.
	832
	833		config FB_SBUS
	834		bool "SBUS and UPA framebuffers"
	835		depends on (FB = y) && SPARC
	836		help
	837		Say Y if you want support for SBUS or UPA based frame buffer device.
	838
	839		config FB_BW2
	840		bool "BWtwo support"
	841		depends on (FB = y) && (SPARC && FB_SBUS)
	842		select FB_CFB_FILLRECT
	843		select FB_CFB_COPYAREA
	844		select FB_CFB_IMAGEBLIT
	845		help
	846		This is the frame buffer device driver for the BWtwo frame buffer.
	847
	848		config FB_CG3
	849		bool "CGthree support"
	850		depends on (FB = y) && (SPARC && FB_SBUS)
	851		select FB_CFB_FILLRECT
	852		select FB_CFB_COPYAREA
	853		select FB_CFB_IMAGEBLIT
	854		help
	855		This is the frame buffer device driver for the CGthree frame buffer.
	856
	857		config FB_CG6
	858		bool "CGsix (GX,TurboGX) support"
	859		depends on (FB = y) && (SPARC && FB_SBUS)
	860		select FB_CFB_COPYAREA
	861		select FB_CFB_IMAGEBLIT
	862		help
	863		This is the frame buffer device driver for the CGsix (GX, TurboGX)
	864		frame buffer.
	865
	866		config FB_FFB
	867		bool "Creator/Creator3D/Elite3D support"
	868		depends on FB_SBUS && SPARC64
	869		select FB_CFB_COPYAREA
	870		select FB_CFB_IMAGEBLIT
	871		help
	872		This is the frame buffer device driver for the Creator, Creator3D,
	873		and Elite3D graphics boards.
	874
	875		config FB_TCX
	876		bool "TCX (SS4/SS5 only) support"
	877		depends on FB_SBUS
	878		select FB_CFB_FILLRECT
	879		select FB_CFB_COPYAREA
	880		select FB_CFB_IMAGEBLIT
	881		help
	882		This is the frame buffer device driver for the TCX 24/8bit frame
	883		buffer.
	884
	885		config FB_CG14
	886		bool "CGfourteen (SX) support"
	887		depends on FB_SBUS
	888		select FB_CFB_FILLRECT
	889		select FB_CFB_COPYAREA
	890		select FB_CFB_IMAGEBLIT
	891		help
	892		This is the frame buffer device driver for the CGfourteen frame
	893		buffer on Desktop SPARCsystems with the SX graphics option.
	894
	895		config FB_P9100
	896		bool "P9100 (Sparcbook 3 only) support"
	897		depends on FB_SBUS
	898		select FB_CFB_FILLRECT
	899		select FB_CFB_COPYAREA
	900		select FB_CFB_IMAGEBLIT
	901		help
	902		This is the frame buffer device driver for the P9100 card
	903		supported on Sparcbook 3 machines.
	904
	905		config FB_LEO
	906		bool "Leo (ZX) support"
	907		depends on FB_SBUS
	908		select FB_CFB_FILLRECT
	909		select FB_CFB_COPYAREA
	910		select FB_CFB_IMAGEBLIT
	911		help
	912		This is the frame buffer device driver for the SBUS-based Sun ZX
	913		(leo) frame buffer cards.
	914
	915		config FB_IGA
	916		bool "IGA 168x display support"
	917		depends on (FB = y) && SPARC32
	918		select FB_CFB_FILLRECT
	919		select FB_CFB_COPYAREA
	920		select FB_CFB_IMAGEBLIT
	921		help
	922		This is the framebuffer device for the INTERGRAPHICS 1680 and
	923		successor frame buffer cards.
	924
	925		config FB_XVR500
	926		bool "Sun XVR-500 3DLABS Wildcat support"
	927		depends on (FB = y) && PCI && SPARC64
	928		select FB_CFB_FILLRECT
	929		select FB_CFB_COPYAREA
	930		select FB_CFB_IMAGEBLIT
	931		help
	932		This is the framebuffer device for the Sun XVR-500 and similar
	933		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	934		only works on sparc64 systems where the system firmware has
	935		mostly initialized the card already. It is treated as a
	936		completely dumb framebuffer device.
	937
	938		config FB_XVR2500
	939		bool "Sun XVR-2500 3DLABS Wildcat support"
	940		depends on (FB = y) && PCI && SPARC64
	941		select FB_CFB_FILLRECT
	942		select FB_CFB_COPYAREA
	943		select FB_CFB_IMAGEBLIT
	944		help
	945		This is the framebuffer device for the Sun XVR-2500 and similar
	946		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	947		only works on sparc64 systems where the system firmware has
	948		mostly initialized the card already. It is treated as a
	949		completely dumb framebuffer device.
	950
	951		config FB_XVR1000
	952		bool "Sun XVR-1000 support"
	953		depends on (FB = y) && SPARC64
	954		select FB_CFB_FILLRECT
	955		select FB_CFB_COPYAREA
	956		select FB_CFB_IMAGEBLIT
	957		help
	958		This is the framebuffer device for the Sun XVR-1000 and similar
	959		graphics cards. The driver only works on sparc64 systems where
	960		the system firmware has mostly initialized the card already. It
	961		is treated as a completely dumb framebuffer device.
	962
	963		config FB_PVR2
	964		tristate "NEC PowerVR 2 display support"
	965		depends on FB && SH_DREAMCAST
	966		select FB_CFB_FILLRECT
	967		select FB_CFB_COPYAREA
	968		select FB_CFB_IMAGEBLIT
	969		---help---
	970		Say Y here if you have a PowerVR 2 card in your box. If you plan to
	971		run linux on your Dreamcast, you will have to say Y here.
	972		This driver may or may not work on other PowerVR 2 cards, but is
	973		totally untested. Use at your own risk. If unsure, say N.
	974
	975		To compile this driver as a module, choose M here: the
	976		module will be called pvr2fb.
	977
	978		You can pass several parameters to the driver at boot time or at
	979		module load time. The parameters look like "video=pvr2:XXX", where
	980		the meaning of XXX can be found at the end of the main source file
	981		(<file:drivers/video/pvr2fb.c>). Please see the file
	982		<file:Documentation/fb/pvr2fb.txt>.
	983
	984		config FB_EPSON1355
	985		bool "Epson 1355 framebuffer support"
	986		depends on (FB = y) && ARCH_CEIVA
	987		select FB_CFB_FILLRECT
	988		select FB_CFB_COPYAREA
	989		select FB_CFB_IMAGEBLIT
	990		help
	991		Build in support for the SED1355 Epson Research Embedded RAMDAC
	992		LCD/CRT Controller (since redesignated as the S1D13505) as a
	993		framebuffer. Product specs at
	994		<http://vdc.epson.com/>.
	995
	996		config FB_S1D13XXX
	997		tristate "Epson S1D13XXX framebuffer support"
	998		depends on FB
	999		select FB_CFB_FILLRECT
	1000		select FB_CFB_COPYAREA
	1001		select FB_CFB_IMAGEBLIT
	1002		help
	1003		Support for S1D13XXX framebuffer device family (currently only
	1004		working with S1D13806). Product specs at
	1005		<http://vdc.epson.com/>
	1006
	1007		config FB_ATMEL
	1008		tristate "AT91/AT32 LCD Controller support"
	1009		depends on FB && HAVE_FB_ATMEL
	1010		select FB_CFB_FILLRECT
	1011		select FB_CFB_COPYAREA
	1012		select FB_CFB_IMAGEBLIT
	1013		help
	1014		This enables support for the AT91/AT32 LCD Controller.
	1015
	1016		config FB_INTSRAM
	1017		bool "Frame Buffer in internal SRAM"
	1018		depends on FB_ATMEL && ARCH_AT91SAM9261
	1019		help
	1020		Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
	1021		to let frame buffer in external SDRAM.
	1022
	1023		config FB_ATMEL_STN
	1024		bool "Use a STN display with AT91/AT32 LCD Controller"
	1025		depends on FB_ATMEL && (MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK)
	1026		default n
	1027		help
	1028		Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
	1029		Controller. Say N if you want to connect a TFT.
	1030
	1031		If unsure, say N.
	1032
	1033		config FB_NVIDIA
	1034		tristate "nVidia Framebuffer Support"
	1035		depends on FB && PCI
	1036		select FB_BACKLIGHT if FB_NVIDIA_BACKLIGHT
	1037		select FB_MODE_HELPERS
	1038		select FB_CFB_FILLRECT
	1039		select FB_CFB_COPYAREA
	1040		select FB_CFB_IMAGEBLIT
	1041		select BITREVERSE
	1042		select VGASTATE
	1043		help
	1044		This driver supports graphics boards with the nVidia chips, TNT
	1045		and newer. For very old chipsets, such as the RIVA128, then use
	1046		the rivafb.
	1047		Say Y if you have such a graphics board.
	1048
	1049		To compile this driver as a module, choose M here: the
	1050		module will be called nvidiafb.
	1051
	1052		config FB_NVIDIA_I2C
	1053		bool "Enable DDC Support"
	1054		depends on FB_NVIDIA
	1055		select FB_DDC
	1056		help
	1057		This enables I2C support for nVidia Chipsets. This is used
	1058		only for getting EDID information from the attached display
	1059		allowing for robust video mode handling and switching.
	1060
	1061		Because fbdev-2.6 requires that drivers must be able to
	1062		independently validate video mode parameters, you should say Y
	1063		here.
	1064
	1065		config FB_NVIDIA_DEBUG
	1066		bool "Lots of debug output"
	1067		depends on FB_NVIDIA
	1068		default n
	1069		help
	1070		Say Y here if you want the nVidia driver to output all sorts
	1071		of debugging information to provide to the maintainer when
	1072		something goes wrong.
	1073
	1074		config FB_NVIDIA_BACKLIGHT
	1075		bool "Support for backlight control"
	1076		depends on FB_NVIDIA
	1077		default y
	1078		help
	1079		Say Y here if you want to control the backlight of your display.
	1080
	1081		config FB_RIVA
	1082		tristate "nVidia Riva support"
	1083		depends on FB && PCI
	1084		select FB_BACKLIGHT if FB_RIVA_BACKLIGHT
	1085		select FB_MODE_HELPERS
	1086		select FB_CFB_FILLRECT
	1087		select FB_CFB_COPYAREA
	1088		select FB_CFB_IMAGEBLIT
	1089		select BITREVERSE
	1090		select VGASTATE
	1091		help
	1092		This driver supports graphics boards with the nVidia Riva/Geforce
	1093		chips.
	1094		Say Y if you have such a graphics board.
	1095
	1096		To compile this driver as a module, choose M here: the
	1097		module will be called rivafb.
	1098
	1099		config FB_RIVA_I2C
	1100		bool "Enable DDC Support"
	1101		depends on FB_RIVA
	1102		select FB_DDC
	1103		help
	1104		This enables I2C support for nVidia Chipsets. This is used
	1105		only for getting EDID information from the attached display
	1106		allowing for robust video mode handling and switching.
	1107
	1108		Because fbdev-2.6 requires that drivers must be able to
	1109		independently validate video mode parameters, you should say Y
	1110		here.
	1111
	1112		config FB_RIVA_DEBUG
	1113		bool "Lots of debug output"
	1114		depends on FB_RIVA
	1115		default n
	1116		help
	1117		Say Y here if you want the Riva driver to output all sorts
	1118		of debugging information to provide to the maintainer when
	1119		something goes wrong.
	1120
	1121		config FB_RIVA_BACKLIGHT
	1122		bool "Support for backlight control"
	1123		depends on FB_RIVA
	1124		default y
	1125		help
	1126		Say Y here if you want to control the backlight of your display.
	1127
	1128		config FB_I810
	1129		tristate "Intel 810/815 support (EXPERIMENTAL)"
	1130		depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
	1131		select FB_MODE_HELPERS
	1132		select FB_CFB_FILLRECT
	1133		select FB_CFB_COPYAREA
	1134		select FB_CFB_IMAGEBLIT
	1135		select VGASTATE
	1136		help
	1137		This driver supports the on-board graphics built in to the Intel 810
	1138		and 815 chipsets. Say Y if you have and plan to use such a board.
	1139
	1140		To compile this driver as a module, choose M here: the
	1141		module will be called i810fb.
	1142
	1143		For more information, please read
	1144		<file:Documentation/fb/intel810.txt>
	1145
	1146		config FB_I810_GTF
	1147		bool "use VESA Generalized Timing Formula"
	1148		depends on FB_I810
	1149		help
	1150		If you say Y, then the VESA standard, Generalized Timing Formula
	1151		or GTF, will be used to calculate the required video timing values
	1152		per video mode. Since the GTF allows nondiscrete timings
	1153		(nondiscrete being a range of values as opposed to discrete being a
	1154		set of values), you'll be able to use any combination of horizontal
	1155		and vertical resolutions, and vertical refresh rates without having
	1156		to specify your own timing parameters. This is especially useful
	1157		to maximize the performance of an aging display, or if you just
	1158		have a display with nonstandard dimensions. A VESA compliant
	1159		monitor is recommended, but can still work with non-compliant ones.
	1160		If you need or want this, then select this option. The timings may
	1161		not be compliant with Intel's recommended values. Use at your own
	1162		risk.
	1163
	1164		If you say N, the driver will revert to discrete video timings
	1165		using a set recommended by Intel in their documentation.
	1166
	1167		If unsure, say N.
	1168
	1169		config FB_I810_I2C
	1170		bool "Enable DDC Support"
	1171		depends on FB_I810 && FB_I810_GTF
	1172		select FB_DDC
	1173		help
	1174
	1175		config FB_LE80578
	1176		tristate "Intel LE80578 (Vermilion) support"
	1177		depends on FB && PCI && X86
	1178		select FB_MODE_HELPERS
	1179		select FB_CFB_FILLRECT
	1180		select FB_CFB_COPYAREA
	1181		select FB_CFB_IMAGEBLIT
	1182		help
	1183		This driver supports the LE80578 (Vermilion Range) chipset
	1184
	1185		config FB_CARILLO_RANCH
	1186		tristate "Intel Carillo Ranch support"
	1187		depends on FB_LE80578 && FB && PCI && X86
	1188		help
	1189		This driver supports the LE80578 (Carillo Ranch) board
	1190
	1191		config FB_INTEL
	1192		tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support (EXPERIMENTAL)"
	1193		depends on EXPERIMENTAL && FB && PCI && X86 && AGP_INTEL && EXPERT
	1194		select FB_MODE_HELPERS
	1195		select FB_CFB_FILLRECT
	1196		select FB_CFB_COPYAREA
	1197		select FB_CFB_IMAGEBLIT
	1198		select FB_BOOT_VESA_SUPPORT if FB_INTEL = y
	1199		depends on !DRM_I915
	1200		help
	1201		This driver supports the on-board graphics built in to the Intel
	1202		830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/965G/965GM chipsets.
	1203		Say Y if you have and plan to use such a board.
	1204
	1205		To make FB_INTELFB=Y work you need to say AGP_INTEL=y too.
	1206
	1207		To compile this driver as a module, choose M here: the
	1208		module will be called intelfb.
	1209
	1210		For more information, please read <file:Documentation/fb/intelfb.txt>
	1211
	1212		config FB_INTEL_DEBUG
	1213		bool "Intel driver Debug Messages"
	1214		depends on FB_INTEL
	1215		---help---
	1216		Say Y here if you want the Intel driver to output all sorts
	1217		of debugging information to provide to the maintainer when
	1218		something goes wrong.
	1219
	1220		config FB_INTEL_I2C
	1221		bool "DDC/I2C for Intel framebuffer support"
	1222		depends on FB_INTEL
	1223		select FB_DDC
	1224		default y
	1225		help
	1226		Say Y here if you want DDC/I2C support for your on-board Intel graphics.
	1227
	1228		config FB_MATROX
	1229		tristate "Matrox acceleration"
	1230		depends on FB && PCI
	1231		select FB_CFB_FILLRECT
	1232		select FB_CFB_COPYAREA
	1233		select FB_CFB_IMAGEBLIT
	1234		select FB_TILEBLITTING
	1235		select FB_MACMODES if PPC_PMAC
	1236		---help---
	1237		Say Y here if you have a Matrox Millennium, Matrox Millennium II,
	1238		Matrox Mystique, Matrox Mystique 220, Matrox Productiva G100, Matrox
	1239		Mystique G200, Matrox Millennium G200, Matrox Marvel G200 video,
	1240		Matrox G400, G450 or G550 card in your box.
	1241
	1242		To compile this driver as a module, choose M here: the
	1243		module will be called matroxfb.
	1244
	1245		You can pass several parameters to the driver at boot time or at
	1246		module load time. The parameters look like "video=matroxfb:XXX", and
	1247		are described in <file:Documentation/fb/matroxfb.txt>.
	1248
	1249		config FB_MATROX_MILLENIUM
	1250		bool "Millennium I/II support"
	1251		depends on FB_MATROX
	1252		help
	1253		Say Y here if you have a Matrox Millennium or Matrox Millennium II
	1254		video card. If you select "Advanced lowlevel driver options" below,
	1255		you should check 4 bpp packed pixel, 8 bpp packed pixel, 16 bpp
	1256		packed pixel, 24 bpp packed pixel and 32 bpp packed pixel. You can
	1257		also use font widths different from 8.
	1258
	1259		config FB_MATROX_MYSTIQUE
	1260		bool "Mystique support"
	1261		depends on FB_MATROX
	1262		help
	1263		Say Y here if you have a Matrox Mystique or Matrox Mystique 220
	1264		video card. If you select "Advanced lowlevel driver options" below,
	1265		you should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp
	1266		packed pixel and 32 bpp packed pixel. You can also use font widths
	1267		different from 8.
	1268
	1269		config FB_MATROX_G
	1270		bool "G100/G200/G400/G450/G550 support"
	1271		depends on FB_MATROX
	1272		---help---
	1273		Say Y here if you have a Matrox G100, G200, G400, G450 or G550 based
	1274		video card. If you select "Advanced lowlevel driver options", you
	1275		should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp packed
	1276		pixel and 32 bpp packed pixel. You can also use font widths
	1277		different from 8.
	1278
	1279		If you need support for G400 secondary head, you must say Y to
	1280		"Matrox I2C support" and "G400 second head support" right below.
	1281		G450/G550 secondary head and digital output are supported without
	1282		additional modules.
	1283
	1284		The driver starts in monitor mode. You must use the matroxset tool
	1285		(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
	1286		swap primary and secondary head outputs, or to change output mode.
	1287		Secondary head driver always start in 640x480 resolution and you
	1288		must use fbset to change it.
	1289
	1290		Do not forget that second head supports only 16 and 32 bpp
	1291		packed pixels, so it is a good idea to compile them into the kernel
	1292		too. You can use only some font widths, as the driver uses generic
	1293		painting procedures (the secondary head does not use acceleration
	1294		engine).
	1295
	1296		G450/G550 hardware can display TV picture only from secondary CRTC,
	1297		and it performs no scaling, so picture must have 525 or 625 lines.
	1298
	1299		config FB_MATROX_I2C
	1300		tristate "Matrox I2C support"
	1301		depends on FB_MATROX
	1302		select FB_DDC
	1303		---help---
	1304		This drivers creates I2C buses which are needed for accessing the
	1305		DDC (I2C) bus present on all Matroxes, an I2C bus which
	1306		interconnects Matrox optional devices, like MGA-TVO on G200 and
	1307		G400, and the secondary head DDC bus, present on G400 only.
	1308
	1309		You can say Y or M here if you want to experiment with monitor
	1310		detection code. You must say Y or M here if you want to use either
	1311		second head of G400 or MGA-TVO on G200 or G400.
	1312
	1313		If you compile it as module, it will create a module named
	1314		i2c-matroxfb.
	1315
	1316		config FB_MATROX_MAVEN
	1317		tristate "G400 second head support"
	1318		depends on FB_MATROX_G && FB_MATROX_I2C
	1319		---help---
	1320		WARNING !!! This support does not work with G450 !!!
	1321
	1322		Say Y or M here if you want to use a secondary head (meaning two
	1323		monitors in parallel) on G400 or MGA-TVO add-on on G200. Secondary
	1324		head is not compatible with accelerated XFree 3.3.x SVGA servers -
	1325		secondary head output is blanked while you are in X. With XFree
	1326		3.9.17 preview you can use both heads if you use SVGA over fbdev or
	1327		the fbdev driver on first head and the fbdev driver on second head.
	1328
	1329		If you compile it as module, two modules are created,
	1330		matroxfb_crtc2 and matroxfb_maven. Matroxfb_maven is needed for
	1331		both G200 and G400, matroxfb_crtc2 is needed only by G400. You must
	1332		also load i2c-matroxfb to get it to run.
	1333
	1334		The driver starts in monitor mode and you must use the matroxset
	1335		tool (available at
	1336		<ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to switch it to
	1337		PAL or NTSC or to swap primary and secondary head outputs.
	1338		Secondary head driver also always start in 640x480 resolution, you
	1339		must use fbset to change it.
	1340
	1341		Also do not forget that second head supports only 16 and 32 bpp
	1342		packed pixels, so it is a good idea to compile them into the kernel
	1343		too. You can use only some font widths, as the driver uses generic
	1344		painting procedures (the secondary head does not use acceleration
	1345		engine).
	1346
	1347		config FB_RADEON
	1348		tristate "ATI Radeon display support"
	1349		depends on FB && PCI
	1350		select FB_BACKLIGHT if FB_RADEON_BACKLIGHT
	1351		select FB_MODE_HELPERS
	1352		select FB_CFB_FILLRECT
	1353		select FB_CFB_COPYAREA
	1354		select FB_CFB_IMAGEBLIT
	1355		select FB_MACMODES if PPC_OF
	1356		help
	1357		Choose this option if you want to use an ATI Radeon graphics card as
	1358		a framebuffer device. There are both PCI and AGP versions. You
	1359		don't need to choose this to run the Radeon in plain VGA mode.
	1360
	1361		There is a product page at
	1362		http://products.amd.com/en-us/GraphicCardResult.aspx
	1363
	1364		config FB_RADEON_I2C
	1365		bool "DDC/I2C for ATI Radeon support"
	1366		depends on FB_RADEON
	1367		select FB_DDC
	1368		default y
	1369		help
	1370		Say Y here if you want DDC/I2C support for your Radeon board.
	1371
	1372		config FB_RADEON_BACKLIGHT
	1373		bool "Support for backlight control"
	1374		depends on FB_RADEON
	1375		default y
	1376		help
	1377		Say Y here if you want to control the backlight of your display.
	1378
	1379		config FB_RADEON_DEBUG
	1380		bool "Lots of debug output from Radeon driver"
	1381		depends on FB_RADEON
	1382		default n
	1383		help
	1384		Say Y here if you want the Radeon driver to output all sorts
	1385		of debugging information to provide to the maintainer when
	1386		something goes wrong.
	1387
	1388		config FB_ATY128
	1389		tristate "ATI Rage128 display support"
	1390		depends on FB && PCI
	1391		select FB_CFB_FILLRECT
	1392		select FB_CFB_COPYAREA
	1393		select FB_CFB_IMAGEBLIT
	1394		select FB_BACKLIGHT if FB_ATY128_BACKLIGHT
	1395		select FB_MACMODES if PPC_PMAC
	1396		help
	1397		This driver supports graphics boards with the ATI Rage128 chips.
	1398		Say Y if you have such a graphics board and read
	1399		<file:Documentation/fb/aty128fb.txt>.
	1400
	1401		To compile this driver as a module, choose M here: the
	1402		module will be called aty128fb.
	1403
	1404		config FB_ATY128_BACKLIGHT
	1405		bool "Support for backlight control"
	1406		depends on FB_ATY128
	1407		default y
	1408		help
	1409		Say Y here if you want to control the backlight of your display.
	1410
	1411		config FB_ATY
	1412		tristate "ATI Mach64 display support" if PCI || ATARI
	1413		depends on FB && !SPARC32
	1414		select FB_CFB_FILLRECT
	1415		select FB_CFB_COPYAREA
	1416		select FB_CFB_IMAGEBLIT
	1417		select FB_BACKLIGHT if FB_ATY_BACKLIGHT
	1418		select FB_MACMODES if PPC
	1419		help
	1420		This driver supports graphics boards with the ATI Mach64 chips.
	1421		Say Y if you have such a graphics board.
	1422
	1423		To compile this driver as a module, choose M here: the
	1424		module will be called atyfb.
	1425
	1426		config FB_ATY_CT
	1427		bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support"
	1428		depends on PCI && FB_ATY
	1429		default y if SPARC64 && PCI
	1430		help
	1431		Say Y here to support use of ATI's 64-bit Rage boards (or other
	1432		boards based on the Mach64 CT, VT, GT, and LT chipsets) as a
	1433		framebuffer device. The ATI product support page for these boards
	1434		is at <http://support.ati.com/products/pc/mach64/mach64.html>.
	1435
	1436		config FB_ATY_GENERIC_LCD
	1437		bool "Mach64 generic LCD support (EXPERIMENTAL)"
	1438		depends on FB_ATY_CT
	1439		help
	1440		Say Y if you have a laptop with an ATI Rage LT PRO, Rage Mobility,
	1441		Rage XC, or Rage XL chipset.
	1442
	1443		config FB_ATY_GX
	1444		bool "Mach64 GX support" if PCI
	1445		depends on FB_ATY
	1446		default y if ATARI
	1447		help
	1448		Say Y here to support use of the ATI Mach64 Graphics Expression
	1449		board (or other boards based on the Mach64 GX chipset) as a
	1450		framebuffer device. The ATI product support page for these boards
	1451		is at
	1452		<http://support.ati.com/products/pc/mach64/graphics_xpression.html>.
	1453
	1454		config FB_ATY_BACKLIGHT
	1455		bool "Support for backlight control"
	1456		depends on FB_ATY
	1457		default y
	1458		help
	1459		Say Y here if you want to control the backlight of your display.
	1460
	1461		config FB_S3
	1462		tristate "S3 Trio/Virge support"
	1463		depends on FB && PCI
	1464		select FB_CFB_FILLRECT
	1465		select FB_CFB_COPYAREA
	1466		select FB_CFB_IMAGEBLIT
	1467		select FB_TILEBLITTING
	1468		select FB_SVGALIB
	1469		select VGASTATE
	1470		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1471		---help---
	1472		Driver for graphics boards with S3 Trio / S3 Virge chip.
	1473
	1474		config FB_S3_DDC
	1475		bool "DDC for S3 support"
	1476		depends on FB_S3
	1477		select FB_DDC
	1478		default y
	1479		help
	1480		Say Y here if you want DDC support for your S3 graphics card.
	1481
	1482		config FB_SAVAGE
	1483		tristate "S3 Savage support"
	1484		depends on FB && PCI && EXPERIMENTAL
	1485		select FB_MODE_HELPERS
	1486		select FB_CFB_FILLRECT
	1487		select FB_CFB_COPYAREA
	1488		select FB_CFB_IMAGEBLIT
	1489		select VGASTATE
	1490		help
	1491		This driver supports notebooks and computers with S3 Savage PCI/AGP
	1492		chips.
	1493
	1494		Say Y if you have such a graphics card.
	1495
	1496		To compile this driver as a module, choose M here; the module
	1497		will be called savagefb.
	1498
	1499		config FB_SAVAGE_I2C
	1500		bool "Enable DDC2 Support"
	1501		depends on FB_SAVAGE
	1502		select FB_DDC
	1503		help
	1504		This enables I2C support for S3 Savage Chipsets. This is used
	1505		only for getting EDID information from the attached display
	1506		allowing for robust video mode handling and switching.
	1507
	1508		Because fbdev-2.6 requires that drivers must be able to
	1509		independently validate video mode parameters, you should say Y
	1510		here.
	1511
	1512		config FB_SAVAGE_ACCEL
	1513		bool "Enable Console Acceleration"
	1514		depends on FB_SAVAGE
	1515		default n
	1516		help
	1517		This option will compile in console acceleration support. If
	1518		the resulting framebuffer console has bothersome glitches, then
	1519		choose N here.
	1520
	1521		config FB_SIS
	1522		tristate "SiS/XGI display support"
	1523		depends on FB && PCI
	1524		select FB_CFB_FILLRECT
	1525		select FB_CFB_COPYAREA
	1526		select FB_CFB_IMAGEBLIT
	1527		select FB_BOOT_VESA_SUPPORT if FB_SIS = y
	1528		help
	1529		This is the frame buffer device driver for the SiS 300, 315, 330
	1530		and 340 series as well as XGI V3XT, V5, V8, Z7 graphics chipsets.
	1531		Specs available at <http://www.sis.com> and <http://www.xgitech.com>.
	1532
	1533		To compile this driver as a module, choose M here; the module
	1534		will be called sisfb.
	1535
	1536		config FB_SIS_300
	1537		bool "SiS 300 series support"
	1538		depends on FB_SIS
	1539		help
	1540		Say Y here to support use of the SiS 300/305, 540, 630 and 730.
	1541
	1542		config FB_SIS_315
	1543		bool "SiS 315/330/340 series and XGI support"
	1544		depends on FB_SIS
	1545		help
	1546		Say Y here to support use of the SiS 315, 330 and 340 series
	1547		(315/H/PRO, 55x, 650, 651, 740, 330, 661, 741, 760, 761) as well
	1548		as XGI V3XT, V5, V8 and Z7.
	1549
	1550		config FB_VIA
	1551		tristate "VIA UniChrome (Pro) and Chrome9 display support"
	1552		depends on FB && PCI && X86
	1553		select FB_CFB_FILLRECT
	1554		select FB_CFB_COPYAREA
	1555		select FB_CFB_IMAGEBLIT
	1556		select I2C_ALGOBIT
	1557		select I2C
	1558		select GPIOLIB
	1559		help
	1560		This is the frame buffer device driver for Graphics chips of VIA
	1561		UniChrome (Pro) Family (CLE266,PM800/CN400,P4M800CE/P4M800Pro/
	1562		CN700/VN800,CX700/VX700,P4M890) and Chrome9 Family (K8M890,CN896
	1563		/P4M900,VX800)
	1564		Say Y if you have a VIA UniChrome graphics board.
	1565
	1566		To compile this driver as a module, choose M here: the
	1567		module will be called viafb.
	1568
	1569		if FB_VIA
	1570
	1571		config FB_VIA_DIRECT_PROCFS
	1572		bool "direct hardware access via procfs (DEPRECATED)(DANGEROUS)"
	1573		depends on FB_VIA
	1574		default n
	1575		help
	1576		Allow direct hardware access to some output registers via procfs.
	1577		This is dangerous but may provide the only chance to get the
	1578		correct output device configuration.
	1579		Its use is strongly discouraged.
	1580
	1581		config FB_VIA_X_COMPATIBILITY
	1582		bool "X server compatibility"
	1583		depends on FB_VIA
	1584		default n
	1585		help
	1586		This option reduces the functionality (power saving, ...) of the
	1587		framebuffer to avoid negative impact on the OpenChrome X server.
	1588		If you use any X server other than fbdev you should enable this
	1589		otherwise it should be safe to disable it and allow using all
	1590		features.
	1591
	1592		endif
	1593
	1594		config FB_NEOMAGIC
	1595		tristate "NeoMagic display support"
	1596		depends on FB && PCI
	1597		select FB_MODE_HELPERS
	1598		select FB_CFB_FILLRECT
	1599		select FB_CFB_COPYAREA
	1600		select FB_CFB_IMAGEBLIT
	1601		select VGASTATE
	1602		help
	1603		This driver supports notebooks with NeoMagic PCI chips.
	1604		Say Y if you have such a graphics card.
	1605
	1606		To compile this driver as a module, choose M here: the
	1607		module will be called neofb.
	1608
	1609		config FB_KYRO
	1610		tristate "IMG Kyro support"
	1611		depends on FB && PCI
	1612		select FB_CFB_FILLRECT
	1613		select FB_CFB_COPYAREA
	1614		select FB_CFB_IMAGEBLIT
	1615		help
	1616		Say Y here if you have a STG4000 / Kyro / PowerVR 3 based
	1617		graphics board.
	1618
	1619		To compile this driver as a module, choose M here: the
	1620		module will be called kyrofb.
	1621
	1622		config FB_3DFX
	1623		tristate "3Dfx Banshee/Voodoo3/Voodoo5 display support"
	1624		depends on FB && PCI
	1625		select FB_CFB_IMAGEBLIT
	1626		select FB_CFB_FILLRECT
	1627		select FB_CFB_COPYAREA
	1628		select FB_MODE_HELPERS
	1629		help
	1630		This driver supports graphics boards with the 3Dfx Banshee,
	1631		Voodoo3 or VSA-100 (aka Voodoo4/5) chips. Say Y if you have
	1632		such a graphics board.
	1633
	1634		To compile this driver as a module, choose M here: the
	1635		module will be called tdfxfb.
	1636
	1637		config FB_3DFX_ACCEL
	1638		bool "3Dfx Acceleration functions (EXPERIMENTAL)"
	1639		depends on FB_3DFX && EXPERIMENTAL
	1640		---help---
	1641		This will compile the 3Dfx Banshee/Voodoo3/VSA-100 frame buffer
	1642		device driver with acceleration functions.
	1643
	1644		config FB_3DFX_I2C
	1645		bool "Enable DDC/I2C support"
	1646		depends on FB_3DFX && EXPERIMENTAL
	1647		select FB_DDC
	1648		default y
	1649		help
	1650		Say Y here if you want DDC/I2C support for your 3dfx Voodoo3.
	1651
	1652		config FB_VOODOO1
	1653		tristate "3Dfx Voodoo Graphics (sst1) support"
	1654		depends on FB && PCI
	1655		select FB_CFB_FILLRECT
	1656		select FB_CFB_COPYAREA
	1657		select FB_CFB_IMAGEBLIT
	1658		---help---
	1659		Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
	1660		Voodoo2 (cvg) based graphics card.
	1661
	1662		To compile this driver as a module, choose M here: the
	1663		module will be called sstfb.
	1664
	1665		WARNING: Do not use any application that uses the 3D engine
	1666		(namely glide) while using this driver.
	1667		Please read the <file:Documentation/fb/sstfb.txt> for supported
	1668		options and other important info support.
	1669
	1670		config FB_VT8623
	1671		tristate "VIA VT8623 support"
	1672		depends on FB && PCI
	1673		select FB_CFB_FILLRECT
	1674		select FB_CFB_COPYAREA
	1675		select FB_CFB_IMAGEBLIT
	1676		select FB_TILEBLITTING
	1677		select FB_SVGALIB
	1678		select VGASTATE
	1679		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1680		---help---
	1681		Driver for CastleRock integrated graphics core in the
	1682		VIA VT8623 [Apollo CLE266] chipset.
	1683
	1684		config FB_TRIDENT
	1685		tristate "Trident/CyberXXX/CyberBlade support"
	1686		depends on FB && PCI
	1687		select FB_CFB_FILLRECT
	1688		select FB_CFB_COPYAREA
	1689		select FB_CFB_IMAGEBLIT
	1690		---help---
	1691		This is the frame buffer device driver for Trident PCI/AGP chipsets.
	1692		Supported chipset families are TGUI 9440/96XX, 3DImage, Blade3D
	1693		and Blade XP.
	1694		There are also integrated versions of these chips called CyberXXXX,
	1695		CyberImage or CyberBlade. These chips are mostly found in laptops
	1696		but also on some motherboards including early VIA EPIA motherboards.
	1697		For more information, read <file:Documentation/fb/tridentfb.txt>
	1698
	1699		Say Y if you have such a graphics board.
	1700
	1701		To compile this driver as a module, choose M here: the
	1702		module will be called tridentfb.
	1703
	1704		config FB_ARK
	1705		tristate "ARK 2000PV support"
	1706		depends on FB && PCI
	1707		select FB_CFB_FILLRECT
	1708		select FB_CFB_COPYAREA
	1709		select FB_CFB_IMAGEBLIT
	1710		select FB_TILEBLITTING
	1711		select FB_SVGALIB
	1712		select VGASTATE
	1713		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1714		---help---
	1715		Driver for PCI graphics boards with ARK 2000PV chip
	1716		and ICS 5342 RAMDAC.
	1717
	1718		config FB_PM3
	1719		tristate "Permedia3 support (EXPERIMENTAL)"
	1720		depends on FB && PCI && EXPERIMENTAL
	1721		select FB_CFB_FILLRECT
	1722		select FB_CFB_COPYAREA
	1723		select FB_CFB_IMAGEBLIT
	1724		help
	1725		This is the frame buffer device driver for the 3DLabs Permedia3
	1726		chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 &
	1727		similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000
	1728		and maybe other boards.
	1729
	1730		config FB_CARMINE
	1731		tristate "Fujitsu carmine frame buffer support"
	1732		depends on FB && PCI
	1733		select FB_CFB_FILLRECT
	1734		select FB_CFB_COPYAREA
	1735		select FB_CFB_IMAGEBLIT
	1736		help
	1737		This is the frame buffer device driver for the Fujitsu Carmine chip.
	1738		The driver provides two independent frame buffer devices.
	1739
	1740		choice
	1741		depends on FB_CARMINE
	1742		prompt "DRAM timing"
	1743		default FB_CARMINE_DRAM_EVAL
	1744
	1745		config FB_CARMINE_DRAM_EVAL
	1746		bool "Eval board timings"
	1747		help
	1748		Use timings which work on the eval card.
	1749
	1750		config CARMINE_DRAM_CUSTOM
	1751		bool "Custom board timings"
	1752		help
	1753		Use custom board timings.
	1754		endchoice
	1755
	1756		config FB_AU1100
	1757		bool "Au1100 LCD Driver"
	1758		depends on (FB = y) && MIPS_ALCHEMY
	1759		select FB_CFB_FILLRECT
	1760		select FB_CFB_COPYAREA
	1761		select FB_CFB_IMAGEBLIT
	1762		help
	1763		This is the framebuffer driver for the AMD Au1100 SOC. It can drive
	1764		various panels and CRTs by passing in kernel cmd line option
	1765		au1100fb:panel=<name>.
	1766
	1767		config FB_AU1200
	1768		bool "Au1200 LCD Driver"
	1769		depends on (FB = y) && MIPS_ALCHEMY
	1770		select FB_SYS_FILLRECT
	1771		select FB_SYS_COPYAREA
	1772		select FB_SYS_IMAGEBLIT
	1773		select FB_SYS_FOPS
	1774		help
	1775		This is the framebuffer driver for the AMD Au1200 SOC. It can drive
	1776		various panels and CRTs by passing in kernel cmd line option
	1777		au1200fb:panel=<name>.
	1778
	1779		config FB_VT8500
	1780		bool "VT8500 LCD Driver"
	1781		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
	1782		select FB_WMT_GE_ROPS
	1783		select FB_SYS_IMAGEBLIT
	1784		help
	1785		This is the framebuffer driver for VIA VT8500 integrated LCD
	1786		controller.
	1787
	1788		config FB_WM8505
	1789		bool "WM8505 frame buffer support"
	1790		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
	1791		select FB_WMT_GE_ROPS
	1792		select FB_SYS_IMAGEBLIT
	1793		help
	1794		This is the framebuffer driver for WonderMedia WM8505
	1795		integrated LCD controller.
	1796
	1797		source "drivers/video/geode/Kconfig"
	1798
	1799		config FB_HIT
	1800		tristate "HD64461 Frame Buffer support"
	1801		depends on FB && HD64461
	1802		select FB_CFB_FILLRECT
	1803		select FB_CFB_COPYAREA
	1804		select FB_CFB_IMAGEBLIT
	1805		help
	1806		This is the frame buffer device driver for the Hitachi HD64461 LCD
	1807		frame buffer card.
	1808
	1809		config FB_PMAG_AA
	1810		bool "PMAG-AA TURBOchannel framebuffer support"
	1811		depends on (FB = y) && TC
	1812		select FB_CFB_FILLRECT
	1813		select FB_CFB_COPYAREA
	1814		select FB_CFB_IMAGEBLIT
	1815		help
	1816		Support for the PMAG-AA TURBOchannel framebuffer card (1280x1024x1)
	1817		used mainly in the MIPS-based DECstation series.
	1818
	1819		config FB_PMAG_BA
	1820		tristate "PMAG-BA TURBOchannel framebuffer support"
	1821		depends on FB && TC
	1822		select FB_CFB_FILLRECT
	1823		select FB_CFB_COPYAREA
	1824		select FB_CFB_IMAGEBLIT
	1825		help
	1826		Support for the PMAG-BA TURBOchannel framebuffer card (1024x864x8)
	1827		used mainly in the MIPS-based DECstation series.
	1828
	1829		config FB_PMAGB_B
	1830		tristate "PMAGB-B TURBOchannel framebuffer support"
	1831		depends on FB && TC
	1832		select FB_CFB_FILLRECT
	1833		select FB_CFB_COPYAREA
	1834		select FB_CFB_IMAGEBLIT
	1835		help
	1836		Support for the PMAGB-B TURBOchannel framebuffer card used mainly
	1837		in the MIPS-based DECstation series. The card is currently only
	1838		supported in 1280x1024x8 mode.
	1839
	1840		config FB_MAXINE
	1841		bool "Maxine (Personal DECstation) onboard framebuffer support"
	1842		depends on (FB = y) && MACH_DECSTATION
	1843		select FB_CFB_FILLRECT
	1844		select FB_CFB_COPYAREA
	1845		select FB_CFB_IMAGEBLIT
	1846		help
	1847		Support for the onboard framebuffer (1024x768x8) in the Personal
	1848		DECstation series (Personal DECstation 5000/20, /25, /33, /50,
	1849		Codename "Maxine").
	1850
	1851		config FB_G364
	1852		bool "G364 frame buffer support"
	1853		depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700)
	1854		select FB_CFB_FILLRECT
	1855		select FB_CFB_COPYAREA
	1856		select FB_CFB_IMAGEBLIT
	1857		help
	1858		The G364 driver is the framebuffer used in MIPS Magnum 4000 and
	1859		Olivetti M700-10 systems.
	1860
	1861		config FB_68328
	1862		bool "Motorola 68328 native frame buffer support"
	1863		depends on (FB = y) && (M68328 || M68EZ328 || M68VZ328)
	1864		select FB_CFB_FILLRECT
	1865		select FB_CFB_COPYAREA
	1866		select FB_CFB_IMAGEBLIT
	1867		help
	1868		Say Y here if you want to support the built-in frame buffer of
	1869		the Motorola 68328 CPU family.
	1870
	1871		config FB_PXA168
	1872		tristate "PXA168/910 LCD framebuffer support"
	1873		depends on FB && (CPU_PXA168 || CPU_PXA910)
	1874		select FB_CFB_FILLRECT
	1875		select FB_CFB_COPYAREA
	1876		select FB_CFB_IMAGEBLIT
	1877		---help---
	1878		Frame buffer driver for the built-in LCD controller in the Marvell
	1879		MMP processor.
	1880
	1881		config FB_PXA
	1882		tristate "PXA LCD framebuffer support"
	1883		depends on FB && ARCH_PXA
	1884		select FB_CFB_FILLRECT
	1885		select FB_CFB_COPYAREA
	1886		select FB_CFB_IMAGEBLIT
	1887		---help---
	1888		Frame buffer driver for the built-in LCD controller in the Intel
	1889		PXA2x0 processor.
	1890
	1891		This driver is also available as a module ( = code which can be
	1892		inserted and removed from the running kernel whenever you want). The
	1893		module will be called pxafb. If you want to compile it as a module,
	1894		say M here and read <file:Documentation/kbuild/modules.txt>.
	1895
	1896		If unsure, say N.
	1897
	1898		config FB_PXA_OVERLAY
	1899		bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
	1900		default n
	1901		depends on FB_PXA && (PXA27x || PXA3xx)
	1902
	1903		config FB_PXA_SMARTPANEL
	1904		bool "PXA Smartpanel LCD support"
	1905		default n
	1906		depends on FB_PXA
	1907
	1908		config FB_PXA_PARAMETERS
	1909		bool "PXA LCD command line parameters"
	1910		default n
	1911		depends on FB_PXA
	1912		---help---
	1913		Enable the use of kernel command line or module parameters
	1914		to configure the physical properties of the LCD panel when
	1915		using the PXA LCD driver.
	1916
	1917		This option allows you to override the panel parameters
	1918		supplied by the platform in order to support multiple
	1919		different models of flatpanel. If you will only be using a
	1920		single model of flatpanel then you can safely leave this
	1921		option disabled.
	1922
	1923		<file:Documentation/fb/pxafb.txt> describes the available parameters.
	1924
	1925		config PXA3XX_GCU
	1926		tristate "PXA3xx 2D graphics accelerator driver"
	1927		depends on FB_PXA
	1928		help
	1929		Kernelspace driver for the 2D graphics controller unit (GCU)
	1930		found on PXA3xx processors. There is a counterpart driver in the
	1931		DirectFB suite, see http://www.directfb.org/
	1932
	1933		If you compile this as a module, it will be called pxa3xx_gcu.
	1934
	1935		config FB_MBX
	1936		tristate "2700G LCD framebuffer support"
	1937		depends on FB && ARCH_PXA
	1938		select FB_CFB_FILLRECT
	1939		select FB_CFB_COPYAREA
	1940		select FB_CFB_IMAGEBLIT
	1941		---help---
	1942		Framebuffer driver for the Intel 2700G (Marathon) Graphics
	1943		Accelerator
	1944
	1945		config FB_MBX_DEBUG
	1946		bool "Enable debugging info via debugfs"
	1947		depends on FB_MBX && DEBUG_FS
	1948		default n
	1949		---help---
	1950		Enable this if you want debugging information using the debug
	1951		filesystem (debugfs)
	1952
	1953		If unsure, say N.
	1954
	1955		config FB_FSL_DIU
	1956		tristate "Freescale DIU framebuffer support"
	1957		depends on FB && FSL_SOC
	1958		select FB_MODE_HELPERS
	1959		select FB_CFB_FILLRECT
	1960		select FB_CFB_COPYAREA
	1961		select FB_CFB_IMAGEBLIT
	1962		select PPC_LIB_RHEAP
	1963		---help---
	1964		Framebuffer driver for the Freescale SoC DIU
	1965
	1966		config FB_W100
	1967		tristate "W100 frame buffer support"
	1968		depends on FB && ARCH_PXA
	1969		select FB_CFB_FILLRECT
	1970		select FB_CFB_COPYAREA
	1971		select FB_CFB_IMAGEBLIT
	1972		---help---
	1973		Frame buffer driver for the w100 as found on the Sharp SL-Cxx series.
	1974		It can also drive the w3220 chip found on iPAQ hx4700.
	1975
	1976		This driver is also available as a module ( = code which can be
	1977		inserted and removed from the running kernel whenever you want). The
	1978		module will be called w100fb. If you want to compile it as a module,
	1979		say M here and read <file:Documentation/kbuild/modules.txt>.
	1980
	1981		If unsure, say N.
	1982
	1983		config FB_SH_MOBILE_LCDC
	1984		tristate "SuperH Mobile LCDC framebuffer support"
	1985		depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	1986		select FB_SYS_FILLRECT
	1987		select FB_SYS_COPYAREA
	1988		select FB_SYS_IMAGEBLIT
	1989		select FB_SYS_FOPS
	1990		select FB_DEFERRED_IO
	1991		select FB_BACKLIGHT
	1992		select SH_MIPI_DSI if SH_LCD_MIPI_DSI
	1993		---help---
	1994		Frame buffer driver for the on-chip SH-Mobile LCD controller.
	1995
	1996		config FB_SH_MOBILE_HDMI
	1997		tristate "SuperH Mobile HDMI controller support"
	1998		depends on FB_SH_MOBILE_LCDC
	1999		select FB_MODE_HELPERS
	2000		select SOUND
	2001		select SND
	2002		select SND_SOC
	2003		---help---
	2004		Driver for the on-chip SH-Mobile HDMI controller.
	2005
	2006		config FB_SH_MOBILE_MERAM
	2007		tristate "SuperH Mobile MERAM read ahead support for LCDC"
	2008		depends on FB_SH_MOBILE_LCDC
	2009		default y
	2010		---help---
	2011		Enable MERAM support for the SH-Mobile LCD controller.
	2012
	2013		This will allow for caching of the framebuffer to provide more
	2014		reliable access under heavy main memory bus traffic situations.
	2015		Up to 4 memory channels can be configured, allowing 4 RGB or
	2016		2 YCbCr framebuffers to be configured.
	2017
	2018		config FB_TMIO
	2019		tristate "Toshiba Mobile IO FrameBuffer support"
	2020		depends on FB && MFD_CORE
	2021		select FB_CFB_FILLRECT
	2022		select FB_CFB_COPYAREA
	2023		select FB_CFB_IMAGEBLIT
	2024		---help---
	2025		Frame buffer driver for the Toshiba Mobile IO integrated as found
	2026		on the Sharp SL-6000 series
	2027
	2028		This driver is also available as a module ( = code which can be
	2029		inserted and removed from the running kernel whenever you want). The
	2030		module will be called tmiofb. If you want to compile it as a module,
	2031		say M here and read <file:Documentation/kbuild/modules.txt>.
	2032
	2033		If unsure, say N.
	2034
	2035		config FB_TMIO_ACCELL
	2036		bool "tmiofb acceleration"
	2037		depends on FB_TMIO
	2038		default y
	2039
	2040		config FB_S3C
	2041		tristate "Samsung S3C framebuffer support"
	2042		depends on FB && (S3C_DEV_FB || S5P_DEV_FIMD0)
	2043		select FB_CFB_FILLRECT
	2044		select FB_CFB_COPYAREA
	2045		select FB_CFB_IMAGEBLIT
	2046		---help---
	2047		Frame buffer driver for the built-in FB controller in the Samsung
	2048		SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
	2049		and the S3C64XX series such as the S3C6400 and S3C6410.
	2050
	2051		These chips all have the same basic framebuffer design with the
	2052		actual capabilities depending on the chip. For instance the S3C6400
	2053		and S3C6410 support 4 hardware windows whereas the S3C24XX series
	2054		currently only have two.
	2055
	2056		Currently the support is only for the S3C6400 and S3C6410 SoCs.
	2057
	2058		config FB_S3C_DEBUG_REGWRITE
	2059		bool "Debug register writes"
	2060		depends on FB_S3C
	2061		---help---
	2062		Show all register writes via printk(KERN_DEBUG)
	2063
	2064		config FB_S3C2410
	2065		tristate "S3C2410 LCD framebuffer support"
	2066		depends on FB && ARCH_S3C2410
	2067		select FB_CFB_FILLRECT
	2068		select FB_CFB_COPYAREA
	2069		select FB_CFB_IMAGEBLIT
	2070		---help---
	2071		Frame buffer driver for the built-in LCD controller in the Samsung
	2072		S3C2410 processor.
	2073
	2074		This driver is also available as a module ( = code which can be
	2075		inserted and removed from the running kernel whenever you want). The
	2076		module will be called s3c2410fb. If you want to compile it as a module,
	2077		say M here and read <file:Documentation/kbuild/modules.txt>.
	2078
	2079		If unsure, say N.
	2080		config FB_S3C2410_DEBUG
	2081		bool "S3C2410 lcd debug messages"
	2082		depends on FB_S3C2410
	2083		help
	2084		Turn on debugging messages. Note that you can set/unset at run time
	2085		through sysfs
	2086
	2087		config FB_NUC900
	2088		bool "NUC900 LCD framebuffer support"
	2089		depends on FB && ARCH_W90X900
	2090		select FB_CFB_FILLRECT
	2091		select FB_CFB_COPYAREA
	2092		select FB_CFB_IMAGEBLIT
	2093		---help---
	2094		Frame buffer driver for the built-in LCD controller in the Nuvoton
	2095		NUC900 processor
	2096
	2097		config GPM1040A0_320X240
	2098		bool "Giantplus Technology GPM1040A0 320x240 Color TFT LCD"
	2099		depends on FB_NUC900
	2100
	2101		config FB_NUC900_DEBUG
	2102		bool "NUC900 lcd debug messages"
	2103		depends on FB_NUC900
	2104		help
	2105		Turn on debugging messages. Note that you can set/unset at run time
	2106		through sysfs
	2107
	2108		config FB_SM501
	2109		tristate "Silicon Motion SM501 framebuffer support"
	2110		depends on FB && MFD_SM501
	2111		select FB_CFB_FILLRECT
	2112		select FB_CFB_COPYAREA
	2113		select FB_CFB_IMAGEBLIT
	2114		---help---
	2115		Frame buffer driver for the CRT and LCD controllers in the Silicon
	2116		Motion SM501.
	2117
	2118		This driver is also available as a module ( = code which can be
	2119		inserted and removed from the running kernel whenever you want). The
	2120		module will be called sm501fb. If you want to compile it as a module,
	2121		say M here and read <file:Documentation/kbuild/modules.txt>.
	2122
	2123		If unsure, say N.
	2124
	2125		config FB_SMSCUFX
	2126		tristate "SMSC UFX6000/7000 USB Framebuffer support"
	2127		depends on FB && USB
	2128		select FB_MODE_HELPERS
	2129		select FB_SYS_FILLRECT
	2130		select FB_SYS_COPYAREA
	2131		select FB_SYS_IMAGEBLIT
	2132		select FB_SYS_FOPS
	2133		select FB_DEFERRED_IO
	2134		---help---
	2135		This is a kernel framebuffer driver for SMSC UFX USB devices.
	2136		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2137		mplayer -vo fbdev. Supports both UFX6000 (USB 2.0) and UFX7000
	2138		(USB 3.0) devices.
	2139		To compile as a module, choose M here: the module name is smscufx.
	2140
	2141		config FB_UDL
	2142		tristate "Displaylink USB Framebuffer support"
	2143		depends on FB && USB
	2144		select FB_MODE_HELPERS
	2145		select FB_SYS_FILLRECT
	2146		select FB_SYS_COPYAREA
	2147		select FB_SYS_IMAGEBLIT
	2148		select FB_SYS_FOPS
	2149		select FB_DEFERRED_IO
	2150		---help---
	2151		This is a kernel framebuffer driver for DisplayLink USB devices.
	2152		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2153		mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
	2154		To compile as a module, choose M here: the module name is udlfb.
	2155
	2156		config FB_PNX4008_DUM
	2157		tristate "Display Update Module support on Philips PNX4008 board"
	2158		depends on FB && ARCH_PNX4008
	2159		---help---
	2160		Say Y here to enable support for PNX4008 Display Update Module (DUM)
	2161
	2162		config FB_PNX4008_DUM_RGB
	2163		tristate "RGB Framebuffer support on Philips PNX4008 board"
	2164		depends on FB_PNX4008_DUM
	2165		select FB_CFB_FILLRECT
	2166		select FB_CFB_COPYAREA
	2167		select FB_CFB_IMAGEBLIT
	2168		---help---
	2169		Say Y here to enable support for PNX4008 RGB Framebuffer
	2170
	2171		config FB_IBM_GXT4500
	2172		tristate "Framebuffer support for IBM GXT4500P adaptor"
	2173		depends on FB && PPC
	2174		select FB_CFB_FILLRECT
	2175		select FB_CFB_COPYAREA
	2176		select FB_CFB_IMAGEBLIT
	2177		---help---
	2178		Say Y here to enable support for the IBM GXT4500P display
	2179		adaptor, found on some IBM System P (pSeries) machines.
	2180
	2181		config FB_PS3
	2182		tristate "PS3 GPU framebuffer driver"
	2183		depends on FB && PS3_PS3AV
	2184		select FB_SYS_FILLRECT
	2185		select FB_SYS_COPYAREA
	2186		select FB_SYS_IMAGEBLIT
	2187		select FB_SYS_FOPS
	2188		select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
	2189		---help---
	2190		Include support for the virtual frame buffer in the PS3 platform.
	2191
	2192		config FB_PS3_DEFAULT_SIZE_M
	2193		int "PS3 default frame buffer size (in MiB)"
	2194		depends on FB_PS3
	2195		default 9
	2196		---help---
	2197		This is the default size (in MiB) of the virtual frame buffer in
	2198		the PS3.
	2199		The default value can be overridden on the kernel command line
	2200		using the "ps3fb" option (e.g. "ps3fb=9M");
	2201
	2202		config FB_XILINX
	2203		tristate "Xilinx frame buffer support"
	2204		depends on FB && (XILINX_VIRTEX || MICROBLAZE)
	2205		select FB_CFB_FILLRECT
	2206		select FB_CFB_COPYAREA
	2207		select FB_CFB_IMAGEBLIT
	2208		---help---
	2209		Include support for the Xilinx ML300/ML403 reference design
	2210		framebuffer. ML300 carries a 640*480 LCD display on the board,
	2211		ML403 uses a standard DB15 VGA connector.
	2212
	2213		config FB_COBALT
	2214		tristate "Cobalt server LCD frame buffer support"
	2215		depends on FB && MIPS_COBALT
	2216
	2217		config FB_SH7760
	2218		bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
	2219		depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
	2220		|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
	2221		select FB_CFB_FILLRECT
	2222		select FB_CFB_COPYAREA
	2223		select FB_CFB_IMAGEBLIT
	2224		---help---
	2225		Support for the SH7760/SH7763/SH7720/SH7721 integrated
	2226		(D)STN/TFT LCD Controller.
	2227		Supports display resolutions up to 1024x1024 pixel, grayscale and
	2228		color operation, with depths ranging from 1 bpp to 8 bpp monochrome
	2229		and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
	2230		panels <= 320 pixel horizontal resolution.
	2231
	2232		config FB_DA8XX
	2233		tristate "DA8xx/OMAP-L1xx Framebuffer support"
	2234		depends on FB && ARCH_DAVINCI_DA8XX
	2235		select FB_CFB_FILLRECT
	2236		select FB_CFB_COPYAREA
	2237		select FB_CFB_IMAGEBLIT
	2238		---help---
	2239		This is the frame buffer device driver for the TI LCD controller
	2240		found on DA8xx/OMAP-L1xx SoCs.
	2241		If unsure, say N.
	2242
	2243		config FB_VIRTUAL
	2244		tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
	2245		depends on FB
	2246		select FB_SYS_FILLRECT
	2247		select FB_SYS_COPYAREA
	2248		select FB_SYS_IMAGEBLIT
	2249		select FB_SYS_FOPS
	2250		---help---
	2251		This is a `virtual' frame buffer device. It operates on a chunk of
	2252		unswappable kernel memory instead of on the memory of a graphics
	2253		board. This means you cannot see any output sent to this frame
	2254		buffer device, while it does consume precious memory. The main use
	2255		of this frame buffer device is testing and debugging the frame
	2256		buffer subsystem. Do NOT enable it for normal systems! To protect
	2257		the innocent, it has to be enabled explicitly at boot time using the
	2258		kernel option `video=vfb:'.
	2259
	2260		To compile this driver as a module, choose M here: the
	2261		module will be called vfb. In order to load it, you must use
	2262		the vfb_enable=1 option.
	2263
	2264		If unsure, say N.
	2265
	2266		config XEN_FBDEV_FRONTEND
	2267		tristate "Xen virtual frame buffer support"
	2268		depends on FB && XEN
	2269		select FB_SYS_FILLRECT
	2270		select FB_SYS_COPYAREA
	2271		select FB_SYS_IMAGEBLIT
	2272		select FB_SYS_FOPS
	2273		select FB_DEFERRED_IO
	2274		select XEN_XENBUS_FRONTEND
	2275		default y
	2276		help
	2277		This driver implements the front-end of the Xen virtual
	2278		frame buffer driver. It communicates with a back-end
	2279		in another domain.
	2280
	2281		config FB_METRONOME
	2282		tristate "E-Ink Metronome/8track controller support"
	2283		depends on FB
	2284		select FB_SYS_FILLRECT
	2285		select FB_SYS_COPYAREA
	2286		select FB_SYS_IMAGEBLIT
	2287		select FB_SYS_FOPS
	2288		select FB_DEFERRED_IO
	2289		help
	2290		This driver implements support for the E-Ink Metronome
	2291		controller. The pre-release name for this device was 8track
	2292		and could also have been called by some vendors as PVI-nnnn.
	2293
	2294		config FB_MB862XX
	2295		tristate "Fujitsu MB862xx GDC support"
	2296		depends on FB
	2297		depends on PCI || (OF && PPC)
	2298		select FB_CFB_FILLRECT
	2299		select FB_CFB_COPYAREA
	2300		select FB_CFB_IMAGEBLIT
	2301		---help---
	2302		Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
	2303
	2304		choice
	2305		prompt "GDC variant"
	2306		depends on FB_MB862XX
	2307
	2308		config FB_MB862XX_PCI_GDC
	2309		bool "Carmine/Coral-P(A) GDC"
	2310		depends on PCI
	2311		---help---
	2312		This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
	2313		PCI graphics controller devices.
	2314
	2315		config FB_MB862XX_LIME
	2316		bool "Lime GDC"
	2317		depends on OF && PPC
	2318		select FB_FOREIGN_ENDIAN
	2319		select FB_LITTLE_ENDIAN
	2320		---help---
	2321		Framebuffer support for Fujitsu Lime GDC on host CPU bus.
	2322
	2323		endchoice
	2324
	2325		config FB_MB862XX_I2C
	2326		bool "Support I2C bus on MB862XX GDC"
	2327		depends on FB_MB862XX && I2C
	2328		default y
	2329		help
	2330		Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
	2331		driver to support accessing I2C devices on controller's I2C bus.
	2332		These are usually some video decoder chips.
	2333
	2334		config FB_EP93XX
	2335		tristate "EP93XX frame buffer support"
	2336		depends on FB && ARCH_EP93XX
	2337		select FB_CFB_FILLRECT
	2338		select FB_CFB_COPYAREA
	2339		select FB_CFB_IMAGEBLIT
	2340		---help---
	2341		Framebuffer driver for the Cirrus Logic EP93XX series of processors.
	2342		This driver is also available as a module. The module will be called
	2343		ep93xx-fb.
	2344
	2345		config FB_PRE_INIT_FB
	2346		bool "Don't reinitialize, use bootloader's GDC/Display configuration"
	2347		depends on FB && FB_MB862XX_LIME
	2348		---help---
	2349		Select this option if display contents should be inherited as set by
	2350		the bootloader.
	2351
	2352		config FB_MSM
	2353		tristate "MSM Framebuffer support"
	2354		depends on FB && ARCH_MSM
	2355		select FB_CFB_FILLRECT
	2356		select FB_CFB_COPYAREA
	2357		select FB_CFB_IMAGEBLIT
	2358
	2359		config FB_MX3
	2360		tristate "MX3 Framebuffer support"
	2361		depends on FB && MX3_IPU
	2362		select FB_CFB_FILLRECT
	2363		select FB_CFB_COPYAREA
	2364		select FB_CFB_IMAGEBLIT
	2365		default y
	2366		help
	2367		This is a framebuffer device for the i.MX31 LCD Controller. So
	2368		far only synchronous displays are supported. If you plan to use
	2369		an LCD display with your i.MX31 system, say Y here.
	2370
	2371		config FB_BROADSHEET
	2372		tristate "E-Ink Broadsheet/Epson S1D13521 controller support"
	2373		depends on FB
	2374		select FB_SYS_FILLRECT
	2375		select FB_SYS_COPYAREA
	2376		select FB_SYS_IMAGEBLIT
	2377		select FB_SYS_FOPS
	2378		select FB_DEFERRED_IO
	2379		help
	2380		This driver implements support for the E-Ink Broadsheet
	2381		controller. The release name for this device was Epson S1D13521
	2382		and could also have been called by other names when coupled with
	2383		a bridge adapter.
	2384
	2385		config FB_JZ4740
	2386		tristate "JZ4740 LCD framebuffer support"
	2387		depends on FB && MACH_JZ4740
	2388		select FB_SYS_FILLRECT
	2389		select FB_SYS_COPYAREA
	2390		select FB_SYS_IMAGEBLIT
	2391		help
	2392		Framebuffer support for the JZ4740 SoC.
	2393
	2394		config FB_MXS
	2395		tristate "MXS LCD framebuffer support"
	2396		depends on FB && ARCH_MXS
	2397		select FB_CFB_FILLRECT
	2398		select FB_CFB_COPYAREA
	2399		select FB_CFB_IMAGEBLIT
	2400		help
	2401		Framebuffer support for the MXS SoC.
	2402
	2403		config FB_PUV3_UNIGFX
	2404		tristate "PKUnity v3 Unigfx framebuffer support"
	2405		depends on FB && UNICORE32 && ARCH_PUV3
	2406		select FB_SYS_FILLRECT
	2407		select FB_SYS_COPYAREA
	2408		select FB_SYS_IMAGEBLIT
	2409		select FB_SYS_FOPS
	2410		help
	2411		Choose this option if you want to use the Unigfx device as a
	2412		framebuffer device. Without the support of PCI & AGP.
	2413
	2414		source "drivers/video/omap/Kconfig"
	2415		source "drivers/video/omap2/Kconfig"
	2416
	2417		source "drivers/video/backlight/Kconfig"
	2418		source "drivers/video/display/Kconfig"
	2419
	2420		if VT
	2421		source "drivers/video/console/Kconfig"
	2422		endif
	2423
	2424		if FB || SGI_NEWPORT_CONSOLE
	2425		source "drivers/video/logo/Kconfig"
	2426		endif
	2427
	2428		endmenu

File drivers/video/Kconfig-3.4.1 added (mode: 100644) (index 0000000..b0d367a)
	1		#
	2		# Video configuration
	3		#
	4
	5		menu "Graphics support"
	6		depends on HAS_IOMEM
	7
	8		config HAVE_FB_ATMEL
	9		bool
	10
	11		config SH_MIPI_DSI
	12		tristate
	13		depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	14
	15		config SH_LCD_MIPI_DSI
	16		bool
	17
	18		source "drivers/char/agp/Kconfig"
	19
	20		source "drivers/gpu/vga/Kconfig"
	21
	22		source "drivers/gpu/alga/Kconfig"
	23
	24		source "drivers/gpu/drm/Kconfig"
	25
	26		source "drivers/gpu/stub/Kconfig"
	27
	28		config VGASTATE
	29		tristate
	30		default n
	31
	32		config VIDEO_OUTPUT_CONTROL
	33		tristate "Lowlevel video output switch controls"
	34		help
	35		This framework adds support for low-level control of the video
	36		output switch.
	37
	38		menuconfig FB
	39		tristate "Support for frame buffer devices"
	40		---help---
	41		The frame buffer device provides an abstraction for the graphics
	42		hardware. It represents the frame buffer of some video hardware and
	43		allows application software to access the graphics hardware through
	44		a well-defined interface, so the software doesn't need to know
	45		anything about the low-level (hardware register) stuff.
	46
	47		Frame buffer devices work identically across the different
	48		architectures supported by Linux and make the implementation of
	49		application programs easier and more portable; at this point, an X
	50		server exists which uses the frame buffer device exclusively.
	51		On several non-X86 architectures, the frame buffer device is the
	52		only way to use the graphics hardware.
	53
	54		The device is accessed through special device nodes, usually located
	55		in the /dev directory, i.e. /dev/fb*.
	56
	57		You need an utility program called fbset to make full use of frame
	58		buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
	59		and the Framebuffer-HOWTO at
	60		<http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
	61		information.
	62
	63		Say Y here and to the driver for your graphics board below if you
	64		are compiling a kernel for a non-x86 architecture.
	65
	66		If you are compiling for the x86 architecture, you can say Y if you
	67		want to play with it, but it is not essential. Please note that
	68		running graphical applications that directly touch the hardware
	69		(e.g. an accelerated X server) and that are not frame buffer
	70		device-aware may cause unexpected results. If unsure, say N.
	71
	72		config FIRMWARE_EDID
	73		bool "Enable firmware EDID"
	74		depends on FB
	75		default n
	76		---help---
	77		This enables access to the EDID transferred from the firmware.
	78		On the i386, this is from the Video BIOS. Enable this if DDC/I2C
	79		transfers do not work for your driver and if you are using
	80		nvidiafb, i810fb or savagefb.
	81
	82		In general, choosing Y for this option is safe. If you
	83		experience extremely long delays while booting before you get
	84		something on your display, try setting this to N. Matrox cards in
	85		combination with certain motherboards and monitors are known to
	86		suffer from this problem.
	87
	88		config FB_DDC
	89		tristate
	90		depends on FB
	91		select I2C_ALGOBIT
	92		select I2C
	93		default n
	94
	95		config FB_BOOT_VESA_SUPPORT
	96		bool
	97		depends on FB
	98		default n
	99		---help---
	100		If true, at least one selected framebuffer driver can take advantage
	101		of VESA video modes set at an early boot stage via the vga= parameter.
	102
	103		config FB_CFB_FILLRECT
	104		tristate
	105		depends on FB
	106		default n
	107		---help---
	108		Include the cfb_fillrect function for generic software rectangle
	109		filling. This is used by drivers that don't provide their own
	110		(accelerated) version.
	111
	112		config FB_CFB_COPYAREA
	113		tristate
	114		depends on FB
	115		default n
	116		---help---
	117		Include the cfb_copyarea function for generic software area copying.
	118		This is used by drivers that don't provide their own (accelerated)
	119		version.
	120
	121		config FB_CFB_IMAGEBLIT
	122		tristate
	123		depends on FB
	124		default n
	125		---help---
	126		Include the cfb_imageblit function for generic software image
	127		blitting. This is used by drivers that don't provide their own
	128		(accelerated) version.
	129
	130		config FB_CFB_REV_PIXELS_IN_BYTE
	131		bool
	132		depends on FB
	133		default n
	134		---help---
	135		Allow generic frame-buffer functions to work on displays with 1, 2
	136		and 4 bits per pixel depths which has opposite order of pixels in
	137		byte order to bytes in long order.
	138
	139		config FB_SYS_FILLRECT
	140		tristate
	141		depends on FB
	142		default n
	143		---help---
	144		Include the sys_fillrect function for generic software rectangle
	145		filling. This is used by drivers that don't provide their own
	146		(accelerated) version and the framebuffer is in system RAM.
	147
	148		config FB_SYS_COPYAREA
	149		tristate
	150		depends on FB
	151		default n
	152		---help---
	153		Include the sys_copyarea function for generic software area copying.
	154		This is used by drivers that don't provide their own (accelerated)
	155		version and the framebuffer is in system RAM.
	156
	157		config FB_SYS_IMAGEBLIT
	158		tristate
	159		depends on FB
	160		default n
	161		---help---
	162		Include the sys_imageblit function for generic software image
	163		blitting. This is used by drivers that don't provide their own
	164		(accelerated) version and the framebuffer is in system RAM.
	165
	166		menuconfig FB_FOREIGN_ENDIAN
	167		bool "Framebuffer foreign endianness support"
	168		depends on FB
	169		---help---
	170		This menu will let you enable support for the framebuffers with
	171		non-native endianness (e.g. Little-Endian framebuffer on a
	172		Big-Endian machine). Most probably you don't have such hardware,
	173		so it's safe to say "n" here.
	174
	175		choice
	176		prompt "Choice endianness support"
	177		depends on FB_FOREIGN_ENDIAN
	178
	179		config FB_BOTH_ENDIAN
	180		bool "Support for Big- and Little-Endian framebuffers"
	181
	182		config FB_BIG_ENDIAN
	183		bool "Support for Big-Endian framebuffers only"
	184
	185		config FB_LITTLE_ENDIAN
	186		bool "Support for Little-Endian framebuffers only"
	187
	188		endchoice
	189
	190		config FB_SYS_FOPS
	191		tristate
	192		depends on FB
	193		default n
	194
	195		config FB_WMT_GE_ROPS
	196		tristate
	197		depends on FB
	198		default n
	199		---help---
	200		Include functions for accelerated rectangle filling and area
	201		copying using WonderMedia Graphics Engine operations.
	202
	203		config FB_DEFERRED_IO
	204		bool
	205		depends on FB
	206
	207		config FB_HECUBA
	208		tristate
	209		depends on FB
	210		depends on FB_DEFERRED_IO
	211
	212		config FB_SVGALIB
	213		tristate
	214		depends on FB
	215		default n
	216		---help---
	217		Common utility functions useful to fbdev drivers of VGA-based
	218		cards.
	219
	220		config FB_MACMODES
	221		tristate
	222		depends on FB
	223		default n
	224
	225		config FB_BACKLIGHT
	226		bool
	227		depends on FB
	228		select BACKLIGHT_LCD_SUPPORT
	229		select BACKLIGHT_CLASS_DEVICE
	230		default n
	231
	232		config FB_MODE_HELPERS
	233		bool "Enable Video Mode Handling Helpers"
	234		depends on FB
	235		default n
	236		---help---
	237		This enables functions for handling video modes using the
	238		Generalized Timing Formula and the EDID parser. A few drivers rely
	239		on this feature such as the radeonfb, rivafb, and the i810fb. If
	240		your driver does not take advantage of this feature, choosing Y will
	241		just increase the kernel size by about 5K.
	242
	243		config FB_TILEBLITTING
	244		bool "Enable Tile Blitting Support"
	245		depends on FB
	246		default n
	247		---help---
	248		This enables tile blitting. Tile blitting is a drawing technique
	249		where the screen is divided into rectangular sections (tiles), whereas
	250		the standard blitting divides the screen into pixels. Because the
	251		default drawing element is a tile, drawing functions will be passed
	252		parameters in terms of number of tiles instead of number of pixels.
	253		For example, to draw a single character, instead of using bitmaps,
	254		an index to an array of bitmaps will be used. To clear or move a
	255		rectangular section of a screen, the rectangle will be described in
	256		terms of number of tiles in the x- and y-axis.
	257
	258		This is particularly important to one driver, matroxfb. If
	259		unsure, say N.
	260
	261		comment "Frame buffer hardware drivers"
	262		depends on FB
	263
	264		config FB_GRVGA
	265		tristate "Aeroflex Gaisler framebuffer support"
	266		depends on FB && SPARC
	267		select FB_CFB_FILLRECT
	268		select FB_CFB_COPYAREA
	269		select FB_CFB_IMAGEBLIT
	270		---help---
	271		This enables support for the SVGACTRL framebuffer in the GRLIB IP library from Aeroflex Gaisler.
	272
	273		config FB_CIRRUS
	274		tristate "Cirrus Logic support"
	275		depends on FB && (ZORRO || PCI)
	276		select FB_CFB_FILLRECT
	277		select FB_CFB_COPYAREA
	278		select FB_CFB_IMAGEBLIT
	279		---help---
	280		This enables support for Cirrus Logic GD542x/543x based boards on
	281		Amiga: SD64, Piccolo, Picasso II/II+, Picasso IV, or EGS Spectrum.
	282
	283		If you have a PCI-based system, this enables support for these
	284		chips: GD-543x, GD-544x, GD-5480.
	285
	286		Please read the file <file:Documentation/fb/cirrusfb.txt>.
	287
	288		Say N unless you have such a graphics board or plan to get one
	289		before you next recompile the kernel.
	290
	291		config FB_PM2
	292		tristate "Permedia2 support"
	293		depends on FB && ((AMIGA && BROKEN) || PCI)
	294		select FB_CFB_FILLRECT
	295		select FB_CFB_COPYAREA
	296		select FB_CFB_IMAGEBLIT
	297		help
	298		This is the frame buffer device driver for cards based on
	299		the 3D Labs Permedia, Permedia 2 and Permedia 2V chips.
	300		The driver was tested on the following cards:
	301		Diamond FireGL 1000 PRO AGP
	302		ELSA Gloria Synergy PCI
	303		Appian Jeronimo PRO (both heads) PCI
	304		3DLabs Oxygen ACX aka EONtronics Picasso P2 PCI
	305		Techsource Raptor GFX-8P (aka Sun PGX-32) on SPARC
	306		ASK Graphic Blaster Exxtreme AGP
	307
	308		To compile this driver as a module, choose M here: the
	309		module will be called pm2fb.
	310
	311		config FB_PM2_FIFO_DISCONNECT
	312		bool "enable FIFO disconnect feature"
	313		depends on FB_PM2 && PCI
	314		help
	315		Support the Permedia2 FIFO disconnect feature.
	316
	317		config FB_ARMCLCD
	318		tristate "ARM PrimeCell PL110 support"
	319		depends on FB && ARM && ARM_AMBA
	320		select FB_CFB_FILLRECT
	321		select FB_CFB_COPYAREA
	322		select FB_CFB_IMAGEBLIT
	323		help
	324		This framebuffer device driver is for the ARM PrimeCell PL110
	325		Colour LCD controller. ARM PrimeCells provide the building
	326		blocks for System on a Chip devices.
	327
	328		If you want to compile this as a module (=code which can be
	329		inserted into and removed from the running kernel), say M
	330		here and read <file:Documentation/kbuild/modules.txt>. The module
	331		will be called amba-clcd.
	332
	333		config FB_ACORN
	334		bool "Acorn VIDC support"
	335		depends on (FB = y) && ARM && ARCH_ACORN
	336		select FB_CFB_FILLRECT
	337		select FB_CFB_COPYAREA
	338		select FB_CFB_IMAGEBLIT
	339		help
	340		This is the frame buffer device driver for the Acorn VIDC graphics
	341		hardware found in Acorn RISC PCs and other ARM-based machines. If
	342		unsure, say N.
	343
	344		config FB_CLPS711X
	345		bool "CLPS711X LCD support"
	346		depends on (FB = y) && ARM && ARCH_CLPS711X
	347		select FB_CFB_FILLRECT
	348		select FB_CFB_COPYAREA
	349		select FB_CFB_IMAGEBLIT
	350		help
	351		Say Y to enable the Framebuffer driver for the CLPS7111 and
	352		EP7212 processors.
	353
	354		config FB_SA1100
	355		bool "SA-1100 LCD support"
	356		depends on (FB = y) && ARM && ARCH_SA1100
	357		select FB_CFB_FILLRECT
	358		select FB_CFB_COPYAREA
	359		select FB_CFB_IMAGEBLIT
	360		help
	361		This is a framebuffer device for the SA-1100 LCD Controller.
	362		See <http://www.linux-fbdev.org/> for information on framebuffer
	363		devices.
	364
	365		If you plan to use the LCD display with your SA-1100 system, say
	366		Y here.
	367
	368		config FB_IMX
	369		tristate "Freescale i.MX LCD support"
	370		depends on FB && IMX_HAVE_PLATFORM_IMX_FB
	371		select FB_CFB_FILLRECT
	372		select FB_CFB_COPYAREA
	373		select FB_CFB_IMAGEBLIT
	374
	375		config FB_CYBER2000
	376		tristate "CyberPro 2000/2010/5000 support"
	377		depends on FB && PCI && (BROKEN || !SPARC64)
	378		select FB_CFB_FILLRECT
	379		select FB_CFB_COPYAREA
	380		select FB_CFB_IMAGEBLIT
	381		help
	382		This enables support for the Integraphics CyberPro 20x0 and 5000
	383		VGA chips used in the Rebel.com Netwinder and other machines.
	384		Say Y if you have a NetWinder or a graphics card containing this
	385		device, otherwise say N.
	386
	387		config FB_CYBER2000_DDC
	388		bool "DDC for CyberPro support"
	389		depends on FB_CYBER2000
	390		select FB_DDC
	391		default y
	392		help
	393		Say Y here if you want DDC support for your CyberPro graphics
	394		card. This is only I2C bus support, driver does not use EDID.
	395
	396		config FB_CYBER2000_I2C
	397		bool "CyberPro 2000/2010/5000 I2C support"
	398		depends on FB_CYBER2000 && I2C && ARCH_NETWINDER
	399		select I2C_ALGOBIT
	400		help
	401		Enable support for the I2C video decoder interface on the
	402		Integraphics CyberPro 20x0 and 5000 VGA chips. This is used
	403		on the Netwinder machines for the SAA7111 video capture.
	404
	405		config FB_APOLLO
	406		bool
	407		depends on (FB = y) && APOLLO
	408		default y
	409		select FB_CFB_FILLRECT
	410		select FB_CFB_IMAGEBLIT
	411
	412		config FB_Q40
	413		bool
	414		depends on (FB = y) && Q40
	415		default y
	416		select FB_CFB_FILLRECT
	417		select FB_CFB_COPYAREA
	418		select FB_CFB_IMAGEBLIT
	419
	420		config FB_AMIGA
	421		tristate "Amiga native chipset support"
	422		depends on FB && AMIGA
	423		help
	424		This is the frame buffer device driver for the builtin graphics
	425		chipset found in Amigas.
	426
	427		To compile this driver as a module, choose M here: the
	428		module will be called amifb.
	429
	430		config FB_AMIGA_OCS
	431		bool "Amiga OCS chipset support"
	432		depends on FB_AMIGA
	433		help
	434		This enables support for the original Agnus and Denise video chips,
	435		found in the Amiga 1000 and most A500's and A2000's. If you intend
	436		to run Linux on any of these systems, say Y; otherwise say N.
	437
	438		config FB_AMIGA_ECS
	439		bool "Amiga ECS chipset support"
	440		depends on FB_AMIGA
	441		help
	442		This enables support for the Enhanced Chip Set, found in later
	443		A500's, later A2000's, the A600, the A3000, the A3000T and CDTV. If
	444		you intend to run Linux on any of these systems, say Y; otherwise
	445		say N.
	446
	447		config FB_AMIGA_AGA
	448		bool "Amiga AGA chipset support"
	449		depends on FB_AMIGA
	450		help
	451		This enables support for the Advanced Graphics Architecture (also
	452		known as the AGA or AA) Chip Set, found in the A1200, A4000, A4000T
	453		and CD32. If you intend to run Linux on any of these systems, say Y;
	454		otherwise say N.
	455
	456		config FB_FM2
	457		bool "Amiga FrameMaster II/Rainbow II support"
	458		depends on (FB = y) && ZORRO
	459		select FB_CFB_FILLRECT
	460		select FB_CFB_COPYAREA
	461		select FB_CFB_IMAGEBLIT
	462		help
	463		This is the frame buffer device driver for the Amiga FrameMaster
	464		card from BSC (exhibited 1992 but not shipped as a CBM product).
	465
	466		config FB_ARC
	467		tristate "Arc Monochrome LCD board support"
	468		depends on FB && X86
	469		select FB_SYS_FILLRECT
	470		select FB_SYS_COPYAREA
	471		select FB_SYS_IMAGEBLIT
	472		select FB_SYS_FOPS
	473		help
	474		This enables support for the Arc Monochrome LCD board. The board
	475		is based on the KS-108 lcd controller and is typically a matrix
	476		of 2*n chips. This driver was tested with a 128x64 panel. This
	477		driver supports it for use with x86 SBCs through a 16 bit GPIO
	478		interface (8 bit data, 8 bit control). If you anticipate using
	479		this driver, say Y or M; otherwise say N. You must specify the
	480		GPIO IO address to be used for setting control and data.
	481
	482		config FB_ATARI
	483		bool "Atari native chipset support"
	484		depends on (FB = y) && ATARI
	485		select FB_CFB_FILLRECT
	486		select FB_CFB_COPYAREA
	487		select FB_CFB_IMAGEBLIT
	488		help
	489		This is the frame buffer device driver for the builtin graphics
	490		chipset found in Ataris.
	491
	492		config FB_OF
	493		bool "Open Firmware frame buffer device support"
	494		depends on (FB = y) && (PPC64 || PPC_OF) && (!PPC_PSERIES || PCI)
	495		select FB_CFB_FILLRECT
	496		select FB_CFB_COPYAREA
	497		select FB_CFB_IMAGEBLIT
	498		select FB_MACMODES
	499		help
	500		Say Y if you want support with Open Firmware for your graphics
	501		board.
	502
	503		config FB_CONTROL
	504		bool "Apple \"control\" display support"
	505		depends on (FB = y) && PPC_PMAC && PPC32
	506		select FB_CFB_FILLRECT
	507		select FB_CFB_COPYAREA
	508		select FB_CFB_IMAGEBLIT
	509		select FB_MACMODES
	510		help
	511		This driver supports a frame buffer for the graphics adapter in the
	512		Power Macintosh 7300 and others.
	513
	514		config FB_PLATINUM
	515		bool "Apple \"platinum\" display support"
	516		depends on (FB = y) && PPC_PMAC && PPC32
	517		select FB_CFB_FILLRECT
	518		select FB_CFB_COPYAREA
	519		select FB_CFB_IMAGEBLIT
	520		select FB_MACMODES
	521		help
	522		This driver supports a frame buffer for the "platinum" graphics
	523		adapter in some Power Macintoshes.
	524
	525		config FB_VALKYRIE
	526		bool "Apple \"valkyrie\" display support"
	527		depends on (FB = y) && (MAC || (PPC_PMAC && PPC32))
	528		select FB_CFB_FILLRECT
	529		select FB_CFB_COPYAREA
	530		select FB_CFB_IMAGEBLIT
	531		select FB_MACMODES
	532		help
	533		This driver supports a frame buffer for the "valkyrie" graphics
	534		adapter in some Power Macintoshes.
	535
	536		config FB_CT65550
	537		bool "Chips 65550 display support"
	538		depends on (FB = y) && PPC32 && PCI
	539		select FB_CFB_FILLRECT
	540		select FB_CFB_COPYAREA
	541		select FB_CFB_IMAGEBLIT
	542		help
	543		This is the frame buffer device driver for the Chips & Technologies
	544		65550 graphics chip in PowerBooks.
	545
	546		config FB_ASILIANT
	547		bool "Asiliant (Chips) 69000 display support"
	548		depends on (FB = y) && PCI
	549		select FB_CFB_FILLRECT
	550		select FB_CFB_COPYAREA
	551		select FB_CFB_IMAGEBLIT
	552		help
	553		This is the frame buffer device driver for the Asiliant 69030 chipset
	554
	555		config FB_IMSTT
	556		bool "IMS Twin Turbo display support"
	557		depends on (FB = y) && PCI
	558		select FB_CFB_IMAGEBLIT
	559		select FB_MACMODES if PPC
	560		help
	561		The IMS Twin Turbo is a PCI-based frame buffer card bundled with
	562		many Macintosh and compatible computers.
	563
	564		config FB_VGA16
	565		tristate "VGA 16-color graphics support"
	566		depends on FB && (X86 || PPC)
	567		select FB_CFB_FILLRECT
	568		select FB_CFB_COPYAREA
	569		select FB_CFB_IMAGEBLIT
	570		select VGASTATE
	571		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	572		help
	573		This is the frame buffer device driver for VGA 16 color graphic
	574		cards. Say Y if you have such a card.
	575
	576		To compile this driver as a module, choose M here: the
	577		module will be called vga16fb.
	578
	579		config FB_BF54X_LQ043
	580		tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)"
	581		depends on FB && (BF54x) && !BF542
	582		select FB_CFB_FILLRECT
	583		select FB_CFB_COPYAREA
	584		select FB_CFB_IMAGEBLIT
	585		help
	586		This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD
	587
	588		config FB_BFIN_T350MCQB
	589		tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)"
	590		depends on FB && BLACKFIN
	591		select BFIN_GPTIMERS
	592		select FB_CFB_FILLRECT
	593		select FB_CFB_COPYAREA
	594		select FB_CFB_IMAGEBLIT
	595		help
	596		This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD
	597		This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
	598		It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
	599
	600		config FB_BFIN_LQ035Q1
	601		tristate "SHARP LQ035Q1DH02 TFT LCD"
	602		depends on FB && BLACKFIN && SPI
	603		select FB_CFB_FILLRECT
	604		select FB_CFB_COPYAREA
	605		select FB_CFB_IMAGEBLIT
	606		select BFIN_GPTIMERS
	607		help
	608		This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
	609		the Blackfin Landscape LCD EZ-Extender Card.
	610		This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
	611		It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
	612
	613		To compile this driver as a module, choose M here: the
	614		module will be called bfin-lq035q1-fb.
	615
	616		config FB_BF537_LQ035
	617		tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
	618		depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
	619		select FB_CFB_FILLRECT
	620		select FB_CFB_COPYAREA
	621		select FB_CFB_IMAGEBLIT
	622		select BFIN_GPTIMERS
	623		help
	624		This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
	625		attached to a BF537.
	626
	627		To compile this driver as a module, choose M here: the
	628		module will be called bf537-lq035.
	629
	630		config FB_BFIN_7393
	631		tristate "Blackfin ADV7393 Video encoder"
	632		depends on FB && BLACKFIN
	633		select I2C
	634		select FB_CFB_FILLRECT
	635		select FB_CFB_COPYAREA
	636		select FB_CFB_IMAGEBLIT
	637		help
	638		This is the framebuffer device for a ADV7393 video encoder
	639		attached to a Blackfin on the PPI port.
	640		If your Blackfin board has a ADV7393 select Y.
	641
	642		To compile this driver as a module, choose M here: the
	643		module will be called bfin_adv7393fb.
	644
	645		choice
	646		prompt "Video mode support"
	647		depends on FB_BFIN_7393
	648		default NTSC
	649
	650		config NTSC
	651		bool 'NTSC 720x480'
	652
	653		config PAL
	654		bool 'PAL 720x576'
	655
	656		config NTSC_640x480
	657		bool 'NTSC 640x480 (Experimental)'
	658
	659		config PAL_640x480
	660		bool 'PAL 640x480 (Experimental)'
	661
	662		config NTSC_YCBCR
	663		bool 'NTSC 720x480 YCbCR input'
	664
	665		config PAL_YCBCR
	666		bool 'PAL 720x576 YCbCR input'
	667
	668		endchoice
	669
	670		choice
	671		prompt "Size of ADV7393 frame buffer memory Single/Double Size"
	672		depends on (FB_BFIN_7393)
	673		default ADV7393_1XMEM
	674
	675		config ADV7393_1XMEM
	676		bool 'Single'
	677
	678		config ADV7393_2XMEM
	679		bool 'Double'
	680		endchoice
	681
	682		config FB_STI
	683		tristate "HP STI frame buffer device support"
	684		depends on FB && PARISC
	685		select FB_CFB_FILLRECT
	686		select FB_CFB_COPYAREA
	687		select FB_CFB_IMAGEBLIT
	688		select STI_CONSOLE
	689		select VT
	690		default y
	691		---help---
	692		STI refers to the HP "Standard Text Interface" which is a set of
	693		BIOS routines contained in a ROM chip in HP PA-RISC based machines.
	694		Enabling this option will implement the linux framebuffer device
	695		using calls to the STI BIOS routines for initialisation.
	696
	697		If you enable this option, you will get a planar framebuffer device
	698		/dev/fb which will work on the most common HP graphic cards of the
	699		NGLE family, including the artist chips (in the 7xx and Bxxx series),
	700		HCRX, HCRX24, CRX, CRX24 and VisEG series.
	701
	702		It is safe to enable this option, so you should probably say "Y".
	703
	704		config FB_MAC
	705		bool "Generic Macintosh display support"
	706		depends on (FB = y) && MAC
	707		select FB_CFB_FILLRECT
	708		select FB_CFB_COPYAREA
	709		select FB_CFB_IMAGEBLIT
	710		select FB_MACMODES
	711
	712		config FB_HP300
	713		bool
	714		depends on (FB = y) && DIO
	715		select FB_CFB_IMAGEBLIT
	716		default y
	717
	718		config FB_TGA
	719		tristate "TGA/SFB+ framebuffer support"
	720		depends on FB && (ALPHA || TC)
	721		select FB_CFB_FILLRECT
	722		select FB_CFB_COPYAREA
	723		select FB_CFB_IMAGEBLIT
	724		select BITREVERSE
	725		---help---
	726		This is the frame buffer device driver for generic TGA and SFB+
	727		graphic cards. These include DEC ZLXp-E1, -E2 and -E3 PCI cards,
	728		also known as PBXGA-A, -B and -C, and DEC ZLX-E1, -E2 and -E3
	729		TURBOchannel cards, also known as PMAGD-A, -B and -C.
	730
	731		Due to hardware limitations ZLX-E2 and E3 cards are not supported
	732		for DECstation 5000/200 systems. Additionally due to firmware
	733		limitations these cards may cause troubles with booting DECstation
	734		5000/240 and /260 systems, but are fully supported under Linux if
	735		you manage to get it going. ;-)
	736
	737		Say Y if you have one of those.
	738
	739		config FB_UVESA
	740		tristate "Userspace VESA VGA graphics support"
	741		depends on FB && CONNECTOR
	742		select FB_CFB_FILLRECT
	743		select FB_CFB_COPYAREA
	744		select FB_CFB_IMAGEBLIT
	745		select FB_MODE_HELPERS
	746		help
	747		This is the frame buffer driver for generic VBE 2.0 compliant
	748		graphic cards. It can also take advantage of VBE 3.0 features,
	749		such as refresh rate adjustment.
	750
	751		This driver generally provides more features than vesafb but
	752		requires a userspace helper application called 'v86d'. See
	753		<file:Documentation/fb/uvesafb.txt> for more information.
	754
	755		If unsure, say N.
	756
	757		config FB_VESA
	758		bool "VESA VGA graphics support"
	759		depends on (FB = y) && X86
	760		select FB_CFB_FILLRECT
	761		select FB_CFB_COPYAREA
	762		select FB_CFB_IMAGEBLIT
	763		select FB_BOOT_VESA_SUPPORT
	764		help
	765		This is the frame buffer device driver for generic VESA 2.0
	766		compliant graphic cards. The older VESA 1.2 cards are not supported.
	767		You will get a boot time penguin logo at no additional cost. Please
	768		read <file:Documentation/fb/vesafb.txt>. If unsure, say Y.
	769
	770		config FB_EFI
	771		bool "EFI-based Framebuffer Support"
	772		depends on (FB = y) && X86 && EFI
	773		select FB_CFB_FILLRECT
	774		select FB_CFB_COPYAREA
	775		select FB_CFB_IMAGEBLIT
	776		help
	777		This is the EFI frame buffer device driver. If the firmware on
	778		your platform is EFI 1.10 or UEFI 2.0, select Y to add support for
	779		using the EFI framebuffer as your console.
	780
	781		config FB_N411
	782		tristate "N411 Apollo/Hecuba devkit support"
	783		depends on FB && X86 && MMU
	784		select FB_SYS_FILLRECT
	785		select FB_SYS_COPYAREA
	786		select FB_SYS_IMAGEBLIT
	787		select FB_SYS_FOPS
	788		select FB_DEFERRED_IO
	789		select FB_HECUBA
	790		help
	791		This enables support for the Apollo display controller in its
	792		Hecuba form using the n411 devkit.
	793
	794		config FB_HGA
	795		tristate "Hercules mono graphics support"
	796		depends on FB && X86
	797		help
	798		Say Y here if you have a Hercules mono graphics card.
	799
	800		To compile this driver as a module, choose M here: the
	801		module will be called hgafb.
	802
	803		As this card technology is at least 25 years old,
	804		most people will answer N here.
	805
	806		config FB_SGIVW
	807		tristate "SGI Visual Workstation framebuffer support"
	808		depends on FB && X86_VISWS
	809		select FB_CFB_FILLRECT
	810		select FB_CFB_COPYAREA
	811		select FB_CFB_IMAGEBLIT
	812		help
	813		SGI Visual Workstation support for framebuffer graphics.
	814
	815		config FB_GBE
	816		bool "SGI Graphics Backend frame buffer support"
	817		depends on (FB = y) && (SGI_IP32 || X86_VISWS)
	818		select FB_CFB_FILLRECT
	819		select FB_CFB_COPYAREA
	820		select FB_CFB_IMAGEBLIT
	821		help
	822		This is the frame buffer device driver for SGI Graphics Backend.
	823		This chip is used in SGI O2 and Visual Workstation 320/540.
	824
	825		config FB_GBE_MEM
	826		int "Video memory size in MB"
	827		depends on FB_GBE
	828		default 4
	829		help
	830		This is the amount of memory reserved for the framebuffer,
	831		which can be any value between 1MB and 8MB.
	832
	833		config FB_SBUS
	834		bool "SBUS and UPA framebuffers"
	835		depends on (FB = y) && SPARC
	836		help
	837		Say Y if you want support for SBUS or UPA based frame buffer device.
	838
	839		config FB_BW2
	840		bool "BWtwo support"
	841		depends on (FB = y) && (SPARC && FB_SBUS)
	842		select FB_CFB_FILLRECT
	843		select FB_CFB_COPYAREA
	844		select FB_CFB_IMAGEBLIT
	845		help
	846		This is the frame buffer device driver for the BWtwo frame buffer.
	847
	848		config FB_CG3
	849		bool "CGthree support"
	850		depends on (FB = y) && (SPARC && FB_SBUS)
	851		select FB_CFB_FILLRECT
	852		select FB_CFB_COPYAREA
	853		select FB_CFB_IMAGEBLIT
	854		help
	855		This is the frame buffer device driver for the CGthree frame buffer.
	856
	857		config FB_CG6
	858		bool "CGsix (GX,TurboGX) support"
	859		depends on (FB = y) && (SPARC && FB_SBUS)
	860		select FB_CFB_COPYAREA
	861		select FB_CFB_IMAGEBLIT
	862		help
	863		This is the frame buffer device driver for the CGsix (GX, TurboGX)
	864		frame buffer.
	865
	866		config FB_FFB
	867		bool "Creator/Creator3D/Elite3D support"
	868		depends on FB_SBUS && SPARC64
	869		select FB_CFB_COPYAREA
	870		select FB_CFB_IMAGEBLIT
	871		help
	872		This is the frame buffer device driver for the Creator, Creator3D,
	873		and Elite3D graphics boards.
	874
	875		config FB_TCX
	876		bool "TCX (SS4/SS5 only) support"
	877		depends on FB_SBUS
	878		select FB_CFB_FILLRECT
	879		select FB_CFB_COPYAREA
	880		select FB_CFB_IMAGEBLIT
	881		help
	882		This is the frame buffer device driver for the TCX 24/8bit frame
	883		buffer.
	884
	885		config FB_CG14
	886		bool "CGfourteen (SX) support"
	887		depends on FB_SBUS
	888		select FB_CFB_FILLRECT
	889		select FB_CFB_COPYAREA
	890		select FB_CFB_IMAGEBLIT
	891		help
	892		This is the frame buffer device driver for the CGfourteen frame
	893		buffer on Desktop SPARCsystems with the SX graphics option.
	894
	895		config FB_P9100
	896		bool "P9100 (Sparcbook 3 only) support"
	897		depends on FB_SBUS
	898		select FB_CFB_FILLRECT
	899		select FB_CFB_COPYAREA
	900		select FB_CFB_IMAGEBLIT
	901		help
	902		This is the frame buffer device driver for the P9100 card
	903		supported on Sparcbook 3 machines.
	904
	905		config FB_LEO
	906		bool "Leo (ZX) support"
	907		depends on FB_SBUS
	908		select FB_CFB_FILLRECT
	909		select FB_CFB_COPYAREA
	910		select FB_CFB_IMAGEBLIT
	911		help
	912		This is the frame buffer device driver for the SBUS-based Sun ZX
	913		(leo) frame buffer cards.
	914
	915		config FB_IGA
	916		bool "IGA 168x display support"
	917		depends on (FB = y) && SPARC32
	918		select FB_CFB_FILLRECT
	919		select FB_CFB_COPYAREA
	920		select FB_CFB_IMAGEBLIT
	921		help
	922		This is the framebuffer device for the INTERGRAPHICS 1680 and
	923		successor frame buffer cards.
	924
	925		config FB_XVR500
	926		bool "Sun XVR-500 3DLABS Wildcat support"
	927		depends on (FB = y) && PCI && SPARC64
	928		select FB_CFB_FILLRECT
	929		select FB_CFB_COPYAREA
	930		select FB_CFB_IMAGEBLIT
	931		help
	932		This is the framebuffer device for the Sun XVR-500 and similar
	933		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	934		only works on sparc64 systems where the system firmware has
	935		mostly initialized the card already. It is treated as a
	936		completely dumb framebuffer device.
	937
	938		config FB_XVR2500
	939		bool "Sun XVR-2500 3DLABS Wildcat support"
	940		depends on (FB = y) && PCI && SPARC64
	941		select FB_CFB_FILLRECT
	942		select FB_CFB_COPYAREA
	943		select FB_CFB_IMAGEBLIT
	944		help
	945		This is the framebuffer device for the Sun XVR-2500 and similar
	946		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	947		only works on sparc64 systems where the system firmware has
	948		mostly initialized the card already. It is treated as a
	949		completely dumb framebuffer device.
	950
	951		config FB_XVR1000
	952		bool "Sun XVR-1000 support"
	953		depends on (FB = y) && SPARC64
	954		select FB_CFB_FILLRECT
	955		select FB_CFB_COPYAREA
	956		select FB_CFB_IMAGEBLIT
	957		help
	958		This is the framebuffer device for the Sun XVR-1000 and similar
	959		graphics cards. The driver only works on sparc64 systems where
	960		the system firmware has mostly initialized the card already. It
	961		is treated as a completely dumb framebuffer device.
	962
	963		config FB_PVR2
	964		tristate "NEC PowerVR 2 display support"
	965		depends on FB && SH_DREAMCAST
	966		select FB_CFB_FILLRECT
	967		select FB_CFB_COPYAREA
	968		select FB_CFB_IMAGEBLIT
	969		---help---
	970		Say Y here if you have a PowerVR 2 card in your box. If you plan to
	971		run linux on your Dreamcast, you will have to say Y here.
	972		This driver may or may not work on other PowerVR 2 cards, but is
	973		totally untested. Use at your own risk. If unsure, say N.
	974
	975		To compile this driver as a module, choose M here: the
	976		module will be called pvr2fb.
	977
	978		You can pass several parameters to the driver at boot time or at
	979		module load time. The parameters look like "video=pvr2:XXX", where
	980		the meaning of XXX can be found at the end of the main source file
	981		(<file:drivers/video/pvr2fb.c>). Please see the file
	982		<file:Documentation/fb/pvr2fb.txt>.
	983
	984		config FB_EPSON1355
	985		bool "Epson 1355 framebuffer support"
	986		depends on (FB = y) && ARCH_CEIVA
	987		select FB_CFB_FILLRECT
	988		select FB_CFB_COPYAREA
	989		select FB_CFB_IMAGEBLIT
	990		help
	991		Build in support for the SED1355 Epson Research Embedded RAMDAC
	992		LCD/CRT Controller (since redesignated as the S1D13505) as a
	993		framebuffer. Product specs at
	994		<http://vdc.epson.com/>.
	995
	996		config FB_S1D13XXX
	997		tristate "Epson S1D13XXX framebuffer support"
	998		depends on FB
	999		select FB_CFB_FILLRECT
	1000		select FB_CFB_COPYAREA
	1001		select FB_CFB_IMAGEBLIT
	1002		help
	1003		Support for S1D13XXX framebuffer device family (currently only
	1004		working with S1D13806). Product specs at
	1005		<http://vdc.epson.com/>
	1006
	1007		config FB_ATMEL
	1008		tristate "AT91/AT32 LCD Controller support"
	1009		depends on FB && HAVE_FB_ATMEL
	1010		select FB_CFB_FILLRECT
	1011		select FB_CFB_COPYAREA
	1012		select FB_CFB_IMAGEBLIT
	1013		help
	1014		This enables support for the AT91/AT32 LCD Controller.
	1015
	1016		config FB_INTSRAM
	1017		bool "Frame Buffer in internal SRAM"
	1018		depends on FB_ATMEL && ARCH_AT91SAM9261
	1019		help
	1020		Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
	1021		to let frame buffer in external SDRAM.
	1022
	1023		config FB_ATMEL_STN
	1024		bool "Use a STN display with AT91/AT32 LCD Controller"
	1025		depends on FB_ATMEL && (MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK)
	1026		default n
	1027		help
	1028		Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
	1029		Controller. Say N if you want to connect a TFT.
	1030
	1031		If unsure, say N.
	1032
	1033		config FB_NVIDIA
	1034		tristate "nVidia Framebuffer Support"
	1035		depends on FB && PCI
	1036		select FB_BACKLIGHT if FB_NVIDIA_BACKLIGHT
	1037		select FB_MODE_HELPERS
	1038		select FB_CFB_FILLRECT
	1039		select FB_CFB_COPYAREA
	1040		select FB_CFB_IMAGEBLIT
	1041		select BITREVERSE
	1042		select VGASTATE
	1043		help
	1044		This driver supports graphics boards with the nVidia chips, TNT
	1045		and newer. For very old chipsets, such as the RIVA128, then use
	1046		the rivafb.
	1047		Say Y if you have such a graphics board.
	1048
	1049		To compile this driver as a module, choose M here: the
	1050		module will be called nvidiafb.
	1051
	1052		config FB_NVIDIA_I2C
	1053		bool "Enable DDC Support"
	1054		depends on FB_NVIDIA
	1055		select FB_DDC
	1056		help
	1057		This enables I2C support for nVidia Chipsets. This is used
	1058		only for getting EDID information from the attached display
	1059		allowing for robust video mode handling and switching.
	1060
	1061		Because fbdev-2.6 requires that drivers must be able to
	1062		independently validate video mode parameters, you should say Y
	1063		here.
	1064
	1065		config FB_NVIDIA_DEBUG
	1066		bool "Lots of debug output"
	1067		depends on FB_NVIDIA
	1068		default n
	1069		help
	1070		Say Y here if you want the nVidia driver to output all sorts
	1071		of debugging information to provide to the maintainer when
	1072		something goes wrong.
	1073
	1074		config FB_NVIDIA_BACKLIGHT
	1075		bool "Support for backlight control"
	1076		depends on FB_NVIDIA
	1077		default y
	1078		help
	1079		Say Y here if you want to control the backlight of your display.
	1080
	1081		config FB_RIVA
	1082		tristate "nVidia Riva support"
	1083		depends on FB && PCI
	1084		select FB_BACKLIGHT if FB_RIVA_BACKLIGHT
	1085		select FB_MODE_HELPERS
	1086		select FB_CFB_FILLRECT
	1087		select FB_CFB_COPYAREA
	1088		select FB_CFB_IMAGEBLIT
	1089		select BITREVERSE
	1090		select VGASTATE
	1091		help
	1092		This driver supports graphics boards with the nVidia Riva/Geforce
	1093		chips.
	1094		Say Y if you have such a graphics board.
	1095
	1096		To compile this driver as a module, choose M here: the
	1097		module will be called rivafb.
	1098
	1099		config FB_RIVA_I2C
	1100		bool "Enable DDC Support"
	1101		depends on FB_RIVA
	1102		select FB_DDC
	1103		help
	1104		This enables I2C support for nVidia Chipsets. This is used
	1105		only for getting EDID information from the attached display
	1106		allowing for robust video mode handling and switching.
	1107
	1108		Because fbdev-2.6 requires that drivers must be able to
	1109		independently validate video mode parameters, you should say Y
	1110		here.
	1111
	1112		config FB_RIVA_DEBUG
	1113		bool "Lots of debug output"
	1114		depends on FB_RIVA
	1115		default n
	1116		help
	1117		Say Y here if you want the Riva driver to output all sorts
	1118		of debugging information to provide to the maintainer when
	1119		something goes wrong.
	1120
	1121		config FB_RIVA_BACKLIGHT
	1122		bool "Support for backlight control"
	1123		depends on FB_RIVA
	1124		default y
	1125		help
	1126		Say Y here if you want to control the backlight of your display.
	1127
	1128		config FB_I740
	1129		tristate "Intel740 support (EXPERIMENTAL)"
	1130		depends on EXPERIMENTAL && FB && PCI
	1131		select FB_MODE_HELPERS
	1132		select FB_CFB_FILLRECT
	1133		select FB_CFB_COPYAREA
	1134		select FB_CFB_IMAGEBLIT
	1135		select VGASTATE
	1136		select FB_DDC
	1137		help
	1138		This driver supports graphics cards based on Intel740 chip.
	1139
	1140		config FB_I810
	1141		tristate "Intel 810/815 support (EXPERIMENTAL)"
	1142		depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
	1143		select FB_MODE_HELPERS
	1144		select FB_CFB_FILLRECT
	1145		select FB_CFB_COPYAREA
	1146		select FB_CFB_IMAGEBLIT
	1147		select VGASTATE
	1148		help
	1149		This driver supports the on-board graphics built in to the Intel 810
	1150		and 815 chipsets. Say Y if you have and plan to use such a board.
	1151
	1152		To compile this driver as a module, choose M here: the
	1153		module will be called i810fb.
	1154
	1155		For more information, please read
	1156		<file:Documentation/fb/intel810.txt>
	1157
	1158		config FB_I810_GTF
	1159		bool "use VESA Generalized Timing Formula"
	1160		depends on FB_I810
	1161		help
	1162		If you say Y, then the VESA standard, Generalized Timing Formula
	1163		or GTF, will be used to calculate the required video timing values
	1164		per video mode. Since the GTF allows nondiscrete timings
	1165		(nondiscrete being a range of values as opposed to discrete being a
	1166		set of values), you'll be able to use any combination of horizontal
	1167		and vertical resolutions, and vertical refresh rates without having
	1168		to specify your own timing parameters. This is especially useful
	1169		to maximize the performance of an aging display, or if you just
	1170		have a display with nonstandard dimensions. A VESA compliant
	1171		monitor is recommended, but can still work with non-compliant ones.
	1172		If you need or want this, then select this option. The timings may
	1173		not be compliant with Intel's recommended values. Use at your own
	1174		risk.
	1175
	1176		If you say N, the driver will revert to discrete video timings
	1177		using a set recommended by Intel in their documentation.
	1178
	1179		If unsure, say N.
	1180
	1181		config FB_I810_I2C
	1182		bool "Enable DDC Support"
	1183		depends on FB_I810 && FB_I810_GTF
	1184		select FB_DDC
	1185		help
	1186
	1187		config FB_LE80578
	1188		tristate "Intel LE80578 (Vermilion) support"
	1189		depends on FB && PCI && X86
	1190		select FB_MODE_HELPERS
	1191		select FB_CFB_FILLRECT
	1192		select FB_CFB_COPYAREA
	1193		select FB_CFB_IMAGEBLIT
	1194		help
	1195		This driver supports the LE80578 (Vermilion Range) chipset
	1196
	1197		config FB_CARILLO_RANCH
	1198		tristate "Intel Carillo Ranch support"
	1199		depends on FB_LE80578 && FB && PCI && X86
	1200		help
	1201		This driver supports the LE80578 (Carillo Ranch) board
	1202
	1203		config FB_INTEL
	1204		tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support (EXPERIMENTAL)"
	1205		depends on EXPERIMENTAL && FB && PCI && X86 && AGP_INTEL && EXPERT
	1206		select FB_MODE_HELPERS
	1207		select FB_CFB_FILLRECT
	1208		select FB_CFB_COPYAREA
	1209		select FB_CFB_IMAGEBLIT
	1210		select FB_BOOT_VESA_SUPPORT if FB_INTEL = y
	1211		depends on !DRM_I915
	1212		help
	1213		This driver supports the on-board graphics built in to the Intel
	1214		830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/965G/965GM chipsets.
	1215		Say Y if you have and plan to use such a board.
	1216
	1217		To make FB_INTELFB=Y work you need to say AGP_INTEL=y too.
	1218
	1219		To compile this driver as a module, choose M here: the
	1220		module will be called intelfb.
	1221
	1222		For more information, please read <file:Documentation/fb/intelfb.txt>
	1223
	1224		config FB_INTEL_DEBUG
	1225		bool "Intel driver Debug Messages"
	1226		depends on FB_INTEL
	1227		---help---
	1228		Say Y here if you want the Intel driver to output all sorts
	1229		of debugging information to provide to the maintainer when
	1230		something goes wrong.
	1231
	1232		config FB_INTEL_I2C
	1233		bool "DDC/I2C for Intel framebuffer support"
	1234		depends on FB_INTEL
	1235		select FB_DDC
	1236		default y
	1237		help
	1238		Say Y here if you want DDC/I2C support for your on-board Intel graphics.
	1239
	1240		config FB_MATROX
	1241		tristate "Matrox acceleration"
	1242		depends on FB && PCI
	1243		select FB_CFB_FILLRECT
	1244		select FB_CFB_COPYAREA
	1245		select FB_CFB_IMAGEBLIT
	1246		select FB_TILEBLITTING
	1247		select FB_MACMODES if PPC_PMAC
	1248		---help---
	1249		Say Y here if you have a Matrox Millennium, Matrox Millennium II,
	1250		Matrox Mystique, Matrox Mystique 220, Matrox Productiva G100, Matrox
	1251		Mystique G200, Matrox Millennium G200, Matrox Marvel G200 video,
	1252		Matrox G400, G450 or G550 card in your box.
	1253
	1254		To compile this driver as a module, choose M here: the
	1255		module will be called matroxfb.
	1256
	1257		You can pass several parameters to the driver at boot time or at
	1258		module load time. The parameters look like "video=matroxfb:XXX", and
	1259		are described in <file:Documentation/fb/matroxfb.txt>.
	1260
	1261		config FB_MATROX_MILLENIUM
	1262		bool "Millennium I/II support"
	1263		depends on FB_MATROX
	1264		help
	1265		Say Y here if you have a Matrox Millennium or Matrox Millennium II
	1266		video card. If you select "Advanced lowlevel driver options" below,
	1267		you should check 4 bpp packed pixel, 8 bpp packed pixel, 16 bpp
	1268		packed pixel, 24 bpp packed pixel and 32 bpp packed pixel. You can
	1269		also use font widths different from 8.
	1270
	1271		config FB_MATROX_MYSTIQUE
	1272		bool "Mystique support"
	1273		depends on FB_MATROX
	1274		help
	1275		Say Y here if you have a Matrox Mystique or Matrox Mystique 220
	1276		video card. If you select "Advanced lowlevel driver options" below,
	1277		you should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp
	1278		packed pixel and 32 bpp packed pixel. You can also use font widths
	1279		different from 8.
	1280
	1281		config FB_MATROX_G
	1282		bool "G100/G200/G400/G450/G550 support"
	1283		depends on FB_MATROX
	1284		---help---
	1285		Say Y here if you have a Matrox G100, G200, G400, G450 or G550 based
	1286		video card. If you select "Advanced lowlevel driver options", you
	1287		should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp packed
	1288		pixel and 32 bpp packed pixel. You can also use font widths
	1289		different from 8.
	1290
	1291		If you need support for G400 secondary head, you must say Y to
	1292		"Matrox I2C support" and "G400 second head support" right below.
	1293		G450/G550 secondary head and digital output are supported without
	1294		additional modules.
	1295
	1296		The driver starts in monitor mode. You must use the matroxset tool
	1297		(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
	1298		swap primary and secondary head outputs, or to change output mode.
	1299		Secondary head driver always start in 640x480 resolution and you
	1300		must use fbset to change it.
	1301
	1302		Do not forget that second head supports only 16 and 32 bpp
	1303		packed pixels, so it is a good idea to compile them into the kernel
	1304		too. You can use only some font widths, as the driver uses generic
	1305		painting procedures (the secondary head does not use acceleration
	1306		engine).
	1307
	1308		G450/G550 hardware can display TV picture only from secondary CRTC,
	1309		and it performs no scaling, so picture must have 525 or 625 lines.
	1310
	1311		config FB_MATROX_I2C
	1312		tristate "Matrox I2C support"
	1313		depends on FB_MATROX
	1314		select FB_DDC
	1315		---help---
	1316		This drivers creates I2C buses which are needed for accessing the
	1317		DDC (I2C) bus present on all Matroxes, an I2C bus which
	1318		interconnects Matrox optional devices, like MGA-TVO on G200 and
	1319		G400, and the secondary head DDC bus, present on G400 only.
	1320
	1321		You can say Y or M here if you want to experiment with monitor
	1322		detection code. You must say Y or M here if you want to use either
	1323		second head of G400 or MGA-TVO on G200 or G400.
	1324
	1325		If you compile it as module, it will create a module named
	1326		i2c-matroxfb.
	1327
	1328		config FB_MATROX_MAVEN
	1329		tristate "G400 second head support"
	1330		depends on FB_MATROX_G && FB_MATROX_I2C
	1331		---help---
	1332		WARNING !!! This support does not work with G450 !!!
	1333
	1334		Say Y or M here if you want to use a secondary head (meaning two
	1335		monitors in parallel) on G400 or MGA-TVO add-on on G200. Secondary
	1336		head is not compatible with accelerated XFree 3.3.x SVGA servers -
	1337		secondary head output is blanked while you are in X. With XFree
	1338		3.9.17 preview you can use both heads if you use SVGA over fbdev or
	1339		the fbdev driver on first head and the fbdev driver on second head.
	1340
	1341		If you compile it as module, two modules are created,
	1342		matroxfb_crtc2 and matroxfb_maven. Matroxfb_maven is needed for
	1343		both G200 and G400, matroxfb_crtc2 is needed only by G400. You must
	1344		also load i2c-matroxfb to get it to run.
	1345
	1346		The driver starts in monitor mode and you must use the matroxset
	1347		tool (available at
	1348		<ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to switch it to
	1349		PAL or NTSC or to swap primary and secondary head outputs.
	1350		Secondary head driver also always start in 640x480 resolution, you
	1351		must use fbset to change it.
	1352
	1353		Also do not forget that second head supports only 16 and 32 bpp
	1354		packed pixels, so it is a good idea to compile them into the kernel
	1355		too. You can use only some font widths, as the driver uses generic
	1356		painting procedures (the secondary head does not use acceleration
	1357		engine).
	1358
	1359		config FB_RADEON
	1360		tristate "ATI Radeon display support"
	1361		depends on FB && PCI
	1362		select FB_BACKLIGHT if FB_RADEON_BACKLIGHT
	1363		select FB_MODE_HELPERS
	1364		select FB_CFB_FILLRECT
	1365		select FB_CFB_COPYAREA
	1366		select FB_CFB_IMAGEBLIT
	1367		select FB_MACMODES if PPC_OF
	1368		help
	1369		Choose this option if you want to use an ATI Radeon graphics card as
	1370		a framebuffer device. There are both PCI and AGP versions. You
	1371		don't need to choose this to run the Radeon in plain VGA mode.
	1372
	1373		There is a product page at
	1374		http://products.amd.com/en-us/GraphicCardResult.aspx
	1375
	1376		config FB_RADEON_I2C
	1377		bool "DDC/I2C for ATI Radeon support"
	1378		depends on FB_RADEON
	1379		select FB_DDC
	1380		default y
	1381		help
	1382		Say Y here if you want DDC/I2C support for your Radeon board.
	1383
	1384		config FB_RADEON_BACKLIGHT
	1385		bool "Support for backlight control"
	1386		depends on FB_RADEON
	1387		default y
	1388		help
	1389		Say Y here if you want to control the backlight of your display.
	1390
	1391		config FB_RADEON_DEBUG
	1392		bool "Lots of debug output from Radeon driver"
	1393		depends on FB_RADEON
	1394		default n
	1395		help
	1396		Say Y here if you want the Radeon driver to output all sorts
	1397		of debugging information to provide to the maintainer when
	1398		something goes wrong.
	1399
	1400		config FB_ATY128
	1401		tristate "ATI Rage128 display support"
	1402		depends on FB && PCI
	1403		select FB_CFB_FILLRECT
	1404		select FB_CFB_COPYAREA
	1405		select FB_CFB_IMAGEBLIT
	1406		select FB_BACKLIGHT if FB_ATY128_BACKLIGHT
	1407		select FB_MACMODES if PPC_PMAC
	1408		help
	1409		This driver supports graphics boards with the ATI Rage128 chips.
	1410		Say Y if you have such a graphics board and read
	1411		<file:Documentation/fb/aty128fb.txt>.
	1412
	1413		To compile this driver as a module, choose M here: the
	1414		module will be called aty128fb.
	1415
	1416		config FB_ATY128_BACKLIGHT
	1417		bool "Support for backlight control"
	1418		depends on FB_ATY128
	1419		default y
	1420		help
	1421		Say Y here if you want to control the backlight of your display.
	1422
	1423		config FB_ATY
	1424		tristate "ATI Mach64 display support" if PCI || ATARI
	1425		depends on FB && !SPARC32
	1426		select FB_CFB_FILLRECT
	1427		select FB_CFB_COPYAREA
	1428		select FB_CFB_IMAGEBLIT
	1429		select FB_BACKLIGHT if FB_ATY_BACKLIGHT
	1430		select FB_MACMODES if PPC
	1431		help
	1432		This driver supports graphics boards with the ATI Mach64 chips.
	1433		Say Y if you have such a graphics board.
	1434
	1435		To compile this driver as a module, choose M here: the
	1436		module will be called atyfb.
	1437
	1438		config FB_ATY_CT
	1439		bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support"
	1440		depends on PCI && FB_ATY
	1441		default y if SPARC64 && PCI
	1442		help
	1443		Say Y here to support use of ATI's 64-bit Rage boards (or other
	1444		boards based on the Mach64 CT, VT, GT, and LT chipsets) as a
	1445		framebuffer device. The ATI product support page for these boards
	1446		is at <http://support.ati.com/products/pc/mach64/mach64.html>.
	1447
	1448		config FB_ATY_GENERIC_LCD
	1449		bool "Mach64 generic LCD support (EXPERIMENTAL)"
	1450		depends on FB_ATY_CT
	1451		help
	1452		Say Y if you have a laptop with an ATI Rage LT PRO, Rage Mobility,
	1453		Rage XC, or Rage XL chipset.
	1454
	1455		config FB_ATY_GX
	1456		bool "Mach64 GX support" if PCI
	1457		depends on FB_ATY
	1458		default y if ATARI
	1459		help
	1460		Say Y here to support use of the ATI Mach64 Graphics Expression
	1461		board (or other boards based on the Mach64 GX chipset) as a
	1462		framebuffer device. The ATI product support page for these boards
	1463		is at
	1464		<http://support.ati.com/products/pc/mach64/graphics_xpression.html>.
	1465
	1466		config FB_ATY_BACKLIGHT
	1467		bool "Support for backlight control"
	1468		depends on FB_ATY
	1469		default y
	1470		help
	1471		Say Y here if you want to control the backlight of your display.
	1472
	1473		config FB_S3
	1474		tristate "S3 Trio/Virge support"
	1475		depends on FB && PCI
	1476		select FB_CFB_FILLRECT
	1477		select FB_CFB_COPYAREA
	1478		select FB_CFB_IMAGEBLIT
	1479		select FB_TILEBLITTING
	1480		select FB_SVGALIB
	1481		select VGASTATE
	1482		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1483		---help---
	1484		Driver for graphics boards with S3 Trio / S3 Virge chip.
	1485
	1486		config FB_S3_DDC
	1487		bool "DDC for S3 support"
	1488		depends on FB_S3
	1489		select FB_DDC
	1490		default y
	1491		help
	1492		Say Y here if you want DDC support for your S3 graphics card.
	1493
	1494		config FB_SAVAGE
	1495		tristate "S3 Savage support"
	1496		depends on FB && PCI && EXPERIMENTAL
	1497		select FB_MODE_HELPERS
	1498		select FB_CFB_FILLRECT
	1499		select FB_CFB_COPYAREA
	1500		select FB_CFB_IMAGEBLIT
	1501		select VGASTATE
	1502		help
	1503		This driver supports notebooks and computers with S3 Savage PCI/AGP
	1504		chips.
	1505
	1506		Say Y if you have such a graphics card.
	1507
	1508		To compile this driver as a module, choose M here; the module
	1509		will be called savagefb.
	1510
	1511		config FB_SAVAGE_I2C
	1512		bool "Enable DDC2 Support"
	1513		depends on FB_SAVAGE
	1514		select FB_DDC
	1515		help
	1516		This enables I2C support for S3 Savage Chipsets. This is used
	1517		only for getting EDID information from the attached display
	1518		allowing for robust video mode handling and switching.
	1519
	1520		Because fbdev-2.6 requires that drivers must be able to
	1521		independently validate video mode parameters, you should say Y
	1522		here.
	1523
	1524		config FB_SAVAGE_ACCEL
	1525		bool "Enable Console Acceleration"
	1526		depends on FB_SAVAGE
	1527		default n
	1528		help
	1529		This option will compile in console acceleration support. If
	1530		the resulting framebuffer console has bothersome glitches, then
	1531		choose N here.
	1532
	1533		config FB_SIS
	1534		tristate "SiS/XGI display support"
	1535		depends on FB && PCI
	1536		select FB_CFB_FILLRECT
	1537		select FB_CFB_COPYAREA
	1538		select FB_CFB_IMAGEBLIT
	1539		select FB_BOOT_VESA_SUPPORT if FB_SIS = y
	1540		help
	1541		This is the frame buffer device driver for the SiS 300, 315, 330
	1542		and 340 series as well as XGI V3XT, V5, V8, Z7 graphics chipsets.
	1543		Specs available at <http://www.sis.com> and <http://www.xgitech.com>.
	1544
	1545		To compile this driver as a module, choose M here; the module
	1546		will be called sisfb.
	1547
	1548		config FB_SIS_300
	1549		bool "SiS 300 series support"
	1550		depends on FB_SIS
	1551		help
	1552		Say Y here to support use of the SiS 300/305, 540, 630 and 730.
	1553
	1554		config FB_SIS_315
	1555		bool "SiS 315/330/340 series and XGI support"
	1556		depends on FB_SIS
	1557		help
	1558		Say Y here to support use of the SiS 315, 330 and 340 series
	1559		(315/H/PRO, 55x, 650, 651, 740, 330, 661, 741, 760, 761) as well
	1560		as XGI V3XT, V5, V8 and Z7.
	1561
	1562		config FB_VIA
	1563		tristate "VIA UniChrome (Pro) and Chrome9 display support"
	1564		depends on FB && PCI && X86
	1565		select FB_CFB_FILLRECT
	1566		select FB_CFB_COPYAREA
	1567		select FB_CFB_IMAGEBLIT
	1568		select I2C_ALGOBIT
	1569		select I2C
	1570		select GPIOLIB
	1571		help
	1572		This is the frame buffer device driver for Graphics chips of VIA
	1573		UniChrome (Pro) Family (CLE266,PM800/CN400,P4M800CE/P4M800Pro/
	1574		CN700/VN800,CX700/VX700,P4M890) and Chrome9 Family (K8M890,CN896
	1575		/P4M900,VX800)
	1576		Say Y if you have a VIA UniChrome graphics board.
	1577
	1578		To compile this driver as a module, choose M here: the
	1579		module will be called viafb.
	1580
	1581		if FB_VIA
	1582
	1583		config FB_VIA_DIRECT_PROCFS
	1584		bool "direct hardware access via procfs (DEPRECATED)(DANGEROUS)"
	1585		depends on FB_VIA
	1586		default n
	1587		help
	1588		Allow direct hardware access to some output registers via procfs.
	1589		This is dangerous but may provide the only chance to get the
	1590		correct output device configuration.
	1591		Its use is strongly discouraged.
	1592
	1593		config FB_VIA_X_COMPATIBILITY
	1594		bool "X server compatibility"
	1595		depends on FB_VIA
	1596		default n
	1597		help
	1598		This option reduces the functionality (power saving, ...) of the
	1599		framebuffer to avoid negative impact on the OpenChrome X server.
	1600		If you use any X server other than fbdev you should enable this
	1601		otherwise it should be safe to disable it and allow using all
	1602		features.
	1603
	1604		endif
	1605
	1606		config FB_NEOMAGIC
	1607		tristate "NeoMagic display support"
	1608		depends on FB && PCI
	1609		select FB_MODE_HELPERS
	1610		select FB_CFB_FILLRECT
	1611		select FB_CFB_COPYAREA
	1612		select FB_CFB_IMAGEBLIT
	1613		select VGASTATE
	1614		help
	1615		This driver supports notebooks with NeoMagic PCI chips.
	1616		Say Y if you have such a graphics card.
	1617
	1618		To compile this driver as a module, choose M here: the
	1619		module will be called neofb.
	1620
	1621		config FB_KYRO
	1622		tristate "IMG Kyro support"
	1623		depends on FB && PCI
	1624		select FB_CFB_FILLRECT
	1625		select FB_CFB_COPYAREA
	1626		select FB_CFB_IMAGEBLIT
	1627		help
	1628		Say Y here if you have a STG4000 / Kyro / PowerVR 3 based
	1629		graphics board.
	1630
	1631		To compile this driver as a module, choose M here: the
	1632		module will be called kyrofb.
	1633
	1634		config FB_3DFX
	1635		tristate "3Dfx Banshee/Voodoo3/Voodoo5 display support"
	1636		depends on FB && PCI
	1637		select FB_CFB_IMAGEBLIT
	1638		select FB_CFB_FILLRECT
	1639		select FB_CFB_COPYAREA
	1640		select FB_MODE_HELPERS
	1641		help
	1642		This driver supports graphics boards with the 3Dfx Banshee,
	1643		Voodoo3 or VSA-100 (aka Voodoo4/5) chips. Say Y if you have
	1644		such a graphics board.
	1645
	1646		To compile this driver as a module, choose M here: the
	1647		module will be called tdfxfb.
	1648
	1649		config FB_3DFX_ACCEL
	1650		bool "3Dfx Acceleration functions (EXPERIMENTAL)"
	1651		depends on FB_3DFX && EXPERIMENTAL
	1652		---help---
	1653		This will compile the 3Dfx Banshee/Voodoo3/VSA-100 frame buffer
	1654		device driver with acceleration functions.
	1655
	1656		config FB_3DFX_I2C
	1657		bool "Enable DDC/I2C support"
	1658		depends on FB_3DFX && EXPERIMENTAL
	1659		select FB_DDC
	1660		default y
	1661		help
	1662		Say Y here if you want DDC/I2C support for your 3dfx Voodoo3.
	1663
	1664		config FB_VOODOO1
	1665		tristate "3Dfx Voodoo Graphics (sst1) support"
	1666		depends on FB && PCI
	1667		select FB_CFB_FILLRECT
	1668		select FB_CFB_COPYAREA
	1669		select FB_CFB_IMAGEBLIT
	1670		---help---
	1671		Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
	1672		Voodoo2 (cvg) based graphics card.
	1673
	1674		To compile this driver as a module, choose M here: the
	1675		module will be called sstfb.
	1676
	1677		WARNING: Do not use any application that uses the 3D engine
	1678		(namely glide) while using this driver.
	1679		Please read the <file:Documentation/fb/sstfb.txt> for supported
	1680		options and other important info support.
	1681
	1682		config FB_VT8623
	1683		tristate "VIA VT8623 support"
	1684		depends on FB && PCI
	1685		select FB_CFB_FILLRECT
	1686		select FB_CFB_COPYAREA
	1687		select FB_CFB_IMAGEBLIT
	1688		select FB_TILEBLITTING
	1689		select FB_SVGALIB
	1690		select VGASTATE
	1691		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1692		---help---
	1693		Driver for CastleRock integrated graphics core in the
	1694		VIA VT8623 [Apollo CLE266] chipset.
	1695
	1696		config FB_TRIDENT
	1697		tristate "Trident/CyberXXX/CyberBlade support"
	1698		depends on FB && PCI
	1699		select FB_CFB_FILLRECT
	1700		select FB_CFB_COPYAREA
	1701		select FB_CFB_IMAGEBLIT
	1702		---help---
	1703		This is the frame buffer device driver for Trident PCI/AGP chipsets.
	1704		Supported chipset families are TGUI 9440/96XX, 3DImage, Blade3D
	1705		and Blade XP.
	1706		There are also integrated versions of these chips called CyberXXXX,
	1707		CyberImage or CyberBlade. These chips are mostly found in laptops
	1708		but also on some motherboards including early VIA EPIA motherboards.
	1709		For more information, read <file:Documentation/fb/tridentfb.txt>
	1710
	1711		Say Y if you have such a graphics board.
	1712
	1713		To compile this driver as a module, choose M here: the
	1714		module will be called tridentfb.
	1715
	1716		config FB_ARK
	1717		tristate "ARK 2000PV support"
	1718		depends on FB && PCI
	1719		select FB_CFB_FILLRECT
	1720		select FB_CFB_COPYAREA
	1721		select FB_CFB_IMAGEBLIT
	1722		select FB_TILEBLITTING
	1723		select FB_SVGALIB
	1724		select VGASTATE
	1725		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1726		---help---
	1727		Driver for PCI graphics boards with ARK 2000PV chip
	1728		and ICS 5342 RAMDAC.
	1729
	1730		config FB_PM3
	1731		tristate "Permedia3 support (EXPERIMENTAL)"
	1732		depends on FB && PCI && EXPERIMENTAL
	1733		select FB_CFB_FILLRECT
	1734		select FB_CFB_COPYAREA
	1735		select FB_CFB_IMAGEBLIT
	1736		help
	1737		This is the frame buffer device driver for the 3DLabs Permedia3
	1738		chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 &
	1739		similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000
	1740		and maybe other boards.
	1741
	1742		config FB_CARMINE
	1743		tristate "Fujitsu carmine frame buffer support"
	1744		depends on FB && PCI
	1745		select FB_CFB_FILLRECT
	1746		select FB_CFB_COPYAREA
	1747		select FB_CFB_IMAGEBLIT
	1748		help
	1749		This is the frame buffer device driver for the Fujitsu Carmine chip.
	1750		The driver provides two independent frame buffer devices.
	1751
	1752		choice
	1753		depends on FB_CARMINE
	1754		prompt "DRAM timing"
	1755		default FB_CARMINE_DRAM_EVAL
	1756
	1757		config FB_CARMINE_DRAM_EVAL
	1758		bool "Eval board timings"
	1759		help
	1760		Use timings which work on the eval card.
	1761
	1762		config CARMINE_DRAM_CUSTOM
	1763		bool "Custom board timings"
	1764		help
	1765		Use custom board timings.
	1766		endchoice
	1767
	1768		config FB_AU1100
	1769		bool "Au1100 LCD Driver"
	1770		depends on (FB = y) && MIPS_ALCHEMY
	1771		select FB_CFB_FILLRECT
	1772		select FB_CFB_COPYAREA
	1773		select FB_CFB_IMAGEBLIT
	1774		help
	1775		This is the framebuffer driver for the AMD Au1100 SOC. It can drive
	1776		various panels and CRTs by passing in kernel cmd line option
	1777		au1100fb:panel=<name>.
	1778
	1779		config FB_AU1200
	1780		bool "Au1200/Au1300 LCD Driver"
	1781		depends on (FB = y) && MIPS_ALCHEMY
	1782		select FB_SYS_FILLRECT
	1783		select FB_SYS_COPYAREA
	1784		select FB_SYS_IMAGEBLIT
	1785		select FB_SYS_FOPS
	1786		help
	1787		This is the framebuffer driver for the Au1200/Au1300 SOCs.
	1788		It can drive various panels and CRTs by passing in kernel cmd line
	1789		option au1200fb:panel=<name>.
	1790
	1791		config FB_VT8500
	1792		bool "VT8500 LCD Driver"
	1793		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
	1794		select FB_WMT_GE_ROPS
	1795		select FB_SYS_IMAGEBLIT
	1796		help
	1797		This is the framebuffer driver for VIA VT8500 integrated LCD
	1798		controller.
	1799
	1800		config FB_WM8505
	1801		bool "WM8505 frame buffer support"
	1802		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
	1803		select FB_WMT_GE_ROPS
	1804		select FB_SYS_IMAGEBLIT
	1805		help
	1806		This is the framebuffer driver for WonderMedia WM8505
	1807		integrated LCD controller.
	1808
	1809		source "drivers/video/geode/Kconfig"
	1810
	1811		config FB_HIT
	1812		tristate "HD64461 Frame Buffer support"
	1813		depends on FB && HD64461
	1814		select FB_CFB_FILLRECT
	1815		select FB_CFB_COPYAREA
	1816		select FB_CFB_IMAGEBLIT
	1817		help
	1818		This is the frame buffer device driver for the Hitachi HD64461 LCD
	1819		frame buffer card.
	1820
	1821		config FB_PMAG_AA
	1822		bool "PMAG-AA TURBOchannel framebuffer support"
	1823		depends on (FB = y) && TC
	1824		select FB_CFB_FILLRECT
	1825		select FB_CFB_COPYAREA
	1826		select FB_CFB_IMAGEBLIT
	1827		help
	1828		Support for the PMAG-AA TURBOchannel framebuffer card (1280x1024x1)
	1829		used mainly in the MIPS-based DECstation series.
	1830
	1831		config FB_PMAG_BA
	1832		tristate "PMAG-BA TURBOchannel framebuffer support"
	1833		depends on FB && TC
	1834		select FB_CFB_FILLRECT
	1835		select FB_CFB_COPYAREA
	1836		select FB_CFB_IMAGEBLIT
	1837		help
	1838		Support for the PMAG-BA TURBOchannel framebuffer card (1024x864x8)
	1839		used mainly in the MIPS-based DECstation series.
	1840
	1841		config FB_PMAGB_B
	1842		tristate "PMAGB-B TURBOchannel framebuffer support"
	1843		depends on FB && TC
	1844		select FB_CFB_FILLRECT
	1845		select FB_CFB_COPYAREA
	1846		select FB_CFB_IMAGEBLIT
	1847		help
	1848		Support for the PMAGB-B TURBOchannel framebuffer card used mainly
	1849		in the MIPS-based DECstation series. The card is currently only
	1850		supported in 1280x1024x8 mode.
	1851
	1852		config FB_MAXINE
	1853		bool "Maxine (Personal DECstation) onboard framebuffer support"
	1854		depends on (FB = y) && MACH_DECSTATION
	1855		select FB_CFB_FILLRECT
	1856		select FB_CFB_COPYAREA
	1857		select FB_CFB_IMAGEBLIT
	1858		help
	1859		Support for the onboard framebuffer (1024x768x8) in the Personal
	1860		DECstation series (Personal DECstation 5000/20, /25, /33, /50,
	1861		Codename "Maxine").
	1862
	1863		config FB_G364
	1864		bool "G364 frame buffer support"
	1865		depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700)
	1866		select FB_CFB_FILLRECT
	1867		select FB_CFB_COPYAREA
	1868		select FB_CFB_IMAGEBLIT
	1869		help
	1870		The G364 driver is the framebuffer used in MIPS Magnum 4000 and
	1871		Olivetti M700-10 systems.
	1872
	1873		config FB_68328
	1874		bool "Motorola 68328 native frame buffer support"
	1875		depends on (FB = y) && (M68328 || M68EZ328 || M68VZ328)
	1876		select FB_CFB_FILLRECT
	1877		select FB_CFB_COPYAREA
	1878		select FB_CFB_IMAGEBLIT
	1879		help
	1880		Say Y here if you want to support the built-in frame buffer of
	1881		the Motorola 68328 CPU family.
	1882
	1883		config FB_PXA168
	1884		tristate "PXA168/910 LCD framebuffer support"
	1885		depends on FB && (CPU_PXA168 || CPU_PXA910)
	1886		select FB_CFB_FILLRECT
	1887		select FB_CFB_COPYAREA
	1888		select FB_CFB_IMAGEBLIT
	1889		---help---
	1890		Frame buffer driver for the built-in LCD controller in the Marvell
	1891		MMP processor.
	1892
	1893		config FB_PXA
	1894		tristate "PXA LCD framebuffer support"
	1895		depends on FB && ARCH_PXA
	1896		select FB_CFB_FILLRECT
	1897		select FB_CFB_COPYAREA
	1898		select FB_CFB_IMAGEBLIT
	1899		---help---
	1900		Frame buffer driver for the built-in LCD controller in the Intel
	1901		PXA2x0 processor.
	1902
	1903		This driver is also available as a module ( = code which can be
	1904		inserted and removed from the running kernel whenever you want). The
	1905		module will be called pxafb. If you want to compile it as a module,
	1906		say M here and read <file:Documentation/kbuild/modules.txt>.
	1907
	1908		If unsure, say N.
	1909
	1910		config FB_PXA_OVERLAY
	1911		bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
	1912		default n
	1913		depends on FB_PXA && (PXA27x || PXA3xx)
	1914
	1915		config FB_PXA_SMARTPANEL
	1916		bool "PXA Smartpanel LCD support"
	1917		default n
	1918		depends on FB_PXA
	1919
	1920		config FB_PXA_PARAMETERS
	1921		bool "PXA LCD command line parameters"
	1922		default n
	1923		depends on FB_PXA
	1924		---help---
	1925		Enable the use of kernel command line or module parameters
	1926		to configure the physical properties of the LCD panel when
	1927		using the PXA LCD driver.
	1928
	1929		This option allows you to override the panel parameters
	1930		supplied by the platform in order to support multiple
	1931		different models of flatpanel. If you will only be using a
	1932		single model of flatpanel then you can safely leave this
	1933		option disabled.
	1934
	1935		<file:Documentation/fb/pxafb.txt> describes the available parameters.
	1936
	1937		config PXA3XX_GCU
	1938		tristate "PXA3xx 2D graphics accelerator driver"
	1939		depends on FB_PXA
	1940		help
	1941		Kernelspace driver for the 2D graphics controller unit (GCU)
	1942		found on PXA3xx processors. There is a counterpart driver in the
	1943		DirectFB suite, see http://www.directfb.org/
	1944
	1945		If you compile this as a module, it will be called pxa3xx_gcu.
	1946
	1947		config FB_MBX
	1948		tristate "2700G LCD framebuffer support"
	1949		depends on FB && ARCH_PXA
	1950		select FB_CFB_FILLRECT
	1951		select FB_CFB_COPYAREA
	1952		select FB_CFB_IMAGEBLIT
	1953		---help---
	1954		Framebuffer driver for the Intel 2700G (Marathon) Graphics
	1955		Accelerator
	1956
	1957		config FB_MBX_DEBUG
	1958		bool "Enable debugging info via debugfs"
	1959		depends on FB_MBX && DEBUG_FS
	1960		default n
	1961		---help---
	1962		Enable this if you want debugging information using the debug
	1963		filesystem (debugfs)
	1964
	1965		If unsure, say N.
	1966
	1967		config FB_FSL_DIU
	1968		tristate "Freescale DIU framebuffer support"
	1969		depends on FB && FSL_SOC
	1970		select FB_MODE_HELPERS
	1971		select FB_CFB_FILLRECT
	1972		select FB_CFB_COPYAREA
	1973		select FB_CFB_IMAGEBLIT
	1974		select PPC_LIB_RHEAP
	1975		---help---
	1976		Framebuffer driver for the Freescale SoC DIU
	1977
	1978		config FB_W100
	1979		tristate "W100 frame buffer support"
	1980		depends on FB && ARCH_PXA
	1981		select FB_CFB_FILLRECT
	1982		select FB_CFB_COPYAREA
	1983		select FB_CFB_IMAGEBLIT
	1984		---help---
	1985		Frame buffer driver for the w100 as found on the Sharp SL-Cxx series.
	1986		It can also drive the w3220 chip found on iPAQ hx4700.
	1987
	1988		This driver is also available as a module ( = code which can be
	1989		inserted and removed from the running kernel whenever you want). The
	1990		module will be called w100fb. If you want to compile it as a module,
	1991		say M here and read <file:Documentation/kbuild/modules.txt>.
	1992
	1993		If unsure, say N.
	1994
	1995		config FB_SH_MOBILE_LCDC
	1996		tristate "SuperH Mobile LCDC framebuffer support"
	1997		depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	1998		select FB_SYS_FILLRECT
	1999		select FB_SYS_COPYAREA
	2000		select FB_SYS_IMAGEBLIT
	2001		select FB_SYS_FOPS
	2002		select FB_DEFERRED_IO
	2003		select FB_BACKLIGHT
	2004		select SH_MIPI_DSI if SH_LCD_MIPI_DSI
	2005		---help---
	2006		Frame buffer driver for the on-chip SH-Mobile LCD controller.
	2007
	2008		config FB_SH_MOBILE_HDMI
	2009		tristate "SuperH Mobile HDMI controller support"
	2010		depends on FB_SH_MOBILE_LCDC
	2011		select FB_MODE_HELPERS
	2012		select SOUND
	2013		select SND
	2014		select SND_SOC
	2015		---help---
	2016		Driver for the on-chip SH-Mobile HDMI controller.
	2017
	2018		config FB_TMIO
	2019		tristate "Toshiba Mobile IO FrameBuffer support"
	2020		depends on FB && MFD_CORE
	2021		select FB_CFB_FILLRECT
	2022		select FB_CFB_COPYAREA
	2023		select FB_CFB_IMAGEBLIT
	2024		---help---
	2025		Frame buffer driver for the Toshiba Mobile IO integrated as found
	2026		on the Sharp SL-6000 series
	2027
	2028		This driver is also available as a module ( = code which can be
	2029		inserted and removed from the running kernel whenever you want). The
	2030		module will be called tmiofb. If you want to compile it as a module,
	2031		say M here and read <file:Documentation/kbuild/modules.txt>.
	2032
	2033		If unsure, say N.
	2034
	2035		config FB_TMIO_ACCELL
	2036		bool "tmiofb acceleration"
	2037		depends on FB_TMIO
	2038		default y
	2039
	2040		config FB_S3C
	2041		tristate "Samsung S3C framebuffer support"
	2042		depends on FB && (S3C_DEV_FB || S5P_DEV_FIMD0)
	2043		select FB_CFB_FILLRECT
	2044		select FB_CFB_COPYAREA
	2045		select FB_CFB_IMAGEBLIT
	2046		---help---
	2047		Frame buffer driver for the built-in FB controller in the Samsung
	2048		SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
	2049		and the S3C64XX series such as the S3C6400 and S3C6410.
	2050
	2051		These chips all have the same basic framebuffer design with the
	2052		actual capabilities depending on the chip. For instance the S3C6400
	2053		and S3C6410 support 4 hardware windows whereas the S3C24XX series
	2054		currently only have two.
	2055
	2056		Currently the support is only for the S3C6400 and S3C6410 SoCs.
	2057
	2058		config FB_S3C_DEBUG_REGWRITE
	2059		bool "Debug register writes"
	2060		depends on FB_S3C
	2061		---help---
	2062		Show all register writes via printk(KERN_DEBUG)
	2063
	2064		config FB_S3C2410
	2065		tristate "S3C2410 LCD framebuffer support"
	2066		depends on FB && ARCH_S3C24XX
	2067		select FB_CFB_FILLRECT
	2068		select FB_CFB_COPYAREA
	2069		select FB_CFB_IMAGEBLIT
	2070		---help---
	2071		Frame buffer driver for the built-in LCD controller in the Samsung
	2072		S3C2410 processor.
	2073
	2074		This driver is also available as a module ( = code which can be
	2075		inserted and removed from the running kernel whenever you want). The
	2076		module will be called s3c2410fb. If you want to compile it as a module,
	2077		say M here and read <file:Documentation/kbuild/modules.txt>.
	2078
	2079		If unsure, say N.
	2080		config FB_S3C2410_DEBUG
	2081		bool "S3C2410 lcd debug messages"
	2082		depends on FB_S3C2410
	2083		help
	2084		Turn on debugging messages. Note that you can set/unset at run time
	2085		through sysfs
	2086
	2087		config FB_NUC900
	2088		bool "NUC900 LCD framebuffer support"
	2089		depends on FB && ARCH_W90X900
	2090		select FB_CFB_FILLRECT
	2091		select FB_CFB_COPYAREA
	2092		select FB_CFB_IMAGEBLIT
	2093		---help---
	2094		Frame buffer driver for the built-in LCD controller in the Nuvoton
	2095		NUC900 processor
	2096
	2097		config GPM1040A0_320X240
	2098		bool "Giantplus Technology GPM1040A0 320x240 Color TFT LCD"
	2099		depends on FB_NUC900
	2100
	2101		config FB_NUC900_DEBUG
	2102		bool "NUC900 lcd debug messages"
	2103		depends on FB_NUC900
	2104		help
	2105		Turn on debugging messages. Note that you can set/unset at run time
	2106		through sysfs
	2107
	2108		config FB_SM501
	2109		tristate "Silicon Motion SM501 framebuffer support"
	2110		depends on FB && MFD_SM501
	2111		select FB_CFB_FILLRECT
	2112		select FB_CFB_COPYAREA
	2113		select FB_CFB_IMAGEBLIT
	2114		---help---
	2115		Frame buffer driver for the CRT and LCD controllers in the Silicon
	2116		Motion SM501.
	2117
	2118		This driver is also available as a module ( = code which can be
	2119		inserted and removed from the running kernel whenever you want). The
	2120		module will be called sm501fb. If you want to compile it as a module,
	2121		say M here and read <file:Documentation/kbuild/modules.txt>.
	2122
	2123		If unsure, say N.
	2124
	2125		config FB_SMSCUFX
	2126		tristate "SMSC UFX6000/7000 USB Framebuffer support"
	2127		depends on FB && USB
	2128		select FB_MODE_HELPERS
	2129		select FB_SYS_FILLRECT
	2130		select FB_SYS_COPYAREA
	2131		select FB_SYS_IMAGEBLIT
	2132		select FB_SYS_FOPS
	2133		select FB_DEFERRED_IO
	2134		---help---
	2135		This is a kernel framebuffer driver for SMSC UFX USB devices.
	2136		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2137		mplayer -vo fbdev. Supports both UFX6000 (USB 2.0) and UFX7000
	2138		(USB 3.0) devices.
	2139		To compile as a module, choose M here: the module name is smscufx.
	2140
	2141		config FB_UDL
	2142		tristate "Displaylink USB Framebuffer support"
	2143		depends on FB && USB
	2144		select FB_MODE_HELPERS
	2145		select FB_SYS_FILLRECT
	2146		select FB_SYS_COPYAREA
	2147		select FB_SYS_IMAGEBLIT
	2148		select FB_SYS_FOPS
	2149		select FB_DEFERRED_IO
	2150		---help---
	2151		This is a kernel framebuffer driver for DisplayLink USB devices.
	2152		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2153		mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
	2154		To compile as a module, choose M here: the module name is udlfb.
	2155
	2156		config FB_PNX4008_DUM
	2157		tristate "Display Update Module support on Philips PNX4008 board"
	2158		depends on FB && ARCH_PNX4008
	2159		---help---
	2160		Say Y here to enable support for PNX4008 Display Update Module (DUM)
	2161
	2162		config FB_PNX4008_DUM_RGB
	2163		tristate "RGB Framebuffer support on Philips PNX4008 board"
	2164		depends on FB_PNX4008_DUM
	2165		select FB_CFB_FILLRECT
	2166		select FB_CFB_COPYAREA
	2167		select FB_CFB_IMAGEBLIT
	2168		---help---
	2169		Say Y here to enable support for PNX4008 RGB Framebuffer
	2170
	2171		config FB_IBM_GXT4500
	2172		tristate "Framebuffer support for IBM GXT4500P adaptor"
	2173		depends on FB && PPC
	2174		select FB_CFB_FILLRECT
	2175		select FB_CFB_COPYAREA
	2176		select FB_CFB_IMAGEBLIT
	2177		---help---
	2178		Say Y here to enable support for the IBM GXT4500P display
	2179		adaptor, found on some IBM System P (pSeries) machines.
	2180
	2181		config FB_PS3
	2182		tristate "PS3 GPU framebuffer driver"
	2183		depends on FB && PS3_PS3AV
	2184		select FB_SYS_FILLRECT
	2185		select FB_SYS_COPYAREA
	2186		select FB_SYS_IMAGEBLIT
	2187		select FB_SYS_FOPS
	2188		select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
	2189		---help---
	2190		Include support for the virtual frame buffer in the PS3 platform.
	2191
	2192		config FB_PS3_DEFAULT_SIZE_M
	2193		int "PS3 default frame buffer size (in MiB)"
	2194		depends on FB_PS3
	2195		default 9
	2196		---help---
	2197		This is the default size (in MiB) of the virtual frame buffer in
	2198		the PS3.
	2199		The default value can be overridden on the kernel command line
	2200		using the "ps3fb" option (e.g. "ps3fb=9M");
	2201
	2202		config FB_XILINX
	2203		tristate "Xilinx frame buffer support"
	2204		depends on FB && (XILINX_VIRTEX || MICROBLAZE)
	2205		select FB_CFB_FILLRECT
	2206		select FB_CFB_COPYAREA
	2207		select FB_CFB_IMAGEBLIT
	2208		---help---
	2209		Include support for the Xilinx ML300/ML403 reference design
	2210		framebuffer. ML300 carries a 640*480 LCD display on the board,
	2211		ML403 uses a standard DB15 VGA connector.
	2212
	2213		config FB_COBALT
	2214		tristate "Cobalt server LCD frame buffer support"
	2215		depends on FB && MIPS_COBALT
	2216
	2217		config FB_SH7760
	2218		bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
	2219		depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
	2220		|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
	2221		select FB_CFB_FILLRECT
	2222		select FB_CFB_COPYAREA
	2223		select FB_CFB_IMAGEBLIT
	2224		---help---
	2225		Support for the SH7760/SH7763/SH7720/SH7721 integrated
	2226		(D)STN/TFT LCD Controller.
	2227		Supports display resolutions up to 1024x1024 pixel, grayscale and
	2228		color operation, with depths ranging from 1 bpp to 8 bpp monochrome
	2229		and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
	2230		panels <= 320 pixel horizontal resolution.
	2231
	2232		config FB_DA8XX
	2233		tristate "DA8xx/OMAP-L1xx Framebuffer support"
	2234		depends on FB && ARCH_DAVINCI_DA8XX
	2235		select FB_CFB_FILLRECT
	2236		select FB_CFB_COPYAREA
	2237		select FB_CFB_IMAGEBLIT
	2238		select FB_CFB_REV_PIXELS_IN_BYTE
	2239		---help---
	2240		This is the frame buffer device driver for the TI LCD controller
	2241		found on DA8xx/OMAP-L1xx SoCs.
	2242		If unsure, say N.
	2243
	2244		config FB_VIRTUAL
	2245		tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
	2246		depends on FB
	2247		select FB_SYS_FILLRECT
	2248		select FB_SYS_COPYAREA
	2249		select FB_SYS_IMAGEBLIT
	2250		select FB_SYS_FOPS
	2251		---help---
	2252		This is a `virtual' frame buffer device. It operates on a chunk of
	2253		unswappable kernel memory instead of on the memory of a graphics
	2254		board. This means you cannot see any output sent to this frame
	2255		buffer device, while it does consume precious memory. The main use
	2256		of this frame buffer device is testing and debugging the frame
	2257		buffer subsystem. Do NOT enable it for normal systems! To protect
	2258		the innocent, it has to be enabled explicitly at boot time using the
	2259		kernel option `video=vfb:'.
	2260
	2261		To compile this driver as a module, choose M here: the
	2262		module will be called vfb. In order to load it, you must use
	2263		the vfb_enable=1 option.
	2264
	2265		If unsure, say N.
	2266
	2267		config XEN_FBDEV_FRONTEND
	2268		tristate "Xen virtual frame buffer support"
	2269		depends on FB && XEN
	2270		select FB_SYS_FILLRECT
	2271		select FB_SYS_COPYAREA
	2272		select FB_SYS_IMAGEBLIT
	2273		select FB_SYS_FOPS
	2274		select FB_DEFERRED_IO
	2275		select INPUT_XEN_KBDDEV_FRONTEND
	2276		select XEN_XENBUS_FRONTEND
	2277		default y
	2278		help
	2279		This driver implements the front-end of the Xen virtual
	2280		frame buffer driver. It communicates with a back-end
	2281		in another domain.
	2282
	2283		config FB_METRONOME
	2284		tristate "E-Ink Metronome/8track controller support"
	2285		depends on FB
	2286		select FB_SYS_FILLRECT
	2287		select FB_SYS_COPYAREA
	2288		select FB_SYS_IMAGEBLIT
	2289		select FB_SYS_FOPS
	2290		select FB_DEFERRED_IO
	2291		help
	2292		This driver implements support for the E-Ink Metronome
	2293		controller. The pre-release name for this device was 8track
	2294		and could also have been called by some vendors as PVI-nnnn.
	2295
	2296		config FB_MB862XX
	2297		tristate "Fujitsu MB862xx GDC support"
	2298		depends on FB
	2299		depends on PCI || (OF && PPC)
	2300		select FB_CFB_FILLRECT
	2301		select FB_CFB_COPYAREA
	2302		select FB_CFB_IMAGEBLIT
	2303		---help---
	2304		Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
	2305
	2306		choice
	2307		prompt "GDC variant"
	2308		depends on FB_MB862XX
	2309
	2310		config FB_MB862XX_PCI_GDC
	2311		bool "Carmine/Coral-P(A) GDC"
	2312		depends on PCI
	2313		---help---
	2314		This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
	2315		PCI graphics controller devices.
	2316
	2317		config FB_MB862XX_LIME
	2318		bool "Lime GDC"
	2319		depends on OF && PPC
	2320		select FB_FOREIGN_ENDIAN
	2321		select FB_LITTLE_ENDIAN
	2322		---help---
	2323		Framebuffer support for Fujitsu Lime GDC on host CPU bus.
	2324
	2325		endchoice
	2326
	2327		config FB_MB862XX_I2C
	2328		bool "Support I2C bus on MB862XX GDC"
	2329		depends on FB_MB862XX && I2C
	2330		default y
	2331		help
	2332		Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
	2333		driver to support accessing I2C devices on controller's I2C bus.
	2334		These are usually some video decoder chips.
	2335
	2336		config FB_EP93XX
	2337		tristate "EP93XX frame buffer support"
	2338		depends on FB && ARCH_EP93XX
	2339		select FB_CFB_FILLRECT
	2340		select FB_CFB_COPYAREA
	2341		select FB_CFB_IMAGEBLIT
	2342		---help---
	2343		Framebuffer driver for the Cirrus Logic EP93XX series of processors.
	2344		This driver is also available as a module. The module will be called
	2345		ep93xx-fb.
	2346
	2347		config FB_PRE_INIT_FB
	2348		bool "Don't reinitialize, use bootloader's GDC/Display configuration"
	2349		depends on FB && FB_MB862XX_LIME
	2350		---help---
	2351		Select this option if display contents should be inherited as set by
	2352		the bootloader.
	2353
	2354		config FB_MSM
	2355		tristate "MSM Framebuffer support"
	2356		depends on FB && ARCH_MSM
	2357		select FB_CFB_FILLRECT
	2358		select FB_CFB_COPYAREA
	2359		select FB_CFB_IMAGEBLIT
	2360
	2361		config FB_MX3
	2362		tristate "MX3 Framebuffer support"
	2363		depends on FB && MX3_IPU
	2364		select FB_CFB_FILLRECT
	2365		select FB_CFB_COPYAREA
	2366		select FB_CFB_IMAGEBLIT
	2367		default y
	2368		help
	2369		This is a framebuffer device for the i.MX31 LCD Controller. So
	2370		far only synchronous displays are supported. If you plan to use
	2371		an LCD display with your i.MX31 system, say Y here.
	2372
	2373		config FB_BROADSHEET
	2374		tristate "E-Ink Broadsheet/Epson S1D13521 controller support"
	2375		depends on FB
	2376		select FB_SYS_FILLRECT
	2377		select FB_SYS_COPYAREA
	2378		select FB_SYS_IMAGEBLIT
	2379		select FB_SYS_FOPS
	2380		select FB_DEFERRED_IO
	2381		help
	2382		This driver implements support for the E-Ink Broadsheet
	2383		controller. The release name for this device was Epson S1D13521
	2384		and could also have been called by other names when coupled with
	2385		a bridge adapter.
	2386
	2387		config FB_JZ4740
	2388		tristate "JZ4740 LCD framebuffer support"
	2389		depends on FB && MACH_JZ4740
	2390		select FB_SYS_FILLRECT
	2391		select FB_SYS_COPYAREA
	2392		select FB_SYS_IMAGEBLIT
	2393		help
	2394		Framebuffer support for the JZ4740 SoC.
	2395
	2396		config FB_MXS
	2397		tristate "MXS LCD framebuffer support"
	2398		depends on FB && ARCH_MXS
	2399		select FB_CFB_FILLRECT
	2400		select FB_CFB_COPYAREA
	2401		select FB_CFB_IMAGEBLIT
	2402		help
	2403		Framebuffer support for the MXS SoC.
	2404
	2405		config FB_PUV3_UNIGFX
	2406		tristate "PKUnity v3 Unigfx framebuffer support"
	2407		depends on FB && UNICORE32 && ARCH_PUV3
	2408		select FB_SYS_FILLRECT
	2409		select FB_SYS_COPYAREA
	2410		select FB_SYS_IMAGEBLIT
	2411		select FB_SYS_FOPS
	2412		help
	2413		Choose this option if you want to use the Unigfx device as a
	2414		framebuffer device. Without the support of PCI & AGP.
	2415
	2416		source "drivers/video/omap/Kconfig"
	2417		source "drivers/video/omap2/Kconfig"
	2418		source "drivers/video/exynos/Kconfig"
	2419		source "drivers/video/backlight/Kconfig"
	2420
	2421		if VT
	2422		source "drivers/video/console/Kconfig"
	2423		endif
	2424
	2425		if FB || SGI_NEWPORT_CONSOLE
	2426		source "drivers/video/logo/Kconfig"
	2427		endif
	2428
	2429		config FB_SH_MOBILE_MERAM
	2430		tristate "SuperH Mobile MERAM read ahead support"
	2431		depends on (SUPERH || ARCH_SHMOBILE)
	2432		select GENERIC_ALLOCATOR
	2433		---help---
	2434		Enable MERAM support for the SuperH controller.
	2435
	2436		This will allow for caching of the framebuffer to provide more
	2437		reliable access under heavy main memory bus traffic situations.
	2438		Up to 4 memory channels can be configured, allowing 4 RGB or
	2439		2 YCbCr framebuffers to be configured.
	2440
	2441		endmenu

File drivers/video/Kconfig-3.4.2 added (mode: 100644) (index 0000000..b0d367a)
	1		#
	2		# Video configuration
	3		#
	4
	5		menu "Graphics support"
	6		depends on HAS_IOMEM
	7
	8		config HAVE_FB_ATMEL
	9		bool
	10
	11		config SH_MIPI_DSI
	12		tristate
	13		depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	14
	15		config SH_LCD_MIPI_DSI
	16		bool
	17
	18		source "drivers/char/agp/Kconfig"
	19
	20		source "drivers/gpu/vga/Kconfig"
	21
	22		source "drivers/gpu/alga/Kconfig"
	23
	24		source "drivers/gpu/drm/Kconfig"
	25
	26		source "drivers/gpu/stub/Kconfig"
	27
	28		config VGASTATE
	29		tristate
	30		default n
	31
	32		config VIDEO_OUTPUT_CONTROL
	33		tristate "Lowlevel video output switch controls"
	34		help
	35		This framework adds support for low-level control of the video
	36		output switch.
	37
	38		menuconfig FB
	39		tristate "Support for frame buffer devices"
	40		---help---
	41		The frame buffer device provides an abstraction for the graphics
	42		hardware. It represents the frame buffer of some video hardware and
	43		allows application software to access the graphics hardware through
	44		a well-defined interface, so the software doesn't need to know
	45		anything about the low-level (hardware register) stuff.
	46
	47		Frame buffer devices work identically across the different
	48		architectures supported by Linux and make the implementation of
	49		application programs easier and more portable; at this point, an X
	50		server exists which uses the frame buffer device exclusively.
	51		On several non-X86 architectures, the frame buffer device is the
	52		only way to use the graphics hardware.
	53
	54		The device is accessed through special device nodes, usually located
	55		in the /dev directory, i.e. /dev/fb*.
	56
	57		You need an utility program called fbset to make full use of frame
	58		buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
	59		and the Framebuffer-HOWTO at
	60		<http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
	61		information.
	62
	63		Say Y here and to the driver for your graphics board below if you
	64		are compiling a kernel for a non-x86 architecture.
	65
	66		If you are compiling for the x86 architecture, you can say Y if you
	67		want to play with it, but it is not essential. Please note that
	68		running graphical applications that directly touch the hardware
	69		(e.g. an accelerated X server) and that are not frame buffer
	70		device-aware may cause unexpected results. If unsure, say N.
	71
	72		config FIRMWARE_EDID
	73		bool "Enable firmware EDID"
	74		depends on FB
	75		default n
	76		---help---
	77		This enables access to the EDID transferred from the firmware.
	78		On the i386, this is from the Video BIOS. Enable this if DDC/I2C
	79		transfers do not work for your driver and if you are using
	80		nvidiafb, i810fb or savagefb.
	81
	82		In general, choosing Y for this option is safe. If you
	83		experience extremely long delays while booting before you get
	84		something on your display, try setting this to N. Matrox cards in
	85		combination with certain motherboards and monitors are known to
	86		suffer from this problem.
	87
	88		config FB_DDC
	89		tristate
	90		depends on FB
	91		select I2C_ALGOBIT
	92		select I2C
	93		default n
	94
	95		config FB_BOOT_VESA_SUPPORT
	96		bool
	97		depends on FB
	98		default n
	99		---help---
	100		If true, at least one selected framebuffer driver can take advantage
	101		of VESA video modes set at an early boot stage via the vga= parameter.
	102
	103		config FB_CFB_FILLRECT
	104		tristate
	105		depends on FB
	106		default n
	107		---help---
	108		Include the cfb_fillrect function for generic software rectangle
	109		filling. This is used by drivers that don't provide their own
	110		(accelerated) version.
	111
	112		config FB_CFB_COPYAREA
	113		tristate
	114		depends on FB
	115		default n
	116		---help---
	117		Include the cfb_copyarea function for generic software area copying.
	118		This is used by drivers that don't provide their own (accelerated)
	119		version.
	120
	121		config FB_CFB_IMAGEBLIT
	122		tristate
	123		depends on FB
	124		default n
	125		---help---
	126		Include the cfb_imageblit function for generic software image
	127		blitting. This is used by drivers that don't provide their own
	128		(accelerated) version.
	129
	130		config FB_CFB_REV_PIXELS_IN_BYTE
	131		bool
	132		depends on FB
	133		default n
	134		---help---
	135		Allow generic frame-buffer functions to work on displays with 1, 2
	136		and 4 bits per pixel depths which has opposite order of pixels in
	137		byte order to bytes in long order.
	138
	139		config FB_SYS_FILLRECT
	140		tristate
	141		depends on FB
	142		default n
	143		---help---
	144		Include the sys_fillrect function for generic software rectangle
	145		filling. This is used by drivers that don't provide their own
	146		(accelerated) version and the framebuffer is in system RAM.
	147
	148		config FB_SYS_COPYAREA
	149		tristate
	150		depends on FB
	151		default n
	152		---help---
	153		Include the sys_copyarea function for generic software area copying.
	154		This is used by drivers that don't provide their own (accelerated)
	155		version and the framebuffer is in system RAM.
	156
	157		config FB_SYS_IMAGEBLIT
	158		tristate
	159		depends on FB
	160		default n
	161		---help---
	162		Include the sys_imageblit function for generic software image
	163		blitting. This is used by drivers that don't provide their own
	164		(accelerated) version and the framebuffer is in system RAM.
	165
	166		menuconfig FB_FOREIGN_ENDIAN
	167		bool "Framebuffer foreign endianness support"
	168		depends on FB
	169		---help---
	170		This menu will let you enable support for the framebuffers with
	171		non-native endianness (e.g. Little-Endian framebuffer on a
	172		Big-Endian machine). Most probably you don't have such hardware,
	173		so it's safe to say "n" here.
	174
	175		choice
	176		prompt "Choice endianness support"
	177		depends on FB_FOREIGN_ENDIAN
	178
	179		config FB_BOTH_ENDIAN
	180		bool "Support for Big- and Little-Endian framebuffers"
	181
	182		config FB_BIG_ENDIAN
	183		bool "Support for Big-Endian framebuffers only"
	184
	185		config FB_LITTLE_ENDIAN
	186		bool "Support for Little-Endian framebuffers only"
	187
	188		endchoice
	189
	190		config FB_SYS_FOPS
	191		tristate
	192		depends on FB
	193		default n
	194
	195		config FB_WMT_GE_ROPS
	196		tristate
	197		depends on FB
	198		default n
	199		---help---
	200		Include functions for accelerated rectangle filling and area
	201		copying using WonderMedia Graphics Engine operations.
	202
	203		config FB_DEFERRED_IO
	204		bool
	205		depends on FB
	206
	207		config FB_HECUBA
	208		tristate
	209		depends on FB
	210		depends on FB_DEFERRED_IO
	211
	212		config FB_SVGALIB
	213		tristate
	214		depends on FB
	215		default n
	216		---help---
	217		Common utility functions useful to fbdev drivers of VGA-based
	218		cards.
	219
	220		config FB_MACMODES
	221		tristate
	222		depends on FB
	223		default n
	224
	225		config FB_BACKLIGHT
	226		bool
	227		depends on FB
	228		select BACKLIGHT_LCD_SUPPORT
	229		select BACKLIGHT_CLASS_DEVICE
	230		default n
	231
	232		config FB_MODE_HELPERS
	233		bool "Enable Video Mode Handling Helpers"
	234		depends on FB
	235		default n
	236		---help---
	237		This enables functions for handling video modes using the
	238		Generalized Timing Formula and the EDID parser. A few drivers rely
	239		on this feature such as the radeonfb, rivafb, and the i810fb. If
	240		your driver does not take advantage of this feature, choosing Y will
	241		just increase the kernel size by about 5K.
	242
	243		config FB_TILEBLITTING
	244		bool "Enable Tile Blitting Support"
	245		depends on FB
	246		default n
	247		---help---
	248		This enables tile blitting. Tile blitting is a drawing technique
	249		where the screen is divided into rectangular sections (tiles), whereas
	250		the standard blitting divides the screen into pixels. Because the
	251		default drawing element is a tile, drawing functions will be passed
	252		parameters in terms of number of tiles instead of number of pixels.
	253		For example, to draw a single character, instead of using bitmaps,
	254		an index to an array of bitmaps will be used. To clear or move a
	255		rectangular section of a screen, the rectangle will be described in
	256		terms of number of tiles in the x- and y-axis.
	257
	258		This is particularly important to one driver, matroxfb. If
	259		unsure, say N.
	260
	261		comment "Frame buffer hardware drivers"
	262		depends on FB
	263
	264		config FB_GRVGA
	265		tristate "Aeroflex Gaisler framebuffer support"
	266		depends on FB && SPARC
	267		select FB_CFB_FILLRECT
	268		select FB_CFB_COPYAREA
	269		select FB_CFB_IMAGEBLIT
	270		---help---
	271		This enables support for the SVGACTRL framebuffer in the GRLIB IP library from Aeroflex Gaisler.
	272
	273		config FB_CIRRUS
	274		tristate "Cirrus Logic support"
	275		depends on FB && (ZORRO || PCI)
	276		select FB_CFB_FILLRECT
	277		select FB_CFB_COPYAREA
	278		select FB_CFB_IMAGEBLIT
	279		---help---
	280		This enables support for Cirrus Logic GD542x/543x based boards on
	281		Amiga: SD64, Piccolo, Picasso II/II+, Picasso IV, or EGS Spectrum.
	282
	283		If you have a PCI-based system, this enables support for these
	284		chips: GD-543x, GD-544x, GD-5480.
	285
	286		Please read the file <file:Documentation/fb/cirrusfb.txt>.
	287
	288		Say N unless you have such a graphics board or plan to get one
	289		before you next recompile the kernel.
	290
	291		config FB_PM2
	292		tristate "Permedia2 support"
	293		depends on FB && ((AMIGA && BROKEN) || PCI)
	294		select FB_CFB_FILLRECT
	295		select FB_CFB_COPYAREA
	296		select FB_CFB_IMAGEBLIT
	297		help
	298		This is the frame buffer device driver for cards based on
	299		the 3D Labs Permedia, Permedia 2 and Permedia 2V chips.
	300		The driver was tested on the following cards:
	301		Diamond FireGL 1000 PRO AGP
	302		ELSA Gloria Synergy PCI
	303		Appian Jeronimo PRO (both heads) PCI
	304		3DLabs Oxygen ACX aka EONtronics Picasso P2 PCI
	305		Techsource Raptor GFX-8P (aka Sun PGX-32) on SPARC
	306		ASK Graphic Blaster Exxtreme AGP
	307
	308		To compile this driver as a module, choose M here: the
	309		module will be called pm2fb.
	310
	311		config FB_PM2_FIFO_DISCONNECT
	312		bool "enable FIFO disconnect feature"
	313		depends on FB_PM2 && PCI
	314		help
	315		Support the Permedia2 FIFO disconnect feature.
	316
	317		config FB_ARMCLCD
	318		tristate "ARM PrimeCell PL110 support"
	319		depends on FB && ARM && ARM_AMBA
	320		select FB_CFB_FILLRECT
	321		select FB_CFB_COPYAREA
	322		select FB_CFB_IMAGEBLIT
	323		help
	324		This framebuffer device driver is for the ARM PrimeCell PL110
	325		Colour LCD controller. ARM PrimeCells provide the building
	326		blocks for System on a Chip devices.
	327
	328		If you want to compile this as a module (=code which can be
	329		inserted into and removed from the running kernel), say M
	330		here and read <file:Documentation/kbuild/modules.txt>. The module
	331		will be called amba-clcd.
	332
	333		config FB_ACORN
	334		bool "Acorn VIDC support"
	335		depends on (FB = y) && ARM && ARCH_ACORN
	336		select FB_CFB_FILLRECT
	337		select FB_CFB_COPYAREA
	338		select FB_CFB_IMAGEBLIT
	339		help
	340		This is the frame buffer device driver for the Acorn VIDC graphics
	341		hardware found in Acorn RISC PCs and other ARM-based machines. If
	342		unsure, say N.
	343
	344		config FB_CLPS711X
	345		bool "CLPS711X LCD support"
	346		depends on (FB = y) && ARM && ARCH_CLPS711X
	347		select FB_CFB_FILLRECT
	348		select FB_CFB_COPYAREA
	349		select FB_CFB_IMAGEBLIT
	350		help
	351		Say Y to enable the Framebuffer driver for the CLPS7111 and
	352		EP7212 processors.
	353
	354		config FB_SA1100
	355		bool "SA-1100 LCD support"
	356		depends on (FB = y) && ARM && ARCH_SA1100
	357		select FB_CFB_FILLRECT
	358		select FB_CFB_COPYAREA
	359		select FB_CFB_IMAGEBLIT
	360		help
	361		This is a framebuffer device for the SA-1100 LCD Controller.
	362		See <http://www.linux-fbdev.org/> for information on framebuffer
	363		devices.
	364
	365		If you plan to use the LCD display with your SA-1100 system, say
	366		Y here.
	367
	368		config FB_IMX
	369		tristate "Freescale i.MX LCD support"
	370		depends on FB && IMX_HAVE_PLATFORM_IMX_FB
	371		select FB_CFB_FILLRECT
	372		select FB_CFB_COPYAREA
	373		select FB_CFB_IMAGEBLIT
	374
	375		config FB_CYBER2000
	376		tristate "CyberPro 2000/2010/5000 support"
	377		depends on FB && PCI && (BROKEN || !SPARC64)
	378		select FB_CFB_FILLRECT
	379		select FB_CFB_COPYAREA
	380		select FB_CFB_IMAGEBLIT
	381		help
	382		This enables support for the Integraphics CyberPro 20x0 and 5000
	383		VGA chips used in the Rebel.com Netwinder and other machines.
	384		Say Y if you have a NetWinder or a graphics card containing this
	385		device, otherwise say N.
	386
	387		config FB_CYBER2000_DDC
	388		bool "DDC for CyberPro support"
	389		depends on FB_CYBER2000
	390		select FB_DDC
	391		default y
	392		help
	393		Say Y here if you want DDC support for your CyberPro graphics
	394		card. This is only I2C bus support, driver does not use EDID.
	395
	396		config FB_CYBER2000_I2C
	397		bool "CyberPro 2000/2010/5000 I2C support"
	398		depends on FB_CYBER2000 && I2C && ARCH_NETWINDER
	399		select I2C_ALGOBIT
	400		help
	401		Enable support for the I2C video decoder interface on the
	402		Integraphics CyberPro 20x0 and 5000 VGA chips. This is used
	403		on the Netwinder machines for the SAA7111 video capture.
	404
	405		config FB_APOLLO
	406		bool
	407		depends on (FB = y) && APOLLO
	408		default y
	409		select FB_CFB_FILLRECT
	410		select FB_CFB_IMAGEBLIT
	411
	412		config FB_Q40
	413		bool
	414		depends on (FB = y) && Q40
	415		default y
	416		select FB_CFB_FILLRECT
	417		select FB_CFB_COPYAREA
	418		select FB_CFB_IMAGEBLIT
	419
	420		config FB_AMIGA
	421		tristate "Amiga native chipset support"
	422		depends on FB && AMIGA
	423		help
	424		This is the frame buffer device driver for the builtin graphics
	425		chipset found in Amigas.
	426
	427		To compile this driver as a module, choose M here: the
	428		module will be called amifb.
	429
	430		config FB_AMIGA_OCS
	431		bool "Amiga OCS chipset support"
	432		depends on FB_AMIGA
	433		help
	434		This enables support for the original Agnus and Denise video chips,
	435		found in the Amiga 1000 and most A500's and A2000's. If you intend
	436		to run Linux on any of these systems, say Y; otherwise say N.
	437
	438		config FB_AMIGA_ECS
	439		bool "Amiga ECS chipset support"
	440		depends on FB_AMIGA
	441		help
	442		This enables support for the Enhanced Chip Set, found in later
	443		A500's, later A2000's, the A600, the A3000, the A3000T and CDTV. If
	444		you intend to run Linux on any of these systems, say Y; otherwise
	445		say N.
	446
	447		config FB_AMIGA_AGA
	448		bool "Amiga AGA chipset support"
	449		depends on FB_AMIGA
	450		help
	451		This enables support for the Advanced Graphics Architecture (also
	452		known as the AGA or AA) Chip Set, found in the A1200, A4000, A4000T
	453		and CD32. If you intend to run Linux on any of these systems, say Y;
	454		otherwise say N.
	455
	456		config FB_FM2
	457		bool "Amiga FrameMaster II/Rainbow II support"
	458		depends on (FB = y) && ZORRO
	459		select FB_CFB_FILLRECT
	460		select FB_CFB_COPYAREA
	461		select FB_CFB_IMAGEBLIT
	462		help
	463		This is the frame buffer device driver for the Amiga FrameMaster
	464		card from BSC (exhibited 1992 but not shipped as a CBM product).
	465
	466		config FB_ARC
	467		tristate "Arc Monochrome LCD board support"
	468		depends on FB && X86
	469		select FB_SYS_FILLRECT
	470		select FB_SYS_COPYAREA
	471		select FB_SYS_IMAGEBLIT
	472		select FB_SYS_FOPS
	473		help
	474		This enables support for the Arc Monochrome LCD board. The board
	475		is based on the KS-108 lcd controller and is typically a matrix
	476		of 2*n chips. This driver was tested with a 128x64 panel. This
	477		driver supports it for use with x86 SBCs through a 16 bit GPIO
	478		interface (8 bit data, 8 bit control). If you anticipate using
	479		this driver, say Y or M; otherwise say N. You must specify the
	480		GPIO IO address to be used for setting control and data.
	481
	482		config FB_ATARI
	483		bool "Atari native chipset support"
	484		depends on (FB = y) && ATARI
	485		select FB_CFB_FILLRECT
	486		select FB_CFB_COPYAREA
	487		select FB_CFB_IMAGEBLIT
	488		help
	489		This is the frame buffer device driver for the builtin graphics
	490		chipset found in Ataris.
	491
	492		config FB_OF
	493		bool "Open Firmware frame buffer device support"
	494		depends on (FB = y) && (PPC64 || PPC_OF) && (!PPC_PSERIES || PCI)
	495		select FB_CFB_FILLRECT
	496		select FB_CFB_COPYAREA
	497		select FB_CFB_IMAGEBLIT
	498		select FB_MACMODES
	499		help
	500		Say Y if you want support with Open Firmware for your graphics
	501		board.
	502
	503		config FB_CONTROL
	504		bool "Apple \"control\" display support"
	505		depends on (FB = y) && PPC_PMAC && PPC32
	506		select FB_CFB_FILLRECT
	507		select FB_CFB_COPYAREA
	508		select FB_CFB_IMAGEBLIT
	509		select FB_MACMODES
	510		help
	511		This driver supports a frame buffer for the graphics adapter in the
	512		Power Macintosh 7300 and others.
	513
	514		config FB_PLATINUM
	515		bool "Apple \"platinum\" display support"
	516		depends on (FB = y) && PPC_PMAC && PPC32
	517		select FB_CFB_FILLRECT
	518		select FB_CFB_COPYAREA
	519		select FB_CFB_IMAGEBLIT
	520		select FB_MACMODES
	521		help
	522		This driver supports a frame buffer for the "platinum" graphics
	523		adapter in some Power Macintoshes.
	524
	525		config FB_VALKYRIE
	526		bool "Apple \"valkyrie\" display support"
	527		depends on (FB = y) && (MAC || (PPC_PMAC && PPC32))
	528		select FB_CFB_FILLRECT
	529		select FB_CFB_COPYAREA
	530		select FB_CFB_IMAGEBLIT
	531		select FB_MACMODES
	532		help
	533		This driver supports a frame buffer for the "valkyrie" graphics
	534		adapter in some Power Macintoshes.
	535
	536		config FB_CT65550
	537		bool "Chips 65550 display support"
	538		depends on (FB = y) && PPC32 && PCI
	539		select FB_CFB_FILLRECT
	540		select FB_CFB_COPYAREA
	541		select FB_CFB_IMAGEBLIT
	542		help
	543		This is the frame buffer device driver for the Chips & Technologies
	544		65550 graphics chip in PowerBooks.
	545
	546		config FB_ASILIANT
	547		bool "Asiliant (Chips) 69000 display support"
	548		depends on (FB = y) && PCI
	549		select FB_CFB_FILLRECT
	550		select FB_CFB_COPYAREA
	551		select FB_CFB_IMAGEBLIT
	552		help
	553		This is the frame buffer device driver for the Asiliant 69030 chipset
	554
	555		config FB_IMSTT
	556		bool "IMS Twin Turbo display support"
	557		depends on (FB = y) && PCI
	558		select FB_CFB_IMAGEBLIT
	559		select FB_MACMODES if PPC
	560		help
	561		The IMS Twin Turbo is a PCI-based frame buffer card bundled with
	562		many Macintosh and compatible computers.
	563
	564		config FB_VGA16
	565		tristate "VGA 16-color graphics support"
	566		depends on FB && (X86 || PPC)
	567		select FB_CFB_FILLRECT
	568		select FB_CFB_COPYAREA
	569		select FB_CFB_IMAGEBLIT
	570		select VGASTATE
	571		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	572		help
	573		This is the frame buffer device driver for VGA 16 color graphic
	574		cards. Say Y if you have such a card.
	575
	576		To compile this driver as a module, choose M here: the
	577		module will be called vga16fb.
	578
	579		config FB_BF54X_LQ043
	580		tristate "SHARP LQ043 TFT LCD (BF548 EZKIT)"
	581		depends on FB && (BF54x) && !BF542
	582		select FB_CFB_FILLRECT
	583		select FB_CFB_COPYAREA
	584		select FB_CFB_IMAGEBLIT
	585		help
	586		This is the framebuffer device driver for a SHARP LQ043T1DG01 TFT LCD
	587
	588		config FB_BFIN_T350MCQB
	589		tristate "Varitronix COG-T350MCQB TFT LCD display (BF527 EZKIT)"
	590		depends on FB && BLACKFIN
	591		select BFIN_GPTIMERS
	592		select FB_CFB_FILLRECT
	593		select FB_CFB_COPYAREA
	594		select FB_CFB_IMAGEBLIT
	595		help
	596		This is the framebuffer device driver for a Varitronix VL-PS-COG-T350MCQB-01 display TFT LCD
	597		This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
	598		It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
	599
	600		config FB_BFIN_LQ035Q1
	601		tristate "SHARP LQ035Q1DH02 TFT LCD"
	602		depends on FB && BLACKFIN && SPI
	603		select FB_CFB_FILLRECT
	604		select FB_CFB_COPYAREA
	605		select FB_CFB_IMAGEBLIT
	606		select BFIN_GPTIMERS
	607		help
	608		This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
	609		the Blackfin Landscape LCD EZ-Extender Card.
	610		This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
	611		It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
	612
	613		To compile this driver as a module, choose M here: the
	614		module will be called bfin-lq035q1-fb.
	615
	616		config FB_BF537_LQ035
	617		tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
	618		depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
	619		select FB_CFB_FILLRECT
	620		select FB_CFB_COPYAREA
	621		select FB_CFB_IMAGEBLIT
	622		select BFIN_GPTIMERS
	623		help
	624		This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
	625		attached to a BF537.
	626
	627		To compile this driver as a module, choose M here: the
	628		module will be called bf537-lq035.
	629
	630		config FB_BFIN_7393
	631		tristate "Blackfin ADV7393 Video encoder"
	632		depends on FB && BLACKFIN
	633		select I2C
	634		select FB_CFB_FILLRECT
	635		select FB_CFB_COPYAREA
	636		select FB_CFB_IMAGEBLIT
	637		help
	638		This is the framebuffer device for a ADV7393 video encoder
	639		attached to a Blackfin on the PPI port.
	640		If your Blackfin board has a ADV7393 select Y.
	641
	642		To compile this driver as a module, choose M here: the
	643		module will be called bfin_adv7393fb.
	644
	645		choice
	646		prompt "Video mode support"
	647		depends on FB_BFIN_7393
	648		default NTSC
	649
	650		config NTSC
	651		bool 'NTSC 720x480'
	652
	653		config PAL
	654		bool 'PAL 720x576'
	655
	656		config NTSC_640x480
	657		bool 'NTSC 640x480 (Experimental)'
	658
	659		config PAL_640x480
	660		bool 'PAL 640x480 (Experimental)'
	661
	662		config NTSC_YCBCR
	663		bool 'NTSC 720x480 YCbCR input'
	664
	665		config PAL_YCBCR
	666		bool 'PAL 720x576 YCbCR input'
	667
	668		endchoice
	669
	670		choice
	671		prompt "Size of ADV7393 frame buffer memory Single/Double Size"
	672		depends on (FB_BFIN_7393)
	673		default ADV7393_1XMEM
	674
	675		config ADV7393_1XMEM
	676		bool 'Single'
	677
	678		config ADV7393_2XMEM
	679		bool 'Double'
	680		endchoice
	681
	682		config FB_STI
	683		tristate "HP STI frame buffer device support"
	684		depends on FB && PARISC
	685		select FB_CFB_FILLRECT
	686		select FB_CFB_COPYAREA
	687		select FB_CFB_IMAGEBLIT
	688		select STI_CONSOLE
	689		select VT
	690		default y
	691		---help---
	692		STI refers to the HP "Standard Text Interface" which is a set of
	693		BIOS routines contained in a ROM chip in HP PA-RISC based machines.
	694		Enabling this option will implement the linux framebuffer device
	695		using calls to the STI BIOS routines for initialisation.
	696
	697		If you enable this option, you will get a planar framebuffer device
	698		/dev/fb which will work on the most common HP graphic cards of the
	699		NGLE family, including the artist chips (in the 7xx and Bxxx series),
	700		HCRX, HCRX24, CRX, CRX24 and VisEG series.
	701
	702		It is safe to enable this option, so you should probably say "Y".
	703
	704		config FB_MAC
	705		bool "Generic Macintosh display support"
	706		depends on (FB = y) && MAC
	707		select FB_CFB_FILLRECT
	708		select FB_CFB_COPYAREA
	709		select FB_CFB_IMAGEBLIT
	710		select FB_MACMODES
	711
	712		config FB_HP300
	713		bool
	714		depends on (FB = y) && DIO
	715		select FB_CFB_IMAGEBLIT
	716		default y
	717
	718		config FB_TGA
	719		tristate "TGA/SFB+ framebuffer support"
	720		depends on FB && (ALPHA || TC)
	721		select FB_CFB_FILLRECT
	722		select FB_CFB_COPYAREA
	723		select FB_CFB_IMAGEBLIT
	724		select BITREVERSE
	725		---help---
	726		This is the frame buffer device driver for generic TGA and SFB+
	727		graphic cards. These include DEC ZLXp-E1, -E2 and -E3 PCI cards,
	728		also known as PBXGA-A, -B and -C, and DEC ZLX-E1, -E2 and -E3
	729		TURBOchannel cards, also known as PMAGD-A, -B and -C.
	730
	731		Due to hardware limitations ZLX-E2 and E3 cards are not supported
	732		for DECstation 5000/200 systems. Additionally due to firmware
	733		limitations these cards may cause troubles with booting DECstation
	734		5000/240 and /260 systems, but are fully supported under Linux if
	735		you manage to get it going. ;-)
	736
	737		Say Y if you have one of those.
	738
	739		config FB_UVESA
	740		tristate "Userspace VESA VGA graphics support"
	741		depends on FB && CONNECTOR
	742		select FB_CFB_FILLRECT
	743		select FB_CFB_COPYAREA
	744		select FB_CFB_IMAGEBLIT
	745		select FB_MODE_HELPERS
	746		help
	747		This is the frame buffer driver for generic VBE 2.0 compliant
	748		graphic cards. It can also take advantage of VBE 3.0 features,
	749		such as refresh rate adjustment.
	750
	751		This driver generally provides more features than vesafb but
	752		requires a userspace helper application called 'v86d'. See
	753		<file:Documentation/fb/uvesafb.txt> for more information.
	754
	755		If unsure, say N.
	756
	757		config FB_VESA
	758		bool "VESA VGA graphics support"
	759		depends on (FB = y) && X86
	760		select FB_CFB_FILLRECT
	761		select FB_CFB_COPYAREA
	762		select FB_CFB_IMAGEBLIT
	763		select FB_BOOT_VESA_SUPPORT
	764		help
	765		This is the frame buffer device driver for generic VESA 2.0
	766		compliant graphic cards. The older VESA 1.2 cards are not supported.
	767		You will get a boot time penguin logo at no additional cost. Please
	768		read <file:Documentation/fb/vesafb.txt>. If unsure, say Y.
	769
	770		config FB_EFI
	771		bool "EFI-based Framebuffer Support"
	772		depends on (FB = y) && X86 && EFI
	773		select FB_CFB_FILLRECT
	774		select FB_CFB_COPYAREA
	775		select FB_CFB_IMAGEBLIT
	776		help
	777		This is the EFI frame buffer device driver. If the firmware on
	778		your platform is EFI 1.10 or UEFI 2.0, select Y to add support for
	779		using the EFI framebuffer as your console.
	780
	781		config FB_N411
	782		tristate "N411 Apollo/Hecuba devkit support"
	783		depends on FB && X86 && MMU
	784		select FB_SYS_FILLRECT
	785		select FB_SYS_COPYAREA
	786		select FB_SYS_IMAGEBLIT
	787		select FB_SYS_FOPS
	788		select FB_DEFERRED_IO
	789		select FB_HECUBA
	790		help
	791		This enables support for the Apollo display controller in its
	792		Hecuba form using the n411 devkit.
	793
	794		config FB_HGA
	795		tristate "Hercules mono graphics support"
	796		depends on FB && X86
	797		help
	798		Say Y here if you have a Hercules mono graphics card.
	799
	800		To compile this driver as a module, choose M here: the
	801		module will be called hgafb.
	802
	803		As this card technology is at least 25 years old,
	804		most people will answer N here.
	805
	806		config FB_SGIVW
	807		tristate "SGI Visual Workstation framebuffer support"
	808		depends on FB && X86_VISWS
	809		select FB_CFB_FILLRECT
	810		select FB_CFB_COPYAREA
	811		select FB_CFB_IMAGEBLIT
	812		help
	813		SGI Visual Workstation support for framebuffer graphics.
	814
	815		config FB_GBE
	816		bool "SGI Graphics Backend frame buffer support"
	817		depends on (FB = y) && (SGI_IP32 || X86_VISWS)
	818		select FB_CFB_FILLRECT
	819		select FB_CFB_COPYAREA
	820		select FB_CFB_IMAGEBLIT
	821		help
	822		This is the frame buffer device driver for SGI Graphics Backend.
	823		This chip is used in SGI O2 and Visual Workstation 320/540.
	824
	825		config FB_GBE_MEM
	826		int "Video memory size in MB"
	827		depends on FB_GBE
	828		default 4
	829		help
	830		This is the amount of memory reserved for the framebuffer,
	831		which can be any value between 1MB and 8MB.
	832
	833		config FB_SBUS
	834		bool "SBUS and UPA framebuffers"
	835		depends on (FB = y) && SPARC
	836		help
	837		Say Y if you want support for SBUS or UPA based frame buffer device.
	838
	839		config FB_BW2
	840		bool "BWtwo support"
	841		depends on (FB = y) && (SPARC && FB_SBUS)
	842		select FB_CFB_FILLRECT
	843		select FB_CFB_COPYAREA
	844		select FB_CFB_IMAGEBLIT
	845		help
	846		This is the frame buffer device driver for the BWtwo frame buffer.
	847
	848		config FB_CG3
	849		bool "CGthree support"
	850		depends on (FB = y) && (SPARC && FB_SBUS)
	851		select FB_CFB_FILLRECT
	852		select FB_CFB_COPYAREA
	853		select FB_CFB_IMAGEBLIT
	854		help
	855		This is the frame buffer device driver for the CGthree frame buffer.
	856
	857		config FB_CG6
	858		bool "CGsix (GX,TurboGX) support"
	859		depends on (FB = y) && (SPARC && FB_SBUS)
	860		select FB_CFB_COPYAREA
	861		select FB_CFB_IMAGEBLIT
	862		help
	863		This is the frame buffer device driver for the CGsix (GX, TurboGX)
	864		frame buffer.
	865
	866		config FB_FFB
	867		bool "Creator/Creator3D/Elite3D support"
	868		depends on FB_SBUS && SPARC64
	869		select FB_CFB_COPYAREA
	870		select FB_CFB_IMAGEBLIT
	871		help
	872		This is the frame buffer device driver for the Creator, Creator3D,
	873		and Elite3D graphics boards.
	874
	875		config FB_TCX
	876		bool "TCX (SS4/SS5 only) support"
	877		depends on FB_SBUS
	878		select FB_CFB_FILLRECT
	879		select FB_CFB_COPYAREA
	880		select FB_CFB_IMAGEBLIT
	881		help
	882		This is the frame buffer device driver for the TCX 24/8bit frame
	883		buffer.
	884
	885		config FB_CG14
	886		bool "CGfourteen (SX) support"
	887		depends on FB_SBUS
	888		select FB_CFB_FILLRECT
	889		select FB_CFB_COPYAREA
	890		select FB_CFB_IMAGEBLIT
	891		help
	892		This is the frame buffer device driver for the CGfourteen frame
	893		buffer on Desktop SPARCsystems with the SX graphics option.
	894
	895		config FB_P9100
	896		bool "P9100 (Sparcbook 3 only) support"
	897		depends on FB_SBUS
	898		select FB_CFB_FILLRECT
	899		select FB_CFB_COPYAREA
	900		select FB_CFB_IMAGEBLIT
	901		help
	902		This is the frame buffer device driver for the P9100 card
	903		supported on Sparcbook 3 machines.
	904
	905		config FB_LEO
	906		bool "Leo (ZX) support"
	907		depends on FB_SBUS
	908		select FB_CFB_FILLRECT
	909		select FB_CFB_COPYAREA
	910		select FB_CFB_IMAGEBLIT
	911		help
	912		This is the frame buffer device driver for the SBUS-based Sun ZX
	913		(leo) frame buffer cards.
	914
	915		config FB_IGA
	916		bool "IGA 168x display support"
	917		depends on (FB = y) && SPARC32
	918		select FB_CFB_FILLRECT
	919		select FB_CFB_COPYAREA
	920		select FB_CFB_IMAGEBLIT
	921		help
	922		This is the framebuffer device for the INTERGRAPHICS 1680 and
	923		successor frame buffer cards.
	924
	925		config FB_XVR500
	926		bool "Sun XVR-500 3DLABS Wildcat support"
	927		depends on (FB = y) && PCI && SPARC64
	928		select FB_CFB_FILLRECT
	929		select FB_CFB_COPYAREA
	930		select FB_CFB_IMAGEBLIT
	931		help
	932		This is the framebuffer device for the Sun XVR-500 and similar
	933		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	934		only works on sparc64 systems where the system firmware has
	935		mostly initialized the card already. It is treated as a
	936		completely dumb framebuffer device.
	937
	938		config FB_XVR2500
	939		bool "Sun XVR-2500 3DLABS Wildcat support"
	940		depends on (FB = y) && PCI && SPARC64
	941		select FB_CFB_FILLRECT
	942		select FB_CFB_COPYAREA
	943		select FB_CFB_IMAGEBLIT
	944		help
	945		This is the framebuffer device for the Sun XVR-2500 and similar
	946		graphics cards based upon the 3DLABS Wildcat chipset. The driver
	947		only works on sparc64 systems where the system firmware has
	948		mostly initialized the card already. It is treated as a
	949		completely dumb framebuffer device.
	950
	951		config FB_XVR1000
	952		bool "Sun XVR-1000 support"
	953		depends on (FB = y) && SPARC64
	954		select FB_CFB_FILLRECT
	955		select FB_CFB_COPYAREA
	956		select FB_CFB_IMAGEBLIT
	957		help
	958		This is the framebuffer device for the Sun XVR-1000 and similar
	959		graphics cards. The driver only works on sparc64 systems where
	960		the system firmware has mostly initialized the card already. It
	961		is treated as a completely dumb framebuffer device.
	962
	963		config FB_PVR2
	964		tristate "NEC PowerVR 2 display support"
	965		depends on FB && SH_DREAMCAST
	966		select FB_CFB_FILLRECT
	967		select FB_CFB_COPYAREA
	968		select FB_CFB_IMAGEBLIT
	969		---help---
	970		Say Y here if you have a PowerVR 2 card in your box. If you plan to
	971		run linux on your Dreamcast, you will have to say Y here.
	972		This driver may or may not work on other PowerVR 2 cards, but is
	973		totally untested. Use at your own risk. If unsure, say N.
	974
	975		To compile this driver as a module, choose M here: the
	976		module will be called pvr2fb.
	977
	978		You can pass several parameters to the driver at boot time or at
	979		module load time. The parameters look like "video=pvr2:XXX", where
	980		the meaning of XXX can be found at the end of the main source file
	981		(<file:drivers/video/pvr2fb.c>). Please see the file
	982		<file:Documentation/fb/pvr2fb.txt>.
	983
	984		config FB_EPSON1355
	985		bool "Epson 1355 framebuffer support"
	986		depends on (FB = y) && ARCH_CEIVA
	987		select FB_CFB_FILLRECT
	988		select FB_CFB_COPYAREA
	989		select FB_CFB_IMAGEBLIT
	990		help
	991		Build in support for the SED1355 Epson Research Embedded RAMDAC
	992		LCD/CRT Controller (since redesignated as the S1D13505) as a
	993		framebuffer. Product specs at
	994		<http://vdc.epson.com/>.
	995
	996		config FB_S1D13XXX
	997		tristate "Epson S1D13XXX framebuffer support"
	998		depends on FB
	999		select FB_CFB_FILLRECT
	1000		select FB_CFB_COPYAREA
	1001		select FB_CFB_IMAGEBLIT
	1002		help
	1003		Support for S1D13XXX framebuffer device family (currently only
	1004		working with S1D13806). Product specs at
	1005		<http://vdc.epson.com/>
	1006
	1007		config FB_ATMEL
	1008		tristate "AT91/AT32 LCD Controller support"
	1009		depends on FB && HAVE_FB_ATMEL
	1010		select FB_CFB_FILLRECT
	1011		select FB_CFB_COPYAREA
	1012		select FB_CFB_IMAGEBLIT
	1013		help
	1014		This enables support for the AT91/AT32 LCD Controller.
	1015
	1016		config FB_INTSRAM
	1017		bool "Frame Buffer in internal SRAM"
	1018		depends on FB_ATMEL && ARCH_AT91SAM9261
	1019		help
	1020		Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
	1021		to let frame buffer in external SDRAM.
	1022
	1023		config FB_ATMEL_STN
	1024		bool "Use a STN display with AT91/AT32 LCD Controller"
	1025		depends on FB_ATMEL && (MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK)
	1026		default n
	1027		help
	1028		Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
	1029		Controller. Say N if you want to connect a TFT.
	1030
	1031		If unsure, say N.
	1032
	1033		config FB_NVIDIA
	1034		tristate "nVidia Framebuffer Support"
	1035		depends on FB && PCI
	1036		select FB_BACKLIGHT if FB_NVIDIA_BACKLIGHT
	1037		select FB_MODE_HELPERS
	1038		select FB_CFB_FILLRECT
	1039		select FB_CFB_COPYAREA
	1040		select FB_CFB_IMAGEBLIT
	1041		select BITREVERSE
	1042		select VGASTATE
	1043		help
	1044		This driver supports graphics boards with the nVidia chips, TNT
	1045		and newer. For very old chipsets, such as the RIVA128, then use
	1046		the rivafb.
	1047		Say Y if you have such a graphics board.
	1048
	1049		To compile this driver as a module, choose M here: the
	1050		module will be called nvidiafb.
	1051
	1052		config FB_NVIDIA_I2C
	1053		bool "Enable DDC Support"
	1054		depends on FB_NVIDIA
	1055		select FB_DDC
	1056		help
	1057		This enables I2C support for nVidia Chipsets. This is used
	1058		only for getting EDID information from the attached display
	1059		allowing for robust video mode handling and switching.
	1060
	1061		Because fbdev-2.6 requires that drivers must be able to
	1062		independently validate video mode parameters, you should say Y
	1063		here.
	1064
	1065		config FB_NVIDIA_DEBUG
	1066		bool "Lots of debug output"
	1067		depends on FB_NVIDIA
	1068		default n
	1069		help
	1070		Say Y here if you want the nVidia driver to output all sorts
	1071		of debugging information to provide to the maintainer when
	1072		something goes wrong.
	1073
	1074		config FB_NVIDIA_BACKLIGHT
	1075		bool "Support for backlight control"
	1076		depends on FB_NVIDIA
	1077		default y
	1078		help
	1079		Say Y here if you want to control the backlight of your display.
	1080
	1081		config FB_RIVA
	1082		tristate "nVidia Riva support"
	1083		depends on FB && PCI
	1084		select FB_BACKLIGHT if FB_RIVA_BACKLIGHT
	1085		select FB_MODE_HELPERS
	1086		select FB_CFB_FILLRECT
	1087		select FB_CFB_COPYAREA
	1088		select FB_CFB_IMAGEBLIT
	1089		select BITREVERSE
	1090		select VGASTATE
	1091		help
	1092		This driver supports graphics boards with the nVidia Riva/Geforce
	1093		chips.
	1094		Say Y if you have such a graphics board.
	1095
	1096		To compile this driver as a module, choose M here: the
	1097		module will be called rivafb.
	1098
	1099		config FB_RIVA_I2C
	1100		bool "Enable DDC Support"
	1101		depends on FB_RIVA
	1102		select FB_DDC
	1103		help
	1104		This enables I2C support for nVidia Chipsets. This is used
	1105		only for getting EDID information from the attached display
	1106		allowing for robust video mode handling and switching.
	1107
	1108		Because fbdev-2.6 requires that drivers must be able to
	1109		independently validate video mode parameters, you should say Y
	1110		here.
	1111
	1112		config FB_RIVA_DEBUG
	1113		bool "Lots of debug output"
	1114		depends on FB_RIVA
	1115		default n
	1116		help
	1117		Say Y here if you want the Riva driver to output all sorts
	1118		of debugging information to provide to the maintainer when
	1119		something goes wrong.
	1120
	1121		config FB_RIVA_BACKLIGHT
	1122		bool "Support for backlight control"
	1123		depends on FB_RIVA
	1124		default y
	1125		help
	1126		Say Y here if you want to control the backlight of your display.
	1127
	1128		config FB_I740
	1129		tristate "Intel740 support (EXPERIMENTAL)"
	1130		depends on EXPERIMENTAL && FB && PCI
	1131		select FB_MODE_HELPERS
	1132		select FB_CFB_FILLRECT
	1133		select FB_CFB_COPYAREA
	1134		select FB_CFB_IMAGEBLIT
	1135		select VGASTATE
	1136		select FB_DDC
	1137		help
	1138		This driver supports graphics cards based on Intel740 chip.
	1139
	1140		config FB_I810
	1141		tristate "Intel 810/815 support (EXPERIMENTAL)"
	1142		depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
	1143		select FB_MODE_HELPERS
	1144		select FB_CFB_FILLRECT
	1145		select FB_CFB_COPYAREA
	1146		select FB_CFB_IMAGEBLIT
	1147		select VGASTATE
	1148		help
	1149		This driver supports the on-board graphics built in to the Intel 810
	1150		and 815 chipsets. Say Y if you have and plan to use such a board.
	1151
	1152		To compile this driver as a module, choose M here: the
	1153		module will be called i810fb.
	1154
	1155		For more information, please read
	1156		<file:Documentation/fb/intel810.txt>
	1157
	1158		config FB_I810_GTF
	1159		bool "use VESA Generalized Timing Formula"
	1160		depends on FB_I810
	1161		help
	1162		If you say Y, then the VESA standard, Generalized Timing Formula
	1163		or GTF, will be used to calculate the required video timing values
	1164		per video mode. Since the GTF allows nondiscrete timings
	1165		(nondiscrete being a range of values as opposed to discrete being a
	1166		set of values), you'll be able to use any combination of horizontal
	1167		and vertical resolutions, and vertical refresh rates without having
	1168		to specify your own timing parameters. This is especially useful
	1169		to maximize the performance of an aging display, or if you just
	1170		have a display with nonstandard dimensions. A VESA compliant
	1171		monitor is recommended, but can still work with non-compliant ones.
	1172		If you need or want this, then select this option. The timings may
	1173		not be compliant with Intel's recommended values. Use at your own
	1174		risk.
	1175
	1176		If you say N, the driver will revert to discrete video timings
	1177		using a set recommended by Intel in their documentation.
	1178
	1179		If unsure, say N.
	1180
	1181		config FB_I810_I2C
	1182		bool "Enable DDC Support"
	1183		depends on FB_I810 && FB_I810_GTF
	1184		select FB_DDC
	1185		help
	1186
	1187		config FB_LE80578
	1188		tristate "Intel LE80578 (Vermilion) support"
	1189		depends on FB && PCI && X86
	1190		select FB_MODE_HELPERS
	1191		select FB_CFB_FILLRECT
	1192		select FB_CFB_COPYAREA
	1193		select FB_CFB_IMAGEBLIT
	1194		help
	1195		This driver supports the LE80578 (Vermilion Range) chipset
	1196
	1197		config FB_CARILLO_RANCH
	1198		tristate "Intel Carillo Ranch support"
	1199		depends on FB_LE80578 && FB && PCI && X86
	1200		help
	1201		This driver supports the LE80578 (Carillo Ranch) board
	1202
	1203		config FB_INTEL
	1204		tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G/945GM/965G/965GM support (EXPERIMENTAL)"
	1205		depends on EXPERIMENTAL && FB && PCI && X86 && AGP_INTEL && EXPERT
	1206		select FB_MODE_HELPERS
	1207		select FB_CFB_FILLRECT
	1208		select FB_CFB_COPYAREA
	1209		select FB_CFB_IMAGEBLIT
	1210		select FB_BOOT_VESA_SUPPORT if FB_INTEL = y
	1211		depends on !DRM_I915
	1212		help
	1213		This driver supports the on-board graphics built in to the Intel
	1214		830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/965G/965GM chipsets.
	1215		Say Y if you have and plan to use such a board.
	1216
	1217		To make FB_INTELFB=Y work you need to say AGP_INTEL=y too.
	1218
	1219		To compile this driver as a module, choose M here: the
	1220		module will be called intelfb.
	1221
	1222		For more information, please read <file:Documentation/fb/intelfb.txt>
	1223
	1224		config FB_INTEL_DEBUG
	1225		bool "Intel driver Debug Messages"
	1226		depends on FB_INTEL
	1227		---help---
	1228		Say Y here if you want the Intel driver to output all sorts
	1229		of debugging information to provide to the maintainer when
	1230		something goes wrong.
	1231
	1232		config FB_INTEL_I2C
	1233		bool "DDC/I2C for Intel framebuffer support"
	1234		depends on FB_INTEL
	1235		select FB_DDC
	1236		default y
	1237		help
	1238		Say Y here if you want DDC/I2C support for your on-board Intel graphics.
	1239
	1240		config FB_MATROX
	1241		tristate "Matrox acceleration"
	1242		depends on FB && PCI
	1243		select FB_CFB_FILLRECT
	1244		select FB_CFB_COPYAREA
	1245		select FB_CFB_IMAGEBLIT
	1246		select FB_TILEBLITTING
	1247		select FB_MACMODES if PPC_PMAC
	1248		---help---
	1249		Say Y here if you have a Matrox Millennium, Matrox Millennium II,
	1250		Matrox Mystique, Matrox Mystique 220, Matrox Productiva G100, Matrox
	1251		Mystique G200, Matrox Millennium G200, Matrox Marvel G200 video,
	1252		Matrox G400, G450 or G550 card in your box.
	1253
	1254		To compile this driver as a module, choose M here: the
	1255		module will be called matroxfb.
	1256
	1257		You can pass several parameters to the driver at boot time or at
	1258		module load time. The parameters look like "video=matroxfb:XXX", and
	1259		are described in <file:Documentation/fb/matroxfb.txt>.
	1260
	1261		config FB_MATROX_MILLENIUM
	1262		bool "Millennium I/II support"
	1263		depends on FB_MATROX
	1264		help
	1265		Say Y here if you have a Matrox Millennium or Matrox Millennium II
	1266		video card. If you select "Advanced lowlevel driver options" below,
	1267		you should check 4 bpp packed pixel, 8 bpp packed pixel, 16 bpp
	1268		packed pixel, 24 bpp packed pixel and 32 bpp packed pixel. You can
	1269		also use font widths different from 8.
	1270
	1271		config FB_MATROX_MYSTIQUE
	1272		bool "Mystique support"
	1273		depends on FB_MATROX
	1274		help
	1275		Say Y here if you have a Matrox Mystique or Matrox Mystique 220
	1276		video card. If you select "Advanced lowlevel driver options" below,
	1277		you should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp
	1278		packed pixel and 32 bpp packed pixel. You can also use font widths
	1279		different from 8.
	1280
	1281		config FB_MATROX_G
	1282		bool "G100/G200/G400/G450/G550 support"
	1283		depends on FB_MATROX
	1284		---help---
	1285		Say Y here if you have a Matrox G100, G200, G400, G450 or G550 based
	1286		video card. If you select "Advanced lowlevel driver options", you
	1287		should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp packed
	1288		pixel and 32 bpp packed pixel. You can also use font widths
	1289		different from 8.
	1290
	1291		If you need support for G400 secondary head, you must say Y to
	1292		"Matrox I2C support" and "G400 second head support" right below.
	1293		G450/G550 secondary head and digital output are supported without
	1294		additional modules.
	1295
	1296		The driver starts in monitor mode. You must use the matroxset tool
	1297		(available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
	1298		swap primary and secondary head outputs, or to change output mode.
	1299		Secondary head driver always start in 640x480 resolution and you
	1300		must use fbset to change it.
	1301
	1302		Do not forget that second head supports only 16 and 32 bpp
	1303		packed pixels, so it is a good idea to compile them into the kernel
	1304		too. You can use only some font widths, as the driver uses generic
	1305		painting procedures (the secondary head does not use acceleration
	1306		engine).
	1307
	1308		G450/G550 hardware can display TV picture only from secondary CRTC,
	1309		and it performs no scaling, so picture must have 525 or 625 lines.
	1310
	1311		config FB_MATROX_I2C
	1312		tristate "Matrox I2C support"
	1313		depends on FB_MATROX
	1314		select FB_DDC
	1315		---help---
	1316		This drivers creates I2C buses which are needed for accessing the
	1317		DDC (I2C) bus present on all Matroxes, an I2C bus which
	1318		interconnects Matrox optional devices, like MGA-TVO on G200 and
	1319		G400, and the secondary head DDC bus, present on G400 only.
	1320
	1321		You can say Y or M here if you want to experiment with monitor
	1322		detection code. You must say Y or M here if you want to use either
	1323		second head of G400 or MGA-TVO on G200 or G400.
	1324
	1325		If you compile it as module, it will create a module named
	1326		i2c-matroxfb.
	1327
	1328		config FB_MATROX_MAVEN
	1329		tristate "G400 second head support"
	1330		depends on FB_MATROX_G && FB_MATROX_I2C
	1331		---help---
	1332		WARNING !!! This support does not work with G450 !!!
	1333
	1334		Say Y or M here if you want to use a secondary head (meaning two
	1335		monitors in parallel) on G400 or MGA-TVO add-on on G200. Secondary
	1336		head is not compatible with accelerated XFree 3.3.x SVGA servers -
	1337		secondary head output is blanked while you are in X. With XFree
	1338		3.9.17 preview you can use both heads if you use SVGA over fbdev or
	1339		the fbdev driver on first head and the fbdev driver on second head.
	1340
	1341		If you compile it as module, two modules are created,
	1342		matroxfb_crtc2 and matroxfb_maven. Matroxfb_maven is needed for
	1343		both G200 and G400, matroxfb_crtc2 is needed only by G400. You must
	1344		also load i2c-matroxfb to get it to run.
	1345
	1346		The driver starts in monitor mode and you must use the matroxset
	1347		tool (available at
	1348		<ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to switch it to
	1349		PAL or NTSC or to swap primary and secondary head outputs.
	1350		Secondary head driver also always start in 640x480 resolution, you
	1351		must use fbset to change it.
	1352
	1353		Also do not forget that second head supports only 16 and 32 bpp
	1354		packed pixels, so it is a good idea to compile them into the kernel
	1355		too. You can use only some font widths, as the driver uses generic
	1356		painting procedures (the secondary head does not use acceleration
	1357		engine).
	1358
	1359		config FB_RADEON
	1360		tristate "ATI Radeon display support"
	1361		depends on FB && PCI
	1362		select FB_BACKLIGHT if FB_RADEON_BACKLIGHT
	1363		select FB_MODE_HELPERS
	1364		select FB_CFB_FILLRECT
	1365		select FB_CFB_COPYAREA
	1366		select FB_CFB_IMAGEBLIT
	1367		select FB_MACMODES if PPC_OF
	1368		help
	1369		Choose this option if you want to use an ATI Radeon graphics card as
	1370		a framebuffer device. There are both PCI and AGP versions. You
	1371		don't need to choose this to run the Radeon in plain VGA mode.
	1372
	1373		There is a product page at
	1374		http://products.amd.com/en-us/GraphicCardResult.aspx
	1375
	1376		config FB_RADEON_I2C
	1377		bool "DDC/I2C for ATI Radeon support"
	1378		depends on FB_RADEON
	1379		select FB_DDC
	1380		default y
	1381		help
	1382		Say Y here if you want DDC/I2C support for your Radeon board.
	1383
	1384		config FB_RADEON_BACKLIGHT
	1385		bool "Support for backlight control"
	1386		depends on FB_RADEON
	1387		default y
	1388		help
	1389		Say Y here if you want to control the backlight of your display.
	1390
	1391		config FB_RADEON_DEBUG
	1392		bool "Lots of debug output from Radeon driver"
	1393		depends on FB_RADEON
	1394		default n
	1395		help
	1396		Say Y here if you want the Radeon driver to output all sorts
	1397		of debugging information to provide to the maintainer when
	1398		something goes wrong.
	1399
	1400		config FB_ATY128
	1401		tristate "ATI Rage128 display support"
	1402		depends on FB && PCI
	1403		select FB_CFB_FILLRECT
	1404		select FB_CFB_COPYAREA
	1405		select FB_CFB_IMAGEBLIT
	1406		select FB_BACKLIGHT if FB_ATY128_BACKLIGHT
	1407		select FB_MACMODES if PPC_PMAC
	1408		help
	1409		This driver supports graphics boards with the ATI Rage128 chips.
	1410		Say Y if you have such a graphics board and read
	1411		<file:Documentation/fb/aty128fb.txt>.
	1412
	1413		To compile this driver as a module, choose M here: the
	1414		module will be called aty128fb.
	1415
	1416		config FB_ATY128_BACKLIGHT
	1417		bool "Support for backlight control"
	1418		depends on FB_ATY128
	1419		default y
	1420		help
	1421		Say Y here if you want to control the backlight of your display.
	1422
	1423		config FB_ATY
	1424		tristate "ATI Mach64 display support" if PCI || ATARI
	1425		depends on FB && !SPARC32
	1426		select FB_CFB_FILLRECT
	1427		select FB_CFB_COPYAREA
	1428		select FB_CFB_IMAGEBLIT
	1429		select FB_BACKLIGHT if FB_ATY_BACKLIGHT
	1430		select FB_MACMODES if PPC
	1431		help
	1432		This driver supports graphics boards with the ATI Mach64 chips.
	1433		Say Y if you have such a graphics board.
	1434
	1435		To compile this driver as a module, choose M here: the
	1436		module will be called atyfb.
	1437
	1438		config FB_ATY_CT
	1439		bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support"
	1440		depends on PCI && FB_ATY
	1441		default y if SPARC64 && PCI
	1442		help
	1443		Say Y here to support use of ATI's 64-bit Rage boards (or other
	1444		boards based on the Mach64 CT, VT, GT, and LT chipsets) as a
	1445		framebuffer device. The ATI product support page for these boards
	1446		is at <http://support.ati.com/products/pc/mach64/mach64.html>.
	1447
	1448		config FB_ATY_GENERIC_LCD
	1449		bool "Mach64 generic LCD support (EXPERIMENTAL)"
	1450		depends on FB_ATY_CT
	1451		help
	1452		Say Y if you have a laptop with an ATI Rage LT PRO, Rage Mobility,
	1453		Rage XC, or Rage XL chipset.
	1454
	1455		config FB_ATY_GX
	1456		bool "Mach64 GX support" if PCI
	1457		depends on FB_ATY
	1458		default y if ATARI
	1459		help
	1460		Say Y here to support use of the ATI Mach64 Graphics Expression
	1461		board (or other boards based on the Mach64 GX chipset) as a
	1462		framebuffer device. The ATI product support page for these boards
	1463		is at
	1464		<http://support.ati.com/products/pc/mach64/graphics_xpression.html>.
	1465
	1466		config FB_ATY_BACKLIGHT
	1467		bool "Support for backlight control"
	1468		depends on FB_ATY
	1469		default y
	1470		help
	1471		Say Y here if you want to control the backlight of your display.
	1472
	1473		config FB_S3
	1474		tristate "S3 Trio/Virge support"
	1475		depends on FB && PCI
	1476		select FB_CFB_FILLRECT
	1477		select FB_CFB_COPYAREA
	1478		select FB_CFB_IMAGEBLIT
	1479		select FB_TILEBLITTING
	1480		select FB_SVGALIB
	1481		select VGASTATE
	1482		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1483		---help---
	1484		Driver for graphics boards with S3 Trio / S3 Virge chip.
	1485
	1486		config FB_S3_DDC
	1487		bool "DDC for S3 support"
	1488		depends on FB_S3
	1489		select FB_DDC
	1490		default y
	1491		help
	1492		Say Y here if you want DDC support for your S3 graphics card.
	1493
	1494		config FB_SAVAGE
	1495		tristate "S3 Savage support"
	1496		depends on FB && PCI && EXPERIMENTAL
	1497		select FB_MODE_HELPERS
	1498		select FB_CFB_FILLRECT
	1499		select FB_CFB_COPYAREA
	1500		select FB_CFB_IMAGEBLIT
	1501		select VGASTATE
	1502		help
	1503		This driver supports notebooks and computers with S3 Savage PCI/AGP
	1504		chips.
	1505
	1506		Say Y if you have such a graphics card.
	1507
	1508		To compile this driver as a module, choose M here; the module
	1509		will be called savagefb.
	1510
	1511		config FB_SAVAGE_I2C
	1512		bool "Enable DDC2 Support"
	1513		depends on FB_SAVAGE
	1514		select FB_DDC
	1515		help
	1516		This enables I2C support for S3 Savage Chipsets. This is used
	1517		only for getting EDID information from the attached display
	1518		allowing for robust video mode handling and switching.
	1519
	1520		Because fbdev-2.6 requires that drivers must be able to
	1521		independently validate video mode parameters, you should say Y
	1522		here.
	1523
	1524		config FB_SAVAGE_ACCEL
	1525		bool "Enable Console Acceleration"
	1526		depends on FB_SAVAGE
	1527		default n
	1528		help
	1529		This option will compile in console acceleration support. If
	1530		the resulting framebuffer console has bothersome glitches, then
	1531		choose N here.
	1532
	1533		config FB_SIS
	1534		tristate "SiS/XGI display support"
	1535		depends on FB && PCI
	1536		select FB_CFB_FILLRECT
	1537		select FB_CFB_COPYAREA
	1538		select FB_CFB_IMAGEBLIT
	1539		select FB_BOOT_VESA_SUPPORT if FB_SIS = y
	1540		help
	1541		This is the frame buffer device driver for the SiS 300, 315, 330
	1542		and 340 series as well as XGI V3XT, V5, V8, Z7 graphics chipsets.
	1543		Specs available at <http://www.sis.com> and <http://www.xgitech.com>.
	1544
	1545		To compile this driver as a module, choose M here; the module
	1546		will be called sisfb.
	1547
	1548		config FB_SIS_300
	1549		bool "SiS 300 series support"
	1550		depends on FB_SIS
	1551		help
	1552		Say Y here to support use of the SiS 300/305, 540, 630 and 730.
	1553
	1554		config FB_SIS_315
	1555		bool "SiS 315/330/340 series and XGI support"
	1556		depends on FB_SIS
	1557		help
	1558		Say Y here to support use of the SiS 315, 330 and 340 series
	1559		(315/H/PRO, 55x, 650, 651, 740, 330, 661, 741, 760, 761) as well
	1560		as XGI V3XT, V5, V8 and Z7.
	1561
	1562		config FB_VIA
	1563		tristate "VIA UniChrome (Pro) and Chrome9 display support"
	1564		depends on FB && PCI && X86
	1565		select FB_CFB_FILLRECT
	1566		select FB_CFB_COPYAREA
	1567		select FB_CFB_IMAGEBLIT
	1568		select I2C_ALGOBIT
	1569		select I2C
	1570		select GPIOLIB
	1571		help
	1572		This is the frame buffer device driver for Graphics chips of VIA
	1573		UniChrome (Pro) Family (CLE266,PM800/CN400,P4M800CE/P4M800Pro/
	1574		CN700/VN800,CX700/VX700,P4M890) and Chrome9 Family (K8M890,CN896
	1575		/P4M900,VX800)
	1576		Say Y if you have a VIA UniChrome graphics board.
	1577
	1578		To compile this driver as a module, choose M here: the
	1579		module will be called viafb.
	1580
	1581		if FB_VIA
	1582
	1583		config FB_VIA_DIRECT_PROCFS
	1584		bool "direct hardware access via procfs (DEPRECATED)(DANGEROUS)"
	1585		depends on FB_VIA
	1586		default n
	1587		help
	1588		Allow direct hardware access to some output registers via procfs.
	1589		This is dangerous but may provide the only chance to get the
	1590		correct output device configuration.
	1591		Its use is strongly discouraged.
	1592
	1593		config FB_VIA_X_COMPATIBILITY
	1594		bool "X server compatibility"
	1595		depends on FB_VIA
	1596		default n
	1597		help
	1598		This option reduces the functionality (power saving, ...) of the
	1599		framebuffer to avoid negative impact on the OpenChrome X server.
	1600		If you use any X server other than fbdev you should enable this
	1601		otherwise it should be safe to disable it and allow using all
	1602		features.
	1603
	1604		endif
	1605
	1606		config FB_NEOMAGIC
	1607		tristate "NeoMagic display support"
	1608		depends on FB && PCI
	1609		select FB_MODE_HELPERS
	1610		select FB_CFB_FILLRECT
	1611		select FB_CFB_COPYAREA
	1612		select FB_CFB_IMAGEBLIT
	1613		select VGASTATE
	1614		help
	1615		This driver supports notebooks with NeoMagic PCI chips.
	1616		Say Y if you have such a graphics card.
	1617
	1618		To compile this driver as a module, choose M here: the
	1619		module will be called neofb.
	1620
	1621		config FB_KYRO
	1622		tristate "IMG Kyro support"
	1623		depends on FB && PCI
	1624		select FB_CFB_FILLRECT
	1625		select FB_CFB_COPYAREA
	1626		select FB_CFB_IMAGEBLIT
	1627		help
	1628		Say Y here if you have a STG4000 / Kyro / PowerVR 3 based
	1629		graphics board.
	1630
	1631		To compile this driver as a module, choose M here: the
	1632		module will be called kyrofb.
	1633
	1634		config FB_3DFX
	1635		tristate "3Dfx Banshee/Voodoo3/Voodoo5 display support"
	1636		depends on FB && PCI
	1637		select FB_CFB_IMAGEBLIT
	1638		select FB_CFB_FILLRECT
	1639		select FB_CFB_COPYAREA
	1640		select FB_MODE_HELPERS
	1641		help
	1642		This driver supports graphics boards with the 3Dfx Banshee,
	1643		Voodoo3 or VSA-100 (aka Voodoo4/5) chips. Say Y if you have
	1644		such a graphics board.
	1645
	1646		To compile this driver as a module, choose M here: the
	1647		module will be called tdfxfb.
	1648
	1649		config FB_3DFX_ACCEL
	1650		bool "3Dfx Acceleration functions (EXPERIMENTAL)"
	1651		depends on FB_3DFX && EXPERIMENTAL
	1652		---help---
	1653		This will compile the 3Dfx Banshee/Voodoo3/VSA-100 frame buffer
	1654		device driver with acceleration functions.
	1655
	1656		config FB_3DFX_I2C
	1657		bool "Enable DDC/I2C support"
	1658		depends on FB_3DFX && EXPERIMENTAL
	1659		select FB_DDC
	1660		default y
	1661		help
	1662		Say Y here if you want DDC/I2C support for your 3dfx Voodoo3.
	1663
	1664		config FB_VOODOO1
	1665		tristate "3Dfx Voodoo Graphics (sst1) support"
	1666		depends on FB && PCI
	1667		select FB_CFB_FILLRECT
	1668		select FB_CFB_COPYAREA
	1669		select FB_CFB_IMAGEBLIT
	1670		---help---
	1671		Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
	1672		Voodoo2 (cvg) based graphics card.
	1673
	1674		To compile this driver as a module, choose M here: the
	1675		module will be called sstfb.
	1676
	1677		WARNING: Do not use any application that uses the 3D engine
	1678		(namely glide) while using this driver.
	1679		Please read the <file:Documentation/fb/sstfb.txt> for supported
	1680		options and other important info support.
	1681
	1682		config FB_VT8623
	1683		tristate "VIA VT8623 support"
	1684		depends on FB && PCI
	1685		select FB_CFB_FILLRECT
	1686		select FB_CFB_COPYAREA
	1687		select FB_CFB_IMAGEBLIT
	1688		select FB_TILEBLITTING
	1689		select FB_SVGALIB
	1690		select VGASTATE
	1691		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1692		---help---
	1693		Driver for CastleRock integrated graphics core in the
	1694		VIA VT8623 [Apollo CLE266] chipset.
	1695
	1696		config FB_TRIDENT
	1697		tristate "Trident/CyberXXX/CyberBlade support"
	1698		depends on FB && PCI
	1699		select FB_CFB_FILLRECT
	1700		select FB_CFB_COPYAREA
	1701		select FB_CFB_IMAGEBLIT
	1702		---help---
	1703		This is the frame buffer device driver for Trident PCI/AGP chipsets.
	1704		Supported chipset families are TGUI 9440/96XX, 3DImage, Blade3D
	1705		and Blade XP.
	1706		There are also integrated versions of these chips called CyberXXXX,
	1707		CyberImage or CyberBlade. These chips are mostly found in laptops
	1708		but also on some motherboards including early VIA EPIA motherboards.
	1709		For more information, read <file:Documentation/fb/tridentfb.txt>
	1710
	1711		Say Y if you have such a graphics board.
	1712
	1713		To compile this driver as a module, choose M here: the
	1714		module will be called tridentfb.
	1715
	1716		config FB_ARK
	1717		tristate "ARK 2000PV support"
	1718		depends on FB && PCI
	1719		select FB_CFB_FILLRECT
	1720		select FB_CFB_COPYAREA
	1721		select FB_CFB_IMAGEBLIT
	1722		select FB_TILEBLITTING
	1723		select FB_SVGALIB
	1724		select VGASTATE
	1725		select FONT_8x16 if FRAMEBUFFER_CONSOLE
	1726		---help---
	1727		Driver for PCI graphics boards with ARK 2000PV chip
	1728		and ICS 5342 RAMDAC.
	1729
	1730		config FB_PM3
	1731		tristate "Permedia3 support (EXPERIMENTAL)"
	1732		depends on FB && PCI && EXPERIMENTAL
	1733		select FB_CFB_FILLRECT
	1734		select FB_CFB_COPYAREA
	1735		select FB_CFB_IMAGEBLIT
	1736		help
	1737		This is the frame buffer device driver for the 3DLabs Permedia3
	1738		chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 &
	1739		similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000
	1740		and maybe other boards.
	1741
	1742		config FB_CARMINE
	1743		tristate "Fujitsu carmine frame buffer support"
	1744		depends on FB && PCI
	1745		select FB_CFB_FILLRECT
	1746		select FB_CFB_COPYAREA
	1747		select FB_CFB_IMAGEBLIT
	1748		help
	1749		This is the frame buffer device driver for the Fujitsu Carmine chip.
	1750		The driver provides two independent frame buffer devices.
	1751
	1752		choice
	1753		depends on FB_CARMINE
	1754		prompt "DRAM timing"
	1755		default FB_CARMINE_DRAM_EVAL
	1756
	1757		config FB_CARMINE_DRAM_EVAL
	1758		bool "Eval board timings"
	1759		help
	1760		Use timings which work on the eval card.
	1761
	1762		config CARMINE_DRAM_CUSTOM
	1763		bool "Custom board timings"
	1764		help
	1765		Use custom board timings.
	1766		endchoice
	1767
	1768		config FB_AU1100
	1769		bool "Au1100 LCD Driver"
	1770		depends on (FB = y) && MIPS_ALCHEMY
	1771		select FB_CFB_FILLRECT
	1772		select FB_CFB_COPYAREA
	1773		select FB_CFB_IMAGEBLIT
	1774		help
	1775		This is the framebuffer driver for the AMD Au1100 SOC. It can drive
	1776		various panels and CRTs by passing in kernel cmd line option
	1777		au1100fb:panel=<name>.
	1778
	1779		config FB_AU1200
	1780		bool "Au1200/Au1300 LCD Driver"
	1781		depends on (FB = y) && MIPS_ALCHEMY
	1782		select FB_SYS_FILLRECT
	1783		select FB_SYS_COPYAREA
	1784		select FB_SYS_IMAGEBLIT
	1785		select FB_SYS_FOPS
	1786		help
	1787		This is the framebuffer driver for the Au1200/Au1300 SOCs.
	1788		It can drive various panels and CRTs by passing in kernel cmd line
	1789		option au1200fb:panel=<name>.
	1790
	1791		config FB_VT8500
	1792		bool "VT8500 LCD Driver"
	1793		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
	1794		select FB_WMT_GE_ROPS
	1795		select FB_SYS_IMAGEBLIT
	1796		help
	1797		This is the framebuffer driver for VIA VT8500 integrated LCD
	1798		controller.
	1799
	1800		config FB_WM8505
	1801		bool "WM8505 frame buffer support"
	1802		depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
	1803		select FB_WMT_GE_ROPS
	1804		select FB_SYS_IMAGEBLIT
	1805		help
	1806		This is the framebuffer driver for WonderMedia WM8505
	1807		integrated LCD controller.
	1808
	1809		source "drivers/video/geode/Kconfig"
	1810
	1811		config FB_HIT
	1812		tristate "HD64461 Frame Buffer support"
	1813		depends on FB && HD64461
	1814		select FB_CFB_FILLRECT
	1815		select FB_CFB_COPYAREA
	1816		select FB_CFB_IMAGEBLIT
	1817		help
	1818		This is the frame buffer device driver for the Hitachi HD64461 LCD
	1819		frame buffer card.
	1820
	1821		config FB_PMAG_AA
	1822		bool "PMAG-AA TURBOchannel framebuffer support"
	1823		depends on (FB = y) && TC
	1824		select FB_CFB_FILLRECT
	1825		select FB_CFB_COPYAREA
	1826		select FB_CFB_IMAGEBLIT
	1827		help
	1828		Support for the PMAG-AA TURBOchannel framebuffer card (1280x1024x1)
	1829		used mainly in the MIPS-based DECstation series.
	1830
	1831		config FB_PMAG_BA
	1832		tristate "PMAG-BA TURBOchannel framebuffer support"
	1833		depends on FB && TC
	1834		select FB_CFB_FILLRECT
	1835		select FB_CFB_COPYAREA
	1836		select FB_CFB_IMAGEBLIT
	1837		help
	1838		Support for the PMAG-BA TURBOchannel framebuffer card (1024x864x8)
	1839		used mainly in the MIPS-based DECstation series.
	1840
	1841		config FB_PMAGB_B
	1842		tristate "PMAGB-B TURBOchannel framebuffer support"
	1843		depends on FB && TC
	1844		select FB_CFB_FILLRECT
	1845		select FB_CFB_COPYAREA
	1846		select FB_CFB_IMAGEBLIT
	1847		help
	1848		Support for the PMAGB-B TURBOchannel framebuffer card used mainly
	1849		in the MIPS-based DECstation series. The card is currently only
	1850		supported in 1280x1024x8 mode.
	1851
	1852		config FB_MAXINE
	1853		bool "Maxine (Personal DECstation) onboard framebuffer support"
	1854		depends on (FB = y) && MACH_DECSTATION
	1855		select FB_CFB_FILLRECT
	1856		select FB_CFB_COPYAREA
	1857		select FB_CFB_IMAGEBLIT
	1858		help
	1859		Support for the onboard framebuffer (1024x768x8) in the Personal
	1860		DECstation series (Personal DECstation 5000/20, /25, /33, /50,
	1861		Codename "Maxine").
	1862
	1863		config FB_G364
	1864		bool "G364 frame buffer support"
	1865		depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700)
	1866		select FB_CFB_FILLRECT
	1867		select FB_CFB_COPYAREA
	1868		select FB_CFB_IMAGEBLIT
	1869		help
	1870		The G364 driver is the framebuffer used in MIPS Magnum 4000 and
	1871		Olivetti M700-10 systems.
	1872
	1873		config FB_68328
	1874		bool "Motorola 68328 native frame buffer support"
	1875		depends on (FB = y) && (M68328 || M68EZ328 || M68VZ328)
	1876		select FB_CFB_FILLRECT
	1877		select FB_CFB_COPYAREA
	1878		select FB_CFB_IMAGEBLIT
	1879		help
	1880		Say Y here if you want to support the built-in frame buffer of
	1881		the Motorola 68328 CPU family.
	1882
	1883		config FB_PXA168
	1884		tristate "PXA168/910 LCD framebuffer support"
	1885		depends on FB && (CPU_PXA168 || CPU_PXA910)
	1886		select FB_CFB_FILLRECT
	1887		select FB_CFB_COPYAREA
	1888		select FB_CFB_IMAGEBLIT
	1889		---help---
	1890		Frame buffer driver for the built-in LCD controller in the Marvell
	1891		MMP processor.
	1892
	1893		config FB_PXA
	1894		tristate "PXA LCD framebuffer support"
	1895		depends on FB && ARCH_PXA
	1896		select FB_CFB_FILLRECT
	1897		select FB_CFB_COPYAREA
	1898		select FB_CFB_IMAGEBLIT
	1899		---help---
	1900		Frame buffer driver for the built-in LCD controller in the Intel
	1901		PXA2x0 processor.
	1902
	1903		This driver is also available as a module ( = code which can be
	1904		inserted and removed from the running kernel whenever you want). The
	1905		module will be called pxafb. If you want to compile it as a module,
	1906		say M here and read <file:Documentation/kbuild/modules.txt>.
	1907
	1908		If unsure, say N.
	1909
	1910		config FB_PXA_OVERLAY
	1911		bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
	1912		default n
	1913		depends on FB_PXA && (PXA27x || PXA3xx)
	1914
	1915		config FB_PXA_SMARTPANEL
	1916		bool "PXA Smartpanel LCD support"
	1917		default n
	1918		depends on FB_PXA
	1919
	1920		config FB_PXA_PARAMETERS
	1921		bool "PXA LCD command line parameters"
	1922		default n
	1923		depends on FB_PXA
	1924		---help---
	1925		Enable the use of kernel command line or module parameters
	1926		to configure the physical properties of the LCD panel when
	1927		using the PXA LCD driver.
	1928
	1929		This option allows you to override the panel parameters
	1930		supplied by the platform in order to support multiple
	1931		different models of flatpanel. If you will only be using a
	1932		single model of flatpanel then you can safely leave this
	1933		option disabled.
	1934
	1935		<file:Documentation/fb/pxafb.txt> describes the available parameters.
	1936
	1937		config PXA3XX_GCU
	1938		tristate "PXA3xx 2D graphics accelerator driver"
	1939		depends on FB_PXA
	1940		help
	1941		Kernelspace driver for the 2D graphics controller unit (GCU)
	1942		found on PXA3xx processors. There is a counterpart driver in the
	1943		DirectFB suite, see http://www.directfb.org/
	1944
	1945		If you compile this as a module, it will be called pxa3xx_gcu.
	1946
	1947		config FB_MBX
	1948		tristate "2700G LCD framebuffer support"
	1949		depends on FB && ARCH_PXA
	1950		select FB_CFB_FILLRECT
	1951		select FB_CFB_COPYAREA
	1952		select FB_CFB_IMAGEBLIT
	1953		---help---
	1954		Framebuffer driver for the Intel 2700G (Marathon) Graphics
	1955		Accelerator
	1956
	1957		config FB_MBX_DEBUG
	1958		bool "Enable debugging info via debugfs"
	1959		depends on FB_MBX && DEBUG_FS
	1960		default n
	1961		---help---
	1962		Enable this if you want debugging information using the debug
	1963		filesystem (debugfs)
	1964
	1965		If unsure, say N.
	1966
	1967		config FB_FSL_DIU
	1968		tristate "Freescale DIU framebuffer support"
	1969		depends on FB && FSL_SOC
	1970		select FB_MODE_HELPERS
	1971		select FB_CFB_FILLRECT
	1972		select FB_CFB_COPYAREA
	1973		select FB_CFB_IMAGEBLIT
	1974		select PPC_LIB_RHEAP
	1975		---help---
	1976		Framebuffer driver for the Freescale SoC DIU
	1977
	1978		config FB_W100
	1979		tristate "W100 frame buffer support"
	1980		depends on FB && ARCH_PXA
	1981		select FB_CFB_FILLRECT
	1982		select FB_CFB_COPYAREA
	1983		select FB_CFB_IMAGEBLIT
	1984		---help---
	1985		Frame buffer driver for the w100 as found on the Sharp SL-Cxx series.
	1986		It can also drive the w3220 chip found on iPAQ hx4700.
	1987
	1988		This driver is also available as a module ( = code which can be
	1989		inserted and removed from the running kernel whenever you want). The
	1990		module will be called w100fb. If you want to compile it as a module,
	1991		say M here and read <file:Documentation/kbuild/modules.txt>.
	1992
	1993		If unsure, say N.
	1994
	1995		config FB_SH_MOBILE_LCDC
	1996		tristate "SuperH Mobile LCDC framebuffer support"
	1997		depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
	1998		select FB_SYS_FILLRECT
	1999		select FB_SYS_COPYAREA
	2000		select FB_SYS_IMAGEBLIT
	2001		select FB_SYS_FOPS
	2002		select FB_DEFERRED_IO
	2003		select FB_BACKLIGHT
	2004		select SH_MIPI_DSI if SH_LCD_MIPI_DSI
	2005		---help---
	2006		Frame buffer driver for the on-chip SH-Mobile LCD controller.
	2007
	2008		config FB_SH_MOBILE_HDMI
	2009		tristate "SuperH Mobile HDMI controller support"
	2010		depends on FB_SH_MOBILE_LCDC
	2011		select FB_MODE_HELPERS
	2012		select SOUND
	2013		select SND
	2014		select SND_SOC
	2015		---help---
	2016		Driver for the on-chip SH-Mobile HDMI controller.
	2017
	2018		config FB_TMIO
	2019		tristate "Toshiba Mobile IO FrameBuffer support"
	2020		depends on FB && MFD_CORE
	2021		select FB_CFB_FILLRECT
	2022		select FB_CFB_COPYAREA
	2023		select FB_CFB_IMAGEBLIT
	2024		---help---
	2025		Frame buffer driver for the Toshiba Mobile IO integrated as found
	2026		on the Sharp SL-6000 series
	2027
	2028		This driver is also available as a module ( = code which can be
	2029		inserted and removed from the running kernel whenever you want). The
	2030		module will be called tmiofb. If you want to compile it as a module,
	2031		say M here and read <file:Documentation/kbuild/modules.txt>.
	2032
	2033		If unsure, say N.
	2034
	2035		config FB_TMIO_ACCELL
	2036		bool "tmiofb acceleration"
	2037		depends on FB_TMIO
	2038		default y
	2039
	2040		config FB_S3C
	2041		tristate "Samsung S3C framebuffer support"
	2042		depends on FB && (S3C_DEV_FB || S5P_DEV_FIMD0)
	2043		select FB_CFB_FILLRECT
	2044		select FB_CFB_COPYAREA
	2045		select FB_CFB_IMAGEBLIT
	2046		---help---
	2047		Frame buffer driver for the built-in FB controller in the Samsung
	2048		SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
	2049		and the S3C64XX series such as the S3C6400 and S3C6410.
	2050
	2051		These chips all have the same basic framebuffer design with the
	2052		actual capabilities depending on the chip. For instance the S3C6400
	2053		and S3C6410 support 4 hardware windows whereas the S3C24XX series
	2054		currently only have two.
	2055
	2056		Currently the support is only for the S3C6400 and S3C6410 SoCs.
	2057
	2058		config FB_S3C_DEBUG_REGWRITE
	2059		bool "Debug register writes"
	2060		depends on FB_S3C
	2061		---help---
	2062		Show all register writes via printk(KERN_DEBUG)
	2063
	2064		config FB_S3C2410
	2065		tristate "S3C2410 LCD framebuffer support"
	2066		depends on FB && ARCH_S3C24XX
	2067		select FB_CFB_FILLRECT
	2068		select FB_CFB_COPYAREA
	2069		select FB_CFB_IMAGEBLIT
	2070		---help---
	2071		Frame buffer driver for the built-in LCD controller in the Samsung
	2072		S3C2410 processor.
	2073
	2074		This driver is also available as a module ( = code which can be
	2075		inserted and removed from the running kernel whenever you want). The
	2076		module will be called s3c2410fb. If you want to compile it as a module,
	2077		say M here and read <file:Documentation/kbuild/modules.txt>.
	2078
	2079		If unsure, say N.
	2080		config FB_S3C2410_DEBUG
	2081		bool "S3C2410 lcd debug messages"
	2082		depends on FB_S3C2410
	2083		help
	2084		Turn on debugging messages. Note that you can set/unset at run time
	2085		through sysfs
	2086
	2087		config FB_NUC900
	2088		bool "NUC900 LCD framebuffer support"
	2089		depends on FB && ARCH_W90X900
	2090		select FB_CFB_FILLRECT
	2091		select FB_CFB_COPYAREA
	2092		select FB_CFB_IMAGEBLIT
	2093		---help---
	2094		Frame buffer driver for the built-in LCD controller in the Nuvoton
	2095		NUC900 processor
	2096
	2097		config GPM1040A0_320X240
	2098		bool "Giantplus Technology GPM1040A0 320x240 Color TFT LCD"
	2099		depends on FB_NUC900
	2100
	2101		config FB_NUC900_DEBUG
	2102		bool "NUC900 lcd debug messages"
	2103		depends on FB_NUC900
	2104		help
	2105		Turn on debugging messages. Note that you can set/unset at run time
	2106		through sysfs
	2107
	2108		config FB_SM501
	2109		tristate "Silicon Motion SM501 framebuffer support"
	2110		depends on FB && MFD_SM501
	2111		select FB_CFB_FILLRECT
	2112		select FB_CFB_COPYAREA
	2113		select FB_CFB_IMAGEBLIT
	2114		---help---
	2115		Frame buffer driver for the CRT and LCD controllers in the Silicon
	2116		Motion SM501.
	2117
	2118		This driver is also available as a module ( = code which can be
	2119		inserted and removed from the running kernel whenever you want). The
	2120		module will be called sm501fb. If you want to compile it as a module,
	2121		say M here and read <file:Documentation/kbuild/modules.txt>.
	2122
	2123		If unsure, say N.
	2124
	2125		config FB_SMSCUFX
	2126		tristate "SMSC UFX6000/7000 USB Framebuffer support"
	2127		depends on FB && USB
	2128		select FB_MODE_HELPERS
	2129		select FB_SYS_FILLRECT
	2130		select FB_SYS_COPYAREA
	2131		select FB_SYS_IMAGEBLIT
	2132		select FB_SYS_FOPS
	2133		select FB_DEFERRED_IO
	2134		---help---
	2135		This is a kernel framebuffer driver for SMSC UFX USB devices.
	2136		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2137		mplayer -vo fbdev. Supports both UFX6000 (USB 2.0) and UFX7000
	2138		(USB 3.0) devices.
	2139		To compile as a module, choose M here: the module name is smscufx.
	2140
	2141		config FB_UDL
	2142		tristate "Displaylink USB Framebuffer support"
	2143		depends on FB && USB
	2144		select FB_MODE_HELPERS
	2145		select FB_SYS_FILLRECT
	2146		select FB_SYS_COPYAREA
	2147		select FB_SYS_IMAGEBLIT
	2148		select FB_SYS_FOPS
	2149		select FB_DEFERRED_IO
	2150		---help---
	2151		This is a kernel framebuffer driver for DisplayLink USB devices.
	2152		Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
	2153		mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
	2154		To compile as a module, choose M here: the module name is udlfb.
	2155
	2156		config FB_PNX4008_DUM
	2157		tristate "Display Update Module support on Philips PNX4008 board"
	2158		depends on FB && ARCH_PNX4008
	2159		---help---
	2160		Say Y here to enable support for PNX4008 Display Update Module (DUM)
	2161
	2162		config FB_PNX4008_DUM_RGB
	2163		tristate "RGB Framebuffer support on Philips PNX4008 board"
	2164		depends on FB_PNX4008_DUM
	2165		select FB_CFB_FILLRECT
	2166		select FB_CFB_COPYAREA
	2167		select FB_CFB_IMAGEBLIT
	2168		---help---
	2169		Say Y here to enable support for PNX4008 RGB Framebuffer
	2170
	2171		config FB_IBM_GXT4500
	2172		tristate "Framebuffer support for IBM GXT4500P adaptor"
	2173		depends on FB && PPC
	2174		select FB_CFB_FILLRECT
	2175		select FB_CFB_COPYAREA
	2176		select FB_CFB_IMAGEBLIT
	2177		---help---
	2178		Say Y here to enable support for the IBM GXT4500P display
	2179		adaptor, found on some IBM System P (pSeries) machines.
	2180
	2181		config FB_PS3
	2182		tristate "PS3 GPU framebuffer driver"
	2183		depends on FB && PS3_PS3AV
	2184		select FB_SYS_FILLRECT
	2185		select FB_SYS_COPYAREA
	2186		select FB_SYS_IMAGEBLIT
	2187		select FB_SYS_FOPS
	2188		select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
	2189		---help---
	2190		Include support for the virtual frame buffer in the PS3 platform.
	2191
	2192		config FB_PS3_DEFAULT_SIZE_M
	2193		int "PS3 default frame buffer size (in MiB)"
	2194		depends on FB_PS3
	2195		default 9
	2196		---help---
	2197		This is the default size (in MiB) of the virtual frame buffer in
	2198		the PS3.
	2199		The default value can be overridden on the kernel command line
	2200		using the "ps3fb" option (e.g. "ps3fb=9M");
	2201
	2202		config FB_XILINX
	2203		tristate "Xilinx frame buffer support"
	2204		depends on FB && (XILINX_VIRTEX || MICROBLAZE)
	2205		select FB_CFB_FILLRECT
	2206		select FB_CFB_COPYAREA
	2207		select FB_CFB_IMAGEBLIT
	2208		---help---
	2209		Include support for the Xilinx ML300/ML403 reference design
	2210		framebuffer. ML300 carries a 640*480 LCD display on the board,
	2211		ML403 uses a standard DB15 VGA connector.
	2212
	2213		config FB_COBALT
	2214		tristate "Cobalt server LCD frame buffer support"
	2215		depends on FB && MIPS_COBALT
	2216
	2217		config FB_SH7760
	2218		bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
	2219		depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
	2220		|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
	2221		select FB_CFB_FILLRECT
	2222		select FB_CFB_COPYAREA
	2223		select FB_CFB_IMAGEBLIT
	2224		---help---
	2225		Support for the SH7760/SH7763/SH7720/SH7721 integrated
	2226		(D)STN/TFT LCD Controller.
	2227		Supports display resolutions up to 1024x1024 pixel, grayscale and
	2228		color operation, with depths ranging from 1 bpp to 8 bpp monochrome
	2229		and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
	2230		panels <= 320 pixel horizontal resolution.
	2231
	2232		config FB_DA8XX
	2233		tristate "DA8xx/OMAP-L1xx Framebuffer support"
	2234		depends on FB && ARCH_DAVINCI_DA8XX
	2235		select FB_CFB_FILLRECT
	2236		select FB_CFB_COPYAREA
	2237		select FB_CFB_IMAGEBLIT
	2238		select FB_CFB_REV_PIXELS_IN_BYTE
	2239		---help---
	2240		This is the frame buffer device driver for the TI LCD controller
	2241		found on DA8xx/OMAP-L1xx SoCs.
	2242		If unsure, say N.
	2243
	2244		config FB_VIRTUAL
	2245		tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
	2246		depends on FB
	2247		select FB_SYS_FILLRECT
	2248		select FB_SYS_COPYAREA
	2249		select FB_SYS_IMAGEBLIT
	2250		select FB_SYS_FOPS
	2251		---help---
	2252		This is a `virtual' frame buffer device. It operates on a chunk of
	2253		unswappable kernel memory instead of on the memory of a graphics
	2254		board. This means you cannot see any output sent to this frame
	2255		buffer device, while it does consume precious memory. The main use
	2256		of this frame buffer device is testing and debugging the frame
	2257		buffer subsystem. Do NOT enable it for normal systems! To protect
	2258		the innocent, it has to be enabled explicitly at boot time using the
	2259		kernel option `video=vfb:'.
	2260
	2261		To compile this driver as a module, choose M here: the
	2262		module will be called vfb. In order to load it, you must use
	2263		the vfb_enable=1 option.
	2264
	2265		If unsure, say N.
	2266
	2267		config XEN_FBDEV_FRONTEND
	2268		tristate "Xen virtual frame buffer support"
	2269		depends on FB && XEN
	2270		select FB_SYS_FILLRECT
	2271		select FB_SYS_COPYAREA
	2272		select FB_SYS_IMAGEBLIT
	2273		select FB_SYS_FOPS
	2274		select FB_DEFERRED_IO
	2275		select INPUT_XEN_KBDDEV_FRONTEND
	2276		select XEN_XENBUS_FRONTEND
	2277		default y
	2278		help
	2279		This driver implements the front-end of the Xen virtual
	2280		frame buffer driver. It communicates with a back-end
	2281		in another domain.
	2282
	2283		config FB_METRONOME
	2284		tristate "E-Ink Metronome/8track controller support"
	2285		depends on FB
	2286		select FB_SYS_FILLRECT
	2287		select FB_SYS_COPYAREA
	2288		select FB_SYS_IMAGEBLIT
	2289		select FB_SYS_FOPS
	2290		select FB_DEFERRED_IO
	2291		help
	2292		This driver implements support for the E-Ink Metronome
	2293		controller. The pre-release name for this device was 8track
	2294		and could also have been called by some vendors as PVI-nnnn.
	2295
	2296		config FB_MB862XX
	2297		tristate "Fujitsu MB862xx GDC support"
	2298		depends on FB
	2299		depends on PCI || (OF && PPC)
	2300		select FB_CFB_FILLRECT
	2301		select FB_CFB_COPYAREA
	2302		select FB_CFB_IMAGEBLIT
	2303		---help---
	2304		Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
	2305
	2306		choice
	2307		prompt "GDC variant"
	2308		depends on FB_MB862XX
	2309
	2310		config FB_MB862XX_PCI_GDC
	2311		bool "Carmine/Coral-P(A) GDC"
	2312		depends on PCI
	2313		---help---
	2314		This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
	2315		PCI graphics controller devices.
	2316
	2317		config FB_MB862XX_LIME
	2318		bool "Lime GDC"
	2319		depends on OF && PPC
	2320		select FB_FOREIGN_ENDIAN
	2321		select FB_LITTLE_ENDIAN
	2322		---help---
	2323		Framebuffer support for Fujitsu Lime GDC on host CPU bus.
	2324
	2325		endchoice
	2326
	2327		config FB_MB862XX_I2C
	2328		bool "Support I2C bus on MB862XX GDC"
	2329		depends on FB_MB862XX && I2C
	2330		default y
	2331		help
	2332		Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
	2333		driver to support accessing I2C devices on controller's I2C bus.
	2334		These are usually some video decoder chips.
	2335
	2336		config FB_EP93XX
	2337		tristate "EP93XX frame buffer support"
	2338		depends on FB && ARCH_EP93XX
	2339		select FB_CFB_FILLRECT
	2340		select FB_CFB_COPYAREA
	2341		select FB_CFB_IMAGEBLIT
	2342		---help---
	2343		Framebuffer driver for the Cirrus Logic EP93XX series of processors.
	2344		This driver is also available as a module. The module will be called
	2345		ep93xx-fb.
	2346
	2347		config FB_PRE_INIT_FB
	2348		bool "Don't reinitialize, use bootloader's GDC/Display configuration"
	2349		depends on FB && FB_MB862XX_LIME
	2350		---help---
	2351		Select this option if display contents should be inherited as set by
	2352		the bootloader.
	2353
	2354		config FB_MSM
	2355		tristate "MSM Framebuffer support"
	2356		depends on FB && ARCH_MSM
	2357		select FB_CFB_FILLRECT
	2358		select FB_CFB_COPYAREA
	2359		select FB_CFB_IMAGEBLIT
	2360
	2361		config FB_MX3
	2362		tristate "MX3 Framebuffer support"
	2363		depends on FB && MX3_IPU
	2364		select FB_CFB_FILLRECT
	2365		select FB_CFB_COPYAREA
	2366		select FB_CFB_IMAGEBLIT
	2367		default y
	2368		help
	2369		This is a framebuffer device for the i.MX31 LCD Controller. So
	2370		far only synchronous displays are supported. If you plan to use
	2371		an LCD display with your i.MX31 system, say Y here.
	2372
	2373		config FB_BROADSHEET
	2374		tristate "E-Ink Broadsheet/Epson S1D13521 controller support"
	2375		depends on FB
	2376		select FB_SYS_FILLRECT
	2377		select FB_SYS_COPYAREA
	2378		select FB_SYS_IMAGEBLIT
	2379		select FB_SYS_FOPS
	2380		select FB_DEFERRED_IO
	2381		help
	2382		This driver implements support for the E-Ink Broadsheet
	2383		controller. The release name for this device was Epson S1D13521
	2384		and could also have been called by other names when coupled with
	2385		a bridge adapter.
	2386
	2387		config FB_JZ4740
	2388		tristate "JZ4740 LCD framebuffer support"
	2389		depends on FB && MACH_JZ4740
	2390		select FB_SYS_FILLRECT
	2391		select FB_SYS_COPYAREA
	2392		select FB_SYS_IMAGEBLIT
	2393		help
	2394		Framebuffer support for the JZ4740 SoC.
	2395
	2396		config FB_MXS
	2397		tristate "MXS LCD framebuffer support"
	2398		depends on FB && ARCH_MXS
	2399		select FB_CFB_FILLRECT
	2400		select FB_CFB_COPYAREA
	2401		select FB_CFB_IMAGEBLIT
	2402		help
	2403		Framebuffer support for the MXS SoC.
	2404
	2405		config FB_PUV3_UNIGFX
	2406		tristate "PKUnity v3 Unigfx framebuffer support"
	2407		depends on FB && UNICORE32 && ARCH_PUV3
	2408		select FB_SYS_FILLRECT
	2409		select FB_SYS_COPYAREA
	2410		select FB_SYS_IMAGEBLIT
	2411		select FB_SYS_FOPS
	2412		help
	2413		Choose this option if you want to use the Unigfx device as a
	2414		framebuffer device. Without the support of PCI & AGP.
	2415
	2416		source "drivers/video/omap/Kconfig"
	2417		source "drivers/video/omap2/Kconfig"
	2418		source "drivers/video/exynos/Kconfig"
	2419		source "drivers/video/backlight/Kconfig"
	2420
	2421		if VT
	2422		source "drivers/video/console/Kconfig"
	2423		endif
	2424
	2425		if FB || SGI_NEWPORT_CONSOLE
	2426		source "drivers/video/logo/Kconfig"
	2427		endif
	2428
	2429		config FB_SH_MOBILE_MERAM
	2430		tristate "SuperH Mobile MERAM read ahead support"
	2431		depends on (SUPERH || ARCH_SHMOBILE)
	2432		select GENERIC_ALLOCATOR
	2433		---help---
	2434		Enable MERAM support for the SuperH controller.
	2435
	2436		This will allow for caching of the framebuffer to provide more
	2437		reliable access under heavy main memory bus traffic situations.
	2438		Up to 4 memory channels can be configured, allowing 4 RGB or
	2439		2 YCbCr framebuffers to be configured.
	2440
	2441		endmenu

File include/alga/alga.h added (mode: 100644) (index 0000000..5ff4816)
	1		#ifndef _ALGA_H
	2		#define _ALGA_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define ALGA_ERR 900
	9		#endif

File include/alga/amd/atombios/atb.h added (mode: 100644) (index 0000000..ac4f981)
	1		#ifndef _ALGA_AMD_ATOMBIOS_ATB_H
	2		#define _ALGA_AMD_ATOMBIOS_ATB_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define ATB_ERR 800
	9
	10		struct atombios;
	11		#include <alga/amd/atombios/atb_dev.h>
	12		struct atombios *atb_alloc(struct atb_dev *adev);
	13		int atb_init(struct atombios *atb);
	14		void atb_cleanup(struct atombios *atb);
	15
	16		int atb_asic_init(struct atombios *atb);
	17		#endif

File include/alga/amd/atombios/atb_dev.h added (mode: 100644) (index 0000000..117cbf6)
	1		#ifndef _ALGA_AMD_ATOMBIOS_ATB_DEV_H
	2		#define _ALGA_AMD_ATOMBIOS_ATB_DEV_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		struct atb_dev {
	9		struct device *dev;
	10		void *rom;
	11		u32 (*rr32)(struct device *dev, unsigned of);
	12		void (*wr32)(struct device *dev, u32 val, unsigned of);
	13		};
	14		#endif
	15

File include/alga/amd/atombios/dce.h added (mode: 100644) (index 0000000..248af97)
	1		#ifndef _ALGA_AMD_ATOMBIOS_DCE_H
	2		#define _ALGA_AMD_ATOMBIOS_DCE_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		void atb_lock(struct atombios *atb, bool lock);
	9		int atb_trans_link_init(struct atombios *atb, unsigned i, bool edp);
	10		int atb_trans_link_off(struct atombios *atb, unsigned i);
	11		int atb_trans_link_on(struct atombios *atb, unsigned i, unsigned dp_lanes_n,
	12		unsigned pixel_clk);
	13		int atb_trans_link_output_off(struct atombios *atb, unsigned i);
	14		int atb_trans_link_output_on(struct atombios *atb, unsigned i, unsigned dp_lanes_n,
	15		unsigned pixel_clk);
	16		int atb_trans_link_pwr(struct atombios *atb, unsigned i, bool on);
	17		int atb_trans_link_vs_pre_emph(struct atombios *atb, unsigned i, u8 vs_pre_emph);
	18
	19		int atb_enc_crtc_src(struct atombios *atb, unsigned i);
	20		int atb_enc_video(struct atombios *atb, unsigned i, bool on);
	21		int atb_enc_setup(struct atombios *atb, unsigned i, unsigned dp_lanes_n,
	22		unsigned dp_link_rate, unsigned bpc, unsigned pixel_clk);
	23		int atb_crtc_blank(struct atombios *atb, unsigned i, bool on);
	24		int atb_crtc_mem_req(struct atombios *atb, unsigned i, bool on);
	25		int atb_crtc(struct atombios *atb, unsigned i, bool on);
	26		int atb_crtc_lock(struct atombios *atb, unsigned i, bool lock);
	27		int atb_crtc_virtual_pixel_clk(struct atombios *atb, unsigned i, unsigned clk);
	28		int atb_crtc_timing(struct atombios *atb, unsigned i, struct alga_timing *t);
	29		int atb_crtc_dcpll(struct atombios *atb);
	30		int atb_crtc_overscan(struct atombios *atb, unsigned i);
	31		int atb_crtc_scaler(struct atombios *atb, unsigned i);
	32
	33		int atb_enc_dp_training_start(struct atombios *atb, unsigned i);
	34		int atb_enc_dp_training_complete(struct atombios *atb, unsigned i);
	35		int atb_enc_dp_tp(struct atombios *atb, unsigned i, unsigned link_rate,
	36		unsigned lanes_n, unsigned tp);
	37
	38		#include <alga/amd/atombios/dp_paths.h>
	39		int atb_dp_paths(struct atombios *atb, struct atb_dp_path **dp_paths,
	40		size_t *dp_paths_n);
	41		void atb_dp_state(struct atombios *atb, unsigned dfp, bool connected);
	42
	43		int atb_dp_aux_native_read(struct atombios *atb, u8 aux_i2c_id, u8 hpd,
	44		u32 addr, u8 *recv_buf, size_t recv_buf_sz);
	45		int atb_dp_aux_native_write(struct atombios *atb, u8 aux_i2c_id, u8 hpd,
	46		u32 addr, u8 *send_buf, size_t send_buf_sz);
	47
	48		#define ATB_MODE_I2C_READ 1
	49		#define ATB_MODE_I2C_WRITE 2
	50		#define ATB_MODE_I2C_START 4
	51		#define ATB_MODE_I2C_STOP 8
	52		int atb_dp_aux_i2c(struct atombios *atb, u8 aux_i2c_id, u8 hpd, u16 addr,
	53		unsigned mode, u8 byte_send, u8 *byte_recv);
	54		#endif

File include/alga/amd/atombios/dp_paths.h added (mode: 100644) (index 0000000..b53f8ac)
	1		#ifndef _DP_PATHS_H
	2		#define _DP_PATHS_H
	3		struct atb_dp_path
	4		{
	5		unsigned i;
	6		unsigned dfp; /* 0~6, for atombios DFP0~6 */
	7		bool edp;
	8		u8 hpd;
	9		u8 aux_i2c_id;
	10		bool uniphy_link_hbr2;
	11		};
	12		#endif

File include/alga/amd/dce6/dce6.h added (mode: 100644) (index 0000000..10468d0)
	1		#ifndef _ALGA_AMD_DCE6_DCE6_H
	2		#define _ALGA_AMD_DCE6_DCE6_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		#define CRTCS_N_MAX 6
	10		#define HPDS_N 6
	11
	12		#ifdef __KERNEL__
	13		#define DCE6_ERR 1000
	14
	15		struct db_fb {
	16		u64 primary;
	17		u64 secondary;
	18		enum alga_pixel_fmt pixel_fmt;
	19
	20		struct alga_timing timing;
	21		unsigned pitch;
	22		};
	23
	24		/* major programming functions: do lock dce state */
	25		struct dce6;
	26		#include <alga/amd/dce6/dce6_dev.h>
	27		struct dce6 *dce6_alloc(struct dce6_dev *ddev);
	28		int dce6_init(struct dce6 *dce, u32 dmif_addr_cfg);
	29		void dce6_shutdown(struct dce6 *dce);
	30		int dce6_sink_mode_set(struct dce6 *dce, unsigned i, struct db_fb *db_fb);
	31		int dce6_dps_info(struct dce6 *dce, unsigned *used, unsigned *connected,
	32		enum alga_pixel_fmt (*fmts)[CRTCS_N_MAX][ALGA_PIXEL_FMTS_MAX],
	33		struct alga_timing (*ts)[CRTCS_N_MAX][ALGA_TIMINGS_MAX]);
	34		int dce6_dp_dpm(struct dce6 *dce, unsigned i);
	35		/* irq thread */
	36		int dce6_irqs_thd(struct dce6 *dce);
	37
	38		/* hard interrupt context: ack and tag hpd/pf events */
	39		void dce6_hpd_irq(struct dce6 *dce, unsigned hpd);
	40		void dce6_pf_irq(struct dce6 *dce, unsigned i);
	41
	42		/* direct hardware access */
	43		void dce6_vga_off(struct dce6 *dce);
	44		void dce6_irqs_ack(struct dce6 *dce);
	45		void dce6_intrs_reset(struct dce6 *dce);
	46		void dce6_hpds_intr_ena(struct dce6 *dce);
	47		int dce6_pf(struct dce6 *dce, unsigned i, unsigned *vblanks_n);
	48
	49		/* direct atombios access */
	50		int dce6_mem_req(struct dce6 *dce, bool ena);
	51		#endif
	52		#endif

File include/alga/amd/dce6/dce6_dev.h added (mode: 100644) (index 0000000..b8ba61f)
	1		#ifndef _ALGA_AMD_DCE6_DCE6_DEV_H
	2		#define _ALGA_AMD_DCE6_DCE6_DEV_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		struct dce6_dev {/* provides device specific services for dce6 */
	9		struct device *dev;
	10		unsigned crtcs_n;
	11		u32 (*rr32)(struct device *dev, unsigned of);
	12		void (*wr32)(struct device *dev, u32 val, unsigned of);
	13		struct atombios *atb;
	14		};
	15		#endif

File include/alga/amd/evergreen/ioctl.h added (mode: 100644) (index 0000000..7b2fbe7)
	1		#ifndef _ALGA_AMD_EVERGREEN_IOCTL_H
	2		#define _ALGA_AMD_EVERGREEN_IOCTL_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define EVERGREEN_NOP 0
	9
	10		#define EVERGREEN_DCE_DPS_INFO 1
	11		#define EVERGREEN_DCE_DP_SET 2
	12		#define EVERGREEN_DCE_DP_DPM 3
	13		#define EVERGREEN_DCE_PF 4
	14		#define EVERGREEN_MEM_ALLOC 5
	15		#define EVERGREEN_MEM_FREE 6
	16		#define EVERGREEN_INFO 7
	17
	18		struct evergreen_dce_dps_info {
	19		unsigned used;
	20		unsigned connected;
	21		enum alga_pixel_fmt pixel_fmts[CRTCS_N_MAX][ALGA_PIXEL_FMTS_MAX];
	22		struct alga_timing timings[CRTCS_N_MAX][ALGA_TIMINGS_MAX];
	23		};
	24
	25		struct evergreen_dce_dp_set {
	26		unsigned i;
	27		uint64_t primary;
	28		uint64_t secondary;
	29		enum alga_pixel_fmt pixel_fmt;
	30		struct alga_timing timing;
	31		unsigned pitch;
	32		};
	33
	34		struct evergreen_mem {
	35		union {
	36		uint64_t gpu_addr; /* output */
	37		struct { /* input */
	38		uint64_t sz;
	39		uint64_t align;
	40		};
	41		};
	42		};
	43
	44		#ifndef __KERNEL__
	45		#define EVERGREEN_GPU_PAGE_SZ 4096
	46		#endif
	47		#endif

File include/alga/dp.h added (mode: 100644) (index 0000000..9c4166e)
	1		#ifndef _ALGA_DP_H
	2		#define _ALGA_DP_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		#define DP_MAX_LANES_N 4
	10
	11		#define DP_AUX_NATIVE_WRITE 0x8
	12		#define DP_AUX_NATIVE_READ 0x9
	13		#define DP_AUX_I2C_WRITE 0x0
	14		#define DP_AUX_I2C_READ 0x1
	15		#define DP_AUX_I2C_STATUS 0x2
	16		#define DP_AUX_I2C_MOT 0x4
	17
	18		#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 4)
	19		#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 4)
	20		#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 4)
	21		#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 4)
	22
	23		#define DP_AUX_I2C_REPLY_ACK (0x0 << 6)
	24		#define DP_AUX_I2C_REPLY_NACK (0x1 << 6)
	25		#define DP_AUX_I2C_REPLY_DEFER (0x2 << 6)
	26		#define DP_AUX_I2C_REPLY_MASK (0x3 << 6)
	27
	28		#define DP_LINK_RATE_UNIT_KHZ 270000
	29		#define DP_LINK_RATE_UNIT_MHZ 270
	30
	31		/* DPCD registers */
	32		#define DPCD_LINK_STATUS_SZ 6 /* 6 dpcd bytes */
	33
	34		#define DPCD_REV 0x0000
	35		#define DPCD_MAX_LINK_RATE 0x0001
	36		#define DPCD_MAX_LANE_COUNT 0x0002
	37		#define DPCD_LANE_COUNT_MASK 0x0f
	38		#define DPCD_LANE_COUNT_ENHANCED_FRAME_EN BIT(7)
	39		#define DPCD_MAX_DOWNSPREAD 0x0003
	40		#define DPCD_MAX_DOWNSPREAD_SUPPORT BIT(0)
	41
	42		#define DPCD_LINK_BW_SET 0x0100
	43		#define DPCD_LINK_BW_1_62 0x06
	44		#define DPCD_LINK_BW_2_7 0x0a
	45		#define DPCD_LINK_BW_5_4 0x14
	46		/* same definition than DPCD_MAX_LANE_COUNT */
	47		#define DPCD_LANE_COUNT_SET 0x0101
	48		#define DPCD_TRAINING_PATTERN_SET 0x0102
	49		#define DPCD_TRAINING_PATTERN_DISABLE 0
	50		#define DPCD_TRAINING_PATTERN_1 1
	51		#define DPCD_TRAINING_PATTERN_2 2
	52		#define DPCD_TRAINING_PATTERN_3 3
	53		#define DPCD_TRAINING_PATTERN_MASK 0x3
	54
	55		#define DPCD_TRAINING_LANE0_SET 0x0103
	56		#define DPCD_TRAINING_LANE1_SET 0x0104
	57		#define DPCD_TRAINING_LANE2_SET 0x0105
	58		#define DPCD_TRAINING_LANE3_SET 0x0106
	59		#define DPCD_VOLTAGE_SWING_SHIFT 0
	60		#define DPCD_VOLTAGE_SWING_MASK (0x3 << \
	61		DPCD_VOLTAGE_SWING_SHIFT)
	62		#define DPCD_MAX_VOLTAGE_SWING_REACHED BIT(2 + \
	63		DPCD_VOLTAGE_SWING_SHIFT)
	64		#define DPCD_VOLTAGE_SWING_400 (0 << \
	65		DPCD_VOLTAGE_SWING_SHIFT)
	66		#define DPCD_VOLTAGE_SWING_600 (1 << \
	67		DPCD_VOLTAGE_SWING_SHIFT)
	68		#define DPCD_VOLTAGE_SWING_800 (2 << \
	69		DPCD_VOLTAGE_SWING_SHIFT)
	70		#define DPCD_VOLTAGE_SWING_1200 (3 << \
	71		DPCD_VOLTAGE_SWING_SHIFT)
	72
	73		#define DPCD_PRE_EMPHASIS_SHIFT 3
	74		#define DPCD_PRE_EMPHASIS_MASK (0x3 << \
	75		DPCD_PRE_EMPHASIS_SHIFT)
	76		#define DPCD_MAX_PRE_EMPHASIS_REACHED BIT(2 + \
	77		DPCD_PRE_EMPHASIS_SHIFT)
	78		#define DPCD_PRE_EMPHASIS_0 (0 << \
	79		DPCD_PRE_EMPHASIS_SHIFT)
	80		#define DPCD_PRE_EMPHASIS_3_5 (1 << \
	81		DPCD_PRE_EMPHASIS_SHIFT)
	82		#define DPCD_PRE_EMPHASIS_6 (2 << \
	83		DPCD_PRE_EMPHASIS_SHIFT)
	84		#define DPCD_PRE_EMPHASIS_9_5 (3 << \
	85		DPCD_PRE_EMPHASIS_SHIFT)
	86
	87		#define DPCD_DOWNSPREAD_CTL 0x0107
	88		#define DPCD_SPREAD_AMP_0_5 BIT(4)
	89
	90		#define DPCD_LANE0_1_STATUS 0x0202
	91		#define DPCD_LANE2_3_STATUS 0x0203
	92		#define DPCD_LANE_CR_DONE BIT(0)
	93		#define DPCD_LANE_CHANNEL_EQ_DONE BIT(1)
	94		#define DPCD_LANE_SYMBOL_LOCKED BIT(2)
	95		#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE | \
	96		DPCD_LANE_CHANNEL_EQ_DONE | \
	97		DPCD_LANE_SYMBOL_LOCKED)
	98		#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x0204
	99		#define DPCD_INTERLANE_ALIGN_DONE BIT(0)
	100		#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED BIT(6)
	101		#define DPCD_LINK_STATUS_UPDATED BIT(7)
	102
	103		#define DPCD_SINK_STATUS 0x0205
	104		#define DPCD_RECEIVE_PORT_0_STATUS BIT(0)
	105		#define DPCD_RECEIVE_PORT_1_STATUS BIT(1)
	106
	107		#define DPCD_ADJUST_REQUEST_LANE0_1 0x0206
	108		#define DPCD_ADJUST_REQUEST_LANE2_3 0x0207
	109		#define DPCD_ADJUST_VOLTAGE_SWING_LANEX_MASK 0x03
	110		#define DPCD_ADJUST_VOLTAGE_SWING_LANEX_SHIFT 0
	111		#define DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK 0x0c
	112		#define DPCD_ADJUST_PRE_EMPHASIS_LANEX_SHIFT 2
	113		#define DPCD_ADJUST_VOLTAGE_SWING_LANEY_MASK 0x30
	114		#define DPCD_ADJUST_VOLTAGE_SWING_LANEY_SHIFT 4
	115		#define DPCD_ADJUST_PRE_EMPHASIS_LANEY_MASK 0xc0
	116		#define DPCD_ADJUST_PRE_EMPHASIS_LANEY_SHIFT 6
	117
	118		#define DPCD_SET_PWR 0x0600
	119		#define DPCD_SET_PWR_D0 0x1
	120		#define DPCD_SET_PWR_D3 0x2
	121
	122		#define DPCD_MAX_LANE_COUNT_MASK 0x0f
	123
	124		void alga_dp_safe_timing(struct alga_timing (*ts)[ALGA_TIMINGS_MAX]);
	125		#endif

File include/alga/edid.h added (mode: 100644) (index 0000000..a630b78)
	1		#ifndef _ALGA_EDID_H
	2		#define _ALGA_EDID_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define EDID_BLK_SZ 128
	9		int alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a, void **edid);
	10		int alga_edid_timings(struct device *dev, void *edid,
	11		struct alga_timing (*ts)[ALGA_TIMINGS_MAX]);
	12		int alga_edid_bpc(struct device *dev, void *edid);
	13		#endif

File include/alga/pixel_fmts.h added (mode: 100644) (index 0000000..be6a127)
	1		#ifndef _ALGA_PIXEL_FMTS_H
	2		#define _ALGA_PIXEL_FMTS_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8
	9		#define ALGA_PIXEL_FMTS_MAX 64
	10
	11		enum alga_pixel_fmt {
	12		ALGA_PIXEL_FMT_INVALID,
	13		ALGA_ARGB6666,
	14		ALGA_ARGB8888,
	15		ALGA_ARGB2101010
	16		};
	17
	18		static unsigned alga_pixel_fmts_sz[] __attribute__ ((unused)) = {
	19		[ALGA_PIXEL_FMT_INVALID]= 0,
	20		[ALGA_ARGB6666] = 4,
	21		[ALGA_ARGB8888] = 4,
	22		[ALGA_ARGB2101010] = 4
	23		};
	24
	25		static unsigned alga_pixel_fmts_bpc[] __attribute__ ((unused)) = {
	26		[ALGA_PIXEL_FMT_INVALID]= 0,
	27		[ALGA_ARGB6666] = 6,
	28		[ALGA_ARGB8888] = 8,
	29		[ALGA_ARGB2101010] = 10
	30		};
	31		#endif

File include/alga/rng_mng.h added (mode: 100644) (index 0000000..6581860)
	1		#ifndef _ALGA_RNG_MNG_H
	2		#define _ALGA_RNG_MNG_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		struct rng {
	9		u64 s;
	10		u64 sz;
	11		struct list_head n;
	12		};
	13		void rng_mng_init(struct rng *mng, u64 s, u64 sz);
	14		void rng_mng_destroy(struct rng *mng);
	15		/* sz must be aligned */
	16		int rng_alloc_align(u64 *s_aligned, struct rng *mng, u64 sz, u64 align);
	17		#define rng_alloc(p, mng, sz) rng_alloc_align((p),(mng), (sz), 1)
	18		void rng_free(struct rng *mng, u64 s);
	19
	20		static inline u64 rng_align(u64 p, u64 align)
	21		{
	22		u64 adjust;
	23
	24		adjust = p % align;
	25		return p + (adjust ? align - adjust : 0);
	26		}
	27		#endif

File include/alga/timing.h added (mode: 100644) (index 0000000..1029d47)
	1		#ifndef _ALGA_TIMING_H
	2		#define _ALGA_TIMING_H
	3		/*
	4		author Sylvain Bertrand <digital.ragnarok@gmail.com>
	5		Protected by GNU Affero GPL v3 with some exceptions.
	6		See README at root of alga tree.
	7		*/
	8		#define ALGA_TIMINGS_MAX 64
	9		struct alga_timing {
	10		/* pixels */
	11		unsigned h;
	12		unsigned h_bl;
	13		unsigned h_so;
	14		unsigned h_spw;
	15		unsigned h_sp; /* 0: high/positive, 1: low/negative */
	16
	17		/* lines */
	18		unsigned v;
	19		unsigned v_bl;
	20		unsigned v_so;
	21		unsigned v_spw;
	22		unsigned v_sp; /* 0: high/positive, 1: low/negative */
	23
	24		unsigned pixel_clk; /* kHz */
	25		};
	26		#endif