sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
gfx stack update 2c819ea9ca081c61a9e5f7961c188324e623b53d Sylvain BERTRAND 2020-07-12 17:50:40
gfx stack update bdc04d6f6e371752d5ff32737f1de0511cebe2b2 Sylvain BERTRAND 2020-07-05 18:03:47
gfx stack update 6bf84e0e956e8676945e47d8457f4b63857c912f Sylvain BERTRAND 2020-06-29 18:23:49
gfx stack update e5bc37ec0e4e5b33446eb377eb3c66f33ad79020 Sylvain BERTRAND 2020-06-15 02:43:05
add sample code for raw x11 cursor visibility 042be7d6259fd2ab4c759409fb0dceaf3043f4d9 Sylvain BERTRAND 2020-06-09 15:04:53
gfx stack update 7518a03d3592c7eefd8266d73545a803054fd807 Sylvain BERTRAND 2020-06-07 17:37:18
dwm: add npv to floating layout c270a17aeaee624528587328942ba20cd29a9e37 Sylvain BERTRAND 2020-06-05 22:19:55
st: update c4cdf6d812f06b0df6258fee5f798301c75744d7 Sylvain BERTRAND 2020-05-31 22:16:26
gfx stack update 53541f08719e9d5ea0757216d98790823fa34051 Sylvain BERTRAND 2020-05-31 14:37:45
nyanmp update and mesa-gl fix f60565861320e73b6cea95b9317fb988c1ebc6b0 Sylvain BERTRAND 2020-05-29 21:25:45
npv:significant update 6e4c2f9809e3340efbe80680f88881dcc69ae305 Sylvain BERTRAND 2020-05-27 00:06:17
gfx stack update 0ab2792ed36c66cd1bbae6a49d19884aa550fab8 Sylvain BERTRAND 2020-05-26 02:24:04
gfx stack update d0ed82ed5188f2b81e0113f75493327d958fe933 Sylvain BERTRAND 2020-05-17 15:15:05
dwm: update 1657315d53a52f19a60b8e0267935a2ccecea9f9 Sylvain BERTRAND 2020-05-15 15:17:46
nyanmp update baaccd7c04aad6d9c1ed8ee034564452f46eb17d Sylvain BERTRAND 2020-05-15 15:03:33
update nyanmp bd9db1b2810c5263ffea28ead6d0978df2e9c7d3 Sylvain BERTRAND 2020-05-13 15:49:26
gfx stack update a09f6394201749553c21896b88640e385431fef6 Sylvain BERTRAND 2020-05-10 16:59:25
gfx stack update 72e0a51ec20a038ed5a689f0beafcc2f68bc4b67 Sylvain BERTRAND 2020-05-03 14:32:45
gfx stack update and more (llvm broke mesa) 1151a2582d4056e3a21f427501fcacc87454cc34 Sylvain BERTRAND 2020-04-26 17:24:21
gfx update, moving builds to ram, aka being gentle to ssds 47d1bcf83681b21a306eefbc90de5da2414725e8 Sylvain BERTRAND 2020-04-20 00:39:01
Commit 2c819ea9ca081c61a9e5f7961c188324e623b53d - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2020-07-12 17:50
Committer name: Sylvain BERTRAND
Committer date (UTC): 2020-07-12 17:50
Parent(s): bdc04d6f6e371752d5ff32737f1de0511cebe2b2
Signer:
Signing key:
Signing status: N
Tree: a596682253b2a7e8344a1e16d9057acb4b59eba4
File Lines added Lines deleted
builders/ffmpeg-0/builder.sh 1 1
builders/llvm-1/builder.sh 1 1
builders/llvm/builder.sh 1 2
builders/mesa-gl-1/builder.sh 1 1
builders/mesa-gl-1/contrib/compiler_nir.sh 2 0
builders/mesa-gl-1/contrib/egl.sh 1 0
builders/mesa-vulkan-1/builder.sh 1 1
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/generic.c 18 14
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/load.c 2 2
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/store.c 13 1
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/system_values.c 24 0
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/ir3.c 0 29
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/load.c 15 0
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/store.c 14 0
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c 4 0
builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 3 0
builders/xserver-0/builder.sh 1 1
File builders/ffmpeg-0/builder.sh changed (mode: 100644) (index 6ebf426..f010899)
1 git_commit=fdead2a31a4686488a29d45c3d2e9b8b7723c0ef
1 git_commit=2dabee7c0faef202ed04e20856e9f58cb4415810
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/ffmpeg/builder.sh . $nyan_root/builders/ffmpeg/builder.sh
File builders/llvm-1/builder.sh changed (mode: 100644) (index 08598b5..b650937)
1 git_commit=e07a982693353aad85590301357035e9d583bbbc
1 git_commit=66f1dcd872dba189ee054fb016f4bff535fb5afc
2 2 version=11.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt version=11.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt
3 3 slot=1 slot=1
4 4 . $nyan_root/builders/llvm/builder.sh . $nyan_root/builders/llvm/builder.sh
File builders/llvm/builder.sh changed (mode: 100644) (index 21675c5..b5ae627)
... ... cmake -G Ninja \
37 37 -DLLVM_BUILD_UTILS=off \ -DLLVM_BUILD_UTILS=off \
38 38 $pkg_dir/llvm $pkg_dir/llvm
39 39
40 #cmake --build . -- -j $threads_n
41 cmake --build . -- -j 4
40 cmake --build . -- -j $threads_n
42 41 # ninja does not know of DESTDIR, the llvm-config does ignore the sysroot anyway and will be useless on the target machine # ninja does not know of DESTDIR, the llvm-config does ignore the sysroot anyway and will be useless on the target machine
43 42 cmake -DCMAKE_INSTALL_PREFIX=/nyan/llvm/$slot -P ./cmake_install.cmake cmake -DCMAKE_INSTALL_PREFIX=/nyan/llvm/$slot -P ./cmake_install.cmake
44 43 export PATH=$OLD_PATH export PATH=$OLD_PATH
File builders/mesa-gl-1/builder.sh changed (mode: 100644) (index e05dbb9..44ba18d)
1 git_commit=7d31bc9a34ccc4b8570c4145379177c007922504
1 git_commit=55776a0ae0660d730293f11b435dc055753774fd
2 2 slot=1 slot=1
3 3 . $nyan_root/builders/mesa-gl/builder.sh . $nyan_root/builders/mesa-gl/builder.sh
File builders/mesa-gl-1/contrib/compiler_nir.sh changed (mode: 100644) (index 811e570..82e67b4)
... ... $src_dir/src/compiler/nir/nir_lower_bool_to_int32.c \
67 67 $src_dir/src/compiler/nir/nir_lower_clamp_color_outputs.c \ $src_dir/src/compiler/nir/nir_lower_clamp_color_outputs.c \
68 68 $src_dir/src/compiler/nir/nir_lower_clip.c \ $src_dir/src/compiler/nir/nir_lower_clip.c \
69 69 $src_dir/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c \ $src_dir/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c \
70 $src_dir/src/compiler/nir/nir_lower_clip_disable.c \
70 71 $src_dir/src/compiler/nir/nir_lower_clip_halfz.c \ $src_dir/src/compiler/nir/nir_lower_clip_halfz.c \
71 72 $src_dir/src/compiler/nir/nir_lower_discard_to_demote.c \ $src_dir/src/compiler/nir/nir_lower_discard_to_demote.c \
72 73 $src_dir/src/compiler/nir/nir_lower_double_ops.c \ $src_dir/src/compiler/nir/nir_lower_double_ops.c \
 
... ... $src_dir/src/compiler/nir/nir_lower_drawpixels.c \
74 75 $src_dir/src/compiler/nir/nir_lower_fb_read.c \ $src_dir/src/compiler/nir/nir_lower_fb_read.c \
75 76 $src_dir/src/compiler/nir/nir_lower_flatshade.c \ $src_dir/src/compiler/nir/nir_lower_flatshade.c \
76 77 $src_dir/src/compiler/nir/nir_lower_flrp.c \ $src_dir/src/compiler/nir/nir_lower_flrp.c \
78 $src_dir/src/compiler/nir/nir_lower_fragcolor.c \
77 79 $src_dir/src/compiler/nir/nir_lower_fragcoord_wtrans.c \ $src_dir/src/compiler/nir/nir_lower_fragcoord_wtrans.c \
78 80 $src_dir/src/compiler/nir/nir_lower_frexp.c \ $src_dir/src/compiler/nir/nir_lower_frexp.c \
79 81 $src_dir/src/compiler/nir/nir_lower_global_vars_to_local.c \ $src_dir/src/compiler/nir/nir_lower_global_vars_to_local.c \
File builders/mesa-gl-1/contrib/egl.sh changed (mode: 100644) (index b1fe4fa..784d3b6)
... ... $src_dir/src/egl/main/eglsync.c \
30 30 \ \
31 31 $build_dir/src/egl/egl_dri2.c \ $build_dir/src/egl/egl_dri2.c \
32 32 \ \
33 $src_dir/src/egl/drivers/dri2/platform_surfaceless.c \
33 34 $src_dir/src/egl/drivers/dri2/platform_drm.c \ $src_dir/src/egl/drivers/dri2/platform_drm.c \
34 35 $src_dir/src/egl/drivers/dri2/platform_device.c \ $src_dir/src/egl/drivers/dri2/platform_device.c \
35 36 " "
File builders/mesa-vulkan-1/builder.sh changed (mode: 100644) (index dec11f4..dc382ce)
1 git_commit=7d31bc9a34ccc4b8570c4145379177c007922504
1 git_commit=55776a0ae0660d730293f11b435dc055753774fd
2 2 slot=1 slot=1
3 3 . $nyan_root/builders/mesa-vulkan/builder.sh . $nyan_root/builders/mesa-vulkan/builder.sh
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/generic.c changed (mode: 100644) (index cda3b68..6ff528b)
... ... struct nir_intrinsic nir_shuffle_xor = {
1256 1256 .has_dest = true, .has_dest = true,
1257 1257 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1258 1258 }; };
1259 /******************************************************************************/
1260 /* ssbo atomic -- start */
1259 1261 struct nir_intrinsic nir_ssbo_atomic_add = { struct nir_intrinsic nir_ssbo_atomic_add = {
1260 1262 .name = "ssbo_atomic_add", .name = "ssbo_atomic_add",
1261 1263 .srcs_n = 3, .srcs_n = 3,
1262 1264 .src_components_n = { .src_components_n = {
1263 1,1,1
1265 -1,1,1
1264 1266 }, },
1265 1267 .has_dest = true, .has_dest = true,
1266 1268 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_and = {
1273 1275 .name = "ssbo_atomic_and", .name = "ssbo_atomic_and",
1274 1276 .srcs_n = 3, .srcs_n = 3,
1275 1277 .src_components_n = { .src_components_n = {
1276 1,1,1
1278 -1,1,1
1277 1279 }, },
1278 1280 .has_dest = true, .has_dest = true,
1279 1281 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_comp_swap = {
1286 1288 .name = "ssbo_atomic_comp_swap", .name = "ssbo_atomic_comp_swap",
1287 1289 .srcs_n = 4, .srcs_n = 4,
1288 1290 .src_components_n = { .src_components_n = {
1289 1,1,1,1
1291 -1,1,1,1
1290 1292 }, },
1291 1293 .has_dest = true, .has_dest = true,
1292 1294 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_exchange = {
1299 1301 .name = "ssbo_atomic_exchange", .name = "ssbo_atomic_exchange",
1300 1302 .srcs_n = 3, .srcs_n = 3,
1301 1303 .src_components_n = { .src_components_n = {
1302 1,1,1
1304 -1,1,1
1303 1305 }, },
1304 1306 .has_dest = true, .has_dest = true,
1305 1307 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_fadd = {
1312 1314 .name = "ssbo_atomic_fadd", .name = "ssbo_atomic_fadd",
1313 1315 .srcs_n = 3, .srcs_n = 3,
1314 1316 .src_components_n = { .src_components_n = {
1315 1,1,1
1317 -1,1,1
1316 1318 }, },
1317 1319 .has_dest = true, .has_dest = true,
1318 1320 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_fcomp_swap = {
1325 1327 .name = "ssbo_atomic_fcomp_swap", .name = "ssbo_atomic_fcomp_swap",
1326 1328 .srcs_n = 4, .srcs_n = 4,
1327 1329 .src_components_n = { .src_components_n = {
1328 1,1,1,1
1330 -1,1,1,1
1329 1331 }, },
1330 1332 .has_dest = true, .has_dest = true,
1331 1333 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_fmax = {
1338 1340 .name = "ssbo_atomic_fmax", .name = "ssbo_atomic_fmax",
1339 1341 .srcs_n = 3, .srcs_n = 3,
1340 1342 .src_components_n = { .src_components_n = {
1341 1,1,1
1343 -1,1,1
1342 1344 }, },
1343 1345 .has_dest = true, .has_dest = true,
1344 1346 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_fmin = {
1351 1353 .name = "ssbo_atomic_fmin", .name = "ssbo_atomic_fmin",
1352 1354 .srcs_n = 3, .srcs_n = 3,
1353 1355 .src_components_n = { .src_components_n = {
1354 1,1,1
1356 -1,1,1
1355 1357 }, },
1356 1358 .has_dest = true, .has_dest = true,
1357 1359 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_imax = {
1364 1366 .name = "ssbo_atomic_imax", .name = "ssbo_atomic_imax",
1365 1367 .srcs_n = 3, .srcs_n = 3,
1366 1368 .src_components_n = { .src_components_n = {
1367 1,1,1
1369 -1,1,1
1368 1370 }, },
1369 1371 .has_dest = true, .has_dest = true,
1370 1372 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_imin = {
1377 1379 .name = "ssbo_atomic_imin", .name = "ssbo_atomic_imin",
1378 1380 .srcs_n = 3, .srcs_n = 3,
1379 1381 .src_components_n = { .src_components_n = {
1380 1,1,1
1382 -1,1,1
1381 1383 }, },
1382 1384 .has_dest = true, .has_dest = true,
1383 1385 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_or = {
1390 1392 .name = "ssbo_atomic_or", .name = "ssbo_atomic_or",
1391 1393 .srcs_n = 3, .srcs_n = 3,
1392 1394 .src_components_n = { .src_components_n = {
1393 1,1,1
1395 -1,1,1
1394 1396 }, },
1395 1397 .has_dest = true, .has_dest = true,
1396 1398 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_umax = {
1403 1405 .name = "ssbo_atomic_umax", .name = "ssbo_atomic_umax",
1404 1406 .srcs_n = 3, .srcs_n = 3,
1405 1407 .src_components_n = { .src_components_n = {
1406 1,1,1
1408 -1,1,1
1407 1409 }, },
1408 1410 .has_dest = true, .has_dest = true,
1409 1411 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_umin = {
1416 1418 .name = "ssbo_atomic_umin", .name = "ssbo_atomic_umin",
1417 1419 .srcs_n = 3, .srcs_n = 3,
1418 1420 .src_components_n = { .src_components_n = {
1419 1,1,1
1421 -1,1,1
1420 1422 }, },
1421 1423 .has_dest = true, .has_dest = true,
1422 1424 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_xor = {
1429 1431 .name = "ssbo_atomic_xor", .name = "ssbo_atomic_xor",
1430 1432 .srcs_n = 3, .srcs_n = 3,
1431 1433 .src_components_n = { .src_components_n = {
1432 1,1,1
1434 -1,1,1
1433 1435 }, },
1434 1436 .has_dest = true, .has_dest = true,
1435 1437 .dest_components_n = 1, .dest_components_n = 1,
 
... ... struct nir_intrinsic nir_ssbo_atomic_xor = {
1438 1440 [NIR_INTRINSIC_IDX_ACCESS] = 1 [NIR_INTRINSIC_IDX_ACCESS] = 1
1439 1441 } }
1440 1442 }; };
1443 /* ssbo atomic -- end */
1444 /******************************************************************************/
1441 1445 struct nir_intrinsic nir_store_deref = { struct nir_intrinsic nir_store_deref = {
1442 1446 .name = "store_deref", .name = "store_deref",
1443 1447 .srcs_n = 2, .srcs_n = 2,
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/load.c changed (mode: 100644) (index 14c370e..a91b4d0)
... ... struct nir_intrinsic nir_load_ubo = {
40 40 .name = "load_ubo", .name = "load_ubo",
41 41 .srcs_n = 2, .srcs_n = 2,
42 42 .src_components_n = { .src_components_n = {
43 1,1
43 -1,1
44 44 }, },
45 45 .has_dest = true, .has_dest = true,
46 46 .idxs_n = 3, .idxs_n = 3,
 
... ... struct nir_intrinsic nir_load_ssbo = {
118 118 .name = "load_ssbo", .name = "load_ssbo",
119 119 .srcs_n = 2, .srcs_n = 2,
120 120 .src_components_n = { .src_components_n = {
121 1,1
121 -1,1
122 122 }, },
123 123 .has_dest = true, .has_dest = true,
124 124 .idxs_n = 3, .idxs_n = 3,
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/store.c changed (mode: 100644) (index ea645b9..5f98be9)
... ... struct nir_intrinsic nir_store_ssbo = {
38 38 .name = "store_ssbo", .name = "store_ssbo",
39 39 .srcs_n = 3, .srcs_n = 3,
40 40 .src_components_n = { .src_components_n = {
41 0,1,1
41 0,-1,1
42 42 }, },
43 43 .idxs_n = 4, .idxs_n = 4,
44 44 .idxs_map = { .idxs_map = {
 
... ... struct nir_intrinsic nir_store_raw_output_pan = {
119 119 0 0
120 120 } }
121 121 }; };
122 struct nir_intrinsic nir_store_combined_output_pan = {
123 .name = "store_combined_output_pan",
124 .srcs_n = 4,
125 .src_components_n = {
126 0,1,1,1
127 },
128 .idxs_n = 2,
129 .idxs_map = {
130 [NIR_INTRINSIC_IDX_BASE] = 1,
131 [NIR_INTRINSIC_IDX_COMPONENT] = 2
132 }
133 };
122 134 struct nir_intrinsic nir_store_zs_output_pan = { struct nir_intrinsic nir_store_zs_output_pan = {
123 135 .name = "store_zs_output_pan", .name = "store_zs_output_pan",
124 136 .srcs_n = 1, .srcs_n = 1,
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/system_values.c changed (mode: 100644) (index bb96237..ab47b77)
... ... static struct nir_intrinsic nir_load_work_dim = {
366 366 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER, .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
367 367 .system_value = true .system_value = true
368 368 }; };
369 static struct nir_intrinsic nir_load_line_coord = {
370 .name = "load_line_coord",
371 .has_dest = true,
372 .dest_components_n = 1,
373 .bit_szs = 0x20,
374 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
375 .system_value = true
376 };
377 static struct nir_intrinsic nir_load_line_width = {
378 .name = "load_line_width",
379 .has_dest = true,
380 .dest_components_n = 1,
381 .bit_szs = 0x20,
382 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
383 .system_value = true
384 };
385 static struct nir_intrinsic nir_load_aa_line_width = {
386 .name = "aa_load_line_width",
387 .has_dest = true,
388 .dest_components_n = 1,
389 .bit_szs = 0x20,
390 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
391 .system_value = true
392 };
369 393 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
370 394 /* /*
371 395 * Driver-specific viewport scale/offset parameters. * Driver-specific viewport scale/offset parameters.
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/ir3.c changed (mode: 100644) (index c35b6b5..fcd16d1)
11 11 * The float versions are not handled because those are not supported * The float versions are not handled because those are not supported
12 12 * by the backend. * by the backend.
13 13 */ */
14 struct nir_intrinsic nir_store_ssbo_ir3 = {
15 .name = "store_ssbo_ir3",
16 .srcs_n = 4,
17 .src_components_n = {
18 0,1,1,1
19 },
20 .idxs_n = 4,
21 .idxs_map = {
22 [NIR_INTRINSIC_IDX_WRMASK] = 1,
23 [NIR_INTRINSIC_IDX_ACCESS] = 2,
24 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
25 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
26 }
27 };
28 struct nir_intrinsic nir_load_ssbo_ir3 = {
29 .name = "load_ssbo_ir3",
30 .srcs_n = 3,
31 .src_components_n = {
32 1,1,1
33 },
34 .has_dest = true,
35 .idxs_n = 3,
36 .idxs_map = {
37 [NIR_INTRINSIC_IDX_ACCESS] = 1,
38 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
39 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
40 },
41 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
42 };
43 14 struct nir_intrinsic nir_ssbo_atomic_add_ir3 = { struct nir_intrinsic nir_ssbo_atomic_add_ir3 = {
44 15 .name = "ssbo_atomic_add_ir3", .name = "ssbo_atomic_add_ir3",
45 16 .srcs_n = 4, .srcs_n = 4,
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/load.c changed (mode: 100644) (index 9372618..5f58f48)
... ... struct nir_intrinsic nir_load_shared_ir3 = {
17 17 }, },
18 18 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
19 19 }; };
20 struct nir_intrinsic nir_load_ssbo_ir3 = {
21 .name = "load_ssbo_ir3",
22 .srcs_n = 3,
23 .src_components_n = {
24 1,1,1
25 },
26 .has_dest = true,
27 .idxs_n = 3,
28 .idxs_map = {
29 [NIR_INTRINSIC_IDX_ACCESS] = 1,
30 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
31 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
32 },
33 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
34 };
20 35 /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
21 36 /* /*
22 37 * IR3-specific load/store global intrinsics. They take a 64-bit base address * IR3-specific load/store global intrinsics. They take a 64-bit base address
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/ir3/store.c changed (mode: 100644) (index d716067..d5307e2)
... ... struct nir_intrinsic nir_store_shared_ir3 = {
16 16 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
17 17 } }
18 18 }; };
19 struct nir_intrinsic nir_store_ssbo_ir3 = {
20 .name = "store_ssbo_ir3",
21 .srcs_n = 4,
22 .src_components_n = {
23 0,1,1,1
24 },
25 .idxs_n = 4,
26 .idxs_map = {
27 [NIR_INTRINSIC_IDX_WRMASK] = 1,
28 [NIR_INTRINSIC_IDX_ACCESS] = 2,
29 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
30 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
31 }
32 };
19 33 /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
20 34 /* /*
21 35 * IR3-specific load/store global intrinsics. They take a 64-bit base address * IR3-specific load/store global intrinsics. They take a 64-bit base address
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index f3dff1f..0d4e3af)
... ... struct nir_intrinsic *nir_intrinsics[] = {
287 287 &nir_load_view_index, &nir_load_view_index,
288 288 &nir_load_vulkan_descriptor, &nir_load_vulkan_descriptor,
289 289 &nir_load_work_dim, &nir_load_work_dim,
290 &nir_load_line_coord,
291 &nir_load_line_width,
292 &nir_load_aa_line_width,
290 293 &nir_load_work_group_id, &nir_load_work_group_id,
291 294 &nir_memory_barrier, &nir_memory_barrier,
292 295 &nir_memory_barrier_atomic_counter, &nir_memory_barrier_atomic_counter,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
395 398 &nir_demote, &nir_demote,
396 399 &nir_is_helper_invocation, &nir_is_helper_invocation,
397 400 &nir_store_raw_output_pan, &nir_store_raw_output_pan,
401 &nir_store_combined_output_pan,
398 402 &nir_load_raw_output_pan, &nir_load_raw_output_pan,
399 403 &nir_load_tlb_color_v3d, &nir_load_tlb_color_v3d,
400 404 &nir_load_point_coord, &nir_load_point_coord,
File builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index 6f5b3f6..0c4e6eb)
... ... $ar $build_dir/libvulkan_util.a \
680 680 # wsi x11 (wsi Window System Interface?) # wsi x11 (wsi Window System Interface?)
681 681 cppflags="\ cppflags="\
682 682 $cppflags_common \ $cppflags_common \
683 -I$build_dir \
683 684 -I$src_dir/src \ -I$src_dir/src \
684 685 -I$src_dir/src/vulkan/util \ -I$src_dir/src/vulkan/util \
685 686 -I$src_dir/include \ -I$src_dir/include \
 
... ... $src_dir/src/compiler/nir/nir_lower_bool_to_bitsize.c \
1063 1064 $src_dir/src/compiler/nir/nir_lower_clamp_color_outputs.c \ $src_dir/src/compiler/nir/nir_lower_clamp_color_outputs.c \
1064 1065 $src_dir/src/compiler/nir/nir_lower_clip.c \ $src_dir/src/compiler/nir/nir_lower_clip.c \
1065 1066 $src_dir/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c \ $src_dir/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c \
1067 $src_dir/src/compiler/nir/nir_lower_clip_disable.c \
1066 1068 $src_dir/src/compiler/nir/nir_lower_discard_to_demote.c \ $src_dir/src/compiler/nir/nir_lower_discard_to_demote.c \
1067 1069 $src_dir/src/compiler/nir/nir_lower_double_ops.c \ $src_dir/src/compiler/nir/nir_lower_double_ops.c \
1068 1070 $src_dir/src/compiler/nir/nir_lower_drawpixels.c \ $src_dir/src/compiler/nir/nir_lower_drawpixels.c \
1069 1071 $src_dir/src/compiler/nir/nir_lower_fb_read.c \ $src_dir/src/compiler/nir/nir_lower_fb_read.c \
1070 1072 $src_dir/src/compiler/nir/nir_lower_flatshade.c \ $src_dir/src/compiler/nir/nir_lower_flatshade.c \
1071 1073 $src_dir/src/compiler/nir/nir_lower_flrp.c \ $src_dir/src/compiler/nir/nir_lower_flrp.c \
1074 $src_dir/src/compiler/nir/nir_lower_fragcolor.c \
1072 1075 $src_dir/src/compiler/nir/nir_lower_fragcoord_wtrans.c \ $src_dir/src/compiler/nir/nir_lower_fragcoord_wtrans.c \
1073 1076 $src_dir/src/compiler/nir/nir_lower_frexp.c \ $src_dir/src/compiler/nir/nir_lower_frexp.c \
1074 1077 $src_dir/src/compiler/nir/nir_lower_global_vars_to_local.c \ $src_dir/src/compiler/nir/nir_lower_global_vars_to_local.c \
File builders/xserver-0/builder.sh changed (mode: 100644) (index fafd73c..a674688)
1 git_commit=fc4f248544f207ffd68303da22ea1e27beb3729f
1 git_commit=ea47af87f692b291a988834c6f14d73a08cb1d75
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/xserver/builder.sh . $nyan_root/builders/xserver/builder.sh
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/nyanlinux

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/nyanlinux

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main