sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
gfx stack update 6d88b857b58746eeba42ecd80783a86b83c80873 Sylvain BERTRAND 2019-04-22 00:32:26
gfx stack update f15d969566f9086bafde3a4bc93002f4754c8cb9 Sylvain BERTRAND 2019-04-15 00:54:25
gfx stack update f8462abf96c574e11aaaa205501762d8ef992fe5 Sylvain BERTRAND 2019-04-07 18:13:09
st update 621f819d99cae6702c030260cfdb6c2149d2fe7c Sylvain BERTRAND 2019-03-31 20:46:30
gfx stack update b1170f07df68214631cf8ae3f5de7f89b01c3cd5 Sylvain BERTRAND 2019-03-31 19:35:24
gfx stack update 9495f93d2bcbca9e9022ef59d52a786a33df057c Sylvain BERTRAND 2019-03-26 20:04:36
fix corner case of coarse hls streamer ae91638afc50c36168f33ac9ba2adb41674d8609 Sylvain BERTRAND 2019-03-22 00:20:16
coarse shell based hls streamer e947b82ed648cd494b51a8932d10e5b8299c273a Sylvain BERTRAND 2019-03-21 21:53:17
gfx stack update 552c8c60c92b1dbfb4c37ec1f957436395a6055e Sylvain BERTRAND 2019-03-17 20:09:29
gfx stack update 6f475db9d1b456e3c45e318cb9e0aeed3201bbb0 Sylvain BERTRAND 2019-03-10 22:32:05
mouse configurator rival110 2e3dd8db64049fdf37695d9ac0c06417330aa249 Sylvain BERTRAND 2019-03-05 21:12:39
mesa vulkan, deprecate some old code generators 43834baf73a9f533a4431bf4eb97475330e92ca9 Sylvain BERTRAND 2019-03-03 22:50:51
gfx stack update df10ca787938876d174aa2eb41b92e239db04005 Sylvain BERTRAND 2019-03-03 14:46:42
fvwm, add some layer control 53847e6fc401bd894282fb5198c32bb3b9476f21 Sylvain BERTRAND 2019-02-23 18:21:32
mesa vulkan, deprecate an old code generator e7ccf1a1b7a0110ea6eee49a40d013a4772d9b3f Sylvain BERTRAND 2019-02-21 22:01:15
gfx stack update bc7d71ed215fc30652d43473410419b9cc1eeae2 Sylvain BERTRAND 2019-02-17 17:58:29
fvwm add noborder for steam wm_class a7e20b76b3f9a7086146a3d54a5546fcb52a329d Sylvain BERTRAND 2019-02-17 17:56:53
xprop addition 5844da71a842f6b270be1aa370311b4e4980debc Sylvain BERTRAND 2019-02-17 17:33:28
csgo fvwm conf 8711d86672830dc1ae6c3cb5ce6f4bf56fde3109 Sylvain BERTRAND 2019-02-15 00:03:55
fix lynx patch 6f3d57b58b38669a9f3cb9d09ea14e275048279b Sylvain BERTRAND 2019-02-12 12:22:12
Commit 6d88b857b58746eeba42ecd80783a86b83c80873 - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2019-04-22 00:32
Committer name: Sylvain BERTRAND
Committer date (UTC): 2019-04-22 00:32
Parent(s): f15d969566f9086bafde3a4bc93002f4754c8cb9
Signer:
Signing key:
Signing status: N
Tree: 4698493b4020ba352130ee576759ae0504f0af91
File Lines added Lines deleted
builders/drm-1/builder.sh 1 1
builders/ffmpeg-1/builder.sh 1 1
builders/llvm-0/builder.sh 1 1
builders/mesa-gl-1/builder.sh 1 1
builders/mesa-gl-1/contrib/compiler_glsl.sh 1 0
builders/mesa-gl-1/contrib/compiler_nir.sh 2 1
builders/mesa-vulkan-1/builder.sh 1 1
builders/mesa-vulkan-1/contrib/generators/nir/nir_database.c 4 6330
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_alu.c 2965 0
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c 3444 0
builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 3 1
builders/mplayer-0/builder.sh 2 2
builders/xserver-0/builder.sh 1 1
File builders/drm-1/builder.sh changed (mode: 100644) (index 4a397a7..5102aa8)
1 1 src_name=drm src_name=drm
2 git_commit=4735ca71af9f741e2438104d543dc3c5a8107f35
2 git_commit=be3b07617fc999e366e8185dbc7851ae5943df27
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/ffmpeg-1/builder.sh changed (mode: 100644) (index ed3f867..525c1e4)
1 1 src_name=ffmpeg src_name=ffmpeg
2 git_commit=4c8e3725d9ffe4baa5b5e3adec06aa2e68a89455
2 git_commit=6e0488cac43130124e17722c589f1b5c9f4fe3f6
3 3 git_url0=https://git.ffmpeg.org/$src_name.git git_url0=https://git.ffmpeg.org/$src_name.git
4 4
5 5 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
File builders/llvm-0/builder.sh changed (mode: 100644) (index 94ba219..11fafdf)
1 1 src_name=llvm src_name=llvm
2 git_commit=e0a373b55706246ce1e3e75c92486689ab13ef3b
2 git_commit=cc532a593e04874bcada3fa45a6db893f2606800
3 3 git_url0=http://llvm.org/git/llvm.git git_url0=http://llvm.org/git/llvm.git
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/mesa-gl-1/builder.sh changed (mode: 100644) (index 5c8de07..3252e9a)
1 1 src_name=mesa src_name=mesa
2 git_commit=10a2fdacfa3f96a57fec304cf54d1c298e4f0943
2 git_commit=a6ccc4c0c893cfd978068f1d75ad0e001182b381
3 3 git_url0=git://anongit.freedesktop.org/mesa/$pkg_name git_url0=git://anongit.freedesktop.org/mesa/$pkg_name
4 4
5 5 slot=1 slot=1
File builders/mesa-gl-1/contrib/compiler_glsl.sh changed (mode: 100644) (index cd41962..fec9eac)
... ... wait
79 79
80 80 libglsl_c_files="\ libglsl_c_files="\
81 81 $src_dir/src/compiler/glsl/gl_nir_lower_atomics.c \ $src_dir/src/compiler/glsl/gl_nir_lower_atomics.c \
82 $src_dir/src/compiler/glsl/gl_nir_lower_bindless_images.c \
82 83 $src_dir/src/compiler/glsl/gl_nir_lower_buffers.c \ $src_dir/src/compiler/glsl/gl_nir_lower_buffers.c \
83 84 $src_dir/src/compiler/glsl/gl_nir_lower_samplers.c \ $src_dir/src/compiler/glsl/gl_nir_lower_samplers.c \
84 85 $src_dir/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c \ $src_dir/src/compiler/glsl/gl_nir_lower_samplers_as_deref.c \
File builders/mesa-gl-1/contrib/compiler_nir.sh changed (mode: 100644) (index 4b8ebff..39f2017)
... ... $src_dir/src/compiler/nir/nir_lower_patch_vertices.c \
84 84 $src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \ $src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \
85 85 $src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \ $src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \
86 86 $src_dir/src/compiler/nir/nir_lower_returns.c \ $src_dir/src/compiler/nir/nir_lower_returns.c \
87 $src_dir/src/compiler/nir/nir_lower_scratch.c \
87 88 $src_dir/src/compiler/nir/nir_lower_subgroups.c \ $src_dir/src/compiler/nir/nir_lower_subgroups.c \
88 89 $src_dir/src/compiler/nir/nir_lower_system_values.c \ $src_dir/src/compiler/nir/nir_lower_system_values.c \
89 90 $src_dir/src/compiler/nir/nir_lower_tex.c \ $src_dir/src/compiler/nir/nir_lower_tex.c \
 
... ... $src_dir/src/compiler/nir/nir_lower_two_sided_color.c \
92 93 $src_dir/src/compiler/nir/nir_lower_vars_to_ssa.c \ $src_dir/src/compiler/nir/nir_lower_vars_to_ssa.c \
93 94 $src_dir/src/compiler/nir/nir_lower_var_copies.c \ $src_dir/src/compiler/nir/nir_lower_var_copies.c \
94 95 $src_dir/src/compiler/nir/nir_lower_vec_to_movs.c \ $src_dir/src/compiler/nir/nir_lower_vec_to_movs.c \
96 $src_dir/src/compiler/nir/nir_lower_viewport_transform.c \
95 97 $src_dir/src/compiler/nir/nir_lower_wpos_center.c \ $src_dir/src/compiler/nir/nir_lower_wpos_center.c \
96 98 $src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \ $src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \
97 99 $src_dir/src/compiler/nir/nir_lower_bit_size.c \ $src_dir/src/compiler/nir/nir_lower_bit_size.c \
 
... ... $src_dir/src/compiler/nir/nir_opt_dead_cf.c \
111 113 $src_dir/src/compiler/nir/nir_opt_dead_write_vars.c \ $src_dir/src/compiler/nir/nir_opt_dead_write_vars.c \
112 114 $src_dir/src/compiler/nir/nir_opt_find_array_copies.c \ $src_dir/src/compiler/nir/nir_opt_find_array_copies.c \
113 115 $src_dir/src/compiler/nir/nir_opt_gcm.c \ $src_dir/src/compiler/nir/nir_opt_gcm.c \
114 $src_dir/src/compiler/nir/nir_opt_global_to_local.c \
115 116 $src_dir/src/compiler/nir/nir_opt_idiv_const.c \ $src_dir/src/compiler/nir/nir_opt_idiv_const.c \
116 117 $src_dir/src/compiler/nir/nir_opt_if.c \ $src_dir/src/compiler/nir/nir_opt_if.c \
117 118 $src_dir/src/compiler/nir/nir_opt_intrinsics.c \ $src_dir/src/compiler/nir/nir_opt_intrinsics.c \
File builders/mesa-vulkan-1/builder.sh changed (mode: 100644) (index b31443d..c47f57d)
1 1 src_name=mesa src_name=mesa
2 git_commit=10a2fdacfa3f96a57fec304cf54d1c298e4f0943
2 git_commit=a6ccc4c0c893cfd978068f1d75ad0e001182b381
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 slot=1 slot=1
The diff for file builders/mesa-vulkan-1/contrib/generators/nir/nir_database.c is too big (6334 changes) and cannot be shown.
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_alu.c added (mode: 100644) (index 0000000..7fda1f5)
1 /*
2 * instead of starting top->bottom from the old generators, work
3 * bottom->top to re-construction the nir ops families, if ever...
4 */
5 #define NIR_TYPE_BOOL 1
6 #define NIR_TYPE_BOOL1 2
7 #define NIR_TYPE_BOOL32 3
8 #define NIR_TYPE_INT 4
9 #define NIR_TYPE_INT1 5
10 #define NIR_TYPE_INT8 6
11 #define NIR_TYPE_INT16 7
12 #define NIR_TYPE_INT32 8
13 #define NIR_TYPE_INT64 9
14 #define NIR_TYPE_UINT 10
15 #define NIR_TYPE_UINT1 11
16 #define NIR_TYPE_UINT8 12
17 #define NIR_TYPE_UINT16 13
18 #define NIR_TYPE_UINT32 14
19 #define NIR_TYPE_UINT64 15
20 #define NIR_TYPE_FLOAT 16
21 #define NIR_TYPE_FLOAT16 17
22 #define NIR_TYPE_FLOAT32 18
23 #define NIR_TYPE_FLOAT64 19
24
25 #define NIR_OP_TYPE_UNDEFINED 0
26 /* XXX: current database factorization makes the following useless */
27 #define NIR_OP_TYPE_ALU 1
28
29 #define NIR_OP_INPUTS_N_MAX 4
30 #define NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE 0x01
31 #define NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE 0x02
32 struct nir_op {
33 char *name;
34 u8 type;
35
36 u8 output_sz;
37 u8 output_type;
38
39 u8 inputs_n;
40 u8 inputs_szs[NIR_OP_INPUTS_N_MAX];
41 u8 inputs_types[NIR_OP_INPUTS_N_MAX];
42
43 u8 algebraic_properties;
44 };
45
46 static struct nir_op nir_b2f16 = {
47 "b2f16",
48 NIR_OP_TYPE_ALU,
49 0,
50 NIR_TYPE_FLOAT16,
51 1,
52 {0},
53 {NIR_TYPE_BOOL},
54 0
55 };
56 static struct nir_op nir_b2f32 = {
57 "b2f32",
58 NIR_OP_TYPE_ALU,
59 0,
60 NIR_TYPE_FLOAT32,
61 1,
62 {0},
63 {NIR_TYPE_BOOL},
64 0
65 };
66 static struct nir_op nir_b2f64 = {
67 "b2f64",
68 NIR_OP_TYPE_ALU,
69 0,
70 NIR_TYPE_FLOAT64,
71 1,
72 {0},
73 {NIR_TYPE_BOOL},
74 0
75 };
76 static struct nir_op nir_b2i1 = {
77 "b2i1",
78 NIR_OP_TYPE_ALU,
79 0,
80 NIR_TYPE_INT1,
81 1,
82 {0},
83 {NIR_TYPE_BOOL},
84 0
85 };
86 static struct nir_op nir_b2i16 = {
87 "b2i16",
88 NIR_OP_TYPE_ALU,
89 0,
90 NIR_TYPE_INT16,
91 1,
92 {0},
93 {NIR_TYPE_BOOL},
94 0
95 };
96 static struct nir_op nir_b2i32 = {
97 "b2i32",
98 NIR_OP_TYPE_ALU,
99 0,
100 NIR_TYPE_INT32,
101 1,
102 {0},
103 {NIR_TYPE_BOOL},
104 0
105 };
106 static struct nir_op nir_b2i64 = {
107 "b2i64",
108 NIR_OP_TYPE_ALU,
109 0,
110 NIR_TYPE_INT64,
111 1,
112 {0},
113 {NIR_TYPE_BOOL},
114 0
115 };
116 static struct nir_op nir_b2i8 = {
117 "b2i8",
118 NIR_OP_TYPE_ALU,
119 0,
120 NIR_TYPE_INT8,
121 1,
122 {0},
123 {NIR_TYPE_BOOL},
124 0
125 };
126 static struct nir_op nir_b32all_fequal2 = {
127 "b32all_fequal2",
128 NIR_OP_TYPE_ALU,
129 1,
130 NIR_TYPE_BOOL32,
131 2,
132 {2,2},
133 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
134 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
135 };
136 static struct nir_op nir_b32all_fequal3 = {
137 "b32all_fequal3",
138 NIR_OP_TYPE_ALU,
139 1,
140 NIR_TYPE_BOOL32,
141 2,
142 {3,3},
143 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
144 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
145 };
146 static struct nir_op nir_b32all_fequal4 = {
147 "b32all_fequal4",
148 NIR_OP_TYPE_ALU,
149 1,
150 NIR_TYPE_BOOL32,
151 2,
152 {4,4},
153 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
154 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
155 };
156 static struct nir_op nir_b32all_iequal2 = {
157 "b32all_iequal2",
158 NIR_OP_TYPE_ALU,
159 1,
160 NIR_TYPE_BOOL32,
161 2,
162 {2,2},
163 {NIR_TYPE_INT,NIR_TYPE_INT},
164 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
165 };
166 static struct nir_op nir_b32all_iequal3 = {
167 "b32all_iequal3",
168 NIR_OP_TYPE_ALU,
169 1,
170 NIR_TYPE_BOOL32,
171 2,
172 {3,3},
173 {NIR_TYPE_INT,NIR_TYPE_INT},
174 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
175 };
176 static struct nir_op nir_b32all_iequal4 = {
177 "b32all_iequal4",
178 NIR_OP_TYPE_ALU,
179 1,
180 NIR_TYPE_BOOL32,
181 2,
182 {4,4},
183 {NIR_TYPE_INT,NIR_TYPE_INT},
184 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
185 };
186 static struct nir_op nir_b32any_fnequal2 = {
187 "b32any_fnequal2",
188 NIR_OP_TYPE_ALU,
189 1,
190 NIR_TYPE_BOOL32,
191 2,
192 {2,2},
193 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
194 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
195 };
196 static struct nir_op nir_b32any_fnequal3 = {
197 "b32any_fnequal3",
198 NIR_OP_TYPE_ALU,
199 1,
200 NIR_TYPE_BOOL32,
201 2,
202 {3,3},
203 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
204 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
205 };
206 static struct nir_op nir_b32any_fnequal4 = {
207 "b32any_fnequal4",
208 NIR_OP_TYPE_ALU,
209 1,
210 NIR_TYPE_BOOL32,
211 2,
212 {4,4},
213 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
214 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
215 };
216 static struct nir_op nir_b32any_inequal2 = {
217 "b32any_inequal2",
218 NIR_OP_TYPE_ALU,
219 1,
220 NIR_TYPE_BOOL32,
221 2,
222 {2,2},
223 {NIR_TYPE_INT,NIR_TYPE_INT},
224 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
225 };
226 static struct nir_op nir_b32any_inequal3 = {
227 "b32any_inequal3",
228 NIR_OP_TYPE_ALU,
229 1,
230 NIR_TYPE_BOOL32,
231 2,
232 {3,3},
233 {NIR_TYPE_INT,NIR_TYPE_INT},
234 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
235 };
236 static struct nir_op nir_b32any_inequal4 = {
237 "b32any_inequal4",
238 NIR_OP_TYPE_ALU,
239 1,
240 NIR_TYPE_BOOL32,
241 2,
242 {4,4},
243 {NIR_TYPE_INT,NIR_TYPE_INT},
244 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
245 };
246 static struct nir_op nir_b32csel = {
247 "b32csel",
248 NIR_OP_TYPE_ALU,
249 0,
250 NIR_TYPE_UINT,
251 3,
252 {0,0,0},
253 {NIR_TYPE_BOOL32,NIR_TYPE_UINT,NIR_TYPE_UINT},
254 0
255 };
256 static struct nir_op nir_ball_fequal2 = {
257 "ball_fequal2",
258 NIR_OP_TYPE_ALU,
259 1,
260 NIR_TYPE_BOOL1,
261 2,
262 {2,2},
263 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
264 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
265 };
266 static struct nir_op nir_ball_fequal3 = {
267 "ball_fequal3",
268 NIR_OP_TYPE_ALU,
269 1,
270 NIR_TYPE_BOOL1,
271 2,
272 {3,3},
273 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
274 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
275 };
276 static struct nir_op nir_ball_fequal4 = {
277 "ball_fequal4",
278 NIR_OP_TYPE_ALU,
279 1,
280 NIR_TYPE_BOOL1,
281 2,
282 {4,4},
283 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
284 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
285 };
286 static struct nir_op nir_ball_iequal2 = {
287 "ball_iequal2",
288 NIR_OP_TYPE_ALU,
289 1,
290 NIR_TYPE_BOOL1,
291 2,
292 {2,2},
293 {NIR_TYPE_INT,NIR_TYPE_INT},
294 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
295 };
296 static struct nir_op nir_ball_iequal3 = {
297 "ball_iequal3",
298 NIR_OP_TYPE_ALU,
299 1,
300 NIR_TYPE_BOOL1,
301 2,
302 {3,3},
303 {NIR_TYPE_INT,NIR_TYPE_INT},
304 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
305 };
306 static struct nir_op nir_ball_iequal4 = {
307 "ball_iequal4",
308 NIR_OP_TYPE_ALU,
309 1,
310 NIR_TYPE_BOOL1,
311 2,
312 {4,4},
313 {NIR_TYPE_INT,NIR_TYPE_INT},
314 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
315 };
316 static struct nir_op nir_bany_fnequal2 = {
317 "bany_fnequal2",
318 NIR_OP_TYPE_ALU,
319 1,
320 NIR_TYPE_BOOL1,
321 2,
322 {2,2},
323 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
324 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
325 };
326 static struct nir_op nir_bany_fnequal3 = {
327 "bany_fnequal3",
328 NIR_OP_TYPE_ALU,
329 1,
330 NIR_TYPE_BOOL1,
331 2,
332 {3,3},
333 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
334 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
335 };
336 static struct nir_op nir_bany_fnequal4 = {
337 "bany_fnequal4",
338 NIR_OP_TYPE_ALU,
339 1,
340 NIR_TYPE_BOOL1,
341 2,
342 {4,4},
343 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
344 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
345 };
346 static struct nir_op nir_bany_inequal2 = {
347 "bany_inequal2",
348 NIR_OP_TYPE_ALU,
349 1,
350 NIR_TYPE_BOOL1,
351 2,
352 {2,2},
353 {NIR_TYPE_INT,NIR_TYPE_INT},
354 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
355 };
356 static struct nir_op nir_bany_inequal3 = {
357 "bany_inequal3",
358 NIR_OP_TYPE_ALU,
359 1,
360 NIR_TYPE_BOOL1,
361 2,
362 {3,3},
363 {NIR_TYPE_INT,NIR_TYPE_INT},
364 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
365 };
366 static struct nir_op nir_bany_inequal4 = {
367 "bany_inequal4",
368 NIR_OP_TYPE_ALU,
369 1,
370 NIR_TYPE_BOOL1,
371 2,
372 {4,4},
373 {NIR_TYPE_INT,NIR_TYPE_INT},
374 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
375 };
376 static struct nir_op nir_bcsel = {
377 "bcsel",
378 NIR_OP_TYPE_ALU,
379 0,
380 NIR_TYPE_UINT,
381 3,
382 {0,0,0},
383 {NIR_TYPE_BOOL1,NIR_TYPE_UINT,NIR_TYPE_UINT32},
384 0
385 };
386 static struct nir_op nir_bfi = {
387 "bfi",
388 NIR_OP_TYPE_ALU,
389 0,
390 NIR_TYPE_UINT32,
391 3,
392 {0,0,0},
393 {NIR_TYPE_UINT32,NIR_TYPE_UINT32,NIR_TYPE_UINT32},
394 0
395 };
396 static struct nir_op nir_bfm = {
397 "bfm",
398 NIR_OP_TYPE_ALU,
399 0,
400 NIR_TYPE_UINT32,
401 2,
402 {0,0},
403 {NIR_TYPE_INT32,NIR_TYPE_INT32},
404 0
405 };
406 static struct nir_op nir_bit_count = {
407 "bit_count",
408 NIR_OP_TYPE_ALU,
409 0,
410 NIR_TYPE_UINT32,
411 1,
412 {0},
413 {NIR_TYPE_INT},
414 0
415 };
416 static struct nir_op nir_bitfield_insert = {
417 "bitfield_insert",
418 NIR_OP_TYPE_ALU,
419 0,
420 NIR_TYPE_UINT32,
421 4,
422 {0,0,0,0},
423 {NIR_TYPE_UINT32,NIR_TYPE_UINT32,NIR_TYPE_UINT32,NIR_TYPE_UINT32},
424 0
425 };
426 static struct nir_op nir_bitfield_reverse = {
427 "bitfield_reverse",
428 NIR_OP_TYPE_ALU,
429 0,
430 NIR_TYPE_UINT32,
431 1,
432 {0},
433 {NIR_TYPE_UINT32},
434 0
435 };
436 static struct nir_op nir_cube_face_coord = {
437 "cube_face_coord",
438 NIR_OP_TYPE_ALU,
439 2,
440 NIR_TYPE_FLOAT32,
441 1,
442 {3},
443 {NIR_TYPE_FLOAT32},
444 0
445 };
446 static struct nir_op nir_cube_face_index = {
447 "cube_face_index",
448 NIR_OP_TYPE_ALU,
449 1,
450 NIR_TYPE_FLOAT32,
451 1,
452 {3},
453 {NIR_TYPE_FLOAT32},
454 0
455 };
456 static struct nir_op nir_extract_i16 = {
457 "extract_i16",
458 NIR_OP_TYPE_ALU,
459 0,
460 NIR_TYPE_INT,
461 2,
462 {0,0},
463 {NIR_TYPE_INT,NIR_TYPE_INT},
464 0
465 };
466 static struct nir_op nir_extract_i8 = {
467 "extract_i8",
468 NIR_OP_TYPE_ALU,
469 0,
470 NIR_TYPE_INT,
471 2,
472 {0,0},
473 {NIR_TYPE_INT,NIR_TYPE_INT},
474 0
475 };
476 static struct nir_op nir_extract_u16 = {
477 "extract_u16",
478 NIR_OP_TYPE_ALU,
479 0,
480 NIR_TYPE_UINT,
481 2,
482 {0,0},
483 {NIR_TYPE_UINT,NIR_TYPE_UINT},
484 0
485 };
486 static struct nir_op nir_extract_u8 = {
487 "extract_u8",
488 NIR_OP_TYPE_ALU,
489 0,
490 NIR_TYPE_UINT,
491 2,
492 {0,0},
493 {NIR_TYPE_UINT,NIR_TYPE_UINT},
494 0
495 };
496 static struct nir_op nir_f2b1 = {
497 "f2b1",
498 NIR_OP_TYPE_ALU,
499 0,
500 NIR_TYPE_BOOL1,
501 1,
502 {0},
503 {NIR_TYPE_FLOAT},
504 0
505 };
506 static struct nir_op nir_f2b32 = {
507 "f2b32",
508 NIR_OP_TYPE_ALU,
509 0,
510 NIR_TYPE_BOOL32,
511 1,
512 {0},
513 {NIR_TYPE_FLOAT},
514 0
515 };
516 static struct nir_op nir_f2f16 = {
517 "f2f16",
518 NIR_OP_TYPE_ALU,
519 0,
520 NIR_TYPE_FLOAT16,
521 1,
522 {0},
523 {NIR_TYPE_FLOAT},
524 0
525 };
526 static struct nir_op nir_f2f16_rtne = {
527 "f2f16_rtne",
528 NIR_OP_TYPE_ALU,
529 0,
530 NIR_TYPE_FLOAT16,
531 1,
532 {0},
533 {NIR_TYPE_FLOAT},
534 0
535 };
536 static struct nir_op nir_f2f16_rtz = {
537 "f2f16_rtz",
538 NIR_OP_TYPE_ALU,
539 0,
540 NIR_TYPE_FLOAT16,
541 1,
542 {0},
543 {NIR_TYPE_FLOAT},
544 0
545 };
546 static struct nir_op nir_f2f32 = {
547 "f2f32",
548 NIR_OP_TYPE_ALU,
549 0,
550 NIR_TYPE_FLOAT32,
551 1,
552 {0},
553 {NIR_TYPE_FLOAT},
554 0
555 };
556 static struct nir_op nir_f2f64 = {
557 "f2f64",
558 NIR_OP_TYPE_ALU,
559 0,
560 NIR_TYPE_FLOAT64,
561 1,
562 {0},
563 {NIR_TYPE_FLOAT},
564 0
565 };
566 static struct nir_op nir_f2i1 = {
567 "f2i1",
568 NIR_OP_TYPE_ALU,
569 0,
570 NIR_TYPE_INT1,
571 1,
572 {0},
573 {NIR_TYPE_FLOAT},
574 0
575 };
576 static struct nir_op nir_f2i16 = {
577 "f2i16",
578 NIR_OP_TYPE_ALU,
579 0,
580 NIR_TYPE_INT16,
581 1,
582 {0},
583 {NIR_TYPE_FLOAT},
584 0
585 };
586 static struct nir_op nir_f2i32 = {
587 "f2i32",
588 NIR_OP_TYPE_ALU,
589 0,
590 NIR_TYPE_INT32,
591 1,
592 {0},
593 {NIR_TYPE_FLOAT},
594 0
595 };
596 static struct nir_op nir_f2i64 = {
597 "f2i64",
598 NIR_OP_TYPE_ALU,
599 0,
600 NIR_TYPE_INT64,
601 1,
602 {0},
603 {NIR_TYPE_FLOAT},
604 0
605 };
606 static struct nir_op nir_f2i8 = {
607 "f2i8",
608 NIR_OP_TYPE_ALU,
609 0,
610 NIR_TYPE_INT8,
611 1,
612 {0},
613 {NIR_TYPE_FLOAT},
614 0
615 };
616 static struct nir_op nir_f2u1 = {
617 "f2u1",
618 NIR_OP_TYPE_ALU,
619 0,
620 NIR_TYPE_UINT1,
621 1,
622 {0},
623 {NIR_TYPE_FLOAT},
624 0
625 };
626 static struct nir_op nir_f2u16 = {
627 "f2u16",
628 NIR_OP_TYPE_ALU,
629 0,
630 NIR_TYPE_UINT16,
631 1,
632 {0},
633 {NIR_TYPE_FLOAT},
634 0
635 };
636 static struct nir_op nir_f2u32 = {
637 "f2u32",
638 NIR_OP_TYPE_ALU,
639 0,
640 NIR_TYPE_UINT32,
641 1,
642 {0},
643 {NIR_TYPE_FLOAT},
644 0
645 };
646 static struct nir_op nir_f2u64 = {
647 "f2u64",
648 NIR_OP_TYPE_ALU,
649 0,
650 NIR_TYPE_UINT64,
651 1,
652 {0},
653 {NIR_TYPE_FLOAT},
654 0
655 };
656 static struct nir_op nir_f2u8 = {
657 "f2u8",
658 NIR_OP_TYPE_ALU,
659 0,
660 NIR_TYPE_UINT8,
661 1,
662 {0},
663 {NIR_TYPE_FLOAT},
664 0
665 };
666 static struct nir_op nir_fabs = {
667 "fabs",
668 NIR_OP_TYPE_ALU,
669 0,
670 NIR_TYPE_FLOAT,
671 1,
672 {0},
673 {NIR_TYPE_FLOAT},
674 0
675 };
676 static struct nir_op nir_fadd = {
677 "fadd",
678 NIR_OP_TYPE_ALU,
679 0,
680 NIR_TYPE_FLOAT,
681 2,
682 {0,0},
683 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
684 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
685 };
686 static struct nir_op nir_fall_equal2 = {
687 "fall_equal2",
688 NIR_OP_TYPE_ALU,
689 1,
690 NIR_TYPE_FLOAT32,
691 2,
692 {2,2},
693 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
694 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
695 };
696 static struct nir_op nir_fall_equal3 = {
697 "fall_equal3",
698 NIR_OP_TYPE_ALU,
699 1,
700 NIR_TYPE_FLOAT32,
701 2,
702 {3,3},
703 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
704 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
705 };
706 static struct nir_op nir_fall_equal4 = {
707 "fall_equal4",
708 NIR_OP_TYPE_ALU,
709 1,
710 NIR_TYPE_FLOAT32,
711 2,
712 {4,4},
713 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
714 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
715 };
716 static struct nir_op nir_fand = {
717 "fand",
718 NIR_OP_TYPE_ALU,
719 0,
720 NIR_TYPE_FLOAT32,
721 2,
722 {0,0},
723 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
724 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
725 };
726 static struct nir_op nir_fany_nequal2 = {
727 "fany_nequal2",
728 NIR_OP_TYPE_ALU,
729 1,
730 NIR_TYPE_FLOAT32,
731 2,
732 {2,2},
733 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
734 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
735 };
736 static struct nir_op nir_fany_nequal3 = {
737 "fany_nequal3",
738 NIR_OP_TYPE_ALU,
739 1,
740 NIR_TYPE_FLOAT32,
741 2,
742 {3,3},
743 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
744 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
745 };
746 static struct nir_op nir_fany_nequal4 = {
747 "fany_nequal4",
748 NIR_OP_TYPE_ALU,
749 1,
750 NIR_TYPE_FLOAT32,
751 2,
752 {4,4},
753 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
754 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
755 };
756 static struct nir_op nir_fceil = {
757 "fceil",
758 NIR_OP_TYPE_ALU,
759 0,
760 NIR_TYPE_FLOAT,
761 1,
762 {0},
763 {NIR_TYPE_FLOAT},
764 0,
765 };
766 static struct nir_op nir_fcos = {
767 "fcos",
768 NIR_OP_TYPE_ALU,
769 0,
770 NIR_TYPE_FLOAT,
771 1,
772 {0},
773 {NIR_TYPE_FLOAT},
774 0
775 };
776 static struct nir_op nir_fcsel = {
777 "fcsel",
778 NIR_OP_TYPE_ALU,
779 0,
780 NIR_TYPE_FLOAT32,
781 3,
782 {0,0,0},
783 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
784 0
785 };
786 static struct nir_op nir_fddx = {
787 "fddx",
788 NIR_OP_TYPE_ALU,
789 0,
790 NIR_TYPE_FLOAT,
791 1,
792 {0},
793 {NIR_TYPE_FLOAT},
794 0
795 };
796 static struct nir_op nir_fddx_coarse = {
797 "fddx_coarse",
798 NIR_OP_TYPE_ALU,
799 0,
800 NIR_TYPE_FLOAT,
801 1,
802 {0},
803 {NIR_TYPE_FLOAT},
804 0
805 };
806 static struct nir_op nir_fddx_fine = {
807 "fddx_fine",
808 NIR_OP_TYPE_ALU,
809 0,
810 NIR_TYPE_FLOAT,
811 1,
812 {0},
813 {NIR_TYPE_FLOAT},
814 0
815 };
816 static struct nir_op nir_fddy = {
817 "fddy",
818 NIR_OP_TYPE_ALU,
819 0,
820 NIR_TYPE_FLOAT,
821 1,
822 {0},
823 {NIR_TYPE_FLOAT},
824 0
825 };
826 static struct nir_op nir_fddy_coarse = {
827 "fddy_coarse",
828 NIR_OP_TYPE_ALU,
829 0,
830 NIR_TYPE_FLOAT,
831 1,
832 {0},
833 {NIR_TYPE_FLOAT},
834 0
835 };
836 static struct nir_op nir_fddy_fine = {
837 "fddy_fine",
838 NIR_OP_TYPE_ALU,
839 0,
840 NIR_TYPE_FLOAT,
841 1,
842 {0},
843 {NIR_TYPE_FLOAT},
844 0
845 };
846 static struct nir_op nir_fdiv = {
847 "fdiv",
848 NIR_OP_TYPE_ALU,
849 0,
850 NIR_TYPE_FLOAT,
851 2,
852 {0,0},
853 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
854 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
855 };
856 static struct nir_op nir_fdot2 = {
857 "fdot2",
858 NIR_OP_TYPE_ALU,
859 1,
860 NIR_TYPE_FLOAT,
861 2,
862 {2,2},
863 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
864 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
865 };
866 static struct nir_op nir_fdot3 = {
867 "fdot3",
868 NIR_OP_TYPE_ALU,
869 1,
870 NIR_TYPE_FLOAT,
871 2,
872 {3,3},
873 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
874 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
875 };
876 static struct nir_op nir_fdot4 = {
877 "fdot4",
878 NIR_OP_TYPE_ALU,
879 1,
880 NIR_TYPE_FLOAT,
881 2,
882 {4,4},
883 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
884 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
885 };
886 static struct nir_op nir_fdot_replicated2 = {
887 "fdot_replicated2",
888 NIR_OP_TYPE_ALU,
889 4,
890 NIR_TYPE_FLOAT,
891 2,
892 {2,2},
893 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
894 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
895 };
896 static struct nir_op nir_fdot_replicated3 = {
897 "fdot_replicated3",
898 NIR_OP_TYPE_ALU,
899 4,
900 NIR_TYPE_FLOAT,
901 2,
902 {3,3},
903 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
904 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
905 };
906 static struct nir_op nir_fdot_replicated4 = {
907 "fdot_replicated4",
908 NIR_OP_TYPE_ALU,
909 4,
910 NIR_TYPE_FLOAT,
911 2,
912 {4,4},
913 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
914 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
915 };
916 static struct nir_op nir_fdph = {
917 "fdph",
918 NIR_OP_TYPE_ALU,
919 1,
920 NIR_TYPE_FLOAT,
921 2,
922 {3,4},
923 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
924 0
925 };
926 static struct nir_op nir_fdph_replicated = {
927 "fdph_replicated",
928 NIR_OP_TYPE_ALU,
929 4,
930 NIR_TYPE_FLOAT,
931 2,
932 {3,4},
933 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
934 0
935 };
936 static struct nir_op nir_feq = {
937 "feq",
938 NIR_OP_TYPE_ALU,
939 0,
940 NIR_TYPE_BOOL1,
941 2,
942 {0,0},
943 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
944 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
945 };
946 static struct nir_op nir_feq32 = {
947 "feq32",
948 NIR_OP_TYPE_ALU,
949 0,
950 NIR_TYPE_BOOL32,
951 2,
952 {0,0},
953 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
954 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
955 };
956 static struct nir_op nir_fexp2 = {
957 "fexp2",
958 NIR_OP_TYPE_ALU,
959 0,
960 NIR_TYPE_FLOAT,
961 1,
962 {0},
963 {NIR_TYPE_FLOAT},
964 0
965 };
966 static struct nir_op nir_ffloor = {
967 "ffloor",
968 NIR_OP_TYPE_ALU,
969 0,
970 NIR_TYPE_FLOAT,
971 1,
972 {0},
973 {NIR_TYPE_FLOAT},
974 0
975 };
976 static struct nir_op nir_ffma = {
977 "ffma",
978 NIR_OP_TYPE_ALU,
979 0,
980 NIR_TYPE_FLOAT,
981 3,
982 {0,0,0},
983 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
984 0
985 };
986 static struct nir_op nir_ffract = {
987 "ffract",
988 NIR_OP_TYPE_ALU,
989 0,
990 NIR_TYPE_FLOAT,
991 1,
992 {0},
993 {NIR_TYPE_FLOAT},
994 0
995 };
996 static struct nir_op nir_fge = {
997 "fge",
998 NIR_OP_TYPE_ALU,
999 0,
1000 NIR_TYPE_BOOL1,
1001 2,
1002 {0,0},
1003 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1004 0
1005 };
1006 static struct nir_op nir_fge32 = {
1007 "fge32",
1008 NIR_OP_TYPE_ALU,
1009 0,
1010 NIR_TYPE_BOOL32,
1011 2,
1012 {0,0},
1013 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1014 0
1015 };
1016 static struct nir_op nir_find_lsb = {
1017 "find_lsb",
1018 NIR_OP_TYPE_ALU,
1019 0,
1020 NIR_TYPE_INT32,
1021 1,
1022 {0},
1023 {NIR_TYPE_INT},
1024 0
1025 };
1026 static struct nir_op nir_flog2 = {
1027 "flog2",
1028 NIR_OP_TYPE_ALU,
1029 0,
1030 NIR_TYPE_FLOAT,
1031 1,
1032 {0},
1033 {NIR_TYPE_FLOAT},
1034 0
1035 };
1036 static struct nir_op nir_flrp = {
1037 "flrp",
1038 NIR_OP_TYPE_ALU,
1039 0,
1040 NIR_TYPE_FLOAT,
1041 3,
1042 {0,0,0},
1043 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1044 0
1045 };
1046 static struct nir_op nir_flt = {
1047 "flt",
1048 NIR_OP_TYPE_ALU,
1049 0,
1050 NIR_TYPE_BOOL1,
1051 2,
1052 {0,0},
1053 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1054 0
1055 };
1056 static struct nir_op nir_flt32 = {
1057 "flt32",
1058 NIR_OP_TYPE_ALU,
1059 0,
1060 NIR_TYPE_FLOAT,
1061 2,
1062 {0,0},
1063 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1064 0
1065 };
1066 static struct nir_op nir_fmax = {
1067 "fmax",
1068 NIR_OP_TYPE_ALU,
1069 0,
1070 NIR_TYPE_FLOAT,
1071 2,
1072 {0,0},
1073 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1074 0
1075 };
1076 static struct nir_op nir_fmax3 = {
1077 "fmax3",
1078 NIR_OP_TYPE_ALU,
1079 0,
1080 NIR_TYPE_FLOAT,
1081 3,
1082 {0,0,0},
1083 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1084 0
1085 };
1086 static struct nir_op nir_fmed3 = {
1087 "fmed3",
1088 NIR_OP_TYPE_ALU,
1089 0,
1090 NIR_TYPE_FLOAT,
1091 3,
1092 {0,0,0},
1093 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1094 0
1095 };
1096 static struct nir_op nir_fmin = {
1097 "fmin",
1098 NIR_OP_TYPE_ALU,
1099 0,
1100 NIR_TYPE_FLOAT,
1101 2,
1102 {0,0},
1103 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1104 0
1105 };
1106 static struct nir_op nir_fmin3 = {
1107 "fmin3",
1108 NIR_OP_TYPE_ALU,
1109 0,
1110 NIR_TYPE_FLOAT,
1111 3,
1112 {0,0,0},
1113 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1114 0
1115 };
1116 static struct nir_op nir_fmod = {
1117 "fmod",
1118 NIR_OP_TYPE_ALU,
1119 0,
1120 NIR_TYPE_FLOAT,
1121 2,
1122 {0,0},
1123 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1124 0
1125 };
1126 static struct nir_op nir_fmov = {
1127 "fmov",
1128 NIR_OP_TYPE_ALU,
1129 0,
1130 NIR_TYPE_FLOAT,
1131 1,
1132 {0},
1133 {NIR_TYPE_FLOAT},
1134 0
1135 };
1136 static struct nir_op nir_fmul = {
1137 "fmul",
1138 NIR_OP_TYPE_ALU,
1139 0,
1140 NIR_TYPE_FLOAT,
1141 2,
1142 {0,0},
1143 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1144 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1145 };
1146 static struct nir_op nir_fne = {
1147 "fne",
1148 NIR_OP_TYPE_ALU,
1149 0,
1150 NIR_TYPE_BOOL1,
1151 2,
1152 {0,0},
1153 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1154 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1155 };
1156 static struct nir_op nir_fne32 = {
1157 "fne32",
1158 NIR_OP_TYPE_ALU,
1159 0,
1160 NIR_TYPE_BOOL32,
1161 2,
1162 {0,0},
1163 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1164 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1165 };
1166 static struct nir_op nir_fneg = {
1167 "fneg",
1168 NIR_OP_TYPE_ALU,
1169 0,
1170 NIR_TYPE_FLOAT,
1171 1,
1172 {0},
1173 {NIR_TYPE_FLOAT},
1174 0
1175 };
1176 static struct nir_op nir_fnoise1_1 = {
1177 "fnoise1_1",
1178 NIR_OP_TYPE_ALU,
1179 1,
1180 NIR_TYPE_FLOAT,
1181 1,
1182 {1},
1183 {NIR_TYPE_FLOAT},
1184 0
1185 };
1186 static struct nir_op nir_fnoise1_2 = {
1187 "fnoise1_2",
1188 NIR_OP_TYPE_ALU,
1189 1,
1190 NIR_TYPE_FLOAT,
1191 1,
1192 {2},
1193 {NIR_TYPE_FLOAT},
1194 0
1195 };
1196 static struct nir_op nir_fnoise1_3 = {
1197 "fnoise1_3",
1198 NIR_OP_TYPE_ALU,
1199 1,
1200 NIR_TYPE_FLOAT,
1201 1,
1202 {3},
1203 {NIR_TYPE_FLOAT},
1204 0
1205 };
1206 static struct nir_op nir_fnoise1_4 = {
1207 "fnoise1_4",
1208 NIR_OP_TYPE_ALU,
1209 1,
1210 NIR_TYPE_FLOAT,
1211 1,
1212 {4},
1213 {NIR_TYPE_FLOAT},
1214 0
1215 };
1216 static struct nir_op nir_fnoise2_1 = {
1217 "fnoise2_1",
1218 NIR_OP_TYPE_ALU,
1219 2,
1220 NIR_TYPE_FLOAT,
1221 1,
1222 {1},
1223 {NIR_TYPE_FLOAT},
1224 0
1225 };
1226 static struct nir_op nir_fnoise2_2 = {
1227 "fnoise2_2",
1228 NIR_OP_TYPE_ALU,
1229 2,
1230 NIR_TYPE_FLOAT,
1231 1,
1232 {2},
1233 {NIR_TYPE_FLOAT},
1234 0
1235 };
1236 static struct nir_op nir_fnoise2_3 = {
1237 "fnoise2_3",
1238 NIR_OP_TYPE_ALU,
1239 2,
1240 NIR_TYPE_FLOAT,
1241 1,
1242 {3},
1243 {NIR_TYPE_FLOAT},
1244 0
1245 };
1246 static struct nir_op nir_fnoise2_4 = {
1247 "fnoise2_4",
1248 NIR_OP_TYPE_ALU,
1249 2,
1250 NIR_TYPE_FLOAT,
1251 1,
1252 {4},
1253 {NIR_TYPE_FLOAT},
1254 0
1255 };
1256 static struct nir_op nir_fnoise3_1 = {
1257 "fnoise3_1",
1258 NIR_OP_TYPE_ALU,
1259 3,
1260 NIR_TYPE_FLOAT,
1261 1,
1262 {1},
1263 {NIR_TYPE_FLOAT},
1264 0
1265 };
1266 static struct nir_op nir_fnoise3_2 = {
1267 "fnoise3_2",
1268 NIR_OP_TYPE_ALU,
1269 3,
1270 NIR_TYPE_FLOAT,
1271 1,
1272 {2},
1273 {NIR_TYPE_FLOAT},
1274 0
1275 };
1276 static struct nir_op nir_fnoise3_3 = {
1277 "fnoise3_3",
1278 NIR_OP_TYPE_ALU,
1279 3,
1280 NIR_TYPE_FLOAT,
1281 1,
1282 {3},
1283 {NIR_TYPE_FLOAT},
1284 0
1285 };
1286 static struct nir_op nir_fnoise3_4 = {
1287 "fnoise3_4",
1288 NIR_OP_TYPE_ALU,
1289 3,
1290 NIR_TYPE_FLOAT,
1291 1,
1292 {4},
1293 {NIR_TYPE_FLOAT},
1294 0
1295 };
1296 static struct nir_op nir_fnoise4_1 = {
1297 "fnoise4_1",
1298 NIR_OP_TYPE_ALU,
1299 4,
1300 NIR_TYPE_FLOAT,
1301 1,
1302 {1},
1303 {NIR_TYPE_FLOAT},
1304 0
1305 };
1306 static struct nir_op nir_fnoise4_2 = {
1307 "fnoise4_2",
1308 NIR_OP_TYPE_ALU,
1309 4,
1310 NIR_TYPE_FLOAT,
1311 1,
1312 {2},
1313 {NIR_TYPE_FLOAT},
1314 0
1315 };
1316 static struct nir_op nir_fnoise4_3 = {
1317 "fnoise4_3",
1318 NIR_OP_TYPE_ALU,
1319 4,
1320 NIR_TYPE_FLOAT,
1321 1,
1322 {3},
1323 {NIR_TYPE_FLOAT},
1324 0
1325 };
1326 static struct nir_op nir_fnoise4_4 = {
1327 "fnoise4_4",
1328 NIR_OP_TYPE_ALU,
1329 4,
1330 NIR_TYPE_FLOAT,
1331 1,
1332 {4},
1333 {NIR_TYPE_FLOAT},
1334 0
1335 };
1336 static struct nir_op nir_fnot = {
1337 "fnot",
1338 NIR_OP_TYPE_ALU,
1339 0,
1340 NIR_TYPE_FLOAT,
1341 1,
1342 {0},
1343 {NIR_TYPE_FLOAT},
1344 0
1345 };
1346 static struct nir_op nir_for = {
1347 "for",
1348 NIR_OP_TYPE_ALU,
1349 0,
1350 NIR_TYPE_FLOAT32,
1351 2,
1352 {0,0},
1353 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1354 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1355 };
1356 static struct nir_op nir_fpow = {
1357 "fpow",
1358 NIR_OP_TYPE_ALU,
1359 0,
1360 NIR_TYPE_FLOAT,
1361 2,
1362 {0,0},
1363 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1364 0
1365
1366 };
1367 static struct nir_op nir_fquantize2f16 = {
1368 "fquantize2f16",
1369 NIR_OP_TYPE_ALU,
1370 0,
1371 NIR_TYPE_FLOAT,
1372 1,
1373 {0},
1374 {NIR_TYPE_FLOAT},
1375 0
1376 };
1377 static struct nir_op nir_frcp = {
1378 "frcp",
1379 NIR_OP_TYPE_ALU,
1380 0,
1381 NIR_TYPE_FLOAT,
1382 1,
1383 {0},
1384 {NIR_TYPE_FLOAT},
1385 0
1386 };
1387 static struct nir_op nir_frem = {
1388 "frem",
1389 NIR_OP_TYPE_ALU,
1390 0,
1391 NIR_TYPE_FLOAT,
1392 2,
1393 {0,0},
1394 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1395 0
1396 };
1397 static struct nir_op nir_frexp_exp = {
1398 "frexp_exp",
1399 NIR_OP_TYPE_ALU,
1400 0,
1401 NIR_TYPE_INT32,
1402 1,
1403 {0},
1404 {NIR_TYPE_FLOAT},
1405 0
1406 };
1407 static struct nir_op nir_frexp_sig = {
1408 "frexp_sig",
1409 NIR_OP_TYPE_ALU,
1410 0,
1411 NIR_TYPE_FLOAT,
1412 1,
1413 {0},
1414 {NIR_TYPE_FLOAT},
1415 0
1416 };
1417 static struct nir_op nir_fround_even = {
1418 "fround_even",
1419 NIR_OP_TYPE_ALU,
1420 0,
1421 NIR_TYPE_FLOAT,
1422 1,
1423 {0},
1424 {NIR_TYPE_FLOAT},
1425 0
1426 };
1427 static struct nir_op nir_frsq = {
1428 "frsq",
1429 NIR_OP_TYPE_ALU,
1430 0,
1431 NIR_TYPE_FLOAT,
1432 1,
1433 {0},
1434 {NIR_TYPE_FLOAT},
1435 0
1436 };
1437 static struct nir_op nir_fsat = {
1438 "fsat",
1439 NIR_OP_TYPE_ALU,
1440 0,
1441 NIR_TYPE_FLOAT,
1442 1,
1443 {0},
1444 {NIR_TYPE_FLOAT},
1445 0
1446 };
1447 static struct nir_op nir_fsign = {
1448 "fsign",
1449 NIR_OP_TYPE_ALU,
1450 0,
1451 NIR_TYPE_FLOAT,
1452 1,
1453 {0},
1454 {NIR_TYPE_FLOAT},
1455 0
1456 };
1457 static struct nir_op nir_fsin = {
1458 "fsin",
1459 NIR_OP_TYPE_ALU,
1460 0,
1461 NIR_TYPE_FLOAT,
1462 1,
1463 {0},
1464 {NIR_TYPE_FLOAT},
1465 0
1466 };
1467 static struct nir_op nir_fsqrt = {
1468 "fsqrt",
1469 NIR_OP_TYPE_ALU,
1470 0,
1471 NIR_TYPE_FLOAT,
1472 1,
1473 {0},
1474 {NIR_TYPE_FLOAT},
1475 0
1476 };
1477 static struct nir_op nir_fsub = {
1478 "fsub",
1479 NIR_OP_TYPE_ALU,
1480 0,
1481 NIR_TYPE_FLOAT,
1482 2,
1483 {0,0},
1484 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
1485 0
1486 };
1487 static struct nir_op nir_ftrunc = {
1488 "ftrunc",
1489 NIR_OP_TYPE_ALU,
1490 0,
1491 NIR_TYPE_FLOAT,
1492 1,
1493 {0},
1494 {NIR_TYPE_FLOAT},
1495 0
1496 };
1497 static struct nir_op nir_fxor = {
1498 "fxor",
1499 NIR_OP_TYPE_ALU,
1500 0,
1501 NIR_TYPE_FLOAT32,
1502 2,
1503 {0,0},
1504 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
1505 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1506 };
1507 static struct nir_op nir_i2b1 = {
1508 "i2b1",
1509 NIR_OP_TYPE_ALU,
1510 0,
1511 NIR_TYPE_BOOL1,
1512 1,
1513 {0},
1514 {NIR_TYPE_INT},
1515 0
1516 };
1517 static struct nir_op nir_i2b32 = {
1518 "i2b32",
1519 NIR_OP_TYPE_ALU,
1520 0,
1521 NIR_TYPE_BOOL32,
1522 1,
1523 {0},
1524 {NIR_TYPE_INT},
1525 0
1526 };
1527 static struct nir_op nir_i2f16 = {
1528 "i2f16",
1529 NIR_OP_TYPE_ALU,
1530 0,
1531 NIR_TYPE_FLOAT16,
1532 1,
1533 {0},
1534 {NIR_TYPE_INT},
1535 0
1536 };
1537 static struct nir_op nir_i2f32 = {
1538 "i2f32",
1539 NIR_OP_TYPE_ALU,
1540 0,
1541 NIR_TYPE_FLOAT32,
1542 1,
1543 {0},
1544 {NIR_TYPE_INT},
1545 0
1546 };
1547 static struct nir_op nir_i2f64 = {
1548 "i2f64",
1549 NIR_OP_TYPE_ALU,
1550 0,
1551 NIR_TYPE_FLOAT64,
1552 1,
1553 {0},
1554 {NIR_TYPE_INT},
1555 0
1556 };
1557 static struct nir_op nir_i2i1 = {
1558 "i2i1",
1559 NIR_OP_TYPE_ALU,
1560 0,
1561 NIR_TYPE_INT1,
1562 1,
1563 {0},
1564 {NIR_TYPE_INT},
1565 0
1566 };
1567 static struct nir_op nir_i2i16 = {
1568 "i2i16",
1569 NIR_OP_TYPE_ALU,
1570 0,
1571 NIR_TYPE_INT16,
1572 1,
1573 {0},
1574 {NIR_TYPE_INT16},
1575 0
1576 };
1577 static struct nir_op nir_i2i32 = {
1578 "i2i32",
1579 NIR_OP_TYPE_ALU,
1580 0,
1581 NIR_TYPE_INT32,
1582 1,
1583 {0},
1584 {NIR_TYPE_INT},
1585 0
1586
1587 };
1588 static struct nir_op nir_i2i64 = {
1589 "i2i64",
1590 NIR_OP_TYPE_ALU,
1591 0,
1592 NIR_TYPE_INT64,
1593 1,
1594 {0},
1595 {NIR_TYPE_INT},
1596 0
1597 };
1598 static struct nir_op nir_i2i8 = {
1599 "i2i8",
1600 NIR_OP_TYPE_ALU,
1601 0,
1602 NIR_TYPE_INT8,
1603 1,
1604 {0},
1605 {NIR_TYPE_INT},
1606 0
1607 };
1608 static struct nir_op nir_iabs = {
1609 "iabs",
1610 NIR_OP_TYPE_ALU,
1611 0,
1612 NIR_TYPE_INT,
1613 1,
1614 {0},
1615 {NIR_TYPE_INT},
1616 0
1617 };
1618 static struct nir_op nir_iadd = {
1619 "iadd",
1620 NIR_OP_TYPE_ALU,
1621 0,
1622 NIR_TYPE_INT,
1623 2,
1624 {0,0},
1625 {NIR_TYPE_INT,NIR_TYPE_INT},
1626 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1627 };
1628 static struct nir_op nir_iadd_sat = {
1629 "iadd_sat",
1630 NIR_OP_TYPE_ALU,
1631 0,
1632 NIR_TYPE_INT,
1633 2,
1634 {0,0},
1635 {NIR_TYPE_INT,NIR_TYPE_INT},
1636 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1637 };
1638 static struct nir_op nir_iand = {
1639 "iand",
1640 NIR_OP_TYPE_ALU,
1641 0,
1642 NIR_TYPE_UINT,
1643 2,
1644 {0,0},
1645 {NIR_TYPE_UINT,NIR_TYPE_UINT},
1646 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1647 };
1648 static struct nir_op nir_ibfe = {
1649 "ibfe",
1650 NIR_OP_TYPE_ALU,
1651 0,
1652 NIR_TYPE_INT32,
1653 3,
1654 {0,0,0},
1655 {NIR_TYPE_INT32,NIR_TYPE_INT32,NIR_TYPE_INT32},
1656 0
1657 };
1658 static struct nir_op nir_ibitfield_extract = {
1659 "ibitfield_extract",
1660 NIR_OP_TYPE_ALU,
1661 0,
1662 NIR_TYPE_INT32,
1663 3,
1664 {0,0,0},
1665 {NIR_TYPE_INT32,NIR_TYPE_INT32,NIR_TYPE_INT32},
1666 0
1667 };
1668 static struct nir_op nir_idiv = {
1669 "idiv",
1670 NIR_OP_TYPE_ALU,
1671 0,
1672 NIR_TYPE_INT,
1673 2,
1674 {0,0},
1675 {NIR_TYPE_INT,NIR_TYPE_INT},
1676 0
1677 };
1678 static struct nir_op nir_ieq = {
1679 "ieq",
1680 NIR_OP_TYPE_ALU,
1681 0,
1682 NIR_TYPE_BOOL1,
1683 2,
1684 {0,0},
1685 {NIR_TYPE_INT,NIR_TYPE_INT},
1686 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1687 };
1688 static struct nir_op nir_ieq32 = {
1689 "ieq32",
1690 NIR_OP_TYPE_ALU,
1691 0,
1692 NIR_TYPE_BOOL32,
1693 2,
1694 {0,0},
1695 {NIR_TYPE_INT,NIR_TYPE_INT},
1696 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1697 };
1698 static struct nir_op nir_ifind_msb = {
1699 "ifind_msb",
1700 NIR_OP_TYPE_ALU,
1701 0,
1702 NIR_TYPE_INT32,
1703 1,
1704 {0},
1705 NIR_TYPE_INT32,
1706 0
1707 };
1708 static struct nir_op nir_ige = {
1709 "ige",
1710 NIR_OP_TYPE_ALU,
1711 0,
1712 NIR_TYPE_BOOL1,
1713 2,
1714 {0,0},
1715 {NIR_TYPE_INT,NIR_TYPE_INT},
1716 0
1717 };
1718 static struct nir_op nir_ige32 = {
1719 "ige32",
1720 NIR_OP_TYPE_ALU,
1721 0,
1722 NIR_TYPE_BOOL32,
1723 2,
1724 {0,0},
1725 {NIR_TYPE_INT,NIR_TYPE_INT},
1726 0
1727 };
1728 static struct nir_op nir_ihadd = {
1729 "ihadd",
1730 NIR_OP_TYPE_ALU,
1731 0,
1732 NIR_TYPE_INT,
1733 2,
1734 {0,0},
1735 {NIR_TYPE_INT,NIR_TYPE_INT},
1736 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1737 };
1738 static struct nir_op nir_ilt = {
1739 "ilt",
1740 NIR_OP_TYPE_ALU,
1741 0,
1742 NIR_TYPE_BOOL1,
1743 2,
1744 {0,0},
1745 {NIR_TYPE_INT,NIR_TYPE_INT},
1746 0
1747 };
1748 static struct nir_op nir_ilt32 = {
1749 "ilt32",
1750 NIR_OP_TYPE_ALU,
1751 0,
1752 NIR_TYPE_BOOL32,
1753 2,
1754 {0,0},
1755 {NIR_TYPE_INT,NIR_TYPE_INT},
1756 0
1757 };
1758 static struct nir_op nir_imax = {
1759 "imax",
1760 NIR_OP_TYPE_ALU,
1761 0,
1762 NIR_TYPE_INT,
1763 2,
1764 {0,0},
1765 {NIR_TYPE_INT,NIR_TYPE_INT},
1766 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1767 };
1768 static struct nir_op nir_imax3 = {
1769 "imax3",
1770 NIR_OP_TYPE_ALU,
1771 0,
1772 NIR_TYPE_INT,
1773 3,
1774 {0,0,0},
1775 {NIR_TYPE_INT,NIR_TYPE_INT,NIR_TYPE_INT},
1776 0
1777 };
1778 static struct nir_op nir_imed3 = {
1779 "imed3",
1780 NIR_OP_TYPE_ALU,
1781 0,
1782 NIR_TYPE_INT,
1783 3,
1784 {0,0,0},
1785 {NIR_TYPE_INT,NIR_TYPE_INT,NIR_TYPE_INT},
1786 0
1787 };
1788 static struct nir_op nir_imin = {
1789 "imin",
1790 NIR_OP_TYPE_ALU,
1791 0,
1792 NIR_TYPE_INT,
1793 2,
1794 {0,0},
1795 {NIR_TYPE_INT,NIR_TYPE_INT},
1796 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1797 };
1798 static struct nir_op nir_imin3 = {
1799 "imin3",
1800 NIR_OP_TYPE_ALU,
1801 0,
1802 NIR_TYPE_INT,
1803 3,
1804 {0,0,0},
1805 {NIR_TYPE_INT,NIR_TYPE_INT,NIR_TYPE_INT},
1806 0
1807 };
1808 static struct nir_op nir_imod = {
1809 "imod",
1810 NIR_OP_TYPE_ALU,
1811 0,
1812 NIR_TYPE_INT,
1813 2,
1814 {0,0},
1815 {NIR_TYPE_INT,NIR_TYPE_INT},
1816 0
1817 };
1818 static struct nir_op nir_imov = {
1819 "imov",
1820 NIR_OP_TYPE_ALU,
1821 0,
1822 NIR_TYPE_INT,
1823 1,
1824 {0},
1825 {NIR_TYPE_INT},
1826 0
1827 };
1828 static struct nir_op nir_imul = {
1829 "imul",
1830 NIR_OP_TYPE_ALU,
1831 0,
1832 NIR_TYPE_INT,
1833 2,
1834 {0,0},
1835 {NIR_TYPE_INT,NIR_TYPE_INT},
1836 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1837 };
1838 static struct nir_op nir_imul_2x32_64 = {
1839 "imul_2x32_64",
1840 NIR_OP_TYPE_ALU,
1841 0,
1842 NIR_TYPE_INT64,
1843 2,
1844 {0,0},
1845 {NIR_TYPE_INT32,NIR_TYPE_INT32},
1846 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1847 };
1848 static struct nir_op nir_imul_high = {
1849 "imul_high",
1850 NIR_OP_TYPE_ALU,
1851 0,
1852 NIR_TYPE_INT,
1853 2,
1854 {0,0},
1855 {NIR_TYPE_INT,NIR_TYPE_INT},
1856 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1857 };
1858 static struct nir_op nir_ine = {
1859 "ine",
1860 NIR_OP_TYPE_ALU,
1861 0,
1862 NIR_TYPE_BOOL1,
1863 2,
1864 {0,0},
1865 {NIR_TYPE_INT,NIR_TYPE_INT},
1866 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1867 };
1868 static struct nir_op nir_ine32 = {
1869 "ine32",
1870 NIR_OP_TYPE_ALU,
1871 0,
1872 NIR_TYPE_BOOL32,
1873 2,
1874 {0,0},
1875 {NIR_TYPE_INT,NIR_TYPE_INT},
1876 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1877 };
1878 static struct nir_op nir_ineg = {
1879 "ineg",
1880 NIR_OP_TYPE_ALU,
1881 0,
1882 NIR_TYPE_INT,
1883 1,
1884 {0},
1885 {NIR_TYPE_INT},
1886 0
1887 };
1888 static struct nir_op nir_inot = {
1889 "inot",
1890 NIR_OP_TYPE_ALU,
1891 0,
1892 NIR_TYPE_INT,
1893 1,
1894 {0},
1895 {NIR_TYPE_INT},
1896 0
1897 };
1898 static struct nir_op nir_ior = {
1899 "ior",
1900 NIR_OP_TYPE_ALU,
1901 0,
1902 NIR_TYPE_UINT,
1903 2,
1904 {0,0},
1905 {NIR_TYPE_UINT,NIR_TYPE_UINT},
1906 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1907 };
1908 static struct nir_op nir_irem = {
1909 "irem",
1910 NIR_OP_TYPE_ALU,
1911 0,
1912 NIR_TYPE_INT,
1913 2,
1914 {0,0},
1915 {NIR_TYPE_INT,NIR_TYPE_INT},
1916 0
1917 };
1918 static struct nir_op nir_irhadd = {
1919 "irhadd",
1920 NIR_OP_TYPE_ALU,
1921 0,
1922 NIR_TYPE_INT,
1923 2,
1924 {0,0},
1925 {NIR_TYPE_INT,NIR_TYPE_INT},
1926 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
1927 };
1928 static struct nir_op nir_ishl = {
1929 "ishl",
1930 NIR_OP_TYPE_ALU,
1931 0,
1932 NIR_TYPE_INT,
1933 2,
1934 {0,0},
1935 {NIR_TYPE_INT,NIR_TYPE_UINT32},
1936 0
1937 };
1938 static struct nir_op nir_ishr = {
1939 "ishr",
1940 NIR_OP_TYPE_ALU,
1941 0,
1942 NIR_TYPE_INT,
1943 2,
1944 {0,0},
1945 {NIR_TYPE_INT,NIR_TYPE_UINT32},
1946 0
1947 };
1948 static struct nir_op nir_isign = {
1949 "isign",
1950 NIR_OP_TYPE_ALU,
1951 0,
1952 NIR_TYPE_INT,
1953 1,
1954 {0},
1955 {NIR_TYPE_INT},
1956 0
1957 };
1958 static struct nir_op nir_isub = {
1959 "isub",
1960 NIR_OP_TYPE_ALU,
1961 0,
1962 NIR_TYPE_INT,
1963 2,
1964 {0,0},
1965 {NIR_TYPE_INT,NIR_TYPE_INT},
1966 0
1967 };
1968 static struct nir_op nir_isub_sat = {
1969 "isub_sat",
1970 NIR_OP_TYPE_ALU,
1971 0,
1972 NIR_TYPE_INT,
1973 2,
1974 {0,0},
1975 {NIR_TYPE_INT,NIR_TYPE_INT},
1976 0
1977 };
1978 static struct nir_op nir_ixor = {
1979 "ixor",
1980 NIR_OP_TYPE_ALU,
1981 0,
1982 NIR_TYPE_UINT,
1983 2,
1984 {0,0},
1985 {NIR_TYPE_UINT,NIR_TYPE_UINT},
1986 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
1987 };
1988 static struct nir_op nir_ldexp = {
1989 "ldexp",
1990 NIR_OP_TYPE_ALU,
1991 0,
1992 NIR_TYPE_FLOAT,
1993 2,
1994 {0,0},
1995 {NIR_TYPE_FLOAT,NIR_TYPE_INT32},
1996 0
1997 };
1998 static struct nir_op nir_pack_32_2x16 = {
1999 "pack_32_2x16",
2000 NIR_OP_TYPE_ALU,
2001 1,
2002 NIR_TYPE_UINT32,
2003 1,
2004 {2},
2005 {NIR_TYPE_UINT16},
2006 0
2007 };
2008 static struct nir_op nir_pack_32_2x16_split = {
2009 "pack_32_2x16_split",
2010 NIR_OP_TYPE_ALU,
2011 0,
2012 NIR_TYPE_UINT32,
2013 2,
2014 {0,0},
2015 {NIR_TYPE_UINT16,NIR_TYPE_UINT16},
2016 0
2017 };
2018 static struct nir_op nir_pack_64_2x32 = {
2019 "pack_64_2x32",
2020 NIR_OP_TYPE_ALU,
2021 1,
2022 NIR_TYPE_UINT64,
2023 1,
2024 {2},
2025 {NIR_TYPE_UINT32},
2026 0
2027 };
2028 static struct nir_op nir_pack_64_2x32_split = {
2029 "pack_64_2x32_split",
2030 NIR_OP_TYPE_ALU,
2031 0,
2032 NIR_TYPE_UINT64,
2033 2,
2034 {0,0},
2035 {NIR_TYPE_UINT32,NIR_TYPE_UINT32},
2036 0
2037 };
2038 static struct nir_op nir_pack_64_4x16 = {
2039 "pack_64_4x16",
2040 NIR_OP_TYPE_ALU,
2041 1,
2042 NIR_TYPE_UINT64,
2043 1,
2044 {4},
2045 {NIR_TYPE_UINT16},
2046 0
2047 };
2048 static struct nir_op nir_pack_half_2x16 = {
2049 "pack_half_2x16",
2050 NIR_OP_TYPE_ALU,
2051 1,
2052 NIR_TYPE_UINT32,
2053 1,
2054 {2},
2055 {NIR_TYPE_FLOAT32},
2056 0
2057 };
2058 static struct nir_op nir_pack_half_2x16_split = {
2059 "pack_half_2x16_split",
2060 NIR_OP_TYPE_ALU,
2061 1,
2062 NIR_TYPE_UINT32,
2063 2,
2064 {1,1},
2065 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
2066 0
2067 };
2068 static struct nir_op nir_pack_snorm_2x16 = {
2069 "pack_snorm_2x16",
2070 NIR_OP_TYPE_ALU,
2071 1,
2072 NIR_TYPE_UINT32,
2073 1,
2074 {2},
2075 {NIR_TYPE_FLOAT32},
2076 0
2077 };
2078 static struct nir_op nir_pack_snorm_4x8 = {
2079 "pack_snorm_4x8",
2080 NIR_OP_TYPE_ALU,
2081 1,
2082 NIR_TYPE_UINT32,
2083 1,
2084 {4},
2085 {NIR_TYPE_FLOAT32},
2086 0
2087 };
2088 static struct nir_op nir_pack_unorm_2x16 = {
2089 "pack_unorm_2x16",
2090 NIR_OP_TYPE_ALU,
2091 1,
2092 NIR_TYPE_UINT32,
2093 1,
2094 {2},
2095 {NIR_TYPE_FLOAT32},
2096 0
2097 };
2098 static struct nir_op nir_pack_unorm_4x8 = {
2099 "pack_unorm_4x8",
2100 NIR_OP_TYPE_ALU,
2101 1,
2102 NIR_TYPE_UINT32,
2103 1,
2104 {4},
2105 {NIR_TYPE_FLOAT32},
2106 0
2107 };
2108 static struct nir_op nir_pack_uvec2_to_uint = {
2109 "pack_uvec2_to_uint",
2110 NIR_OP_TYPE_ALU,
2111 1,
2112 NIR_TYPE_UINT32,
2113 1,
2114 {2},
2115 {NIR_TYPE_UINT32},
2116 0
2117 };
2118 static struct nir_op nir_pack_uvec4_to_uint = {
2119 "pack_uvec4_to_uint",
2120 NIR_OP_TYPE_ALU,
2121 1,
2122 NIR_TYPE_UINT32,
2123 1,
2124 {4},
2125 {NIR_TYPE_UINT32},
2126 0
2127 };
2128 static struct nir_op nir_seq = {
2129 "seq",
2130 NIR_OP_TYPE_ALU,
2131 0,
2132 NIR_TYPE_FLOAT32,
2133 2,
2134 {0,0},
2135 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
2136 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2137 };
2138 static struct nir_op nir_sge = {
2139 "sge",
2140 NIR_OP_TYPE_ALU,
2141 0,
2142 NIR_TYPE_FLOAT,
2143 2,
2144 {0,0},
2145 {NIR_TYPE_FLOAT,NIR_TYPE_FLOAT},
2146 0
2147 };
2148 static struct nir_op nir_slt = {
2149 "slt",
2150 NIR_OP_TYPE_ALU,
2151 0,
2152 NIR_TYPE_FLOAT32,
2153 2,
2154 {0,0},
2155 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
2156 0
2157 };
2158 static struct nir_op nir_sne = {
2159 "sne",
2160 NIR_OP_TYPE_ALU,
2161 0,
2162 NIR_TYPE_FLOAT32,
2163 2,
2164 {0,0},
2165 {NIR_TYPE_FLOAT32,NIR_TYPE_FLOAT32},
2166 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2167 };
2168 static struct nir_op nir_u2f16 = {
2169 "u2f16",
2170 NIR_OP_TYPE_ALU,
2171 0,
2172 NIR_TYPE_FLOAT16,
2173 1,
2174 {0},
2175 {NIR_TYPE_UINT},
2176 0
2177 };
2178 static struct nir_op nir_u2f32 = {
2179 "u2f32",
2180 NIR_OP_TYPE_ALU,
2181 0,
2182 NIR_TYPE_FLOAT32,
2183 1,
2184 {0},
2185 {NIR_TYPE_UINT},
2186 0
2187 };
2188 static struct nir_op nir_u2f64 = {
2189 "u2f64",
2190 NIR_OP_TYPE_ALU,
2191 0,
2192 NIR_TYPE_FLOAT64,
2193 1,
2194 {0},
2195 {NIR_TYPE_UINT},
2196 0
2197 };
2198 static struct nir_op nir_u2u1 = {
2199 "u2u1",
2200 NIR_OP_TYPE_ALU,
2201 0,
2202 NIR_TYPE_UINT1,
2203 1,
2204 {0},
2205 {NIR_TYPE_UINT},
2206 0
2207 };
2208 static struct nir_op nir_u2u16 = {
2209 "u2u16",
2210 NIR_OP_TYPE_ALU,
2211 0,
2212 NIR_TYPE_UINT16,
2213 1,
2214 {0},
2215 {NIR_TYPE_UINT},
2216 0
2217 };
2218 static struct nir_op nir_u2u32 = {
2219 "u2u32",
2220 NIR_OP_TYPE_ALU,
2221 0,
2222 NIR_TYPE_UINT32,
2223 1,
2224 {0},
2225 {NIR_TYPE_UINT},
2226 0
2227 };
2228 static struct nir_op nir_u2u64 = {
2229 "u2u64",
2230 NIR_OP_TYPE_ALU,
2231 0,
2232 NIR_TYPE_UINT64,
2233 1,
2234 {0},
2235 {NIR_TYPE_UINT},
2236 0
2237 };
2238 static struct nir_op nir_u2u8 = {
2239 "u2u8",
2240 NIR_OP_TYPE_ALU,
2241 0,
2242 NIR_TYPE_UINT8,
2243 1,
2244 {0},
2245 {NIR_TYPE_UINT},
2246 0
2247 };
2248 static struct nir_op nir_uadd_carry = {
2249 "uadd_carry",
2250 NIR_OP_TYPE_ALU,
2251 0,
2252 NIR_TYPE_UINT,
2253 2,
2254 {0,0},
2255 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2256 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2257 };
2258 static struct nir_op nir_uadd_sat = {
2259 "uadd_sat",
2260 NIR_OP_TYPE_ALU,
2261 0,
2262 NIR_TYPE_UINT,
2263 2,
2264 {0,0},
2265 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2266 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2267 };
2268 static struct nir_op nir_ubfe = {
2269 "ubfe",
2270 NIR_OP_TYPE_ALU,
2271 0,
2272 NIR_TYPE_UINT32,
2273 3,
2274 {0,0,0},
2275 {NIR_TYPE_UINT32,NIR_TYPE_INT32,NIR_TYPE_INT32},
2276 0
2277 };
2278 static struct nir_op nir_ubitfield_extract = {
2279 "ubitfield_extract",
2280 NIR_OP_TYPE_ALU,
2281 0,
2282 NIR_TYPE_UINT32,
2283 3,
2284 {0,0,0},
2285 {NIR_TYPE_UINT32,NIR_TYPE_UINT32,NIR_TYPE_UINT32},
2286 0
2287 };
2288 static struct nir_op nir_udiv = {
2289 "udiv",
2290 NIR_OP_TYPE_ALU,
2291 0,
2292 NIR_TYPE_UINT,
2293 2,
2294 {0,0},
2295 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2296 0
2297 };
2298 static struct nir_op nir_ufind_msb = {
2299 "ufind_msb",
2300 NIR_OP_TYPE_ALU,
2301 0,
2302 NIR_TYPE_INT32,
2303 1,
2304 {0},
2305 {NIR_TYPE_UINT},
2306 0
2307 };
2308 static struct nir_op nir_uge = {
2309 "uge",
2310 NIR_OP_TYPE_ALU,
2311 0,
2312 NIR_TYPE_BOOL1,
2313 2,
2314 {0,0},
2315 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2316 0
2317 };
2318 static struct nir_op nir_uge32 = {
2319 "uge32",
2320 NIR_OP_TYPE_ALU,
2321 0,
2322 NIR_TYPE_BOOL32,
2323 2,
2324 {0,0},
2325 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2326 0
2327 };
2328 static struct nir_op nir_uhadd = {
2329 "uhadd",
2330 NIR_OP_TYPE_ALU,
2331 0,
2332 NIR_TYPE_UINT,
2333 2,
2334 {0,0},
2335 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2336 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2337 };
2338 static struct nir_op nir_ult = {
2339 "ult",
2340 NIR_OP_TYPE_ALU,
2341 0,
2342 NIR_TYPE_BOOL1,
2343 2,
2344 {0,0},
2345 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2346 0
2347 };
2348 static struct nir_op nir_ult32 = {
2349 "ult32",
2350 NIR_OP_TYPE_ALU,
2351 0,
2352 NIR_TYPE_BOOL32,
2353 2,
2354 {0,0},
2355 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2356 0
2357 };
2358 static struct nir_op nir_umax = {
2359 "umax",
2360 NIR_OP_TYPE_ALU,
2361 0,
2362 NIR_TYPE_UINT,
2363 2,
2364 {0,0},
2365 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2366 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2367 };
2368 static struct nir_op nir_umax3 = {
2369 "umax3",
2370 NIR_OP_TYPE_ALU,
2371 0,
2372 NIR_TYPE_UINT,
2373 3,
2374 {0,0,0},
2375 {NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT},
2376 0
2377 };
2378 static struct nir_op nir_umax_4x8 = {
2379 "umax_4x8",
2380 NIR_OP_TYPE_ALU,
2381 0,
2382 NIR_TYPE_INT32,
2383 2,
2384 {0,0},
2385 {NIR_TYPE_INT32,NIR_TYPE_INT32},
2386 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2387 };
2388 static struct nir_op nir_umed3 = {
2389 "umed3",
2390 NIR_OP_TYPE_ALU,
2391 0,
2392 NIR_TYPE_UINT,
2393 3,
2394 {0,0,0},
2395 {NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT},
2396 0
2397 };
2398 static struct nir_op nir_umin = {
2399 "umin",
2400 NIR_OP_TYPE_ALU,
2401 0,
2402 NIR_TYPE_UINT,
2403 2,
2404 {0,0},
2405 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2406 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2407 };
2408 static struct nir_op nir_umin3 = {
2409 "umin3",
2410 NIR_OP_TYPE_ALU,
2411 0,
2412 NIR_TYPE_UINT,
2413 3,
2414 {0,0,0},
2415 {NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT},
2416 0
2417 };
2418 static struct nir_op nir_umin_4x8 = {
2419 "umin_4x8",
2420 NIR_OP_TYPE_ALU,
2421 0,
2422 NIR_TYPE_INT32,
2423 2,
2424 {0,0},
2425 {NIR_TYPE_UINT32, NIR_TYPE_UINT32},
2426 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2427 };
2428 static struct nir_op nir_umod = {
2429 "umod",
2430 NIR_OP_TYPE_ALU,
2431 0,
2432 NIR_TYPE_UINT,
2433 2,
2434 {0,0},
2435 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2436 0
2437 };
2438 static struct nir_op nir_umul_2x32_64 = {
2439 "umul_2x32_64",
2440 NIR_OP_TYPE_ALU,
2441 0,
2442 NIR_TYPE_UINT64,
2443 2,
2444 {0,0},
2445 {NIR_TYPE_UINT32,NIR_TYPE_UINT32},
2446 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2447 };
2448 static struct nir_op nir_umul_high = {
2449 "umul_high",
2450 NIR_OP_TYPE_ALU,
2451 0,
2452 NIR_TYPE_UINT,
2453 2,
2454 {0,0},
2455 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2456 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2457 };
2458 static struct nir_op nir_umul_unorm_4x8 = {
2459 "umul_unorm_4x8",
2460 NIR_OP_TYPE_ALU,
2461 0,
2462 NIR_TYPE_INT32,
2463 2,
2464 {0,0},
2465 {NIR_TYPE_INT32,NIR_TYPE_INT32},
2466 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2467 };
2468 static struct nir_op nir_unpack_32_2x16 = {
2469 "unpack_32_2x16",
2470 NIR_OP_TYPE_ALU,
2471 2,
2472 NIR_TYPE_UINT16,
2473 1,
2474 {1},
2475 {NIR_TYPE_UINT32},
2476 0
2477 };
2478 static struct nir_op nir_unpack_32_2x16_split_x = {
2479 "unpack_32_2x16_split_x",
2480 NIR_OP_TYPE_ALU,
2481 0,
2482 NIR_TYPE_UINT16,
2483 1,
2484 {0},
2485 {NIR_TYPE_UINT32},
2486 0
2487 };
2488 static struct nir_op nir_unpack_32_2x16_split_y = {
2489 "unpack_32_2x16_split_y",
2490 NIR_OP_TYPE_ALU,
2491 0,
2492 NIR_TYPE_UINT16,
2493 1,
2494 {0},
2495 {NIR_TYPE_UINT32},
2496 0
2497 };
2498 static struct nir_op nir_unpack_64_2x32 = {
2499 "unpack_64_2x32",
2500 NIR_OP_TYPE_ALU,
2501 2,
2502 NIR_TYPE_UINT32,
2503 1,
2504 {1},
2505 {NIR_TYPE_UINT64},
2506 0
2507 };
2508 static struct nir_op nir_unpack_64_2x32_split_x = {
2509 "unpack_64_2x32_split_x",
2510 NIR_OP_TYPE_ALU,
2511 0,
2512 NIR_TYPE_UINT32,
2513 1,
2514 {0},
2515 {NIR_TYPE_UINT64},
2516 0
2517 };
2518 static struct nir_op nir_unpack_64_2x32_split_y = {
2519 "unpack_64_2x32_split_y",
2520 NIR_OP_TYPE_ALU,
2521 0,
2522 NIR_TYPE_UINT32,
2523 1,
2524 {0},
2525 {NIR_TYPE_UINT32},
2526 0
2527 };
2528 static struct nir_op nir_unpack_64_4x16 = {
2529 "unpack_64_4x16",
2530 NIR_OP_TYPE_ALU,
2531 4,
2532 NIR_TYPE_UINT16,
2533 1,
2534 {1},
2535 {NIR_TYPE_UINT64},
2536 0
2537 };
2538 static struct nir_op nir_unpack_half_2x16 = {
2539 "unpack_half_2x16",
2540 NIR_OP_TYPE_ALU,
2541 2,
2542 NIR_TYPE_FLOAT32,
2543 1,
2544 {1},
2545 {NIR_TYPE_UINT32},
2546 0
2547 };
2548 static struct nir_op nir_unpack_half_2x16_split_x = {
2549 "unpack_half_2x16_split_x",
2550 NIR_OP_TYPE_ALU,
2551 0,
2552 NIR_TYPE_FLOAT32,
2553 1,
2554 {0},
2555 {NIR_TYPE_UINT32},
2556 0
2557 };
2558 static struct nir_op nir_unpack_half_2x16_split_y = {
2559 "unpack_half_2x16_split_y",
2560 NIR_OP_TYPE_ALU,
2561 0,
2562 NIR_TYPE_FLOAT32,
2563 1,
2564 {0},
2565 {NIR_TYPE_UINT32},
2566 0
2567 };
2568 static struct nir_op nir_unpack_snorm_2x16 = {
2569 "unpack_snorm_2x16",
2570 NIR_OP_TYPE_ALU,
2571 2,
2572 NIR_TYPE_FLOAT32,
2573 1,
2574 {1},
2575 {NIR_TYPE_UINT32},
2576 0
2577 };
2578 static struct nir_op nir_unpack_snorm_4x8 = {
2579 "unpack_snorm_4x8",
2580 NIR_OP_TYPE_ALU,
2581 4,
2582 NIR_TYPE_FLOAT32,
2583 1,
2584 {1},
2585 {NIR_TYPE_UINT32},
2586 0
2587 };
2588 static struct nir_op nir_unpack_unorm_2x16 = {
2589 "unpack_unorm_2x16",
2590 NIR_OP_TYPE_ALU,
2591 2,
2592 NIR_TYPE_UINT32,
2593 1,
2594 {1},
2595 {NIR_TYPE_UINT32},
2596 0
2597 };
2598 static struct nir_op nir_unpack_unorm_4x8 = {
2599 "unpack_unorm_4x8",
2600 NIR_OP_TYPE_ALU,
2601 4,
2602 NIR_TYPE_FLOAT32,
2603 1,
2604 {1},
2605 {NIR_TYPE_UINT32},
2606 0
2607 };
2608 static struct nir_op nir_urhadd = {
2609 "urhadd",
2610 NIR_OP_TYPE_ALU,
2611 0,
2612 NIR_TYPE_UINT,
2613 2,
2614 {0,0},
2615 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2616 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE
2617 };
2618 static struct nir_op nir_usadd_4x8 = {
2619 "usadd_4x8",
2620 NIR_OP_TYPE_ALU,
2621 0,
2622 NIR_TYPE_INT32,
2623 2,
2624 {0,0},
2625 {NIR_TYPE_INT32,NIR_TYPE_INT32},
2626 NIR_OP_ALGEBRAIC_PROPERTIES_COMMUTATIVE | NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE
2627 };
2628 static struct nir_op nir_ushr = {
2629 "ushr",
2630 NIR_OP_TYPE_ALU,
2631 0,
2632 NIR_TYPE_UINT,
2633 2,
2634 {0,0},
2635 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2636 0
2637 };
2638 static struct nir_op nir_ussub_4x8 = {
2639 "ussub_4x8",
2640 NIR_OP_TYPE_ALU,
2641 0,
2642 NIR_TYPE_INT32,
2643 2,
2644 {0,0},
2645 {NIR_TYPE_INT32,NIR_TYPE_INT32},
2646 0
2647 };
2648 static struct nir_op nir_usub_borrow = {
2649 "usub_borrow",
2650 NIR_OP_TYPE_ALU,
2651 0,
2652 NIR_TYPE_UINT,
2653 2,
2654 {0,0},
2655 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2656 0
2657 };
2658 static struct nir_op nir_usub_sat = {
2659 "usub_sat",
2660 NIR_OP_TYPE_ALU,
2661 0,
2662 NIR_TYPE_UINT,
2663 2,
2664 {0,0},
2665 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2666 0
2667 };
2668 static struct nir_op nir_vec2 = {
2669 "vec2",
2670 NIR_OP_TYPE_ALU,
2671 2,
2672 NIR_TYPE_UINT,
2673 2,
2674 {1,1},
2675 {NIR_TYPE_UINT,NIR_TYPE_UINT},
2676 0
2677 };
2678 static struct nir_op nir_vec3 = {
2679 "vec3",
2680 NIR_OP_TYPE_ALU,
2681 3,
2682 NIR_TYPE_UINT,
2683 3,
2684 {1,1,1},
2685 {NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT},
2686 0
2687 };
2688 static struct nir_op nir_vec4 = {
2689 "vec4",
2690 NIR_OP_TYPE_ALU,
2691 4,
2692 NIR_TYPE_UINT,
2693 4,
2694 {1,1,1,1},
2695 {NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT,NIR_TYPE_UINT},
2696 0
2697 };
2698
2699 static struct nir_op *nir_ops[] = {
2700 &nir_b2f16,
2701 &nir_b2f32,
2702 &nir_b2f64,
2703 &nir_b2i1,
2704 &nir_b2i16,
2705 &nir_b2i32,
2706 &nir_b2i64,
2707 &nir_b2i8,
2708 &nir_b32all_fequal2,
2709 &nir_b32all_fequal3,
2710 &nir_b32all_fequal4,
2711 &nir_b32all_iequal2,
2712 &nir_b32all_iequal3,
2713 &nir_b32all_iequal4,
2714 &nir_b32any_fnequal2,
2715 &nir_b32any_fnequal3,
2716 &nir_b32any_fnequal4,
2717 &nir_b32any_inequal2,
2718 &nir_b32any_inequal3,
2719 &nir_b32any_inequal4,
2720 &nir_b32csel,
2721 &nir_ball_fequal2,
2722 &nir_ball_fequal3,
2723 &nir_ball_fequal4,
2724 &nir_ball_iequal2,
2725 &nir_ball_iequal3,
2726 &nir_ball_iequal4,
2727 &nir_bany_fnequal2,
2728 &nir_bany_fnequal3,
2729 &nir_bany_fnequal4,
2730 &nir_bany_inequal2,
2731 &nir_bany_inequal3,
2732 &nir_bany_inequal4,
2733 &nir_bcsel,
2734 &nir_bfi,
2735 &nir_bfm,
2736 &nir_bit_count,
2737 &nir_bitfield_insert,
2738 &nir_bitfield_reverse,
2739 &nir_cube_face_coord,
2740 &nir_cube_face_index,
2741 &nir_extract_i16,
2742 &nir_extract_i8,
2743 &nir_extract_u16,
2744 &nir_extract_u8,
2745 &nir_f2b1,
2746 &nir_f2b32,
2747 &nir_f2f16,
2748 &nir_f2f16_rtne,
2749 &nir_f2f16_rtz,
2750 &nir_f2f32,
2751 &nir_f2f64,
2752 &nir_f2i1,
2753 &nir_f2i16,
2754 &nir_f2i32,
2755 &nir_f2i64,
2756 &nir_f2i8,
2757 &nir_f2u1,
2758 &nir_f2u16,
2759 &nir_f2u32,
2760 &nir_f2u64,
2761 &nir_f2u8,
2762 &nir_fabs,
2763 &nir_fadd,
2764 &nir_fall_equal2,
2765 &nir_fall_equal3,
2766 &nir_fall_equal4,
2767 &nir_fand,
2768 &nir_fany_nequal2,
2769 &nir_fany_nequal3,
2770 &nir_fany_nequal4,
2771 &nir_fceil,
2772 &nir_fcos,
2773 &nir_fcsel,
2774 &nir_fddx,
2775 &nir_fddx_coarse,
2776 &nir_fddx_fine,
2777 &nir_fddy,
2778 &nir_fddy_coarse,
2779 &nir_fddy_fine,
2780 &nir_fdiv,
2781 &nir_fdot2,
2782 &nir_fdot3,
2783 &nir_fdot4,
2784 &nir_fdot_replicated2,
2785 &nir_fdot_replicated3,
2786 &nir_fdot_replicated4,
2787 &nir_fdph,
2788 &nir_fdph_replicated,
2789 &nir_feq,
2790 &nir_feq32,
2791 &nir_fexp2,
2792 &nir_ffloor,
2793 &nir_ffma,
2794 &nir_ffract,
2795 &nir_fge,
2796 &nir_fge32,
2797 &nir_find_lsb,
2798 &nir_flog2,
2799 &nir_flrp,
2800 &nir_flt,
2801 &nir_flt32,
2802 &nir_fmax,
2803 &nir_fmax3,
2804 &nir_fmed3,
2805 &nir_fmin,
2806 &nir_fmin3,
2807 &nir_fmod,
2808 &nir_fmov,
2809 &nir_fmul,
2810 &nir_fne,
2811 &nir_fne32,
2812 &nir_fneg,
2813 &nir_fnoise1_1,
2814 &nir_fnoise1_2,
2815 &nir_fnoise1_3,
2816 &nir_fnoise1_4,
2817 &nir_fnoise2_1,
2818 &nir_fnoise2_2,
2819 &nir_fnoise2_3,
2820 &nir_fnoise2_4,
2821 &nir_fnoise3_1,
2822 &nir_fnoise3_2,
2823 &nir_fnoise3_3,
2824 &nir_fnoise3_4,
2825 &nir_fnoise4_1,
2826 &nir_fnoise4_2,
2827 &nir_fnoise4_3,
2828 &nir_fnoise4_4,
2829 &nir_fnot,
2830 &nir_for,
2831 &nir_fpow,
2832 &nir_fquantize2f16,
2833 &nir_frcp,
2834 &nir_frem,
2835 &nir_frexp_exp,
2836 &nir_frexp_sig,
2837 &nir_fround_even,
2838 &nir_frsq,
2839 &nir_fsat,
2840 &nir_fsign,
2841 &nir_fsin,
2842 &nir_fsqrt,
2843 &nir_fsub,
2844 &nir_ftrunc,
2845 &nir_fxor,
2846 &nir_i2b1,
2847 &nir_i2b32,
2848 &nir_i2f16,
2849 &nir_i2f32,
2850 &nir_i2f64,
2851 &nir_i2i1,
2852 &nir_i2i16,
2853 &nir_i2i32,
2854 &nir_i2i64,
2855 &nir_i2i8,
2856 &nir_iabs,
2857 &nir_iadd,
2858 &nir_iadd_sat,
2859 &nir_iand,
2860 &nir_ibfe,
2861 &nir_ibitfield_extract,
2862 &nir_idiv,
2863 &nir_ieq,
2864 &nir_ieq32,
2865 &nir_ifind_msb,
2866 &nir_ige,
2867 &nir_ige32,
2868 &nir_ihadd,
2869 &nir_ilt,
2870 &nir_ilt32,
2871 &nir_imax,
2872 &nir_imax3,
2873 &nir_imed3,
2874 &nir_imin,
2875 &nir_imin3,
2876 &nir_imod,
2877 &nir_imov,
2878 &nir_imul,
2879 &nir_imul_2x32_64,
2880 &nir_imul_high,
2881 &nir_ine,
2882 &nir_ine32,
2883 &nir_ineg,
2884 &nir_inot,
2885 &nir_ior,
2886 &nir_irem,
2887 &nir_irhadd,
2888 &nir_ishl,
2889 &nir_ishr,
2890 &nir_isign,
2891 &nir_isub,
2892 &nir_isub_sat,
2893 &nir_ixor,
2894 &nir_ldexp,
2895 &nir_pack_32_2x16,
2896 &nir_pack_32_2x16_split,
2897 &nir_pack_64_2x32,
2898 &nir_pack_64_2x32_split,
2899 &nir_pack_64_4x16,
2900 &nir_pack_half_2x16,
2901 &nir_pack_half_2x16_split,
2902 &nir_pack_snorm_2x16,
2903 &nir_pack_snorm_4x8,
2904 &nir_pack_unorm_2x16,
2905 &nir_pack_unorm_4x8,
2906 &nir_pack_uvec2_to_uint,
2907 &nir_pack_uvec4_to_uint,
2908 &nir_seq,
2909 &nir_sge,
2910 &nir_slt,
2911 &nir_sne,
2912 &nir_u2f16,
2913 &nir_u2f32,
2914 &nir_u2f64,
2915 &nir_u2u1,
2916 &nir_u2u16,
2917 &nir_u2u32,
2918 &nir_u2u64,
2919 &nir_u2u8,
2920 &nir_uadd_carry,
2921 &nir_uadd_sat,
2922 &nir_ubfe,
2923 &nir_ubitfield_extract,
2924 &nir_udiv,
2925 &nir_ufind_msb,
2926 &nir_uge,
2927 &nir_uge32,
2928 &nir_uhadd,
2929 &nir_ult,
2930 &nir_ult32,
2931 &nir_umax,
2932 &nir_umax3,
2933 &nir_umax_4x8,
2934 &nir_umed3,
2935 &nir_umin,
2936 &nir_umin3,
2937 &nir_umin_4x8,
2938 &nir_umod,
2939 &nir_umul_2x32_64,
2940 &nir_umul_high,
2941 &nir_umul_unorm_4x8,
2942 &nir_unpack_32_2x16,
2943 &nir_unpack_32_2x16_split_x,
2944 &nir_unpack_32_2x16_split_y,
2945 &nir_unpack_64_2x32,
2946 &nir_unpack_64_2x32_split_x,
2947 &nir_unpack_64_2x32_split_y,
2948 &nir_unpack_64_4x16,
2949 &nir_unpack_half_2x16,
2950 &nir_unpack_half_2x16_split_x,
2951 &nir_unpack_half_2x16_split_y,
2952 &nir_unpack_snorm_2x16,
2953 &nir_unpack_snorm_4x8,
2954 &nir_unpack_unorm_2x16,
2955 &nir_unpack_unorm_4x8,
2956 &nir_urhadd,
2957 &nir_usadd_4x8,
2958 &nir_ushr,
2959 &nir_ussub_4x8,
2960 &nir_usub_borrow,
2961 &nir_usub_sat,
2962 &nir_vec2,
2963 &nir_vec3,
2964 &nir_vec4,
2965 };
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c added (mode: 100644) (index 0000000..9613fc8)
1 #define NIR_INTRINSIC_SRCS_N_MAX 5
2
3 #define NIR_INTRINSIC_IDX_BASE 1
4 #define NIR_INTRINSIC_IDX_WRMASK 2
5 #define NIR_INTRINSIC_IDX_STREAM_ID 3
6 #define NIR_INTRINSIC_IDX_UCP_ID 4
7 #define NIR_INTRINSIC_IDX_RANGE 5
8 #define NIR_INTRINSIC_IDX_DESC_SET 6
9 #define NIR_INTRINSIC_IDX_BINDING 7
10 #define NIR_INTRINSIC_IDX_COMPONENT 8
11 #define NIR_INTRINSIC_IDX_INTERP_MODE 9
12 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10
13 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11
14 #define NIR_INTRINSIC_IDX_PARAM_IDX 12
15 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13
16 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14
17 #define NIR_INTRINSIC_IDX_FORMAT 15
18 #define NIR_INTRINSIC_IDX_ACCESS 16
19 #define NIR_INTRINSIC_IDX_ALIGN_MUL 17
20 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 18
21 #define NIR_INTRINSIC_IDX_DESC_TYPE 19
22 #define NIR_INTRINSIC_IDXS_N_MAX 20
23
24 #define NIR_INTRINSIC_FLAGS_CAN_ELIMINATE 0x01
25 #define NIR_INTRINSIC_FLAGS_CAN_REORDER 0x02
26
27 struct nir_intrinsic {
28 char *name;
29 u8 srcs_n;
30 s8 src_components_n[NIR_INTRINSIC_SRCS_N_MAX];
31 /* dest_components_n being 0 does not mean there is no dest components */
32 bool has_dest;
33 u8 dest_components_n;
34 u8 idxs_n;
35 u32 idxs_map[NIR_INTRINSIC_IDXS_N_MAX];
36 u32 bit_szs; /* only valid szs are power of 2 bit szs */
37 u8 flags;
38 bool system_value;
39 };
40
41 struct nir_intrinsic nir_atomic_counter_add = {
42 .name = "atomic_counter_add",
43 .srcs_n = 2,
44 .src_components_n = {
45 1,1
46 },
47 .has_dest = true,
48 .dest_components_n = 1,
49 .idxs_n = 1,
50 .idxs_map = {
51 [NIR_INTRINSIC_IDX_BASE] = 1
52 }
53 };
54 struct nir_intrinsic nir_atomic_counter_add_deref = {
55 .name = "atomic_counter_add_deref",
56 .srcs_n = 2,
57 .src_components_n = {
58 -1,1
59 },
60 .has_dest = true,
61 .dest_components_n = 1
62 };
63 struct nir_intrinsic nir_atomic_counter_and = {
64 .name = "atomic_counter_and",
65 .srcs_n = 2,
66 .src_components_n = {
67 1,1
68 },
69 .has_dest = true,
70 .dest_components_n = 1,
71 .idxs_n = 1,
72 .idxs_map = {
73 [NIR_INTRINSIC_IDX_BASE] = 1
74 }
75 };
76 struct nir_intrinsic nir_atomic_counter_and_deref = {
77 .name = "atomic_counter_and_deref",
78 .srcs_n = 2,
79 .src_components_n = {
80 -1,1
81 },
82 .has_dest = true,
83 .dest_components_n = 1
84 };
85 struct nir_intrinsic nir_atomic_counter_comp_swap = {
86 .name = "atomic_counter_comp_swap",
87 .srcs_n = 3,
88 .src_components_n = {
89 1,1,1
90 },
91 .has_dest = true,
92 .dest_components_n = 1,
93 .idxs_n = 1,
94 .idxs_map = {
95 [NIR_INTRINSIC_IDX_BASE] = 1
96 }
97 };
98 struct nir_intrinsic nir_atomic_counter_comp_swap_deref = {
99 .name = "atomic_counter_comp_swap_deref",
100 .srcs_n = 3,
101 .src_components_n = {
102 -1,1,1
103 },
104 .has_dest = true,
105 .dest_components_n = 1
106 };
107 struct nir_intrinsic nir_atomic_counter_exchange = {
108 .name = "atomic_counter_exchange",
109 .srcs_n = 2,
110 .src_components_n = {
111 1,1
112 },
113 .has_dest = true,
114 .dest_components_n = 1,
115 .idxs_n = 1,
116 .idxs_map = {
117 [NIR_INTRINSIC_IDX_BASE] = 1
118 }
119 };
120 struct nir_intrinsic nir_atomic_counter_exchange_deref = {
121 .name = "atomic_counter_exchange_deref",
122 .srcs_n = 2,
123 .src_components_n = {
124 -1,1
125 },
126 .has_dest = true,
127 .dest_components_n = 1
128 };
129 struct nir_intrinsic nir_atomic_counter_inc = {
130 .name = "atomic_counter_inc",
131 .srcs_n = 1,
132 .src_components_n = {
133 1
134 },
135 .has_dest = true,
136 .dest_components_n = 1,
137 .idxs_n = 1,
138 .idxs_map = {
139 [NIR_INTRINSIC_IDX_BASE] = 1
140 }
141 };
142 struct nir_intrinsic nir_atomic_counter_inc_deref = {
143 .name = "atomic_counter_inc_deref",
144 .srcs_n = 1,
145 .src_components_n = {
146 -1
147 },
148 .has_dest = true,
149 .dest_components_n = 1
150 };
151 struct nir_intrinsic nir_atomic_counter_max = {
152 .name = "atomic_counter_max",
153 .srcs_n = 2,
154 .src_components_n = {
155 1,1
156 },
157 .has_dest = true,
158 .dest_components_n = 1,
159 .idxs_n = 1,
160 .idxs_map = {
161 [NIR_INTRINSIC_IDX_BASE] = 1
162 }
163 };
164 struct nir_intrinsic nir_atomic_counter_max_deref = {
165 .name = "atomic_counter_max_deref",
166 .srcs_n = 2,
167 .src_components_n = {
168 -1,1
169 },
170 .has_dest = true,
171 .dest_components_n = 1
172 };
173 struct nir_intrinsic nir_atomic_counter_min = {
174 .name = "atomic_counter_min",
175 .srcs_n = 2,
176 .src_components_n = {
177 1,1
178 },
179 .has_dest = true,
180 .dest_components_n = 1,
181 .idxs_n = 1,
182 .idxs_map = {
183 [NIR_INTRINSIC_IDX_BASE] = 1
184 }
185 };
186 struct nir_intrinsic nir_atomic_counter_min_deref = {
187 .name = "atomic_counter_min_deref",
188 .srcs_n = 2,
189 .src_components_n = {
190 -1,1
191 },
192 .has_dest = true,
193 .dest_components_n = 1
194 };
195 struct nir_intrinsic nir_atomic_counter_or = {
196 .name = "atomic_counter_or",
197 .srcs_n = 2,
198 .src_components_n = {
199 1,1
200 },
201 .has_dest = true,
202 .dest_components_n = 1,
203 .idxs_n = 1,
204 .idxs_map = {
205 [NIR_INTRINSIC_IDX_BASE] = 1
206 }
207 };
208 struct nir_intrinsic nir_atomic_counter_or_deref = {
209 .name = "atomic_counter_or_deref",
210 .srcs_n = 2,
211 .src_components_n = {
212 -1,1
213 },
214 .has_dest = true,
215 .dest_components_n = 1
216 };
217 struct nir_intrinsic nir_atomic_counter_post_dec = {
218 .name = "atomic_counter_post_dec",
219 .srcs_n = 1,
220 .src_components_n = {
221 1
222 },
223 .has_dest = true,
224 .dest_components_n = 1,
225 .idxs_n = 1,
226 .idxs_map = {
227 [NIR_INTRINSIC_IDX_BASE] = 1
228 }
229 };
230 struct nir_intrinsic nir_atomic_counter_post_dec_deref = {
231 .name = "atomic_counter_post_dec_deref",
232 .srcs_n = 1,
233 .src_components_n = {
234 -1
235 },
236 .has_dest = true,
237 .dest_components_n = 1
238 };
239 struct nir_intrinsic nir_atomic_counter_pre_dec = {
240 .name = "atomic_counter_pre_dec",
241 .srcs_n = 1,
242 .src_components_n = {
243 1
244 },
245 .has_dest = true,
246 .dest_components_n = 1,
247 .idxs_n = 1,
248 .idxs_map = {
249 [NIR_INTRINSIC_IDX_BASE] = 1
250 }
251 };
252 struct nir_intrinsic nir_atomic_counter_pre_dec_deref = {
253 .name = "atomic_counter_pre_dec_deref",
254 .srcs_n = 1,
255 .src_components_n = {
256 -1
257 },
258 .has_dest = true,
259 .dest_components_n = 1
260 };
261 struct nir_intrinsic nir_atomic_counter_read = {
262 .name = "atomic_counter_read",
263 .srcs_n = 1,
264 .src_components_n = {
265 1
266 },
267 .has_dest = true,
268 .dest_components_n = 1,
269 .idxs_n = 1,
270 .idxs_map = {
271 [NIR_INTRINSIC_IDX_BASE] = 1
272 },
273 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
274 };
275 struct nir_intrinsic nir_atomic_counter_read_deref = {
276 .name = "atomic_counter_read_deref",
277 .srcs_n = 1,
278 .src_components_n = {
279 -1
280 },
281 .has_dest = true,
282 .dest_components_n = 1,
283 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
284 };
285 struct nir_intrinsic nir_atomic_counter_xor = {
286 .name = "atomic_counter_xor",
287 .srcs_n = 2,
288 .src_components_n = {
289 1,1
290 },
291 .has_dest = true,
292 .dest_components_n = 1,
293 .idxs_n = 1,
294 .idxs_map = {
295 [NIR_INTRINSIC_IDX_BASE] = 1
296 }
297 };
298 struct nir_intrinsic nir_atomic_counter_xor_deref = {
299 .name = "atomic_counter_xor_deref",
300 .srcs_n = 2,
301 .src_components_n = {
302 -1,1
303 },
304 .has_dest = true,
305 .dest_components_n = 1
306 };
307 struct nir_intrinsic nir_ballot = {
308 .name = "ballot",
309 .srcs_n = 1,
310 .src_components_n = {
311 1
312 },
313 .has_dest = true,
314 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
315 };
316 struct nir_intrinsic nir_ballot_bit_count_exclusive = {
317 .name = "ballot_bit_count_exclusive",
318 .srcs_n = 1,
319 .src_components_n = {
320 4
321 },
322 .has_dest = true,
323 .dest_components_n = 1,
324 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
325 };
326 struct nir_intrinsic nir_ballot_bit_count_inclusive = {
327 .name = "ballot_bit_count_inclusive",
328 .srcs_n = 1,
329 .src_components_n = {
330 4
331 },
332 .has_dest = true,
333 .dest_components_n = 1,
334 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
335 };
336 struct nir_intrinsic nir_ballot_bit_count_reduce = {
337 .name = "ballot_bit_count_reduce",
338 .srcs_n = 1,
339 .src_components_n = {
340 4
341 },
342 .has_dest = true,
343 .dest_components_n = 1,
344 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
345 };
346 struct nir_intrinsic nir_ballot_bitfield_extract = {
347 .name = "ballot_bitfield_extract",
348 .srcs_n = 2,
349 .src_components_n = {
350 4,1
351 },
352 .has_dest = true,
353 .dest_components_n = 1,
354 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
355 };
356 struct nir_intrinsic nir_ballot_find_lsb = {
357 .name = "ballot_find_lsb",
358 .srcs_n = 1,
359 .src_components_n = {
360 4
361 },
362 .has_dest = true,
363 .dest_components_n = 1,
364 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
365 };
366 struct nir_intrinsic nir_ballot_find_msb = {
367 .name = "ballot_find_msb",
368 .srcs_n = 1,
369 .src_components_n = {
370 4
371 },
372 .has_dest = true,
373 .dest_components_n = 1,
374 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
375 };
376 struct nir_intrinsic nir_barrier = {
377 .name = "barrier"
378 };
379 struct nir_intrinsic nir_begin_invocation_interlock = {
380 .name = "begin_invocation_interlock"
381 };
382 struct nir_intrinsic nir_copy_deref = {
383 .name = "copy_deref",
384 .srcs_n = 2,
385 .src_components_n = {
386 -1,-1
387 }
388 };
389 struct nir_intrinsic nir_deref_atomic_add = {
390 .name = "deref_atomic_add",
391 .srcs_n = 2,
392 .src_components_n = {
393 -1,1
394 },
395 .has_dest = true,
396 .dest_components_n = 1,
397 .idxs_n = 1,
398 .idxs_map = {
399 [NIR_INTRINSIC_IDX_ACCESS] = 1
400 }
401 };
402 struct nir_intrinsic nir_deref_atomic_and = {
403 .name = "deref_atomic_and",
404 .srcs_n = 2,
405 .src_components_n = {
406 -1,1
407 },
408 .has_dest = true,
409 .dest_components_n = 1,
410 .idxs_n = 1,
411 .idxs_map = {
412 [NIR_INTRINSIC_IDX_ACCESS] = 1
413 }
414 };
415 struct nir_intrinsic nir_deref_atomic_comp_swap = {
416 .name = "deref_atomic_comp_swap",
417 .srcs_n = 3,
418 .src_components_n = {
419 -1,1,1
420 },
421 .has_dest = true,
422 .dest_components_n = 1,
423 .idxs_n = 1,
424 .idxs_map = {
425 [NIR_INTRINSIC_IDX_ACCESS] = 1
426 }
427 };
428 struct nir_intrinsic nir_deref_atomic_exchange = {
429 .name = "deref_atomic_exchange",
430 .srcs_n = 2,
431 .src_components_n = {
432 -1,1
433 },
434 .has_dest = true,
435 .dest_components_n = 1,
436 .idxs_n = 1,
437 .idxs_map = {
438 [NIR_INTRINSIC_IDX_ACCESS] = 1
439 }
440 };
441 struct nir_intrinsic nir_deref_atomic_fadd = {
442 .name = "deref_atomic_fadd",
443 .srcs_n = 2,
444 .src_components_n = {
445 -1,1
446 },
447 .has_dest = true,
448 .dest_components_n = 1,
449 .idxs_n = 1,
450 .idxs_map = {
451 [NIR_INTRINSIC_IDX_ACCESS] = 1
452 }
453 };
454 struct nir_intrinsic nir_deref_atomic_fcomp_swap = {
455 .name = "deref_atomic_fcomp_swap",
456 .srcs_n = 3,
457 .src_components_n = {
458 -1,1,1
459 },
460 .has_dest = true,
461 .dest_components_n = 1,
462 .idxs_n = 1,
463 .idxs_map = {
464 [NIR_INTRINSIC_IDX_ACCESS] = 1
465 }
466 };
467 struct nir_intrinsic nir_deref_atomic_fmax = {
468 .name = "deref_atomic_fmax",
469 .srcs_n = 2,
470 .src_components_n = {
471 -1,1
472 },
473 .has_dest = true,
474 .dest_components_n = 1,
475 .idxs_n = 1,
476 .idxs_map = {
477 [NIR_INTRINSIC_IDX_ACCESS] = 1
478 }
479 };
480 struct nir_intrinsic nir_deref_atomic_fmin = {
481 .name = "deref_atomic_fmin",
482 .srcs_n = 2,
483 .src_components_n = {
484 -1,1
485 },
486 .has_dest = true,
487 .dest_components_n = 1,
488 .idxs_n = 1,
489 .idxs_map = {
490 [NIR_INTRINSIC_IDX_ACCESS] = 1
491 }
492 };
493 struct nir_intrinsic nir_deref_atomic_imax = {
494 .name = "deref_atomic_imax",
495 .srcs_n = 2,
496 .src_components_n = {
497 -1,1
498 },
499 .has_dest = true,
500 .dest_components_n = 1,
501 .idxs_n = 1,
502 .idxs_map = {
503 [NIR_INTRINSIC_IDX_ACCESS] = 1
504 }
505 };
506 struct nir_intrinsic nir_deref_atomic_imin = {
507 .name = "deref_atomic_imin",
508 .srcs_n = 2,
509 .src_components_n = {
510 -1,1
511 },
512 .has_dest = true,
513 .dest_components_n = 1,
514 .idxs_n = 1,
515 .idxs_map = {
516 [NIR_INTRINSIC_IDX_ACCESS] = 1
517 }
518 };
519 struct nir_intrinsic nir_deref_atomic_or = {
520 .name = "deref_atomic_or",
521 .srcs_n = 2,
522 .src_components_n = {
523 -1,1
524 },
525 .has_dest = true,
526 .dest_components_n = 1,
527 .idxs_n = 1,
528 .idxs_map = {
529 [NIR_INTRINSIC_IDX_ACCESS] = 1
530 }
531 };
532 struct nir_intrinsic nir_deref_atomic_umax = {
533 .name = "deref_atomic_umax",
534 .srcs_n = 2,
535 .src_components_n = {
536 -1,1
537 },
538 .has_dest = true,
539 .dest_components_n = 1,
540 .idxs_n = 1,
541 .idxs_map = {
542 [NIR_INTRINSIC_IDX_ACCESS] = 1
543 }
544 };
545 struct nir_intrinsic nir_deref_atomic_umin = {
546 .name = "deref_atomic_umin",
547 .srcs_n = 2,
548 .src_components_n = {
549 -1,1
550 },
551 .has_dest = true,
552 .dest_components_n = 1,
553 .idxs_n = 1,
554 .idxs_map = {
555 [NIR_INTRINSIC_IDX_ACCESS] = 1
556 }
557 };
558 struct nir_intrinsic nir_deref_atomic_xor = {
559 .name = "deref_atomic_xor",
560 .srcs_n = 2,
561 .src_components_n = {
562 -1,1
563 },
564 .has_dest = true,
565 .dest_components_n = 1,
566 .idxs_n = 1,
567 .idxs_map = {
568 [NIR_INTRINSIC_IDX_ACCESS] = 1
569 }
570 };
571 struct nir_intrinsic nir_discard = {
572 .name = "discard"
573 };
574 struct nir_intrinsic nir_discard_if = {
575 .name = "discard_if",
576 .srcs_n = 1,
577 .src_components_n = {
578 1
579 }
580 };
581 struct nir_intrinsic nir_elect = {
582 .name = "elect",
583 .has_dest = true,
584 .dest_components_n = 1,
585 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
586 };
587 struct nir_intrinsic nir_emit_vertex = {
588 .name = "emit_vertex",
589 .idxs_n = 1,
590 .idxs_map = {
591 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
592 }
593 };
594 struct nir_intrinsic nir_emit_vertex_with_counter = {
595 .name = "emit_vertex_with_counter",
596 .srcs_n = 1,
597 .src_components_n = {
598 1
599 },
600 .idxs_n = 1,
601 .idxs_map = {
602 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
603 }
604 };
605 struct nir_intrinsic nir_end_invocation_interlock = {
606 .name = "end_invocation_interlock"
607 };
608 struct nir_intrinsic nir_end_primitive = {
609 .name = "end_primitive",
610 .idxs_n = 1,
611 .idxs_map = {
612 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
613 }
614 };
615 struct nir_intrinsic nir_end_primitive_with_counter = {
616 .name = "end_primitive_with_counter",
617 .srcs_n = 1,
618 .src_components_n = {
619 1
620 },
621 .idxs_n = 1,
622 .idxs_map = {
623 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
624 }
625 };
626 struct nir_intrinsic nir_exclusive_scan = {
627 .name = "exclusive_scan",
628 .srcs_n = 1,
629 .src_components_n = {
630 0
631 },
632 .has_dest = true,
633 .idxs_n = 1,
634 .idxs_map = {
635 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1
636 },
637 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
638 };
639 struct nir_intrinsic nir_first_invocation = {
640 .name = "first_invocation",
641 .has_dest = true,
642 .dest_components_n = 1,
643 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
644 };
645 struct nir_intrinsic nir_get_buffer_size = {
646 .name = "get_buffer_size",
647 .srcs_n = 1,
648 .src_components_n = {
649 1
650 },
651 .has_dest = true,
652 .dest_components_n = 1,
653 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
654 };
655 struct nir_intrinsic nir_global_atomic_add = {
656 .name = "global_atomic_add",
657 .srcs_n = 2,
658 .src_components_n = {
659 1,1
660 },
661 .has_dest = true,
662 .dest_components_n = 1,
663 .idxs_n = 1,
664 .idxs_map = {
665 [NIR_INTRINSIC_IDX_BASE] = 1
666 }
667 };
668 struct nir_intrinsic nir_global_atomic_and = {
669 .name = "global_atomic_and",
670 .srcs_n = 2,
671 .src_components_n = {
672 1,1
673 },
674 .has_dest = true,
675 .dest_components_n = 1,
676 .idxs_n = 1,
677 .idxs_map = {
678 [NIR_INTRINSIC_IDX_BASE] = 1
679 }
680 };
681 struct nir_intrinsic nir_global_atomic_comp_swap = {
682 .name = "global_atomic_comp_swap",
683 .srcs_n = 3,
684 .src_components_n = {
685 1,1,1
686 },
687 .has_dest = true,
688 .dest_components_n = 1,
689 .idxs_n = 1,
690 .idxs_map = {
691 [NIR_INTRINSIC_IDX_BASE] = 1
692 }
693 };
694 struct nir_intrinsic nir_global_atomic_exchange = {
695 .name = "global_atomic_exchange",
696 .srcs_n = 2,
697 .src_components_n = {
698 1,1
699 },
700 .has_dest = true,
701 .dest_components_n = 1,
702 .idxs_n = 1,
703 .idxs_map = {
704 [NIR_INTRINSIC_IDX_BASE] = 1
705 }
706 };
707 struct nir_intrinsic nir_global_atomic_fadd = {
708 .name = "global_atomic_fadd",
709 .srcs_n = 2,
710 .src_components_n = {
711 1,1
712 },
713 .has_dest = true,
714 .dest_components_n = 1,
715 .idxs_n = 1,
716 .idxs_map = {
717 [NIR_INTRINSIC_IDX_BASE] = 1
718 }
719 };
720 struct nir_intrinsic nir_global_atomic_fcomp_swap = {
721 .name = "global_atomic_fcomp_swap",
722 .srcs_n = 3,
723 .src_components_n = {
724 1,1,1
725 },
726 .has_dest = true,
727 .dest_components_n = 1,
728 .idxs_n = 1,
729 .idxs_map = {
730 [NIR_INTRINSIC_IDX_BASE] = 1
731 }
732 };
733 struct nir_intrinsic nir_global_atomic_fmax = {
734 .name = "global_atomic_fmax",
735 .srcs_n = 2,
736 .src_components_n = {
737 1,1
738 },
739 .has_dest = true,
740 .dest_components_n = 1,
741 .idxs_n = 1,
742 .idxs_map = {
743 [NIR_INTRINSIC_IDX_BASE] = 1
744 }
745 };
746 struct nir_intrinsic nir_global_atomic_fmin = {
747 .name = "global_atomic_fmin",
748 .srcs_n = 2,
749 .src_components_n = {
750 1,1
751 },
752 .has_dest = true,
753 .dest_components_n = 1,
754 .idxs_n = 1,
755 .idxs_map = {
756 [NIR_INTRINSIC_IDX_BASE] = 1
757 }
758 };
759 struct nir_intrinsic nir_global_atomic_imax = {
760 .name = "global_atomic_imax",
761 .srcs_n = 2,
762 .src_components_n = {
763 1,1
764 },
765 .has_dest = true,
766 .dest_components_n = 1,
767 .idxs_n = 1,
768 .idxs_map = {
769 [NIR_INTRINSIC_IDX_BASE] = 1
770 }
771 };
772 struct nir_intrinsic nir_global_atomic_imin = {
773 .name = "global_atomic_imin",
774 .srcs_n = 2,
775 .src_components_n = {
776 1,1
777 },
778 .has_dest = true,
779 .dest_components_n = 1,
780 .idxs_n = 1,
781 .idxs_map = {
782 [NIR_INTRINSIC_IDX_BASE] = 1
783 }
784 };
785 struct nir_intrinsic nir_global_atomic_or = {
786 .name = "global_atomic_or",
787 .srcs_n = 2,
788 .src_components_n = {
789 1,1
790 },
791 .has_dest = true,
792 .dest_components_n = 1,
793 .idxs_n = 1,
794 .idxs_map = {
795 [NIR_INTRINSIC_IDX_BASE] = 1
796 }
797 };
798 struct nir_intrinsic nir_global_atomic_umax = {
799 .name = "global_atomic_umax",
800 .srcs_n = 2,
801 .src_components_n = {
802 1,1
803 },
804 .has_dest = true,
805 .dest_components_n = 1,
806 .idxs_n = 1,
807 .idxs_map = {
808 [NIR_INTRINSIC_IDX_BASE] = 1
809 }
810 };
811 struct nir_intrinsic nir_global_atomic_umin = {
812 .name = "global_atomic_umin",
813 .srcs_n = 2,
814 .src_components_n = {
815 1,1
816 },
817 .has_dest = true,
818 .dest_components_n = 1,
819 .idxs_n = 1,
820 .idxs_map = {
821 [NIR_INTRINSIC_IDX_BASE] = 1
822 }
823 };
824 struct nir_intrinsic nir_global_atomic_xor = {
825 .name = "global_atomic_xor",
826 .srcs_n = 2,
827 .src_components_n = {
828 1,1
829 },
830 .has_dest = true,
831 .dest_components_n = 1,
832 .idxs_n = 1,
833 .idxs_map = {
834 [NIR_INTRINSIC_IDX_BASE] = 1
835 }
836 };
837 struct nir_intrinsic nir_group_memory_barrier = {
838 .name = "group_memory_barrier"
839 };
840 /******************************************************************************/
841 /*
842 * Image load, store and atomic intrinsics.
843 *
844 * All image intrinsics come in three versions. One which take an image target
845 * passed as a deref chain as the first source, one which takes an index as the
846 * first source, and one which takes a bindless handle as the first source.
847 * In the first version, the image variable contains the memory and layout
848 * qualifiers that influence the semantics of the intrinsic. In the second and
849 * third, the image format and access qualifiers are provided as constant
850 * indices.
851
852 * All image intrinsics take a four-coordinate vector and a sample index as
853 * 2nd and 3rd sources, determining the location within the image that will be
854 */
855 /*----------------------------------------------------------------------------*/
856 /* deref version */
857 struct nir_intrinsic nir_image_deref_load = {
858 .name = "image_deref_load",
859 .srcs_n = 3,
860 .src_components_n = {
861 1,4,1
862 },
863 .has_dest = true,
864 .dest_components_n = 0,
865 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
866 };
867 struct nir_intrinsic nir_image_deref_store = {
868 .name = "image_deref_store",
869 .srcs_n = 4,
870 .src_components_n = {
871 1,4,1,0
872 }
873 };
874 struct nir_intrinsic nir_image_deref_atomic_add = {
875 .name = "image_deref_atomic_add",
876 .srcs_n = 4,
877 .src_components_n = {
878 1,4,1,1
879 },
880 .has_dest = true,
881 .dest_components_n = 1
882 };
883 struct nir_intrinsic nir_image_deref_atomic_min = {
884 .name = "image_deref_atomic_min",
885 .srcs_n = 4,
886 .src_components_n = {
887 1,4,1,1
888 },
889 .has_dest = true,
890 .dest_components_n = 1
891 };
892 struct nir_intrinsic nir_image_deref_atomic_max = {
893 .name = "image_deref_atomic_max",
894 .srcs_n = 4,
895 .src_components_n = {
896 1,4,1,1
897 },
898 .has_dest = true,
899 .dest_components_n = 1
900 };
901 struct nir_intrinsic nir_image_deref_atomic_and = {
902 .name = "image_deref_atomic_and",
903 .srcs_n = 4,
904 .src_components_n = {
905 1,4,1,1
906 },
907 .has_dest = true,
908 .dest_components_n = 1
909 };
910 struct nir_intrinsic nir_image_deref_atomic_or = {
911 .name = "image_deref_atomic_or",
912 .srcs_n = 4,
913 .src_components_n = {
914 1,4,1,1
915 },
916 .has_dest = true,
917 .dest_components_n = 1
918 };
919 struct nir_intrinsic nir_image_deref_atomic_xor = {
920 .name = "image_deref_atomic_xor",
921 .srcs_n = 4,
922 .src_components_n = {
923 1,4,1,1
924 },
925 .has_dest = true,
926 .dest_components_n = 1
927 };
928 struct nir_intrinsic nir_image_deref_atomic_exchange = {
929 .name = "image_deref_atomic_exchange",
930 .srcs_n = 4,
931 .src_components_n = {
932 1,4,1,1
933 },
934 .has_dest = true,
935 .dest_components_n = 1
936 };
937 struct nir_intrinsic nir_image_deref_atomic_comp_swap = {
938 .name = "image_deref_atomic_comp_swap",
939 .srcs_n = 5,
940 .src_components_n = {
941 1,4,1,1,1
942 },
943 .has_dest = true,
944 .dest_components_n = 1
945 };
946 struct nir_intrinsic nir_image_deref_atomic_fadd = {
947 .name = "image_deref_atomic_fadd",
948 .srcs_n = 5,
949 .src_components_n = {
950 1,1,4,1,1
951 },
952 .has_dest = true,
953 .dest_components_n = 1
954 };
955 struct nir_intrinsic nir_image_deref_size = {
956 .name = "image_deref_size",
957 .srcs_n = 1,
958 .src_components_n = {
959 1
960 },
961 .has_dest = true,
962 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
963 };
964 struct nir_intrinsic nir_image_deref_samples = {
965 .name = "image_deref_samples",
966 .srcs_n = 1,
967 .src_components_n = {
968 1
969 },
970 .has_dest = true,
971 .dest_components_n = 1,
972 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
973 };
974 struct nir_intrinsic nir_image_deref_load_raw_intel = {
975 .name = "image_deref_load_raw_intel",
976 .srcs_n = 2,
977 .src_components_n = {
978 1,1
979 },
980 .has_dest = true,
981 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
982 };
983 struct nir_intrinsic nir_image_deref_store_raw_intel = {
984 .name = "image_deref_store_raw_intel",
985 .srcs_n = 3,
986 .src_components_n = {
987 1,1,0
988 }
989 };
990 /* deref version */
991 /*----------------------------------------------------------------------------*/
992 /* plain version */
993 struct nir_intrinsic nir_image_load = {
994 .name = "image_load",
995 .srcs_n = 3,
996 .src_components_n = {
997 1,4,1
998 },
999 .has_dest = true,
1000 .idxs_n = 4,
1001 .idxs_map = {
1002 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1003 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1004 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1005 [NIR_INTRINSIC_IDX_ACCESS] = 4
1006 },
1007 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1008 };
1009 struct nir_intrinsic nir_image_store = {
1010 .name = "image_store",
1011 .srcs_n = 4,
1012 .src_components_n = {
1013 1,4,1,0
1014 },
1015 .idxs_n = 4,
1016 .idxs_map = {
1017 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1018 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1019 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1020 [NIR_INTRINSIC_IDX_ACCESS] = 4
1021 }
1022 };
1023 struct nir_intrinsic nir_image_atomic_add = {
1024 .name = "image_atomic_add",
1025 .srcs_n = 4,
1026 .src_components_n = {
1027 1,4,1,1
1028 },
1029 .has_dest = true,
1030 .dest_components_n = 1,
1031 .idxs_n = 4,
1032 .idxs_map = {
1033 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1034 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1035 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1036 [NIR_INTRINSIC_IDX_ACCESS] = 4
1037 }
1038 };
1039 struct nir_intrinsic nir_image_atomic_min = {
1040 .name = "image_atomic_min",
1041 .srcs_n = 4,
1042 .src_components_n = {
1043 1,4,1,1
1044 },
1045 .has_dest = true,
1046 .dest_components_n = 1,
1047 .idxs_n = 4,
1048 .idxs_map = {
1049 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1050 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1051 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1052 [NIR_INTRINSIC_IDX_ACCESS] = 4
1053 }
1054 };
1055 struct nir_intrinsic nir_image_atomic_max = {
1056 .name = "image_atomic_max",
1057 .srcs_n = 4,
1058 .src_components_n = {
1059 1,4,1,1
1060 },
1061 .has_dest = true,
1062 .dest_components_n = 1,
1063 .idxs_n = 4,
1064 .idxs_map = {
1065 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1066 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1067 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1068 [NIR_INTRINSIC_IDX_ACCESS] = 4
1069 }
1070 };
1071 struct nir_intrinsic nir_image_atomic_and = {
1072 .name = "image_atomic_and",
1073 .srcs_n = 4,
1074 .src_components_n = {
1075 1,4,1,1
1076 },
1077 .has_dest = true,
1078 .dest_components_n = 1,
1079 .idxs_n = 4,
1080 .idxs_map = {
1081 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1082 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1083 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1084 [NIR_INTRINSIC_IDX_ACCESS] = 4
1085 }
1086 };
1087 struct nir_intrinsic nir_image_atomic_or = {
1088 .name = "image_atomic_or",
1089 .srcs_n = 4,
1090 .src_components_n = {
1091 1,4,1,1
1092 },
1093 .has_dest = true,
1094 .dest_components_n = 1,
1095 .idxs_n = 4,
1096 .idxs_map = {
1097 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1098 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1099 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1100 [NIR_INTRINSIC_IDX_ACCESS] = 4
1101 }
1102 };
1103 struct nir_intrinsic nir_image_atomic_xor = {
1104 .name = "image_atomic_xor",
1105 .srcs_n = 4,
1106 .src_components_n = {
1107 1,4,1,1
1108 },
1109 .has_dest = true,
1110 .dest_components_n = 1,
1111 .idxs_n = 4,
1112 .idxs_map = {
1113 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1114 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1115 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1116 [NIR_INTRINSIC_IDX_ACCESS] = 4
1117 }
1118 };
1119 struct nir_intrinsic nir_image_atomic_exchange = {
1120 .name = "image_atomic_exchange",
1121 .srcs_n = 4,
1122 .src_components_n = {
1123 1,4,1,1
1124 },
1125 .has_dest = true,
1126 .dest_components_n = 1,
1127 .idxs_n = 4,
1128 .idxs_map = {
1129 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1130 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1131 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1132 [NIR_INTRINSIC_IDX_ACCESS] = 4
1133 }
1134 };
1135 struct nir_intrinsic nir_image_atomic_comp_swap = {
1136 .name = "image_atomic_comp_swap",
1137 .srcs_n = 5,
1138 .src_components_n = {
1139 1,4,1,1,1
1140 },
1141 .has_dest = true,
1142 .dest_components_n = 1,
1143 .idxs_n = 4,
1144 .idxs_map = {
1145 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1146 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1147 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1148 [NIR_INTRINSIC_IDX_ACCESS] = 4
1149 }
1150 };
1151 struct nir_intrinsic nir_image_atomic_fadd = {
1152 .name = "image_atomic_fadd",
1153 .srcs_n = 5,
1154 .src_components_n = {
1155 1,1,4,1,1
1156 },
1157 .has_dest = true,
1158 .dest_components_n = 1,
1159 .idxs_n = 4,
1160 .idxs_map = {
1161 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1162 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1163 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1164 [NIR_INTRINSIC_IDX_ACCESS] = 4
1165 }
1166 };
1167 struct nir_intrinsic nir_image_size = {
1168 .name = "image_size",
1169 .srcs_n = 1,
1170 .src_components_n = {
1171 1
1172 },
1173 .has_dest = true,
1174 .idxs_n = 4,
1175 .idxs_map = {
1176 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1177 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1178 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1179 [NIR_INTRINSIC_IDX_ACCESS] = 4
1180 },
1181 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1182 };
1183 struct nir_intrinsic nir_image_samples = {
1184 .name = "image_samples",
1185 .srcs_n = 1,
1186 .src_components_n = {
1187 1
1188 },
1189 .has_dest = true,
1190 .dest_components_n = 1,
1191 .idxs_n = 4,
1192 .idxs_map = {
1193 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1194 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1195 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1196 [NIR_INTRINSIC_IDX_ACCESS] = 4
1197 },
1198 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1199 };
1200 struct nir_intrinsic nir_image_load_raw_intel = {
1201 .name = "image_load_raw_intel",
1202 .srcs_n = 2,
1203 .src_components_n = {
1204 1,1
1205 },
1206 .has_dest = true,
1207 .idxs_n = 4,
1208 .idxs_map = {
1209 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1210 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1211 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1212 [NIR_INTRINSIC_IDX_ACCESS] = 4
1213 },
1214 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1215 };
1216 struct nir_intrinsic nir_image_store_raw_intel = {
1217 .name = "image_store_raw_intel",
1218 .srcs_n = 3,
1219 .src_components_n = {
1220 1,1,0
1221 },
1222 .idxs_n = 4,
1223 .idxs_map = {
1224 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1225 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1226 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1227 [NIR_INTRINSIC_IDX_ACCESS] = 4
1228 }
1229 };
1230 /* plain version */
1231 /*----------------------------------------------------------------------------*/
1232 /* bindless version */
1233 struct nir_intrinsic nir_bindless_image_load = {
1234 .name = "bindless_image_load",
1235 .srcs_n = 3,
1236 .src_components_n = {
1237 1,4,1
1238 },
1239 .has_dest = true,
1240 .idxs_n = 4,
1241 .idxs_map = {
1242 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1243 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1244 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1245 [NIR_INTRINSIC_IDX_ACCESS] = 4
1246 },
1247 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1248 };
1249 struct nir_intrinsic nir_bindless_image_store = {
1250 .name = "bindless_image_store",
1251 .srcs_n = 4,
1252 .src_components_n = {
1253 1,4,1,0
1254 },
1255 .idxs_n = 4,
1256 .idxs_map = {
1257 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1258 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1259 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1260 [NIR_INTRINSIC_IDX_ACCESS] = 4
1261 }
1262 };
1263 struct nir_intrinsic nir_bindless_image_atomic_add = {
1264 .name = "bindless_image_atomic_add",
1265 .srcs_n = 4,
1266 .src_components_n = {
1267 1,4,1,1
1268 },
1269 .has_dest = true,
1270 .dest_components_n = 1,
1271 .idxs_n = 4,
1272 .idxs_map = {
1273 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1274 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1275 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1276 [NIR_INTRINSIC_IDX_ACCESS] = 4
1277 }
1278 };
1279 struct nir_intrinsic nir_bindless_image_atomic_min = {
1280 .name = "bindless_image_atomic_min",
1281 .srcs_n = 4,
1282 .src_components_n = {
1283 1,4,1,1
1284 },
1285 .has_dest = true,
1286 .dest_components_n = 1,
1287 .idxs_n = 4,
1288 .idxs_map = {
1289 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1290 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1291 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1292 [NIR_INTRINSIC_IDX_ACCESS] = 4
1293 }
1294 };
1295 struct nir_intrinsic nir_bindless_image_atomic_max = {
1296 .name = "bindless_image_atomic_max",
1297 .srcs_n = 4,
1298 .src_components_n = {
1299 1,4,1,1
1300 },
1301 .has_dest = true,
1302 .dest_components_n = 1,
1303 .idxs_n = 4,
1304 .idxs_map = {
1305 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1306 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1307 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1308 [NIR_INTRINSIC_IDX_ACCESS] = 4
1309 }
1310 };
1311 struct nir_intrinsic nir_bindless_image_atomic_and = {
1312 .name = "bindless_image_atomic_and",
1313 .srcs_n = 4,
1314 .src_components_n = {
1315 1,4,1,1
1316 },
1317 .has_dest = true,
1318 .dest_components_n = 1,
1319 .idxs_n = 4,
1320 .idxs_map = {
1321 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1322 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1323 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1324 [NIR_INTRINSIC_IDX_ACCESS] = 4
1325 }
1326 };
1327 struct nir_intrinsic nir_bindless_image_atomic_or = {
1328 .name = "bindless_image_atomic_or",
1329 .srcs_n = 4,
1330 .src_components_n = {
1331 1,4,1,1
1332 },
1333 .has_dest = true,
1334 .dest_components_n = 1,
1335 .idxs_n = 4,
1336 .idxs_map = {
1337 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1338 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1339 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1340 [NIR_INTRINSIC_IDX_ACCESS] = 4
1341 }
1342 };
1343 struct nir_intrinsic nir_bindless_image_atomic_xor = {
1344 .name = "bindless_image_atomic_xor",
1345 .srcs_n = 4,
1346 .src_components_n = {
1347 1,4,1,1
1348 },
1349 .has_dest = true,
1350 .dest_components_n = 1,
1351 .idxs_n = 4,
1352 .idxs_map = {
1353 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1354 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1355 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1356 [NIR_INTRINSIC_IDX_ACCESS] = 4
1357 }
1358 };
1359 struct nir_intrinsic nir_bindless_image_atomic_exchange = {
1360 .name = "bindless_image_atomic_exchange",
1361 .srcs_n = 4,
1362 .src_components_n = {
1363 1,4,1,1
1364 },
1365 .has_dest = true,
1366 .dest_components_n = 1,
1367 .idxs_n = 4,
1368 .idxs_map = {
1369 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1370 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1371 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1372 [NIR_INTRINSIC_IDX_ACCESS] = 4
1373 }
1374 };
1375 struct nir_intrinsic nir_bindless_image_atomic_comp_swap = {
1376 .name = "bindless_image_atomic_comp_swap",
1377 .srcs_n = 5,
1378 .src_components_n = {
1379 1,4,1,1,1
1380 },
1381 .has_dest = true,
1382 .dest_components_n = 1,
1383 .idxs_n = 4,
1384 .idxs_map = {
1385 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1386 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1387 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1388 [NIR_INTRINSIC_IDX_ACCESS] = 4
1389 }
1390 };
1391 struct nir_intrinsic nir_bindless_image_atomic_fadd = {
1392 .name = "bindless_image_atomic_fadd",
1393 .srcs_n = 5,
1394 .src_components_n = {
1395 1,1,4,1,1
1396 },
1397 .has_dest = true,
1398 .dest_components_n = 1,
1399 .idxs_n = 4,
1400 .idxs_map = {
1401 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1402 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1403 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1404 [NIR_INTRINSIC_IDX_ACCESS] = 4
1405 }
1406 };
1407 struct nir_intrinsic nir_bindless_image_size = {
1408 .name = "bindless_image_size",
1409 .srcs_n = 1,
1410 .src_components_n = {
1411 1
1412 },
1413 .has_dest = true,
1414 .idxs_n = 4,
1415 .idxs_map = {
1416 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1417 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1418 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1419 [NIR_INTRINSIC_IDX_ACCESS] = 4
1420 },
1421 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1422 };
1423 struct nir_intrinsic nir_bindless_image_samples = {
1424 .name = "bindless_image_samples",
1425 .srcs_n = 1,
1426 .src_components_n = {
1427 1
1428 },
1429 .has_dest = true,
1430 .dest_components_n = 1,
1431 .idxs_n = 4,
1432 .idxs_map = {
1433 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1434 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1435 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1436 [NIR_INTRINSIC_IDX_ACCESS] = 4
1437 },
1438 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1439 };
1440 struct nir_intrinsic nir_bindless_image_load_raw_intel = {
1441 .name = "bindless_image_load_raw_intel",
1442 .srcs_n = 2,
1443 .src_components_n = {
1444 1,1
1445 },
1446 .has_dest = true,
1447 .idxs_n = 4,
1448 .idxs_map = {
1449 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1450 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1451 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1452 [NIR_INTRINSIC_IDX_ACCESS] = 4
1453 },
1454 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1455 };
1456 struct nir_intrinsic nir_bindless_image_store_raw_intel = {
1457 .name = "bindless_image_store_raw_intel",
1458 .srcs_n = 3,
1459 .src_components_n = {
1460 1,1,0
1461 },
1462 .idxs_n = 4,
1463 .idxs_map = {
1464 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1465 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1466 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1467 [NIR_INTRINSIC_IDX_ACCESS] = 4
1468 }
1469 };
1470 /* bindless version */
1471 /*----------------------------------------------------------------------------*/
1472 /* the following is solo */
1473 struct nir_intrinsic nir_image_deref_load_param_intel = {
1474 .name = "image_deref_load_param_intel",
1475 .srcs_n = 1,
1476 .src_components_n = {
1477 1
1478 },
1479 .has_dest = true,
1480 .dest_components_n = 0,
1481 .idxs_n = 1,
1482 .idxs_map = {
1483 [NIR_INTRINSIC_IDX_BASE] = 1
1484 },
1485 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1486 };
1487 /* Image load, store and atomic intrinsics */
1488 /******************************************************************************/
1489 struct nir_intrinsic nir_inclusive_scan = {
1490 .name = "inclusive_scan",
1491 .srcs_n = 1,
1492 .src_components_n = {
1493 0
1494 },
1495 .has_dest = true,
1496 .idxs_n = 1,
1497 .idxs_map = {
1498 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1
1499 },
1500 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1501 };
1502 struct nir_intrinsic nir_interp_deref_at_centroid = {
1503 .name = "interp_deref_at_centroid",
1504 .srcs_n = 1,
1505 .src_components_n = {
1506 1
1507 },
1508 .has_dest = true,
1509 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1510 };
1511 struct nir_intrinsic nir_interp_deref_at_offset = {
1512 .name = "interp_deref_at_offset",
1513 .srcs_n = 2,
1514 .src_components_n = {
1515 1,2
1516 },
1517 .has_dest = true,
1518 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1519 };
1520 struct nir_intrinsic nir_interp_deref_at_sample = {
1521 .name = "interp_deref_at_sample",
1522 .srcs_n = 2,
1523 .src_components_n = {
1524 1,1
1525 },
1526 .has_dest = true,
1527 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1528 };
1529 static struct nir_intrinsic nir_load_alpha_ref_float = {
1530 .name = "load_alpha_ref_float",
1531 .has_dest = true,
1532 .dest_components_n = 1,
1533 .bit_szs = 0x20,
1534 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1535 .system_value = true
1536 };
1537 /******************************************************************************/
1538 /*
1539 * Barycentric coordinate intrinsics.
1540 *
1541 * These set up the barycentric coordinates for a particular interpolation.
1542 * The first three are for the simple cases: pixel, centroid, or per-sample
1543 * (at gl_SampleID). The next two handle interpolating at a specified
1544 * sample location, or interpolating with a vec2 offset,
1545 *
1546 * The interp_mode index should be either the INTERP_MODE_SMOOTH or
1547 * INTERP_MODE_NOPERSPECTIVE enum values.
1548 *
1549 * The vec2 value produced by these intrinsics is intended for use as the
1550 * barycoord source of a load_interpolated_input intrinsic.
1551 */
1552 /*----------------------------------------------------------------------------*/
1553 /* no source */
1554 struct nir_intrinsic nir_load_barycentric_pixel = {
1555 .name = "load_barycentric_pixel",
1556 .srcs_n = 0,
1557 .has_dest = true,
1558 .dest_components_n = 2,
1559 .idxs_n = 1,
1560 .idxs_map = {
1561 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1562 },
1563 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1564 };
1565 struct nir_intrinsic nir_load_barycentric_centroid = {
1566 .name = "load_barycentric_centroid",
1567 .srcs_n = 0,
1568 .has_dest = true,
1569 .dest_components_n = 2,
1570 .idxs_n = 1,
1571 .idxs_map = {
1572 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1573 },
1574 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1575 };
1576 struct nir_intrinsic nir_load_barycentric_sample = {
1577 .name = "load_barycentric_sample",
1578 .srcs_n = 0,
1579 .has_dest = true,
1580 .dest_components_n = 2,
1581 .idxs_n = 1,
1582 .idxs_map = {
1583 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1584 },
1585 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1586 };
1587 /* no source */
1588 /*----------------------------------------------------------------------------*/
1589 /* src[] = { offset.xy } */
1590 struct nir_intrinsic nir_load_barycentric_at_offset = {
1591 .name = "load_barycentric_at_offset",
1592 .srcs_n = 1,
1593 .src_components_n = {
1594 2
1595 },
1596 .has_dest = true,
1597 .dest_components_n = 2,
1598 .idxs_n = 1,
1599 .idxs_map = {
1600 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1601 },
1602 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1603 };
1604 /* src[] = { sample_id } */
1605 struct nir_intrinsic nir_load_barycentric_at_sample = {
1606 .name = "load_barycentric_at_sample",
1607 .srcs_n = 1,
1608 .src_components_n = {
1609 1
1610 },
1611 .has_dest = true,
1612 .dest_components_n = 2,
1613 .idxs_n = 1,
1614 .idxs_map = {
1615 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1616 },
1617 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1618 };
1619 /* Barycentric coordinate intrinsics. */
1620 /******************************************************************************/
1621 static struct nir_intrinsic nir_load_base_instance = {
1622 .name = "load_base_instance",
1623 .has_dest = true,
1624 .dest_components_n = 1,
1625 .bit_szs = 0x20,
1626 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1627 .system_value = true
1628 };
1629 static struct nir_intrinsic nir_load_base_vertex = {
1630 .name = "load_base_vertex",
1631 .has_dest = true,
1632 .dest_components_n = 1,
1633 .bit_szs = 0x20,
1634 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1635 .system_value = true
1636 };
1637 static struct nir_intrinsic nir_load_blend_const_color_a_float = {
1638 .name = "load_blend_const_color_a_float",
1639 .has_dest = true,
1640 .dest_components_n = 1,
1641 .bit_szs = 0x20,
1642 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1643 .system_value = true
1644 };
1645 static struct nir_intrinsic nir_load_blend_const_color_aaaa8888_unorm = {
1646 .name = "load_blend_const_color_aaaa8888_unorm",
1647 .has_dest = true,
1648 .dest_components_n = 1,
1649 .bit_szs = 0x20,
1650 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1651 .system_value = true
1652 };
1653 static struct nir_intrinsic nir_load_blend_const_color_b_float = {
1654 .name = "load_blend_const_color_b_float",
1655 .has_dest = true,
1656 .dest_components_n = 1,
1657 .bit_szs = 0x20,
1658 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1659 .system_value = true
1660 };
1661 static struct nir_intrinsic nir_load_blend_const_color_g_float = {
1662 .name = "load_blend_const_color_g_float",
1663 .has_dest = true,
1664 .dest_components_n = 1,
1665 .bit_szs = 0x20,
1666 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1667 .system_value = true
1668 };
1669 static struct nir_intrinsic nir_load_blend_const_color_r_float = {
1670 .name = "load_blend_const_color_r_float",
1671 .has_dest = true,
1672 .dest_components_n = 1,
1673 .bit_szs = 0x20,
1674 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1675 .system_value = true
1676 };
1677 static struct nir_intrinsic nir_load_blend_const_color_rgba8888_unorm = {
1678 .name = "load_blend_const_color_rgba8888_unorm",
1679 .has_dest = true,
1680 .dest_components_n = 1,
1681 .bit_szs = 0x20,
1682 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1683 .system_value = true
1684 };
1685 struct nir_intrinsic nir_load_deref = {
1686 .name = "load_deref",
1687 .srcs_n = 1,
1688 .src_components_n = {
1689 -1
1690 },
1691 .has_dest = true,
1692 .idxs_n = 1,
1693 .idxs_map = {
1694 [NIR_INTRINSIC_IDX_ACCESS] = 1
1695 },
1696 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1697 };
1698 static struct nir_intrinsic nir_load_draw_id = {
1699 .name = "load_draw_id",
1700 .has_dest = true,
1701 .dest_components_n = 1,
1702 .bit_szs = 0x20,
1703 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1704 .system_value = true
1705 };
1706 static struct nir_intrinsic nir_load_first_vertex = {
1707 .name = "load_first_vertex",
1708 .has_dest = true,
1709 .dest_components_n = 1,
1710 .bit_szs = 0x20,
1711 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1712 .system_value = true
1713 };
1714 static struct nir_intrinsic nir_load_frag_coord = {
1715 .name = "load_frag_coord",
1716 .has_dest = true,
1717 .dest_components_n = 4,
1718 .bit_szs = 0x20,
1719 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1720 .system_value = true
1721 };
1722 static struct nir_intrinsic nir_load_front_face = {
1723 .name = "load_front_face",
1724 .has_dest = true,
1725 .dest_components_n = 1,
1726 .bit_szs = 0x21,
1727 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
1728 .system_value = true
1729 };
1730 /******************************************************************************/
1731 /*
1732 * Load operations pull data from some piece of GPU memory. All load
1733 * operations operate in terms of offsets into some piece of theoretical
1734 * memory. Loads from externally visible memory (UBO and SSBO) simply take a
1735 * byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.)
1736 * take a base+offset pair where the nir_intrinsic_base() gives the location
1737 * of the start of the variable being loaded and and the offset source is a
1738 * offset into that variable.
1739 *
1740 * Uniform load operations have a nir_intrinsic_range() index that specifies the
1741 * range (starting at base) of the data from which we are loading. If
1742 * range == 0, then the range is unknown.
1743 *
1744 * Some load operations such as UBO/SSBO load and per_vertex loads take an
1745 * additional source to specify which UBO/SSBO/vertex to load from.
1746 *
1747 * The exact address type depends on the lowering pass that generates the
1748 * load/store intrinsics. Typically, this is vec4 units for things such as
1749 * varying slots and float units for fragment shader inputs. UBO and SSBO
1750 * offsets are always in bytes.
1751 */
1752 /* src[] = { offset } */
1753 struct nir_intrinsic nir_load_uniform = {
1754 .name = "load_uniform",
1755 .srcs_n = 1,
1756 .src_components_n = {
1757 1
1758 },
1759 .has_dest = true,
1760 .idxs_n = 2,
1761 .idxs_map = {
1762 [NIR_INTRINSIC_IDX_BASE] = 1,
1763 [NIR_INTRINSIC_IDX_RANGE] = 2
1764 },
1765 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1766 };
1767 /* src[] = { buffer_index, offset } */
1768 struct nir_intrinsic nir_load_ubo = {
1769 .name = "load_ubo",
1770 .srcs_n = 2,
1771 .src_components_n = {
1772 1,1
1773 },
1774 .has_dest = true,
1775 .idxs_n = 3,
1776 .idxs_map = {
1777 [NIR_INTRINSIC_IDX_ACCESS] = 1,
1778 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1779 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1780 },
1781 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1782 };
1783 /* src[] = { offset } */
1784 struct nir_intrinsic nir_load_input = {
1785 .name = "load_input",
1786 .srcs_n = 1,
1787 .src_components_n = {
1788 1
1789 },
1790 .has_dest = true,
1791 .idxs_n = 2,
1792 .idxs_map = {
1793 [NIR_INTRINSIC_IDX_BASE] = 1,
1794 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1795 },
1796 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1797 };
1798 /* src[] = { vertex, offset } */
1799 struct nir_intrinsic nir_load_per_vertex_input = {
1800 .name = "load_per_vertex_input",
1801 .srcs_n = 2,
1802 .src_components_n = {
1803 1,1
1804 },
1805 .has_dest = true,
1806 .idxs_n = 2,
1807 .idxs_map = {
1808 [NIR_INTRINSIC_IDX_BASE] = 1,
1809 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1810 },
1811 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1812 };
1813 /* src[] = { barycoord, offset } */
1814 struct nir_intrinsic nir_load_interpolated_input = {
1815 .name = "load_interpolated_input",
1816 .srcs_n = 2,
1817 .src_components_n = {
1818 2,1
1819 },
1820 .has_dest = true,
1821 .idxs_n = 2,
1822 .idxs_map = {
1823 [NIR_INTRINSIC_IDX_BASE] = 1,
1824 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1825 },
1826 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1827 };
1828 /* src[] = { buffer_index, offset } */
1829 struct nir_intrinsic nir_load_ssbo = {
1830 .name = "load_ssbo",
1831 .srcs_n = 2,
1832 .src_components_n = {
1833 1,1
1834 },
1835 .has_dest = true,
1836 .idxs_n = 3,
1837 .idxs_map = {
1838 [NIR_INTRINSIC_IDX_ACCESS] = 1,
1839 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1840 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1841 },
1842 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1843 };
1844 /* src[] = { offset } */
1845 struct nir_intrinsic nir_load_output = {
1846 .name = "load_output",
1847 .srcs_n = 1,
1848 .src_components_n = {
1849 1
1850 },
1851 .has_dest = true,
1852 .idxs_n = 2,
1853 .idxs_map = {
1854 [NIR_INTRINSIC_IDX_BASE] = 1,
1855 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1856 },
1857 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1858 };
1859 /* src[] = { vertex, offset } */
1860 struct nir_intrinsic nir_load_per_vertex_output = {
1861 .name = "load_per_vertex_output",
1862 .srcs_n = 2,
1863 .src_components_n = {
1864 1,1
1865 },
1866 .has_dest = true,
1867 .idxs_n = 2,
1868 .idxs_map = {
1869 [NIR_INTRINSIC_IDX_BASE] = 1,
1870 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1871 },
1872 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1873 };
1874 /* src[] = { offset } */
1875 struct nir_intrinsic nir_load_shared = {
1876 .name = "load_shared",
1877 .srcs_n = 1,
1878 .src_components_n = {
1879 1
1880 },
1881 .has_dest = true,
1882 .idxs_n = 3,
1883 .idxs_map = {
1884 [NIR_INTRINSIC_IDX_BASE] = 1,
1885 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1886 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1887 },
1888 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1889 };
1890 /* src[] = { offset } */
1891 struct nir_intrinsic nir_load_push_constant = {
1892 .name = "load_push_constant",
1893 .srcs_n = 1,
1894 .src_components_n = {
1895 1
1896 },
1897 .has_dest = true,
1898 .idxs_n = 2,
1899 .idxs_map = {
1900 [NIR_INTRINSIC_IDX_BASE] = 1,
1901 [NIR_INTRINSIC_IDX_RANGE] = 2
1902 },
1903 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1904 };
1905 /* src[] = { offset } */
1906 struct nir_intrinsic nir_load_constant = {
1907 .name = "load_constant",
1908 .srcs_n = 1,
1909 .src_components_n = {
1910 1
1911 },
1912 .has_dest = true,
1913 .idxs_n = 2,
1914 .idxs_map = {
1915 [NIR_INTRINSIC_IDX_BASE] = 1,
1916 [NIR_INTRINSIC_IDX_RANGE] = 2
1917 },
1918 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1919 };
1920 /* src[] = { address } */
1921 struct nir_intrinsic nir_load_global = {
1922 .name = "load_global",
1923 .srcs_n = 1,
1924 .src_components_n = {
1925 1
1926 },
1927 .has_dest = true,
1928 .idxs_n = 3,
1929 .idxs_map = {
1930 [NIR_INTRINSIC_IDX_ACCESS] = 1,
1931 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1932 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1933 },
1934 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1935 };
1936 /* src[] = { address } */
1937 struct nir_intrinsic nir_load_kernel_input = {
1938 .name = "load_kernel_input",
1939 .srcs_n = 1,
1940 .src_components_n = {
1941 1
1942 },
1943 .has_dest = true,
1944 .idxs_n = 4,
1945 .idxs_map = {
1946 [NIR_INTRINSIC_IDX_BASE] = 1,
1947 [NIR_INTRINSIC_IDX_RANGE] = 2,
1948 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
1949 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4,
1950 },
1951 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1952 };
1953 /* src[] = { offset } */
1954 struct nir_intrinsic nir_load_scratch = {
1955 .name = "load_scratch",
1956 .srcs_n = 1,
1957 .src_components_n = {
1958 1
1959 },
1960 .has_dest = true,
1961 .idxs_n = 2,
1962 .idxs_map = {
1963 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 1,
1964 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 2,
1965 },
1966 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1967 };
1968 /* Load operations pull data from some piece of GPU memory */
1969 /******************************************************************************/
1970 /******************************************************************************/
1971 /*
1972 * Stores work the same way as loads, except now the first source is the value
1973 * to store and the second (and possibly third) source specify where to store
1974 * the value. SSBO and shared memory stores also have a
1975 * nir_intrinsic_write_mask()
1976 */
1977 /* src[] = { value, offset } */
1978 struct nir_intrinsic nir_store_output = {
1979 .name = "store_output",
1980 .srcs_n = 2,
1981 .src_components_n = {
1982 0,1
1983 },
1984 .idxs_n = 3,
1985 .idxs_map = {
1986 [NIR_INTRINSIC_IDX_BASE] = 1,
1987 [NIR_INTRINSIC_IDX_WRMASK] = 2,
1988 [NIR_INTRINSIC_IDX_COMPONENT] = 3
1989 }
1990 };
1991 /* src[] = { value, vertex, offset } */
1992 struct nir_intrinsic nir_store_per_vertex_output = {
1993 .name = "store_per_vertex_output",
1994 .srcs_n = 3,
1995 .src_components_n = {
1996 0,1,1
1997 },
1998 .idxs_n = 3,
1999 .idxs_map = {
2000 [NIR_INTRINSIC_IDX_BASE] = 1,
2001 [NIR_INTRINSIC_IDX_WRMASK] = 2,
2002 [NIR_INTRINSIC_IDX_COMPONENT] = 3
2003 }
2004 };
2005 /* src[] = { value, block_index, offset } */
2006 struct nir_intrinsic nir_store_ssbo = {
2007 .name = "store_ssbo",
2008 .srcs_n = 3,
2009 .src_components_n = {
2010 0,1,1
2011 },
2012 .idxs_n = 4,
2013 .idxs_map = {
2014 [NIR_INTRINSIC_IDX_WRMASK] = 1,
2015 [NIR_INTRINSIC_IDX_ACCESS] = 2,
2016 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
2017 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
2018 }
2019 };
2020 /* src[] = { value, offset } */
2021 struct nir_intrinsic nir_store_shared = {
2022 .name = "store_shared",
2023 .srcs_n = 2,
2024 .src_components_n = {
2025 0,1
2026 },
2027 .idxs_n = 4,
2028 .idxs_map = {
2029 [NIR_INTRINSIC_IDX_BASE] = 1,
2030 [NIR_INTRINSIC_IDX_WRMASK] = 2,
2031 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
2032 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
2033 }
2034 };
2035 /* src[] = { value, address } */
2036 struct nir_intrinsic nir_store_global = {
2037 .name = "store_global",
2038 .srcs_n = 2,
2039 .src_components_n = {
2040 0,1
2041 },
2042 .idxs_n = 4,
2043 .idxs_map = {
2044 [NIR_INTRINSIC_IDX_WRMASK] = 1,
2045 [NIR_INTRINSIC_IDX_ACCESS] = 2,
2046 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
2047 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
2048 }
2049 };
2050 /* src[] = { value, offset } */
2051 struct nir_intrinsic nir_store_scratch = {
2052 .name = "store_scratch",
2053 .srcs_n = 2,
2054 .src_components_n = {
2055 0,1
2056 },
2057 .idxs_n = 3,
2058 .idxs_map = {
2059 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 1,
2060 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 2,
2061 [NIR_INTRINSIC_IDX_WRMASK] = 3
2062 }
2063 };
2064 /* Stores */
2065 /******************************************************************************/
2066 static struct nir_intrinsic nir_load_global_invocation_id = {
2067 .name = "load_global_invocation_id",
2068 .has_dest = true,
2069 .dest_components_n = 3,
2070 .bit_szs = 0x60,
2071 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2072 .system_value = true
2073 };
2074 static struct nir_intrinsic nir_load_global_invocation_index = {
2075 .name = "load_global_invocation_index",
2076 .has_dest = true,
2077 .dest_components_n = 1,
2078 .bit_szs = 0x60,
2079 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2080 .system_value = true
2081 };
2082 static struct nir_intrinsic nir_load_helper_invocation = {
2083 .name = "load_helper_invocation",
2084 .has_dest = true,
2085 .dest_components_n = 1,
2086 .bit_szs = 0x21,
2087 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2088 .system_value = true
2089 };
2090 static struct nir_intrinsic nir_load_instance_id = {
2091 .name = "load_instance_id",
2092 .has_dest = true,
2093 .dest_components_n = 1,
2094 .bit_szs = 0x20,
2095 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2096 .system_value = true
2097 };
2098 static struct nir_intrinsic nir_load_invocation_id = {
2099 .name = "load_invocation_id",
2100 .has_dest = true,
2101 .dest_components_n = 1,
2102 .bit_szs = 0x20,
2103 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2104 .system_value = true
2105 };
2106 static struct nir_intrinsic nir_load_is_indexed_draw = {
2107 .name = "load_is_indexed_draw",
2108 .has_dest = true,
2109 .dest_components_n = 1,
2110 .bit_szs = 0x20,
2111 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2112 .system_value = true
2113 };
2114 static struct nir_intrinsic nir_load_layer_id = {
2115 .name = "load_layer_id",
2116 .has_dest = true,
2117 .dest_components_n = 1,
2118 .bit_szs = 0x20,
2119 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2120 .system_value = true
2121 };
2122 static struct nir_intrinsic nir_load_local_group_size = {
2123 .name = "load_local_group_size",
2124 .has_dest = true,
2125 .dest_components_n = 3,
2126 .bit_szs = 0x20,
2127 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2128 .system_value = true
2129 };
2130 static struct nir_intrinsic nir_load_local_invocation_id = {
2131 .name = "load_local_invocation_id",
2132 .has_dest = true,
2133 .dest_components_n = 3,
2134 .bit_szs = 0x20,
2135 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2136 .system_value = true
2137 };
2138 static struct nir_intrinsic nir_load_local_invocation_index = {
2139 .name = "load_local_invocation_index",
2140 .has_dest = true,
2141 .dest_components_n = 1,
2142 .bit_szs = 0x20,
2143 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2144 .system_value = true
2145 };
2146 static struct nir_intrinsic nir_load_num_subgroups = {
2147 .name = "load_num_subgroups",
2148 .has_dest = true,
2149 .dest_components_n = 1,
2150 .bit_szs = 0x20,
2151 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2152 .system_value = true
2153 };
2154 static struct nir_intrinsic nir_load_num_work_groups = {
2155 .name = "load_num_work_groups",
2156 .has_dest = true,
2157 .dest_components_n = 3,
2158 .bit_szs = 0x20,
2159 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2160 .system_value = true
2161 };
2162 struct nir_intrinsic nir_load_param = {
2163 .name = "load_param",
2164 .srcs_n = 0,
2165 .has_dest = true,
2166 .idxs_n = 1,
2167 .idxs_map = {
2168 [NIR_INTRINSIC_IDX_PARAM_IDX] = 1
2169 },
2170 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2171 };
2172 static struct nir_intrinsic nir_load_patch_vertices_in = {
2173 .name = "load_patch_vertices_in",
2174 .has_dest = true,
2175 .dest_components_n = 1,
2176 .bit_szs = 0x20,
2177 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2178 .system_value = true
2179 };
2180 static struct nir_intrinsic nir_load_primitive_id = {
2181 .name = "load_primitive_id",
2182 .has_dest = true,
2183 .dest_components_n = 1,
2184 .bit_szs = 0x20,
2185 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2186 .system_value = true
2187 };
2188 static struct nir_intrinsic nir_load_sample_id = {
2189 .name = "load_sample_id",
2190 .has_dest = true,
2191 .dest_components_n = 1,
2192 .bit_szs = 0x20,
2193 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2194 .system_value = true
2195 };
2196 static struct nir_intrinsic nir_load_sample_id_no_per_sample = {
2197 .name = "load_sample_id_no_per_sample",
2198 .has_dest = true,
2199 .dest_components_n = 1,
2200 .bit_szs = 0x20,
2201 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2202 .system_value = true
2203 };
2204 static struct nir_intrinsic nir_load_sample_mask_in = {
2205 .name = "load_sample_mask_in",
2206 .has_dest = true,
2207 .dest_components_n = 1,
2208 .bit_szs = 0x20,
2209 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2210 .system_value = true
2211 };
2212 static struct nir_intrinsic nir_load_sample_pos = {
2213 .name = "load_sample_pos",
2214 .has_dest = true,
2215 .dest_components_n = 2,
2216 .bit_szs = 0x20,
2217 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2218 .system_value = true
2219 };
2220 static struct nir_intrinsic nir_load_subgroup_eq_mask = {
2221 .name = "load_subgroup_eq_mask",
2222 .has_dest = true,
2223 .dest_components_n = 0,
2224 .bit_szs = 0x60,
2225 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2226 .system_value = true
2227 };
2228 static struct nir_intrinsic nir_load_subgroup_ge_mask = {
2229 .name = "load_subgroup_ge_mask",
2230 .has_dest = true,
2231 .dest_components_n = 0,
2232 .bit_szs = 0x60,
2233 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2234 .system_value = true
2235 };
2236 static struct nir_intrinsic nir_load_subgroup_gt_mask = {
2237 .name = "load_subgroup_gt_mask",
2238 .has_dest = true,
2239 .dest_components_n = 0,
2240 .bit_szs = 0x60,
2241 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2242 .system_value = true
2243 };
2244 static struct nir_intrinsic nir_load_subgroup_id = {
2245 .name = "load_subgroup_id",
2246 .has_dest = true,
2247 .dest_components_n = 1,
2248 .bit_szs = 0x20,
2249 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2250 .system_value = true
2251 };
2252 static struct nir_intrinsic nir_load_subgroup_invocation = {
2253 .name = "load_subgroup_invocation",
2254 .has_dest = true,
2255 .dest_components_n = 1,
2256 .bit_szs = 0x20,
2257 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2258 .system_value = true
2259 };
2260 static struct nir_intrinsic nir_load_subgroup_le_mask = {
2261 .name = "load_subgroup_le_mask",
2262 .has_dest = true,
2263 .dest_components_n = 0,
2264 .bit_szs = 0x60,
2265 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2266 .system_value = true
2267 };
2268 static struct nir_intrinsic nir_load_subgroup_lt_mask = {
2269 .name = "load_subgroup_lt_mask",
2270 .has_dest = true,
2271 .dest_components_n = 0,
2272 .bit_szs = 0x60,
2273 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2274 .system_value = true
2275 };
2276 static struct nir_intrinsic nir_load_subgroup_size = {
2277 .name = "load_subgroup_size",
2278 .has_dest = true,
2279 .dest_components_n = 1,
2280 .bit_szs = 0x20,
2281 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2282 .system_value = true
2283 };
2284 static struct nir_intrinsic nir_load_tess_coord = {
2285 .name = "load_tess_coord",
2286 .has_dest = true,
2287 .dest_components_n = 3,
2288 .bit_szs = 0x20,
2289 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2290 .system_value = true
2291 };
2292 static struct nir_intrinsic nir_load_tess_level_inner = {
2293 .name = "load_tess_level_inner",
2294 .has_dest = true,
2295 .dest_components_n = 2,
2296 .bit_szs = 0x20,
2297 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2298 .system_value = true
2299 };
2300 static struct nir_intrinsic nir_load_tess_level_outer = {
2301 .name = "load_tess_level_outer",
2302 .has_dest = true,
2303 .dest_components_n = 4,
2304 .bit_szs = 0x20,
2305 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2306 .system_value = true
2307 };
2308 static struct nir_intrinsic nir_load_user_clip_plane = {
2309 .name = "load_user_clip_plane",
2310 .has_dest = true,
2311 .dest_components_n = 4,
2312 .idxs_n = 1,
2313 .idxs_map = {
2314 [NIR_INTRINSIC_IDX_UCP_ID] = 1,
2315 },
2316 .bit_szs = 0x20,
2317 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2318 .system_value = true
2319 };
2320 static struct nir_intrinsic nir_load_vertex_id = {
2321 .name = "load_vertex_id",
2322 .has_dest = true,
2323 .dest_components_n = 1,
2324 .bit_szs = 0x20,
2325 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2326 .system_value = true
2327 };
2328 static struct nir_intrinsic nir_load_vertex_id_zero_base = {
2329 .name = "load_vertex_id_zero_base",
2330 .has_dest = true,
2331 .dest_components_n = 1,
2332 .bit_szs = 0x20,
2333 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2334 .system_value = true
2335 };
2336 static struct nir_intrinsic nir_load_view_index = {
2337 .name = "load_view_index",
2338 .has_dest = true,
2339 .dest_components_n = 1,
2340 .bit_szs = 0x20,
2341 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2342 .system_value = true
2343 };
2344 struct nir_intrinsic nir_load_vulkan_descriptor = {
2345 .name = "load_vulkan_descriptor",
2346 .srcs_n = 1,
2347 .src_components_n = {
2348 1
2349 },
2350 .has_dest = true,
2351 .idxs_n = 1,
2352 .idxs_map = {
2353 [NIR_INTRINSIC_IDX_DESC_TYPE] = 1
2354 },
2355 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
2356 };
2357 static struct nir_intrinsic nir_load_work_dim = {
2358 .name = "load_work_dim",
2359 .has_dest = true,
2360 .dest_components_n = 1,
2361 .bit_szs = 0x20,
2362 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2363 .system_value = true
2364 };
2365 static struct nir_intrinsic nir_load_work_group_id = {
2366 .name = "load_work_group_id",
2367 .has_dest = true,
2368 .dest_components_n = 3,
2369 .bit_szs = 0x20,
2370 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
2371 .system_value = true
2372 };
2373 struct nir_intrinsic nir_memory_barrier = {
2374 .name = "memory_barrier"
2375 };
2376 struct nir_intrinsic nir_memory_barrier_atomic_counter = {
2377 .name = "memory_barrier_atomic_counter"
2378 };
2379 struct nir_intrinsic nir_memory_barrier_buffer = {
2380 .name = "memory_barrier_buffer"
2381 };
2382 struct nir_intrinsic nir_memory_barrier_image = {
2383 .name = "memory_barrier_image"
2384 };
2385 struct nir_intrinsic nir_memory_barrier_shared = {
2386 .name = "memory_barrier_shared"
2387 };
2388 struct nir_intrinsic nir_nop = {
2389 .name = "nop",
2390 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2391 };
2392 struct nir_intrinsic nir_quad_broadcast = {
2393 .name = "quad_broadcast",
2394 .srcs_n = 2,
2395 .src_components_n = {
2396 0,1
2397 },
2398 .has_dest = true,
2399 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2400 };
2401 struct nir_intrinsic nir_quad_swap_diagonal = {
2402 .name = "quad_swap_diagonal",
2403 .srcs_n = 1,
2404 .src_components_n = {
2405 0
2406 },
2407 .has_dest = true,
2408 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2409 };
2410 struct nir_intrinsic nir_quad_swap_horizontal = {
2411 .name = "quad_swap_horizontal",
2412 .srcs_n = 1,
2413 .src_components_n = {
2414 0
2415 },
2416 .has_dest = true,
2417 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2418 };
2419 struct nir_intrinsic nir_quad_swap_vertical = {
2420 .name = "quad_swap_vertical",
2421 .srcs_n = 1,
2422 .src_components_n = {
2423 0
2424 },
2425 .has_dest = true,
2426 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2427 };
2428 struct nir_intrinsic nir_read_first_invocation = {
2429 .name = "read_first_invocation",
2430 .srcs_n = 1,
2431 .src_components_n = {
2432 0
2433 },
2434 .has_dest = true,
2435 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2436 };
2437 struct nir_intrinsic nir_read_invocation = {
2438 .name = "read_invocation",
2439 .srcs_n = 2,
2440 .src_components_n = {
2441 0,1
2442 },
2443 .has_dest = true,
2444 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2445 };
2446 struct nir_intrinsic nir_reduce = {
2447 .name = "reduce",
2448 .srcs_n = 1,
2449 .src_components_n = {
2450 0
2451 },
2452 .has_dest = true,
2453 .idxs_n = 2,
2454 .idxs_map = {
2455 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1,
2456 [NIR_INTRINSIC_IDX_CLUSTER_SIZE] = 2
2457 },
2458 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2459 };
2460 struct nir_intrinsic nir_set_vertex_count = {
2461 .name = "set_vertex_count",
2462 .srcs_n = 1,
2463 .src_components_n = {
2464 1
2465 }
2466 };
2467 struct nir_intrinsic nir_shader_clock = {
2468 .name = "shader_clock",
2469 .has_dest = true,
2470 .dest_components_n = 2,
2471 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2472 };
2473 struct nir_intrinsic nir_shared_atomic_add = {
2474 .name = "shared_atomic_add",
2475 .srcs_n = 2,
2476 .src_components_n = {
2477 1,1
2478 },
2479 .has_dest = true,
2480 .dest_components_n = 1,
2481 .idxs_n = 1,
2482 .idxs_map = {
2483 [NIR_INTRINSIC_IDX_BASE] = 1
2484 }
2485 };
2486 struct nir_intrinsic nir_shared_atomic_and = {
2487 .name = "shared_atomic_and",
2488 .srcs_n = 2,
2489 .src_components_n = {
2490 1,1
2491 },
2492 .has_dest = true,
2493 .dest_components_n = 1,
2494 .idxs_n = 1,
2495 .idxs_map = {
2496 [NIR_INTRINSIC_IDX_BASE] = 1
2497 }
2498 };
2499 struct nir_intrinsic nir_shared_atomic_comp_swap = {
2500 .name = "shared_atomic_comp_swap",
2501 .srcs_n = 3,
2502 .src_components_n = {
2503 1,1,1
2504 },
2505 .has_dest = true,
2506 .dest_components_n = 1,
2507 .idxs_n = 1,
2508 .idxs_map = {
2509 [NIR_INTRINSIC_IDX_BASE] = 1
2510 }
2511 };
2512 struct nir_intrinsic nir_shared_atomic_exchange = {
2513 .name = "shared_atomic_exchange",
2514 .srcs_n = 2,
2515 .src_components_n = {
2516 1,1
2517 },
2518 .has_dest = true,
2519 .dest_components_n = 1,
2520 .idxs_n = 1,
2521 .idxs_map = {
2522 [NIR_INTRINSIC_IDX_BASE] = 1
2523 }
2524 };
2525 struct nir_intrinsic nir_shared_atomic_fadd = {
2526 .name = "shared_atomic_fadd",
2527 .srcs_n = 2,
2528 .src_components_n = {
2529 1,1
2530 },
2531 .has_dest = true,
2532 .dest_components_n = 1,
2533 .idxs_n = 1,
2534 .idxs_map = {
2535 [NIR_INTRINSIC_IDX_BASE] = 1
2536 }
2537 };
2538 struct nir_intrinsic nir_shared_atomic_fcomp_swap = {
2539 .name = "shared_atomic_fcomp_swap",
2540 .srcs_n = 3,
2541 .src_components_n = {
2542 1,1,1
2543 },
2544 .has_dest = true,
2545 .dest_components_n = 1,
2546 .idxs_n = 1,
2547 .idxs_map = {
2548 [NIR_INTRINSIC_IDX_BASE] = 1
2549 }
2550 };
2551 struct nir_intrinsic nir_shared_atomic_fmax = {
2552 .name = "shared_atomic_fmax",
2553 .srcs_n = 2,
2554 .src_components_n = {
2555 1,1
2556 },
2557 .has_dest = true,
2558 .dest_components_n = 1,
2559 .idxs_n = 1,
2560 .idxs_map = {
2561 [NIR_INTRINSIC_IDX_BASE] = 1
2562 }
2563 };
2564 struct nir_intrinsic nir_shared_atomic_fmin = {
2565 .name = "shared_atomic_fmin",
2566 .srcs_n = 2,
2567 .src_components_n = {
2568 1,1
2569 },
2570 .has_dest = true,
2571 .dest_components_n = 1,
2572 .idxs_n = 1,
2573 .idxs_map = {
2574 [NIR_INTRINSIC_IDX_BASE] = 1
2575 }
2576 };
2577 struct nir_intrinsic nir_shared_atomic_imax = {
2578 .name = "shared_atomic_imax",
2579 .srcs_n = 2,
2580 .src_components_n = {
2581 1,1
2582 },
2583 .has_dest = true,
2584 .dest_components_n = 1,
2585 .idxs_n = 1,
2586 .idxs_map = {
2587 [NIR_INTRINSIC_IDX_BASE] = 1
2588 }
2589 };
2590 struct nir_intrinsic nir_shared_atomic_imin = {
2591 .name = "shared_atomic_imin",
2592 .srcs_n = 2,
2593 .src_components_n = {
2594 1,1
2595 },
2596 .has_dest = true,
2597 .dest_components_n = 1,
2598 .idxs_n = 1,
2599 .idxs_map = {
2600 [NIR_INTRINSIC_IDX_BASE] = 1
2601 }
2602 };
2603 struct nir_intrinsic nir_shared_atomic_or = {
2604 .name = "shared_atomic_or",
2605 .srcs_n = 2,
2606 .src_components_n = {
2607 1,1
2608 },
2609 .has_dest = true,
2610 .dest_components_n = 1,
2611 .idxs_n = 1,
2612 .idxs_map = {
2613 [NIR_INTRINSIC_IDX_BASE] = 1
2614 }
2615 };
2616 struct nir_intrinsic nir_shared_atomic_umax = {
2617 .name = "shared_atomic_umax",
2618 .srcs_n = 2,
2619 .src_components_n = {
2620 1,1
2621 },
2622 .has_dest = true,
2623 .dest_components_n = 1,
2624 .idxs_n = 1,
2625 .idxs_map = {
2626 [NIR_INTRINSIC_IDX_BASE] = 1
2627 }
2628 };
2629 struct nir_intrinsic nir_shared_atomic_umin = {
2630 .name = "shared_atomic_umin",
2631 .srcs_n = 2,
2632 .src_components_n = {
2633 1,1
2634 },
2635 .has_dest = true,
2636 .dest_components_n = 1,
2637 .idxs_n = 1,
2638 .idxs_map = {
2639 [NIR_INTRINSIC_IDX_BASE] = 1
2640 }
2641 };
2642 struct nir_intrinsic nir_shared_atomic_xor = {
2643 .name = "shared_atomic_xor",
2644 .srcs_n = 2,
2645 .src_components_n = {
2646 1,1
2647 },
2648 .has_dest = true,
2649 .dest_components_n = 1,
2650 .idxs_n = 1,
2651 .idxs_map = {
2652 [NIR_INTRINSIC_IDX_BASE] = 1
2653 }
2654 };
2655 struct nir_intrinsic nir_shuffle = {
2656 .name = "shuffle",
2657 .srcs_n = 2,
2658 .src_components_n = {
2659 0,1
2660 },
2661 .has_dest = true,
2662 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2663 };
2664 struct nir_intrinsic nir_shuffle_down = {
2665 .name = "shuffle_down",
2666 .srcs_n = 2,
2667 .src_components_n = {
2668 0,1
2669 },
2670 .has_dest = true,
2671 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2672 };
2673 struct nir_intrinsic nir_shuffle_up = {
2674 .name = "shuffle_up",
2675 .srcs_n = 2,
2676 .src_components_n = {
2677 0,1
2678 },
2679 .has_dest = true,
2680 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2681 };
2682 struct nir_intrinsic nir_shuffle_xor = {
2683 .name = "shuffle_xor",
2684 .srcs_n = 2,
2685 .src_components_n = {
2686 0,1
2687 },
2688 .has_dest = true,
2689 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2690 };
2691 struct nir_intrinsic nir_ssbo_atomic_add = {
2692 .name = "ssbo_atomic_add",
2693 .srcs_n = 3,
2694 .src_components_n = {
2695 1,1,1
2696 },
2697 .has_dest = true,
2698 .dest_components_n = 1,
2699 .idxs_n = 1,
2700 .idxs_map = {
2701 [NIR_INTRINSIC_IDX_ACCESS] = 1
2702 }
2703 };
2704 struct nir_intrinsic nir_ssbo_atomic_and = {
2705 .name = "ssbo_atomic_and",
2706 .srcs_n = 3,
2707 .src_components_n = {
2708 1,1,1
2709 },
2710 .has_dest = true,
2711 .dest_components_n = 1,
2712 .idxs_n = 1,
2713 .idxs_map = {
2714 [NIR_INTRINSIC_IDX_ACCESS] = 1
2715 }
2716 };
2717 struct nir_intrinsic nir_ssbo_atomic_comp_swap = {
2718 .name = "ssbo_atomic_comp_swap",
2719 .srcs_n = 4,
2720 .src_components_n = {
2721 1,1,1,1
2722 },
2723 .has_dest = true,
2724 .dest_components_n = 1,
2725 .idxs_n = 1,
2726 .idxs_map = {
2727 [NIR_INTRINSIC_IDX_ACCESS] = 1
2728 }
2729 };
2730 struct nir_intrinsic nir_ssbo_atomic_exchange = {
2731 .name = "ssbo_atomic_exchange",
2732 .srcs_n = 3,
2733 .src_components_n = {
2734 1,1,1
2735 },
2736 .has_dest = true,
2737 .dest_components_n = 1,
2738 .idxs_n = 1,
2739 .idxs_map = {
2740 [NIR_INTRINSIC_IDX_ACCESS] = 1
2741 }
2742 };
2743 struct nir_intrinsic nir_ssbo_atomic_fadd = {
2744 .name = "ssbo_atomic_fadd",
2745 .srcs_n = 3,
2746 .src_components_n = {
2747 1,1,1
2748 },
2749 .has_dest = true,
2750 .dest_components_n = 1,
2751 .idxs_n = 1,
2752 .idxs_map = {
2753 [NIR_INTRINSIC_IDX_ACCESS] = 1
2754 }
2755 };
2756 struct nir_intrinsic nir_ssbo_atomic_fcomp_swap = {
2757 .name = "ssbo_atomic_fcomp_swap",
2758 .srcs_n = 4,
2759 .src_components_n = {
2760 1,1,1,1
2761 },
2762 .has_dest = true,
2763 .dest_components_n = 1,
2764 .idxs_n = 1,
2765 .idxs_map = {
2766 [NIR_INTRINSIC_IDX_ACCESS] = 1
2767 }
2768 };
2769 struct nir_intrinsic nir_ssbo_atomic_fmax = {
2770 .name = "ssbo_atomic_fmax",
2771 .srcs_n = 3,
2772 .src_components_n = {
2773 1,1,1
2774 },
2775 .has_dest = true,
2776 .dest_components_n = 1,
2777 .idxs_n = 1,
2778 .idxs_map = {
2779 [NIR_INTRINSIC_IDX_ACCESS] = 1
2780 }
2781 };
2782 struct nir_intrinsic nir_ssbo_atomic_fmin = {
2783 .name = "ssbo_atomic_fmin",
2784 .srcs_n = 3,
2785 .src_components_n = {
2786 1,1,1
2787 },
2788 .has_dest = true,
2789 .dest_components_n = 1,
2790 .idxs_n = 1,
2791 .idxs_map = {
2792 [NIR_INTRINSIC_IDX_ACCESS] = 1
2793 }
2794 };
2795 struct nir_intrinsic nir_ssbo_atomic_imax = {
2796 .name = "ssbo_atomic_imax",
2797 .srcs_n = 3,
2798 .src_components_n = {
2799 1,1,1
2800 },
2801 .has_dest = true,
2802 .dest_components_n = 1,
2803 .idxs_n = 1,
2804 .idxs_map = {
2805 [NIR_INTRINSIC_IDX_ACCESS] = 1
2806 }
2807 };
2808 struct nir_intrinsic nir_ssbo_atomic_imin = {
2809 .name = "ssbo_atomic_imin",
2810 .srcs_n = 3,
2811 .src_components_n = {
2812 1,1,1
2813 },
2814 .has_dest = true,
2815 .dest_components_n = 1,
2816 .idxs_n = 1,
2817 .idxs_map = {
2818 [NIR_INTRINSIC_IDX_ACCESS] = 1
2819 }
2820 };
2821 struct nir_intrinsic nir_ssbo_atomic_or = {
2822 .name = "ssbo_atomic_or",
2823 .srcs_n = 3,
2824 .src_components_n = {
2825 1,1,1
2826 },
2827 .has_dest = true,
2828 .dest_components_n = 1,
2829 .idxs_n = 1,
2830 .idxs_map = {
2831 [NIR_INTRINSIC_IDX_ACCESS] = 1
2832 }
2833 };
2834 struct nir_intrinsic nir_ssbo_atomic_umax = {
2835 .name = "ssbo_atomic_umax",
2836 .srcs_n = 3,
2837 .src_components_n = {
2838 1,1,1
2839 },
2840 .has_dest = true,
2841 .dest_components_n = 1,
2842 .idxs_n = 1,
2843 .idxs_map = {
2844 [NIR_INTRINSIC_IDX_ACCESS] = 1
2845 }
2846 };
2847 struct nir_intrinsic nir_ssbo_atomic_umin = {
2848 .name = "ssbo_atomic_umin",
2849 .srcs_n = 3,
2850 .src_components_n = {
2851 1,1,1
2852 },
2853 .has_dest = true,
2854 .dest_components_n = 1,
2855 .idxs_n = 1,
2856 .idxs_map = {
2857 [NIR_INTRINSIC_IDX_ACCESS] = 1
2858 }
2859 };
2860 struct nir_intrinsic nir_ssbo_atomic_xor = {
2861 .name = "ssbo_atomic_xor",
2862 .srcs_n = 3,
2863 .src_components_n = {
2864 1,1,1
2865 },
2866 .has_dest = true,
2867 .dest_components_n = 1,
2868 .idxs_n = 1,
2869 .idxs_map = {
2870 [NIR_INTRINSIC_IDX_ACCESS] = 1
2871 }
2872 };
2873 struct nir_intrinsic nir_store_deref = {
2874 .name = "store_deref",
2875 .srcs_n = 2,
2876 .src_components_n = {
2877 -1,0
2878 },
2879 .idxs_n = 2,
2880 .idxs_map = {
2881 [NIR_INTRINSIC_IDX_WRMASK] = 1,
2882 [NIR_INTRINSIC_IDX_ACCESS] = 2
2883 }
2884 };
2885 struct nir_intrinsic nir_vote_all = {
2886 .name = "vote_all",
2887 .srcs_n = 1,
2888 .src_components_n = {
2889 1
2890 },
2891 .has_dest = true,
2892 .dest_components_n = 1,
2893 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2894 };
2895 struct nir_intrinsic nir_vote_any = {
2896 .name = "vote_any",
2897 .srcs_n = 1,
2898 .src_components_n = {
2899 1
2900 },
2901 .has_dest = true,
2902 .dest_components_n = 1,
2903 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2904 };
2905 struct nir_intrinsic nir_vote_feq = {
2906 .name = "vote_feq",
2907 .srcs_n = 1,
2908 .src_components_n = {
2909 0
2910 },
2911 .has_dest = true,
2912 .dest_components_n = 1,
2913 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2914 };
2915 struct nir_intrinsic nir_vote_ieq = {
2916 .name = "vote_ieq",
2917 .srcs_n = 1,
2918 .src_components_n = {
2919 0
2920 },
2921 .has_dest = true,
2922 .dest_components_n = 1,
2923 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2924 };
2925 struct nir_intrinsic nir_vulkan_resource_index = {
2926 .name = "vulkan_resource_index",
2927 .srcs_n = 1,
2928 .src_components_n = {
2929 1
2930 },
2931 .has_dest = true,
2932 .dest_components_n = 1,
2933 .idxs_n = 3,
2934 .idxs_map = {
2935 [NIR_INTRINSIC_IDX_DESC_SET] = 1,
2936 [NIR_INTRINSIC_IDX_BINDING] = 2,
2937 [NIR_INTRINSIC_IDX_DESC_TYPE] = 3
2938 },
2939 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
2940 };
2941 struct nir_intrinsic nir_vulkan_resource_reindex = {
2942 .name = "vulkan_resource_reindex",
2943 .srcs_n = 2,
2944 .src_components_n = {
2945 1,1
2946 },
2947 .has_dest = true,
2948 .dest_components_n = 1,
2949 .idxs_n = 1,
2950 .idxs_map = {
2951 [NIR_INTRINSIC_IDX_DESC_TYPE] = 1
2952 },
2953 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
2954 };
2955
2956 /* Gets the length of an unsized array at the end of a buffer */
2957 struct nir_intrinsic nir_deref_buffer_array_length = {
2958 .name = "deref_buffer_array_length",
2959 .srcs_n = 1,
2960 .src_components_n = {
2961 -1
2962 },
2963 .has_dest = true,
2964 .dest_components_n = 1,
2965 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
2966 };
2967
2968 /*----------------------------------------------------------------------------*/
2969 /*
2970 * IR3-specific version of most SSBO intrinsics. The only different
2971 * compare to the originals is that they add an extra source to hold
2972 * the dword-offset, which is needed by the backend code apart from
2973 * the byte-offset already provided by NIR in one of the sources.
2974 *
2975 * NIR lowering pass 'ir3_nir_lower_io_offset' will replace the
2976 * original SSBO intrinsics by these, placing the computed
2977 * dword-offset always in the last source.
2978 *
2979 * The float versions are not handled because those are not supported
2980 * by the backend.
2981 */
2982 struct nir_intrinsic nir_store_ssbo_ir3 = {
2983 .name = "store_ssbo_ir3",
2984 .srcs_n = 4,
2985 .src_components_n = {
2986 0,1,1,1
2987 },
2988 .idxs_n = 4,
2989 .idxs_map = {
2990 [NIR_INTRINSIC_IDX_WRMASK] = 1,
2991 [NIR_INTRINSIC_IDX_ACCESS] = 2,
2992 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
2993 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
2994 }
2995 };
2996 struct nir_intrinsic nir_load_ssbo_ir3 = {
2997 .name = "load_ssbo_ir3",
2998 .srcs_n = 3,
2999 .src_components_n = {
3000 1,1,1
3001 },
3002 .has_dest = true,
3003 .idxs_n = 3,
3004 .idxs_map = {
3005 [NIR_INTRINSIC_IDX_ACCESS] = 1,
3006 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
3007 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
3008 },
3009 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
3010 };
3011 struct nir_intrinsic nir_ssbo_atomic_add_ir3 = {
3012 .name = "ssbo_atomic_add_ir3",
3013 .srcs_n = 4,
3014 .src_components_n = {
3015 1,1,1,1
3016 },
3017 .has_dest = true,
3018 .dest_components_n = 1
3019 };
3020 struct nir_intrinsic nir_ssbo_atomic_imin_ir3 = {
3021 .name = "ssbo_atomic_imin_ir3",
3022 .srcs_n = 4,
3023 .src_components_n = {
3024 1,1,1,1
3025 },
3026 .has_dest = true,
3027 .dest_components_n = 1
3028 };
3029 struct nir_intrinsic nir_ssbo_atomic_umin_ir3 = {
3030 .name = "ssbo_atomic_umin_ir3",
3031 .srcs_n = 4,
3032 .src_components_n = {
3033 1,1,1,1
3034 },
3035 .has_dest = true,
3036 .dest_components_n = 1
3037 };
3038 struct nir_intrinsic nir_ssbo_atomic_imax_ir3 = {
3039 .name = "ssbo_atomic_imax_ir3",
3040 .srcs_n = 4,
3041 .src_components_n = {
3042 1,1,1,1
3043 },
3044 .has_dest = true,
3045 .dest_components_n = 1
3046 };
3047 struct nir_intrinsic nir_ssbo_atomic_umax_ir3 = {
3048 .name = "ssbo_atomic_umax_ir3",
3049 .srcs_n = 4,
3050 .src_components_n = {
3051 1,1,1,1
3052 },
3053 .has_dest = true,
3054 .dest_components_n = 1
3055 };
3056 struct nir_intrinsic nir_ssbo_atomic_and_ir3 = {
3057 .name = "ssbo_atomic_and_ir3",
3058 .srcs_n = 4,
3059 .src_components_n = {
3060 1,1,1,1
3061 },
3062 .has_dest = true,
3063 .dest_components_n = 1
3064 };
3065 struct nir_intrinsic nir_ssbo_atomic_or_ir3 = {
3066 .name = "ssbo_atomic_or_ir3",
3067 .srcs_n = 4,
3068 .src_components_n = {
3069 1,1,1,1
3070 },
3071 .has_dest = true,
3072 .dest_components_n = 1
3073 };
3074 struct nir_intrinsic nir_ssbo_atomic_xor_ir3 = {
3075 .name = "ssbo_atomic_xor_ir3",
3076 .srcs_n = 4,
3077 .src_components_n = {
3078 1,1,1,1
3079 },
3080 .has_dest = true,
3081 .dest_components_n = 1
3082 };
3083 struct nir_intrinsic nir_ssbo_atomic_exchange_ir3 = {
3084 .name = "ssbo_atomic_exchange_ir3",
3085 .srcs_n = 4,
3086 .src_components_n = {
3087 1,1,1,1
3088 },
3089 .has_dest = true,
3090 .dest_components_n = 1
3091 };
3092 struct nir_intrinsic nir_ssbo_atomic_swap_ir3 = {
3093 .name = "ssbo_atomic_swap_ir3",
3094 .srcs_n = 5,
3095 .src_components_n = {
3096 1,1,1,1,1
3097 },
3098 .has_dest = true,
3099 .dest_components_n = 1
3100 };
3101
3102 /******************************************************************************/
3103 /*
3104 * Driver-specific viewport scale/offset parameters.
3105 *
3106 * VC4 and V3D need to emit a scaled version of the position in the vertex
3107 * shaders for binning, and having system values lets us move the math for that
3108 * into NIR.
3109 *
3110 * Panfrost needs to implement all coordinate transformation in the
3111 * vertex shader; system values allow us to share this routine in NIR.
3112 */
3113 static struct nir_intrinsic nir_load_viewport_x_scale = {
3114 .name = "load_viewport_x_scale",
3115 .has_dest = true,
3116 .dest_components_n = 1,
3117 .bit_szs = 0x20,
3118 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3119 .system_value = true
3120 };
3121 static struct nir_intrinsic nir_load_viewport_y_scale = {
3122 .name = "load_viewport_y_scale",
3123 .has_dest = true,
3124 .dest_components_n = 1,
3125 .bit_szs = 0x20,
3126 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3127 .system_value = true
3128 };
3129 static struct nir_intrinsic nir_load_viewport_z_scale = {
3130 .name = "load_viewport_z_scale",
3131 .has_dest = true,
3132 .dest_components_n = 1,
3133 .bit_szs = 0x20,
3134 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3135 .system_value = true
3136 };
3137 static struct nir_intrinsic nir_load_viewport_z_offset = {
3138 .name = "load_viewport_z_offset",
3139 .has_dest = true,
3140 .dest_components_n = 1,
3141 .bit_szs = 0x20,
3142 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3143 .system_value = true
3144 };
3145 static struct nir_intrinsic nir_load_viewport_scale = {
3146 .name = "load_viewport_scale",
3147 .has_dest = true,
3148 .dest_components_n = 3,
3149 .bit_szs = 0x20,
3150 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3151 .system_value = true
3152 };
3153 static struct nir_intrinsic nir_load_viewport_offset = {
3154 .name = "load_viewport_offset",
3155 .has_dest = true,
3156 .dest_components_n = 3,
3157 .bit_szs = 0x20,
3158 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
3159 .system_value = true
3160 };
3161 /* viewport */
3162 /******************************************************************************/
3163 /*----------------------------------------------------------------------------*/
3164
3165 struct nir_intrinsic *nir_intrinsics[] = {
3166 &nir_atomic_counter_add,
3167 &nir_atomic_counter_add_deref,
3168 &nir_atomic_counter_and,
3169 &nir_atomic_counter_and_deref,
3170 &nir_atomic_counter_comp_swap,
3171 &nir_atomic_counter_comp_swap_deref,
3172 &nir_atomic_counter_exchange,
3173 &nir_atomic_counter_exchange_deref,
3174 &nir_atomic_counter_inc,
3175 &nir_atomic_counter_inc_deref,
3176 &nir_atomic_counter_max,
3177 &nir_atomic_counter_max_deref,
3178 &nir_atomic_counter_min,
3179 &nir_atomic_counter_min_deref,
3180 &nir_atomic_counter_or,
3181 &nir_atomic_counter_or_deref,
3182 &nir_atomic_counter_post_dec,
3183 &nir_atomic_counter_post_dec_deref,
3184 &nir_atomic_counter_pre_dec,
3185 &nir_atomic_counter_pre_dec_deref,
3186 &nir_atomic_counter_read,
3187 &nir_atomic_counter_read_deref,
3188 &nir_atomic_counter_xor,
3189 &nir_atomic_counter_xor_deref,
3190 &nir_ballot,
3191 &nir_ballot_bit_count_exclusive,
3192 &nir_ballot_bit_count_inclusive,
3193 &nir_ballot_bit_count_reduce,
3194 &nir_ballot_bitfield_extract,
3195 &nir_ballot_find_lsb,
3196 &nir_ballot_find_msb,
3197 &nir_barrier,
3198 &nir_begin_invocation_interlock,
3199 &nir_copy_deref,
3200 &nir_deref_atomic_add,
3201 &nir_deref_atomic_and,
3202 &nir_deref_atomic_comp_swap,
3203 &nir_deref_atomic_exchange,
3204 &nir_deref_atomic_fadd,
3205 &nir_deref_atomic_fcomp_swap,
3206 &nir_deref_atomic_fmax,
3207 &nir_deref_atomic_fmin,
3208 &nir_deref_atomic_imax,
3209 &nir_deref_atomic_imin,
3210 &nir_deref_atomic_or,
3211 &nir_deref_atomic_umax,
3212 &nir_deref_atomic_umin,
3213 &nir_deref_atomic_xor,
3214 &nir_discard,
3215 &nir_discard_if,
3216 &nir_elect,
3217 &nir_emit_vertex,
3218 &nir_emit_vertex_with_counter,
3219 &nir_end_invocation_interlock,
3220 &nir_end_primitive,
3221 &nir_end_primitive_with_counter,
3222 &nir_exclusive_scan,
3223 &nir_first_invocation,
3224 &nir_get_buffer_size,
3225 &nir_global_atomic_add,
3226 &nir_global_atomic_and,
3227 &nir_global_atomic_comp_swap,
3228 &nir_global_atomic_exchange,
3229 &nir_global_atomic_fadd,
3230 &nir_global_atomic_fcomp_swap,
3231 &nir_global_atomic_fmax,
3232 &nir_global_atomic_fmin,
3233 &nir_global_atomic_imax,
3234 &nir_global_atomic_imin,
3235 &nir_global_atomic_or,
3236 &nir_global_atomic_umax,
3237 &nir_global_atomic_umin,
3238 &nir_global_atomic_xor,
3239 &nir_group_memory_barrier,
3240 &nir_image_atomic_add,
3241 &nir_image_atomic_and,
3242 &nir_image_atomic_comp_swap,
3243 &nir_image_atomic_exchange,
3244 &nir_image_atomic_fadd,
3245 &nir_image_atomic_max,
3246 &nir_image_atomic_min,
3247 &nir_image_atomic_or,
3248 &nir_image_atomic_xor,
3249 &nir_image_deref_atomic_add,
3250 &nir_image_deref_atomic_and,
3251 &nir_image_deref_atomic_comp_swap,
3252 &nir_image_deref_atomic_exchange,
3253 &nir_image_deref_atomic_fadd,
3254 &nir_image_deref_atomic_max,
3255 &nir_image_deref_atomic_min,
3256 &nir_image_deref_atomic_or,
3257 &nir_image_deref_atomic_xor,
3258 &nir_image_deref_load,
3259 &nir_image_deref_load_param_intel,
3260 &nir_image_deref_load_raw_intel,
3261 &nir_image_deref_samples,
3262 &nir_image_deref_size,
3263 &nir_image_deref_store,
3264 &nir_image_deref_store_raw_intel,
3265 &nir_image_load,
3266 &nir_image_load_raw_intel,
3267 &nir_image_samples,
3268 &nir_image_size,
3269 &nir_image_store,
3270 &nir_image_store_raw_intel,
3271 &nir_inclusive_scan,
3272 &nir_interp_deref_at_centroid,
3273 &nir_interp_deref_at_offset,
3274 &nir_interp_deref_at_sample,
3275 &nir_load_alpha_ref_float,
3276 &nir_load_barycentric_at_offset,
3277 &nir_load_barycentric_at_sample,
3278 &nir_load_barycentric_centroid,
3279 &nir_load_barycentric_pixel,
3280 &nir_load_barycentric_sample,
3281 &nir_load_base_instance,
3282 &nir_load_base_vertex,
3283 &nir_load_blend_const_color_a_float,
3284 &nir_load_blend_const_color_aaaa8888_unorm,
3285 &nir_load_blend_const_color_b_float,
3286 &nir_load_blend_const_color_g_float,
3287 &nir_load_blend_const_color_r_float,
3288 &nir_load_blend_const_color_rgba8888_unorm,
3289 &nir_load_constant,
3290 &nir_load_deref,
3291 &nir_load_draw_id,
3292 &nir_load_first_vertex,
3293 &nir_load_frag_coord,
3294 &nir_load_front_face,
3295 &nir_load_global,
3296 &nir_load_global_invocation_id,
3297 &nir_load_global_invocation_index,
3298 &nir_load_helper_invocation,
3299 &nir_load_input,
3300 &nir_load_instance_id,
3301 &nir_load_interpolated_input,
3302 &nir_load_invocation_id,
3303 &nir_load_is_indexed_draw,
3304 &nir_load_layer_id,
3305 &nir_load_local_group_size,
3306 &nir_load_local_invocation_id,
3307 &nir_load_local_invocation_index,
3308 &nir_load_num_subgroups,
3309 &nir_load_num_work_groups,
3310 &nir_load_output,
3311 &nir_load_param,
3312 &nir_load_patch_vertices_in,
3313 &nir_load_per_vertex_input,
3314 &nir_load_per_vertex_output,
3315 &nir_load_primitive_id,
3316 &nir_load_push_constant,
3317 &nir_load_sample_id,
3318 &nir_load_sample_id_no_per_sample,
3319 &nir_load_sample_mask_in,
3320 &nir_load_sample_pos,
3321 &nir_load_shared,
3322 &nir_load_ssbo,
3323 &nir_load_subgroup_eq_mask,
3324 &nir_load_subgroup_ge_mask,
3325 &nir_load_subgroup_gt_mask,
3326 &nir_load_subgroup_id,
3327 &nir_load_subgroup_invocation,
3328 &nir_load_subgroup_le_mask,
3329 &nir_load_subgroup_lt_mask,
3330 &nir_load_subgroup_size,
3331 &nir_load_tess_coord,
3332 &nir_load_tess_level_inner,
3333 &nir_load_tess_level_outer,
3334 &nir_load_ubo,
3335 &nir_load_uniform,
3336 &nir_load_user_clip_plane,
3337 &nir_load_vertex_id,
3338 &nir_load_vertex_id_zero_base,
3339 &nir_load_view_index,
3340 &nir_load_vulkan_descriptor,
3341 &nir_load_work_dim,
3342 &nir_load_work_group_id,
3343 &nir_memory_barrier,
3344 &nir_memory_barrier_atomic_counter,
3345 &nir_memory_barrier_buffer,
3346 &nir_memory_barrier_image,
3347 &nir_memory_barrier_shared,
3348 &nir_nop,
3349 &nir_quad_broadcast,
3350 &nir_quad_swap_diagonal,
3351 &nir_quad_swap_horizontal,
3352 &nir_quad_swap_vertical,
3353 &nir_read_first_invocation,
3354 &nir_read_invocation,
3355 &nir_reduce,
3356 &nir_set_vertex_count,
3357 &nir_shader_clock,
3358 &nir_shared_atomic_add,
3359 &nir_shared_atomic_and,
3360 &nir_shared_atomic_comp_swap,
3361 &nir_shared_atomic_exchange,
3362 &nir_shared_atomic_fadd,
3363 &nir_shared_atomic_fcomp_swap,
3364 &nir_shared_atomic_fmax,
3365 &nir_shared_atomic_fmin,
3366 &nir_shared_atomic_imax,
3367 &nir_shared_atomic_imin,
3368 &nir_shared_atomic_or,
3369 &nir_shared_atomic_umax,
3370 &nir_shared_atomic_umin,
3371 &nir_shared_atomic_xor,
3372 &nir_shuffle,
3373 &nir_shuffle_down,
3374 &nir_shuffle_up,
3375 &nir_shuffle_xor,
3376 &nir_ssbo_atomic_add,
3377 &nir_ssbo_atomic_and,
3378 &nir_ssbo_atomic_comp_swap,
3379 &nir_ssbo_atomic_exchange,
3380 &nir_ssbo_atomic_fadd,
3381 &nir_ssbo_atomic_fcomp_swap,
3382 &nir_ssbo_atomic_fmax,
3383 &nir_ssbo_atomic_fmin,
3384 &nir_ssbo_atomic_imax,
3385 &nir_ssbo_atomic_imin,
3386 &nir_ssbo_atomic_or,
3387 &nir_ssbo_atomic_umax,
3388 &nir_ssbo_atomic_umin,
3389 &nir_ssbo_atomic_xor,
3390 &nir_store_deref,
3391 &nir_store_global,
3392 &nir_store_output,
3393 &nir_store_per_vertex_output,
3394 &nir_store_shared,
3395 &nir_store_ssbo,
3396 &nir_vote_all,
3397 &nir_vote_any,
3398 &nir_vote_feq,
3399 &nir_vote_ieq,
3400 &nir_vulkan_resource_index,
3401 &nir_vulkan_resource_reindex,
3402 /* git db944999a1bad94471966862cc38212019165937..58376c6b9be80c2cb74c7638d961d5af64f7143f */
3403 &nir_deref_buffer_array_length,
3404 &nir_store_ssbo_ir3,
3405 &nir_load_ssbo_ir3,
3406 &nir_ssbo_atomic_add_ir3,
3407 &nir_ssbo_atomic_imin_ir3,
3408 &nir_ssbo_atomic_umin_ir3,
3409 &nir_ssbo_atomic_imax_ir3,
3410 &nir_ssbo_atomic_umax_ir3,
3411 &nir_ssbo_atomic_and_ir3,
3412 &nir_ssbo_atomic_or_ir3,
3413 &nir_ssbo_atomic_xor_ir3,
3414 &nir_ssbo_atomic_exchange_ir3,
3415 &nir_ssbo_atomic_swap_ir3,
3416 /* git 58376c6b9be80c2cb74c7638d961d5af64f7143f..15012077bceda24cbf38afeda7723c47e1b0d3c3 */
3417 &nir_load_kernel_input,
3418 /* git 15012077bceda24cbf38afeda7723c47e1b0d3c3..e4e6a3deaff4f84f0fb99b4dec950dc498d507ed */
3419 &nir_bindless_image_load,
3420 &nir_bindless_image_store,
3421 &nir_bindless_image_atomic_add,
3422 &nir_bindless_image_atomic_min,
3423 &nir_bindless_image_atomic_max,
3424 &nir_bindless_image_atomic_and,
3425 &nir_bindless_image_atomic_or,
3426 &nir_bindless_image_atomic_xor,
3427 &nir_bindless_image_atomic_exchange,
3428 &nir_bindless_image_atomic_comp_swap,
3429 &nir_bindless_image_atomic_fadd,
3430 &nir_bindless_image_size,
3431 &nir_bindless_image_samples,
3432 &nir_bindless_image_load_raw_intel,
3433 &nir_bindless_image_store_raw_intel,
3434 /* git e4e6a3deaff4f84f0fb99b4dec950dc498d507ed..10a2fdacfa3f96a57fec304cf54d1c298e4f0943 */
3435 &nir_load_viewport_x_scale,
3436 &nir_load_viewport_y_scale,
3437 &nir_load_viewport_z_scale,
3438 &nir_load_viewport_z_offset,
3439 &nir_load_viewport_scale,
3440 &nir_load_viewport_offset,
3441 /* git 10a2fdacfa3f96a57fec304cf54d1c298e4f0943..1af7701666bea2d6f4d0d226f5efc2fa65103872 */
3442 &nir_load_scratch,
3443 &nir_store_scratch
3444 };
File builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index b769652..9837fdc)
... ... $build_ccld $build_dir/nir_opcodes_h.o \
637 637
638 638 $build_dir/nir_opcodes_h >$build_dir/nir_opcodes.h $build_dir/nir_opcodes_h >$build_dir/nir_opcodes.h
639 639 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
640 # nir_intrinsics.h
640 641 $build_cc -I$src/contrib/generators/nir \ $build_cc -I$src/contrib/generators/nir \
641 642 $src_dir/contrib/generators/nir/nir_intrinsics_h.c \ $src_dir/contrib/generators/nir/nir_intrinsics_h.c \
642 643 -o $build_dir/nir_intrinsics_h.o -o $build_dir/nir_intrinsics_h.o
 
... ... $src_dir/src/compiler/nir/nir_lower_patch_vertices.c \
888 889 $src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \ $src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \
889 890 $src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \ $src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \
890 891 $src_dir/src/compiler/nir/nir_lower_returns.c \ $src_dir/src/compiler/nir/nir_lower_returns.c \
892 $src_dir/src/compiler/nir/nir_lower_scratch.c \
891 893 $src_dir/src/compiler/nir/nir_lower_subgroups.c \ $src_dir/src/compiler/nir/nir_lower_subgroups.c \
892 894 $src_dir/src/compiler/nir/nir_lower_system_values.c \ $src_dir/src/compiler/nir/nir_lower_system_values.c \
893 895 $src_dir/src/compiler/nir/nir_lower_tex.c \ $src_dir/src/compiler/nir/nir_lower_tex.c \
 
... ... $src_dir/src/compiler/nir/nir_lower_two_sided_color.c \
896 898 $src_dir/src/compiler/nir/nir_lower_vars_to_ssa.c \ $src_dir/src/compiler/nir/nir_lower_vars_to_ssa.c \
897 899 $src_dir/src/compiler/nir/nir_lower_var_copies.c \ $src_dir/src/compiler/nir/nir_lower_var_copies.c \
898 900 $src_dir/src/compiler/nir/nir_lower_vec_to_movs.c \ $src_dir/src/compiler/nir/nir_lower_vec_to_movs.c \
901 $src_dir/src/compiler/nir/nir_lower_viewport_transform.c \
899 902 $src_dir/src/compiler/nir/nir_lower_wpos_center.c \ $src_dir/src/compiler/nir/nir_lower_wpos_center.c \
900 903 $src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \ $src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \
901 904 $src_dir/src/compiler/nir/nir_metadata.c \ $src_dir/src/compiler/nir/nir_metadata.c \
 
... ... $src_dir/src/compiler/nir/nir_opt_dead_cf.c \
913 916 $src_dir/src/compiler/nir/nir_opt_dead_write_vars.c \ $src_dir/src/compiler/nir/nir_opt_dead_write_vars.c \
914 917 $src_dir/src/compiler/nir/nir_opt_find_array_copies.c \ $src_dir/src/compiler/nir/nir_opt_find_array_copies.c \
915 918 $src_dir/src/compiler/nir/nir_opt_gcm.c \ $src_dir/src/compiler/nir/nir_opt_gcm.c \
916 $src_dir/src/compiler/nir/nir_opt_global_to_local.c \
917 919 $src_dir/src/compiler/nir/nir_opt_if.c \ $src_dir/src/compiler/nir/nir_opt_if.c \
918 920 $src_dir/src/compiler/nir/nir_opt_intrinsics.c \ $src_dir/src/compiler/nir/nir_opt_intrinsics.c \
919 921 $src_dir/src/compiler/nir/nir_opt_loop_unroll.c \ $src_dir/src/compiler/nir/nir_opt_loop_unroll.c \
File builders/mplayer-0/builder.sh changed (mode: 100644) (index f955e79..3199b34)
1 1 src_name=mplayer src_name=mplayer
2 date=2019-04-07
2 date=2019-04-20
3 3 archive_name=$src_name-export-snapshot.tar.bz2 archive_name=$src_name-export-snapshot.tar.bz2
4 4 url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name
5 ffmpeg_git_commit=4c8e3725d9ffe4baa5b5e3adec06aa2e68a89455
5 ffmpeg_git_commit=6e0488cac43130124e17722c589f1b5c9f4fe3f6
6 6
7 7 src_dir=$src_dir_root/$src_name-export-$date src_dir=$src_dir_root/$src_name-export-$date
8 8 cd $src_dir_root cd $src_dir_root
File builders/xserver-0/builder.sh changed (mode: 100644) (index 41df4a3..639c0ff)
1 1 src_name=xserver src_name=xserver
2 git_commit=0a005c4fe4fccc9bb6c3a5266065f8437621fdb9
2 git_commit=9c7ebf259f49f5e63906f572a1101747ac023b72
3 3 git_url0=git://anongit.freedesktop.org/xorg/$src_name git_url0=git://anongit.freedesktop.org/xorg/$src_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/nyanlinux

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/nyanlinux

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main