sylware / si-user (public) (License: Unspecified) (since 2019-09-09) (hash sha1)
old sample user level code to go with my gpu driver (has interesting code)
Clone URLs: https://rocketgit.com/user/sylware/si-user ssh://rocketgit@ssh.rocketgit.com/user/sylware/si-user git://git.rocketgit.com/user/sylware/si-user
master
List of commits:
Subject Hash Author Date (UTC)
memory caches love c51aedf797f97ec3426511b1578e52d575f25321 Sylvain BERTRAND 2013-08-23 14:48:06
add files 28fe912c85541ca80777d87fc4ac21447e9d57d0 Sylvain BERTRAND 2013-08-23 13:44:21
Initial commit 18d8ad18c54c32f78561e26d949d58efb8483bd3 Sylvain BERTRAND 2013-08-23 12:50:05
Commit c51aedf797f97ec3426511b1578e52d575f25321 - memory caches love
Author: Sylvain BERTRAND
Author date (UTC): 2013-08-23 14:48
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-08-23 14:48
Parent(s): 28fe912c85541ca80777d87fc4ac21447e9d57d0
Signer:
Signing key:
Signing status: N
Tree: b62c5ef2b4d416729d0e21be1a6a790363fb5094
File Lines added Lines deleted
tri.c 4 27
File tri.c changed (mode: 100644) (index 3381aea..cc36516)
... ... static inline uint32_t f2u(float f)
197 197 static void prelude(uint32_t **ib) static void prelude(uint32_t **ib)
198 198 { {
199 199 //---------------------------------------------------------------------------- //----------------------------------------------------------------------------
200 //sync shader caches, texture cache, color block caches
201 ib_wr(PKT3(PKT3_SET_CFG_REG,2));
202 ib_wr(CFG_REG_IDX(CP_COHER_CTL_1));
203 ib_wr(0);
200 //sync shader read/write caches, read/write L1/L2texture caches, read caches
201 //of color blocks (we don't use the depth block).
204 202 ib_wr(PKT3(PKT3_SURF_SYNC,4)); ib_wr(PKT3(PKT3_SURF_SYNC,4));
205 203 //CP_COHER_CTL_0 //CP_COHER_CTL_0
206 ib_wr(CCC_SH_ICACHE_ACTION_ENA|CCC_SH_KCACHE_ACTION_ENA|CCC_TC_ACTION_ENA
207 |CCC_CB_ACTION_ENA|CCC_CB0_DEST_BASE_ENA);
204 ib_wr(CCC_SH_ICACHE_ACTION_ENA|CCC_SH_KCACHE_ACTION_ENA|CCC_TCL2_ACTION_ENA
205 |CCC_CB_ACTION_ENA);
208 206 //CP_COHER_SZ //CP_COHER_SZ
209 207 ib_wr(0xffffffff); ib_wr(0xffffffff);
210 208 //CP_COHER_BASE //CP_COHER_BASE
 
... ... static void draw(uint32_t **ib)
888 886 ib_wr(set(VDI_SRC_SELECT,VDI_AUTO_IDX)); ib_wr(set(VDI_SRC_SELECT,VDI_AUTO_IDX));
889 887 } }
890 888
891 static void flush(uint32_t **ib)
892 {
893 //flush CBs and DB, XXX: miss the main CB?
894 ib_wr(PKT3(PKT3_SET_CFG_REG,2));
895 ib_wr(CFG_REG_IDX(CP_COHER_CTL_1));
896 ib_wr(0);
897 ib_wr(PKT3(PKT3_SURF_SYNC,4));
898 //CP_COHER_CTL_0
899 ib_wr(CCC_CB0_DEST_BASE_ENA|CCC_CB1_DEST_BASE_ENA|CCC_CB2_DEST_BASE_ENA
900 |CCC_CB3_DEST_BASE_ENA|CCC_CB4_DEST_BASE_ENA|CCC_CB5_DEST_BASE_ENA
901 |CCC_CB6_DEST_BASE_ENA|CCC_CB7_DEST_BASE_ENA|CCC_DB_DEST_BASE_ENA
902 |CCC_DB_ACTION_ENA|CCC_TCL1_ACTION_ENA|CCC_TC_ACTION_ENA
903 |CCC_SH_KCACHE_ACTION_ENA|CCC_SH_ICACHE_ACTION_ENA);
904 //CP_COHER_SZ
905 ib_wr(0xffffffff);
906 //CP_COHER_BASE
907 ib_wr(0);
908 ib_wr(0x0000000a);//polling interval, 0xa(10) * 16 clocks
909 }
910
911 889 static void pfp_align(uint32_t **ib,uint32_t *ib_start) static void pfp_align(uint32_t **ib,uint32_t *ib_start)
912 890 { {
913 891 while(((*ib-ib_start)&CP_RING_PFP_DW_MASK)!=0) ib_wr(PKT2); while(((*ib-ib_start)&CP_RING_PFP_DW_MASK)!=0) ib_wr(PKT2);
 
... ... static uint64_t ib_3d(uint32_t *ib_start, struct params_3d *params_3d)
923 901 ctx(&ib,params_3d); ctx(&ib,params_3d);
924 902 //============================================================================ //============================================================================
925 903 draw(&ib); draw(&ib);
926 flush(&ib);
927 904 pfp_align(&ib,ib_start); pfp_align(&ib,ib_start);
928 905 return ib-ib_start; return ib-ib_start;
929 906 } }
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