sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
cp0->gfx 468c65f13f7c967e3481f9c75307cfcb398b909b Sylvain BERTRAND 2013-08-21 13:15:02
cpu aperture to gpu aperture ba4c412fd6afed7ef3094eb6fb060ab43e0fb8c2 Sylvain BERTRAND 2013-08-21 13:06:18
a bit more dma generalization 281fcfd54820d7cf7059cdbf8e198e648642d960 Sylvain BERTRAND 2013-08-19 23:04:52
dma for pt update and l2l byte dma cpy b0542ee460a4f92ad2ad0ffa42293f9fe6d57928 Sylvain BERTRAND 2013-08-10 03:03:17
switch from msleep to usleep_range 3c42fa181b3777dd79bbe1dd0f5a98ed656fb4d5 Sylvain BERTRAND 2013-08-07 13:32:23
GPU is little endian, fimware big endian 13ebc6d59b5ba620db1a974f5920ff88f2ca3174 Sylvain BERTRAND 2013-08-07 13:20:10
naive ring free space wait system b196b09a6adbf72a417ef6e5adb34cff92732018 Sylvain BERTRAND 2013-08-07 12:39:39
mini fence system for DMA 5d183e5998d9f7b7b684ecac253c3cde50dad84f Sylvain BERTRAND 2013-08-06 20:54:12
mainly sg_user mapping 990ec94cf03256d6d2ce5375ea336acdd99fbcf1 Sylvain BERTRAND 2013-08-02 14:36:54
added core DMA mapping methods 677ff382bc0fb7bab3e119f4057fd5fcf40481fc Sylvain BERTRAND 2013-07-31 20:49:30
dma engines, and partial user bus mapping 4c82cabbe66ec9a1c940af37d8954ed87cbfb9eb Sylvain BERTRAND 2013-07-30 15:10:29
add some things to the aperture 695d6688db8ea6ce2145636ed0fb7fa5d6aaebcf Sylvain BERTRAND 2013-07-22 20:11:59
stop mapping vram pci bar 9e32ff2c145282e49503bea50391cb82b926780f Sylvain BERTRAND 2013-07-22 18:30:18
cleanup vram access of patterns 98758af7283b56a9782cb6f0bc2440e3dd54952a Sylvain BERTRAND 2013-07-22 15:33:43
indirect access love d95a68ed1cd564f3a58df468ea6774b53a04f474 Sylvain BERTRAND 2013-07-22 14:23:53
all vram in bus aperture d1c02a0dd98d424ff214d25a245ab6f4aeb277b0 Sylvain BERTRAND 2013-07-22 13:30:40
Create license.md 9103e29244afb22d9ceaf7dbca87c7177abd3fb0 Sylvain BERTRAND 2013-07-17 19:03:40
multi-monitor fix c0af3dfa6f5142553ff7977643d5bdcc2a99ebe2 Sylvain BERTRAND 2013-07-02 02:41:22
displayport fix 348d270e68ca95db356486c24925e42fd998c6b8 Sylvain BERTRAND 2013-07-01 21:45:45
atombios crtcs states init f0c161e2f8cd6a8265fbcbad29c8d5b7e2fef2f3 Sylvain BERTRAND 2013-06-29 15:01:43
Commit 468c65f13f7c967e3481f9c75307cfcb398b909b - cp0->gfx
Author: Sylvain BERTRAND
Author date (UTC): 2013-08-21 13:15
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-08-21 13:15
Parent(s): ba4c412fd6afed7ef3094eb6fb060ab43e0fb8c2
Signer:
Signing key:
Signing status: N
Tree: 78e5cff629d0480157c3373c8c0271ccbff2427e
File Lines added Lines deleted
drivers/gpu/alga/amd/si/bus/ba.c 4 4
drivers/gpu/alga/amd/si/bus/ba.h 1 1
drivers/gpu/alga/amd/si/drv.h 1 1
drivers/gpu/alga/amd/si/gpu/cps.c 42 42
drivers/gpu/alga/amd/si/gpu/cps.h 2 2
drivers/gpu/alga/amd/si/patterns/tri.c 5 5
File drivers/gpu/alga/amd/si/bus/ba.c changed (mode: 100644) (index 34757a4..b22ac37)
... ... long ba_core_map(struct pci_dev *dev)
376 376 if (r == -BA_ERR) if (r == -BA_ERR)
377 377 goto err_unmap_wb; goto err_unmap_wb;
378 378
379 r = cp_ring_map(dev, 0, &dd->ba.cp0_ring_map);
379 r = cp_ring_map(dev, 0, &dd->ba.gfx_ring_map);
380 380 if (r == -BA_ERR) if (r == -BA_ERR)
381 381 goto err_unmap_ih_ring; goto err_unmap_ih_ring;
382 382
383 383 r = cp_ring_map(dev, 1, &dd->ba.cp1_ring_map); r = cp_ring_map(dev, 1, &dd->ba.cp1_ring_map);
384 384 if (r == -BA_ERR) if (r == -BA_ERR)
385 goto err_unmap_cp0_ring;
385 goto err_unmap_gfx_ring;
386 386
387 387 r = cp_ring_map(dev, 2, &dd->ba.cp2_ring_map); r = cp_ring_map(dev, 2, &dd->ba.cp2_ring_map);
388 388 if (r == -BA_ERR) if (r == -BA_ERR)
 
... ... err_unmap_cp2_ring:
413 413 err_unmap_cp1_ring: err_unmap_cp1_ring:
414 414 unmap(dev, dd->ba.cp1_ring_map, 0); unmap(dev, dd->ba.cp1_ring_map, 0);
415 415
416 err_unmap_cp0_ring:
417 unmap(dev, dd->ba.cp0_ring_map, 0);
416 err_unmap_gfx_ring:
417 unmap(dev, dd->ba.gfx_ring_map, 0);
418 418
419 419 err_unmap_ih_ring: err_unmap_ih_ring:
420 420 unmap(dev, dd->ba.ih_ring_map, 0); unmap(dev, dd->ba.ih_ring_map, 0);
File drivers/gpu/alga/amd/si/bus/ba.h changed (mode: 100644) (index 5b25f77..2c77160)
... ... struct ba {
47 47
48 48 struct ba_map *wb_map; struct ba_map *wb_map;
49 49 struct ba_map *ih_ring_map; struct ba_map *ih_ring_map;
50 struct ba_map *cp0_ring_map;/* gfx */
50 struct ba_map *gfx_ring_map;
51 51 /* /*
52 52 * XXX: compute rings are exactly the same, should array them like the * XXX: compute rings are exactly the same, should array them like the
53 53 * dma rings * dma rings
File drivers/gpu/alga/amd/si/drv.h changed (mode: 100644) (index b58a23f..4e8d4ce)
... ... struct dev_drv_data {
51 51 u32 regs_sz; u32 regs_sz;
52 52 struct vram vram; struct vram vram;
53 53 struct ba ba; struct ba ba;
54 struct cp cp0;
54 struct cp gfx;
55 55 struct cp cp1; struct cp cp1;
56 56 struct cp cp2; struct cp cp2;
57 57 struct ih ih; struct ih ih;
File drivers/gpu/alga/amd/si/gpu/cps.c changed (mode: 100644) (index e7ac648..a8ee004)
... ... void cps_ctx_clr(struct pci_dev *dev)
498 498
499 499 ctx_clr_state_init(); ctx_clr_state_init();
500 500
501 cp0_wr(dev, PKT3(PKT3_PREAMBLE_CTL, 1));
502 cp0_wr(dev, PKT3_PREAMBLE_BEGIN_CLR_STATE);
501 gfx_wr(dev, PKT3(PKT3_PREAMBLE_CTL, 1));
502 gfx_wr(dev, PKT3_PREAMBLE_BEGIN_CLR_STATE);
503 503 for (i = 0; i < ARRAY_SIZE(ctx_clr_state); ++i) for (i = 0; i < ARRAY_SIZE(ctx_clr_state); ++i)
504 cp0_wr(dev, ctx_clr_state[i]);
505 cp0_wr(dev, PKT3(PKT3_PREAMBLE_CTL, 1));
506 cp0_wr(dev, PKT3_PREAMBLE_END_CLR_STATE);
507 cp0_wr(dev, PKT3(PKT3_CLR_STATE, 1));
508 cp0_wr(dev, 0);
509 cp0_commit(dev);
504 gfx_wr(dev, ctx_clr_state[i]);
505 gfx_wr(dev, PKT3(PKT3_PREAMBLE_CTL, 1));
506 gfx_wr(dev, PKT3_PREAMBLE_END_CLR_STATE);
507 gfx_wr(dev, PKT3(PKT3_CLR_STATE, 1));
508 gfx_wr(dev, 0);
509 gfx_commit(dev);
510 510
511 511 cp1_wr(dev, PKT3(PKT3_CLR_STATE, 1)); cp1_wr(dev, PKT3(PKT3_CLR_STATE, 1));
512 512 cp1_wr(dev, 0); cp1_wr(dev, 0);
 
... ... void cps_ctx_clr(struct pci_dev *dev)
517 517 cp2_commit(dev); cp2_commit(dev);
518 518
519 519 /* compute state */ /* compute state */
520 cp0_wr(dev, PKT3_COMPUTE(PKT3_CLR_STATE, 1));
521 cp0_wr(dev, 0);
522 cp0_commit(dev);
520 gfx_wr(dev, PKT3_COMPUTE(PKT3_CLR_STATE, 1));
521 gfx_wr(dev, 0);
522 gfx_commit(dev);
523 523
524 524 cp1_wr(dev, PKT3_COMPUTE(PKT3_CLR_STATE, 1)); cp1_wr(dev, PKT3_COMPUTE(PKT3_CLR_STATE, 1));
525 525 cp1_wr(dev, 0); cp1_wr(dev, 0);
 
... ... void cps_me_init(struct pci_dev *dev)
682 682 struct dev_drv_data *dd; struct dev_drv_data *dd;
683 683 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
684 684
685 /* common to all cps, done by cp0 */
686 cp0_wr(dev, PKT3(PKT3_ME_INIT, 6));
687 cp0_wr(dev, 0x1);
688 cp0_wr(dev, 0x0);
689 cp0_wr(dev, dd->cfg.gpu.hw_ctxs_n - 1);
690 cp0_wr(dev, set(PKT3_ME_INIT_DEV_ID, 1));
691 cp0_wr(dev, 0);
692 cp0_wr(dev, 0);
685 /* common to all cps, done by gfx */
686 gfx_wr(dev, PKT3(PKT3_ME_INIT, 6));
687 gfx_wr(dev, 0x1);
688 gfx_wr(dev, 0x0);
689 gfx_wr(dev, dd->cfg.gpu.hw_ctxs_n - 1);
690 gfx_wr(dev, set(PKT3_ME_INIT_DEV_ID, 1));
691 gfx_wr(dev, 0);
692 gfx_wr(dev, 0);
693 693
694 694 /* specific for the ce engine */ /* specific for the ce engine */
695 cp0_wr(dev, PKT3(PKT3_SET_BASE, 3));
696 cp0_wr(dev, set(PKT3_BASE_IDX, PKT3_CE_PARTITION_BASE));
697 cp0_wr(dev, 0xc000);
698 cp0_wr(dev, 0xe000);
695 gfx_wr(dev, PKT3(PKT3_SET_BASE, 3));
696 gfx_wr(dev, set(PKT3_BASE_IDX, PKT3_CE_PARTITION_BASE));
697 gfx_wr(dev, 0xc000);
698 gfx_wr(dev, 0xe000);
699 699
700 cp0_commit(dev);
700 gfx_commit(dev);
701 701 } }
702 702
703 703 /* /*
 
... ... void cps_me_init(struct pci_dev *dev)
706 706 * (4096 bytes) * (4096 bytes)
707 707 */ */
708 708
709 /* ring 0 GFX and compute */
710 static void cp0_init(struct pci_dev *dev)
709 /* ring 0 GFX */
710 static void gfx_init(struct pci_dev *dev)
711 711 { {
712 712 struct dev_drv_data *dd; struct dev_drv_data *dd;
713 713 u32 cp_rb_0_ctl; u32 cp_rb_0_ctl;
 
... ... static void cp0_init(struct pci_dev *dev)
732 732 wr32(dev, lower_32_bits(cp_rb_0_rptr_addr), CP_RB_0_RPTR_ADDR_LO); wr32(dev, lower_32_bits(cp_rb_0_rptr_addr), CP_RB_0_RPTR_ADDR_LO);
733 733 wr32(dev, upper_32_bits(cp_rb_0_rptr_addr), CP_RB_0_RPTR_ADDR_HI); wr32(dev, upper_32_bits(cp_rb_0_rptr_addr), CP_RB_0_RPTR_ADDR_HI);
734 734
735 wr32(dev, 0xff, SCRATCH_UMSK); /* specific to cp0? Not global? */
735 wr32(dev, 0xff, SCRATCH_UMSK); /* specific to gfx? Not global? */
736 736 mdelay(1); mdelay(1);
737 737 wr32(dev, cp_rb_0_ctl, CP_RB_0_CTL); wr32(dev, cp_rb_0_ctl, CP_RB_0_CTL);
738 738
739 739 /* 256 bytes aligned ok because it is GPU_PAGE_SZ aligned */ /* 256 bytes aligned ok because it is GPU_PAGE_SZ aligned */
740 wr32(dev, dd->ba.cp0_ring_map->gpu_addr >> 8, CP_RB_0_BASE);
740 wr32(dev, dd->ba.gfx_ring_map->gpu_addr >> 8, CP_RB_0_BASE);
741 741
742 dd->cp0.rptr = 0;
743 dd->cp0.wptr = 0;
744 spin_lock_init(&dd->cp0.lock);
742 dd->gfx.rptr = 0;
743 dd->gfx.wptr = 0;
744 spin_lock_init(&dd->gfx.lock);
745 745 } }
746 746
747 747 /* ring 1 compute only */ /* ring 1 compute only */
 
... ... void cps_init(struct pci_dev *dev)
857 857 */ */
858 858 wr32(dev, (wb_scratch_addr >> 8) & 0xffffffff, SCRATCH_ADDR); wr32(dev, (wb_scratch_addr >> 8) & 0xffffffff, SCRATCH_ADDR);
859 859
860 cp0_init(dev);
860 gfx_init(dev);
861 861 cp1_init(dev); cp1_init(dev);
862 862 cp2_init(dev); cp2_init(dev);
863 863 } }
864 864
865 void cp0_wr(struct pci_dev *dev, u32 v)
865 void gfx_wr(struct pci_dev *dev, u32 v)
866 866 { {
867 867 struct dev_drv_data *dd; struct dev_drv_data *dd;
868 868 u32 __iomem *r; u32 __iomem *r;
869 869
870 870 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
871 871
872 r = dd->ba.cp0_ring_map->cpu_addr;
873 r[dd->cp0.wptr++] = cpu_to_le32(v);
874 dd->cp0.wptr &= CP_RING_DW_MASK;
872 r = dd->ba.gfx_ring_map->cpu_addr;
873 r[dd->gfx.wptr++] = cpu_to_le32(v);
874 dd->gfx.wptr &= CP_RING_DW_MASK;
875 875 } }
876 876
877 void cp0_commit(struct pci_dev *dev)
877 void gfx_commit(struct pci_dev *dev)
878 878 { {
879 879 struct dev_drv_data *dd; struct dev_drv_data *dd;
880 880 u32 __iomem *r; u32 __iomem *r;
 
... ... void cp0_commit(struct pci_dev *dev)
882 882 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
883 883
884 884 /* match ring fetch alignment */ /* match ring fetch alignment */
885 r = dd->ba.cp0_ring_map->cpu_addr;
886 while (dd->cp0.wptr & CP_RING_PFP_DW_MASK)
887 r[dd->cp0.wptr++] = cpu_to_le32(PKT2);
885 r = dd->ba.gfx_ring_map->cpu_addr;
886 while (dd->gfx.wptr & CP_RING_PFP_DW_MASK)
887 r[dd->gfx.wptr++] = cpu_to_le32(PKT2);
888 888
889 889 wmb(); /* data write operations emitted before dma */ wmb(); /* data write operations emitted before dma */
890 890
891 dd->cp0.wptr &= CP_RING_DW_MASK;
892 wr32(dev, dd->cp0.wptr, CP_RB_0_WPTR);
891 dd->gfx.wptr &= CP_RING_DW_MASK;
892 wr32(dev, dd->gfx.wptr, CP_RB_0_WPTR);
893 893 rr32(dev, CP_RB_0_WPTR); rr32(dev, CP_RB_0_WPTR);
894 894 } }
895 895
File drivers/gpu/alga/amd/si/gpu/cps.h changed (mode: 100644) (index c04d2f0..8cab0fa)
... ... void cps_init(struct pci_dev *dev);
126 126 void cps_me_init(struct pci_dev *dev); void cps_me_init(struct pci_dev *dev);
127 127 void cps_enable(struct pci_dev *dev); void cps_enable(struct pci_dev *dev);
128 128 void cps_ctx_clr(struct pci_dev *dev); void cps_ctx_clr(struct pci_dev *dev);
129 void cp0_wr(struct pci_dev *dev, u32 v);
130 void cp0_commit(struct pci_dev *dev);
129 void gfx_wr(struct pci_dev *dev, u32 v);
130 void gfx_commit(struct pci_dev *dev);
131 131 void cp1_wr(struct pci_dev *dev, u32 v); void cp1_wr(struct pci_dev *dev, u32 v);
132 132 void cp1_commit(struct pci_dev *dev); void cp1_commit(struct pci_dev *dev);
133 133 void cp2_wr(struct pci_dev *dev, u32 v); void cp2_wr(struct pci_dev *dev, u32 v);
File drivers/gpu/alga/amd/si/patterns/tri.c changed (mode: 100644) (index 253dcd9..0601d0e)
... ... long ptn_tri(struct pci_dev *dev, struct ptn_tri *p)
1019 1019 ib.d[ib.dws++] = PKT2; ib.d[ib.dws++] = PKT2;
1020 1020 indirect_cpy(dev, ib.gpu_addr, (u32*)&ib.d[0], ib.dws); indirect_cpy(dev, ib.gpu_addr, (u32*)&ib.d[0], ib.dws);
1021 1021
1022 cp0_wr(dev, PKT3(PKT3_IB, 3));
1023 cp0_wr(dev, lower_32_bits(ib.gpu_addr));
1024 cp0_wr(dev, upper_32_bits(ib.gpu_addr));
1025 cp0_wr(dev, ib.dws);
1026 cp0_commit(dev);
1022 gfx_wr(dev, PKT3(PKT3_IB, 3));
1023 gfx_wr(dev, lower_32_bits(ib.gpu_addr));
1024 gfx_wr(dev, upper_32_bits(ib.gpu_addr));
1025 gfx_wr(dev, ib.dws);
1026 gfx_commit(dev);
1027 1027 return 0; return 0;
1028 1028 } }
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