sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
all vram in bus aperture d1c02a0dd98d424ff214d25a245ab6f4aeb277b0 Sylvain BERTRAND 2013-07-22 13:30:40
multi-monitor fix c0af3dfa6f5142553ff7977643d5bdcc2a99ebe2 Sylvain BERTRAND 2013-07-02 02:41:22
displayport fix 348d270e68ca95db356486c24925e42fd998c6b8 Sylvain BERTRAND 2013-07-01 21:45:45
atombios crtcs states init f0c161e2f8cd6a8265fbcbad29c8d5b7e2fef2f3 Sylvain BERTRAND 2013-06-29 15:01:43
mainly dce tidy 94a5c6a097394b4b8e413207380cb4e4bad9f43a Sylvain BERTRAND 2013-06-29 10:46:13
upstream golden registers 2d9afbd743277f615e089c50ee186a149978b5a5 Sylvain BERTRAND 2013-06-12 23:32:12
suspend-to-ram and gpu context loss support 7a9840cd7d37c89624149f14b44222160f7311ff Sylvain BERTRAND 2013-05-23 19:23:36
verde gpu config upstream fix 05afeb06a76317f028061b8efc66b215338b211d Sylvain BERTRAND 2013-05-21 20:35:16
finally, pp state description index fixed b03152e5f8253db7b01f6d507ed18eb71d4d2a17 Sylvain BERTRAND 2013-05-01 22:27:53
power management continued e8e2e1e2a8dc438a1f15ec3d7ec72b2ecd431f08 Sylvain BERTRAND 2013-05-01 00:57:09
powerplay preliminary support e65cce387d8aed980f48b0f58092bea31175b79d Sylvain BERTRAND 2013-04-26 17:48:11
dce sysfs: remove obsolete crtc word 288dd69b5196b3848b90e993b4d45383d7d0c972 Sylvain BERTRAND 2013-04-26 13:54:02
dce:i te idx 74e29494f7283fa105fef53291053e3630b605bf Sylvain BERTRAND 2013-04-26 13:28:37
upstream: new pci ids dda82ff321c33e0d7123dd06b0466775d9f96141 Sylvain BERTRAND 2013-04-26 12:22:27
cleaner error handling f853e060408068567efa895448ebc5807b5e5485 Sylvain BERTRAND 2013-03-22 01:28:11
alga cosmetics a8b013ce129bb7218fbf5a331f09828322219ac6 Sylvain BERTRAND 2013-03-22 01:21:27
massive comestics f0ff31f57512bd63b707a34d8f6252091facb632 Sylvain BERTRAND 2013-03-22 01:02:42
sysfs discret_vram property cf1c115de509b4449d7e1af1e21bf26010904c46 Sylvain BERTRAND 2013-03-19 00:56:39
dce6 crtc attribute 8f7a977603c22668c56d36c59868b74426fcf371 Sylvain BERTRAND 2013-03-12 17:02:51
ioctl edid not big enough fa9570a5821514fdb281d81ce801c2c86592dc69 Sylvain BERTRAND 2013-03-11 22:14:17
Commit d1c02a0dd98d424ff214d25a245ab6f4aeb277b0 - all vram in bus aperture
Author: Sylvain BERTRAND
Author date (UTC): 2013-07-22 13:30
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-07-22 13:30
Parent(s): c0af3dfa6f5142553ff7977643d5bdcc2a99ebe2
Signer:
Signing key:
Signing status: N
Tree: b88d744ac59b60650ad5e2c9a43fd7849e8afd37
File Lines added Lines deleted
drivers/gpu/alga/amd/si/bus/ba.c 11 8
drivers/gpu/alga/amd/si/bus/ba.h 2 0
drivers/gpu/alga/amd/si/regs.h 6 0
File drivers/gpu/alga/amd/si/bus/ba.c changed (mode: 100644) (index 54683e8..d139374)
32 32 #define PTE_READABLE (1 << 5) #define PTE_READABLE (1 << 5)
33 33 #define PTE_WRITEABLE (1 << 6) #define PTE_WRITEABLE (1 << 6)
34 34
35 /* TODO:should go full vram, and do an identity mapping in aperture */
36 static const u64 ba_range_sz = 512 * 1024 *1024;
37
38 35 static void tlb_flush(struct pci_dev *dev) static void tlb_flush(struct pci_dev *dev)
39 36 { {
40 37 /* flush hdp cache */ /* flush hdp cache */
 
... ... long ba_init(struct pci_dev *dev)
141 138
142 139 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
143 140
144 if (ba_range_sz % GPU_PAGE_SZ) {
141 /* the bus aperture is the size of vram */
142 dd->ba.sz = rr32(dev, CFG_MEM_SZ) * 1024 * 1024;
143
144 if (dd->ba.sz % GPU_PAGE_SZ) {
145 145 dev_err(&dev->dev, dev_err(&dev->dev,
146 "ba:aperture size is not aligned on gpu page size\n");
146 "ba:aperture size (vram size) is not aligned on gpu page size\n");
147 147 return -BA_ERR; return -BA_ERR;
148 148 } }
149 149
 
... ... long ba_init(struct pci_dev *dev)
151 151 ba_start = rng_align(dd->vram.mng.s + dd->vram.mng.sz, GPU_PAGE_SZ); ba_start = rng_align(dd->vram.mng.s + dd->vram.mng.sz, GPU_PAGE_SZ);
152 152
153 153 r = rng_alloc_align(&dd->ba.pt_start, &dd->vram.mng, r = rng_alloc_align(&dd->ba.pt_start, &dd->vram.mng,
154 (ba_range_sz / GPU_PAGE_SZ) * sizeof(u64),
154 (dd->ba.sz / GPU_PAGE_SZ) * sizeof(u64),
155 155 GPU_PAGE_SZ); GPU_PAGE_SZ);
156 156 if (r == -ALGA_ERR) { if (r == -ALGA_ERR) {
157 157 dev_err(&dev->dev, dev_err(&dev->dev,
 
... ... long ba_init(struct pci_dev *dev)
159 159 return -BA_ERR; return -BA_ERR;
160 160 } }
161 161
162 rng_mng_init(&dd->ba.mng, ba_start, ba_range_sz);
162 rng_mng_init(&dd->ba.mng, ba_start, dd->ba.sz);
163 163 INIT_LIST_HEAD(&dd->ba.maps); INIT_LIST_HEAD(&dd->ba.maps);
164 164
165 165 pt_of = dd->ba.pt_start - dd->vram.mng.s; pt_of = dd->ba.pt_start - dd->vram.mng.s;
 
... ... long ba_init(struct pci_dev *dev)
167 167 | PTE_SNOOPED | PTE_READABLE | PTE_WRITEABLE; | PTE_SNOOPED | PTE_READABLE | PTE_WRITEABLE;
168 168
169 169 /* TODO:use indirect vram access, to dismiss the use of PCI bar mapping */ /* TODO:use indirect vram access, to dismiss the use of PCI bar mapping */
170 for (i = 0; i < ba_range_sz/GPU_PAGE_SZ; ++i)
170 for (i = 0; i < dd->ba.sz / GPU_PAGE_SZ; ++i)
171 171 writeq(pte, dd->vram.bar0 + pt_of + i * sizeof(pte)); writeq(pte, dd->vram.bar0 + pt_of + i * sizeof(pte));
172 172
173 173 /* make sure the gpu pte updates where sent over the bus */ /* make sure the gpu pte updates where sent over the bus */
 
... ... long ba_init(struct pci_dev *dev)
176 176 tlb_flush(dev); tlb_flush(dev);
177 177
178 178 pt_init(dev); pt_init(dev);
179 dev_info(&dev->dev,
180 "ba:page table at 0x%016llx aperture size=0x%016llx\n",
181 dd->ba.pt_start, dd->ba.sz);
179 182 return 0; return 0;
180 183 } }
181 184
File drivers/gpu/alga/amd/si/bus/ba.h changed (mode: 100644) (index 11417fc..2d857f9)
... ... struct ba_map {
22 22 }; };
23 23
24 24 struct ba { struct ba {
25 u64 sz;
26
25 27 dma_addr_t dummy_bus_addr; dma_addr_t dummy_bus_addr;
26 28 void *dummy_cpu_addr; void *dummy_cpu_addr;
27 29
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 84a1ab6..e7d2f30)
... ... static inline u32 get(u32 mask, u32 v)
29 29 return (v & mask) >> shift; return (v & mask) >> shift;
30 30 } }
31 31
32 #define MM_IDX 0x0
33 #define MI_VRAM BIT(31)
34 #define MM_DATA 0x4
35
36 #define MM_IDX_HI 0x18
37
32 38 #define SRBM_STATUS 0xe50 #define SRBM_STATUS 0xe50
33 39 #define SS_MC_STATUS 0x00001f00 #define SS_MC_STATUS 0x00001f00
34 40
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