sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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List of commits:
Subject Hash Author Date (UTC)
update atombios set pixel mode 8b22745c66edd8ba7187bef3a96d7b2537b5b003 Sylvain BERTRAND 2012-07-29 22:40:06
si lut code 973e26e467bbe81e2e113aefa9fe35fd8dad18e2 Sylvain BERTRAND 2012-07-29 14:20:21
driver upgrade continued aade78ad4ccb4c1d59a59b6b9b265a58890fe733 Sylvain BERTRAND 2012-07-26 12:52:49
driver upgrade to si continued aa95cdd8e8cf9345a1a0ae41e9939280f46d58ba Sylvain BERTRAND 2012-07-25 23:06:27
si upgrade continuing... 16334c7d664a9c317f94f2a797d46430dab5b5e9 Sylvain BERTRAND 2012-07-24 22:26:44
Initial commit 3389e62de3050a725a673bd3564c49a83f626b33 Sylvain BERTRAND 2012-07-23 21:29:37
Commit 8b22745c66edd8ba7187bef3a96d7b2537b5b003 - update atombios set pixel mode
Author: Sylvain BERTRAND
Author date (UTC): 2012-07-29 22:40
Committer name: Sylvain BERTRAND
Committer date (UTC): 2012-07-29 22:40
Parent(s): 973e26e467bbe81e2e113aefa9fe35fd8dad18e2
Signer:
Signing key:
Signing status: N
Tree: 044db74505621b4bc03018d5af0304be8fea5ff1
File Lines added Lines deleted
drivers/gpu/alga/amd/atombios/dce.c 12 13
drivers/gpu/alga/amd/atombios/tables/pixel_clock_set.h 32 39
drivers/gpu/alga/amd/si/drv.c 19 13
File drivers/gpu/alga/amd/atombios/dce.c changed (mode: 100644) (index 2b80e4f..2678caf)
... ... static int default_disp_clk_freq(struct atombios *atb, u32 *clk)
354 354 } }
355 355 *clk = get_unaligned_le32(&info->default_disp_clk_freq); *clk = get_unaligned_le32(&info->default_disp_clk_freq);
356 356 if (*clk == 0) if (*clk == 0)
357 *clk = 60000; /* 600 Mhz for DCE4 */
357 *clk = 54000; /* 540 Mhz for DCE6 */
358 358 return 0; return 0;
359 359 } }
360 360
 
... ... int atb_crtc_dcpll(struct atombios *atb)
531 531 u16 of; u16 of;
532 532 struct master_cmd_tbl *cmd_tbl; struct master_cmd_tbl *cmd_tbl;
533 533 struct common_cmd_tbl_hdr *pixel_clk_set; struct common_cmd_tbl_hdr *pixel_clk_set;
534 struct pixel_clk_set_params_v1_5 *ps;
534 struct pixel_clk_set_params *ps;
535 535 int r; int r;
536 536 u32 clk_freq; u32 clk_freq;
537 537
 
... ... int atb_crtc_dcpll(struct atombios *atb)
546 546 "%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev, "%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev,
547 547 pixel_clk_set->hdr.tbl_content_rev); pixel_clk_set->hdr.tbl_content_rev);
548 548 if (pixel_clk_set->hdr.tbl_fmt_rev != 1 if (pixel_clk_set->hdr.tbl_fmt_rev != 1
549 || pixel_clk_set->hdr.tbl_content_rev != 5) {
549 || pixel_clk_set->hdr.tbl_content_rev != 6) {
550 550 dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not " dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not "
551 551 "supported"); "supported");
552 552 r = -ATB_ERR; r = -ATB_ERR;
 
... ... int atb_crtc_dcpll(struct atombios *atb)
561 561 r = -ATB_ERR; r = -ATB_ERR;
562 562 goto unlock_mutex; goto unlock_mutex;
563 563 } }
564 ps = (struct pixel_clk_set_params_v1_5 *)atb->g_ctx.ps_top;
564 ps = (struct pixel_clk_set_params *)atb->g_ctx.ps_top;
565 565
566 566 r = default_disp_clk_freq(atb, &clk_freq); r = default_disp_clk_freq(atb, &clk_freq);
567 567 if (r != 0) { if (r != 0) {
 
... ... int atb_crtc_dcpll(struct atombios *atb)
573 573 * if the default dcpll clock is specified, pixel_clk_set provides the * if the default dcpll clock is specified, pixel_clk_set provides the
574 574 * dividers * dividers
575 575 */ */
576 ps->crtc = CRTC_INVALID;
577 put_unaligned_le16((u16)clk_freq, &ps->pixel_clk);
578 ps->ppll = DCPLL;
576 put_unaligned_le16((u16)clk_freq, &ps->disp_eng_clk);
577 ps->ppll = PPLL0;
579 578
580 579 atb->g_ctx.fb_wnd = 0; atb->g_ctx.fb_wnd = 0;
581 580 atb->g_ctx.regs_blk = 0; atb->g_ctx.regs_blk = 0;
 
... ... int atb_crtc_virtual_pixel_clk(struct atombios *atb, unsigned i, unsigned clk)
595 594 u16 of; u16 of;
596 595 struct master_cmd_tbl *cmd_tbl; struct master_cmd_tbl *cmd_tbl;
597 596 struct common_cmd_tbl_hdr *pixel_clk_set; struct common_cmd_tbl_hdr *pixel_clk_set;
598 struct pixel_clk_set_params_v1_5 *ps;
597 struct pixel_clk_set_params *ps;
599 598 int r; int r;
600 599
601 600 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
 
... ... int atb_crtc_virtual_pixel_clk(struct atombios *atb, unsigned i, unsigned clk)
609 608 "%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev, "%u.%u\n", of, pixel_clk_set->hdr.tbl_fmt_rev,
610 609 pixel_clk_set->hdr.tbl_content_rev); pixel_clk_set->hdr.tbl_content_rev);
611 610 if (pixel_clk_set->hdr.tbl_fmt_rev != 1 if (pixel_clk_set->hdr.tbl_fmt_rev != 1
612 || pixel_clk_set->hdr.tbl_content_rev != 5) {
611 || pixel_clk_set->hdr.tbl_content_rev != 6) {
613 612 dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not " dev_err(atb->adev.dev, "atombios: pixel_clk_set revision not "
614 613 "supported"); "supported");
615 614 r = -ATB_ERR; r = -ATB_ERR;
 
... ... int atb_crtc_virtual_pixel_clk(struct atombios *atb, unsigned i, unsigned clk)
624 623 r = -ATB_ERR; r = -ATB_ERR;
625 624 goto unlock_mutex; goto unlock_mutex;
626 625 } }
627 ps = (struct pixel_clk_set_params_v1_5 *)atb->g_ctx.ps_top;
628 ps->crtc = i;
629 ps->ppll = 0xff; /* invalid pll id for dp virtual pixel clk */
630 put_unaligned_le16((u16)(clk / 10), &ps->pixel_clk);
626 ps = (struct pixel_clk_set_params *)atb->g_ctx.ps_top;
627 put_unaligned_le16(SET(CRTC, i) | SET(PIXEL_CLK, clk / 10),
628 &ps->crtc_pixel_clk);
629 ps->ppll = PPLL_INVALID; /* invalid pll id for dp virtual pixel clk */
631 630
632 631 atb->g_ctx.fb_wnd = 0; atb->g_ctx.fb_wnd = 0;
633 632 atb->g_ctx.regs_blk = 0; atb->g_ctx.regs_blk = 0;
File drivers/gpu/alga/amd/atombios/tables/pixel_clock_set.h changed (mode: 100644) (index b20e62d..266373c)
6 6 * Original code from Advanced Micro Devices, Inc. * Original code from Advanced Micro Devices, Inc.
7 7 */ */
8 8
9 #define CRTC0 0
10 #define CRTC1 1
11 #define CRTC2 2
12 #define CRTC3 3
13 #define CRTC4 4
14 #define CRTC5 5
15 #define CRTC_INVALID 0xff
16
17 9 #define PPLL1 0 #define PPLL1 0
18 10 #define PPLL2 1 #define PPLL2 1
19 #define DCPLL 2
20 11 #define PPLL0 2 #define PPLL0 2
21 12 #define EXT_PLL1 8 #define EXT_PLL1 8
22 13 #define EXT_PLL2 9 #define EXT_PLL2 9
23 14 #define EXT_CLK 10 #define EXT_CLK 10
24 15 #define PPLL_INVALID 0xff #define PPLL_INVALID 0xff
25 16
26 struct pixel_clk_set_params_v1_5 {
27 u8 crtc; /* CRTC0~5, indicate the CRTC controller to
28 drive the pixel clock. Not used for DCPLL
29 case. */
17 struct pixel_clk_set_params {
30 18 union { union {
31 u8 rsvd0;
32 u8 frac_fb_div; /* not supposed to be around */
19 __le32 disp_eng_clk;
20 __le32 crtc_pixel_clk; /* Target the pixel clock to drive the
21 CRTC timing. 0 means disable PPLL.
22 10kHz units */
23 #define CRTC_MASK 0xff000000
24 #define CRTC_SHIFT 24
25 #define PIXEL_CLK_MASK 0x00ffffff
26 #define PIXEL_CLK_SHIFT 0
33 27 }; };
34 __le16 pixel_clk; /* Target the pixel clock to drive the CRTC
35 timing. 0 means disable PPLL/DCPLL. 10kHz unit. */
36 __le16 fb_div; /* feedback divider integer part */
37 u8 post_div; /* post divider */
38 u8 ref_div; /* Reference divider */
39 u8 ppll; /* PPLL1/PPLL2/DCPLL */
40 u8 trans_id; /* transmitter object id */
41 u8 enc_mode; /* encoder mode */
42 u8 misc_info; /* [0] Force program PPLL
43 [1] when VGA timing is used
44 [3:2] HDMI panel bit depth
45 0: 24bpp
46 1: 30bpp
47 2: 32bpp
48 [4] RefClock source for PPLL
49 0: XTLAIN (default mode)
50 1: other external clock source, which
51 is pre-defined by VBIOS depend on
52 the feature required.
53 [7:5] reserved */
54 __le32 fb_div_dec_frac; /* 20bits feedback divider decimal fraction
55 part, range from 1~999999 (0.000001 to
56 0.999999) */
57
28 __le16 fb_div; /* feedback divider integer part */
29 u8 post_div; /* post divider */
30 u8 ref_div; /* reference divider */
31 u8 ppll; /* PPLL0/PPLL1/PPLL2 */
32 u8 trans_id; /* transmitter object id */
33 u8 enc_mode; /* encoder mode, 0 for dp */
34 u8 misc_info; /* [0] Force program PPLL
35 [1] when VGA timing is used
36 [3:2] HDMI panel bit depth
37 0: 24bpp
38 1: 36bpp
39 2: 30bpp
40 3: 48bpp
41 [4] RefClock source for PPLL
42 0: XTLAIN (default mode)
43 1: other external clock source,
44 which is pre-defined by
45 VBIOS depend on the feature
46 required.
47 [7:5] reserved */
48 __le32 fb_div_dec_frac; /* 20bits feedback divider decimal
49 fraction part, range from 1~999999
50 (0.000001 to 0.999999) */
58 51 } __packed; } __packed;
59 52 #endif #endif
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index 3c50339..8242a40)
... ... static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id)
791 791 if (mc_wait_for_idle(dev)) if (mc_wait_for_idle(dev))
792 792 dev_warn(&dev->dev, "probe:wait for mc idle timed out\n"); dev_warn(&dev->dev, "probe:wait for mc idle timed out\n");
793 793
794 ucode_mc_program(dev);
794 //TEST:totally unstable
795 //ucode_mc_program(dev);
795 796
796 err = mc_program(dev);
797 if (err)
798 goto err_release_firmware;
797 //err = mc_program(dev);
798 //if (err)
799 // goto err_release_firmware;
799 800 //************************* //*************************
800 801
801 802 hdp_init(dev, addr_cfg); hdp_init(dev, addr_cfg);
802 803
803 err = ba_init(dev);
804 if (err)
805 goto err_release_firmware;
804 //TEST:compiled out because probably dependent on totally unstable mr programming
805 //err = ba_init(dev);
806 //if (err)
807 // goto err_release_firmware;
806 808
807 err = ba_map(dev); /* map wb page, ih ring, cp rings */
808 if (err)
809 goto err_ba_shutdown;
809 //err = ba_map(dev); /* map wb page, ih ring, cp rings */
810 //if (err)
811 // goto err_ba_shutdown;
810 812
811 813 err = dce6_init(dd->dce, addr_cfg); err = dce6_init(dd->dce, addr_cfg);
812 814 if (err) if (err)
 
... ... err_clr_master:
859 861 dce6_shutdown(dd->dce); dce6_shutdown(dd->dce);
860 862
861 863 err_ba_unmap: err_ba_unmap:
862 ba_unmap(dev);
864 //TEST
865 //ba_unmap(dev);
863 866
864 867 err_ba_shutdown: err_ba_shutdown:
865 ba_shutdown(dev);
868 //TEST
869 //ba_shutdown(dev);
866 870
867 871 err_release_firmware: err_release_firmware:
868 872 ucode_release(dev); ucode_release(dev);
 
... ... static void __devexit remove(struct pci_dev *dev)
920 924 kfree(dd->dce); kfree(dd->dce);
921 925 free_irq(dev->irq, (void*)dev); free_irq(dev->irq, (void*)dev);
922 926
923 ba_unmap(dev);
927 //TEST
928 //ba_unmap(dev);
924 929
930 //TEST
925 931 ba_shutdown(dev); ba_shutdown(dev);
926 932
927 933 ucode_release(dev); ucode_release(dev);
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