File drivers/gpu/alga/amd/si/dyn_pm/ctx.h changed (mode: 100644) (index d83e597..30b19d4) |
... |
... |
struct ctx { |
53 |
53 |
struct atb_mc_reg_tbl atb_mc_reg_tbl; |
struct atb_mc_reg_tbl atb_mc_reg_tbl; |
54 |
54 |
u32 atb_mc_regs_valid; |
u32 atb_mc_regs_valid; |
55 |
55 |
|
|
56 |
|
/* upstream: "no room in bios, then added on the fly"... */ |
|
|
56 |
|
/* upstream: "no room in bios, then regs added on the fly"... */ |
57 |
57 |
u8 special_mc_regs_n; |
u8 special_mc_regs_n; |
58 |
58 |
u8 special_mc_regs_valid; |
u8 special_mc_regs_valid; |
59 |
59 |
u32 special_mc_regs_addrs[SPECIAL_MC_REGS_N_MAX]; |
u32 special_mc_regs_addrs[SPECIAL_MC_REGS_N_MAX]; |
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index ea2594d..fc401d9) |
... |
... |
void smc_mc_reg_tbl_initial_init(struct ctx *ctx, |
192 |
192 |
initial_lvl_mem_clk = get_unaligned_be32( |
initial_lvl_mem_clk = get_unaligned_be32( |
193 |
193 |
&smc_state_tbl->initial_lvl.mem_clk.clk); |
&smc_state_tbl->initial_lvl.mem_clk.clk); |
194 |
194 |
|
|
195 |
|
/* select a set of mc regs which can support the pwr lvl */ |
|
|
195 |
|
/* select a set of mc regs which can support the pwr lvl mem clk */ |
196 |
196 |
for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n; |
for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n; |
197 |
197 |
++mc_reg_set_idx) { |
++mc_reg_set_idx) { |
198 |
198 |
struct atb_mc_reg_set *mc_reg_set; |
struct atb_mc_reg_set *mc_reg_set; |
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_reg_tbl.c changed (mode: 100644) (index f552e0d..c9d3a53) |
37 |
37 |
#include "private.h" |
#include "private.h" |
38 |
38 |
#include "initial.h" |
#include "initial.h" |
39 |
39 |
#include "emergency.h" |
#include "emergency.h" |
|
40 |
|
#include "ulv.h" |
40 |
41 |
|
|
41 |
42 |
static u8 all_valid_regs_n_cnt(struct ctx *ctx) |
static u8 all_valid_regs_n_cnt(struct ctx *ctx) |
42 |
43 |
{ |
{ |
|
... |
... |
long smc_mc_reg_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl, |
183 |
184 |
|
|
184 |
185 |
smc_mc_reg_tbl_initial_init(ctx, smc_state_tbl, smc_mc_reg_tbl); |
smc_mc_reg_tbl_initial_init(ctx, smc_state_tbl, smc_mc_reg_tbl); |
185 |
186 |
smc_mc_reg_tbl_emergency_init(ctx, smc_mc_reg_tbl); |
smc_mc_reg_tbl_emergency_init(ctx, smc_mc_reg_tbl); |
|
187 |
|
smc_mc_reg_tbl_ulv_init(ctx, smc_mc_reg_tbl); |
186 |
188 |
return 0; |
return 0; |
187 |
189 |
} |
} |
188 |
190 |
|
|
File drivers/gpu/alga/amd/si/dyn_pm/ulv.c changed (mode: 100644) (index f78a2e4..a444fe2) |
36 |
36 |
#include "private.h" |
#include "private.h" |
37 |
37 |
#include "smc.h" |
#include "smc.h" |
38 |
38 |
#include "smc_lvl.h" |
#include "smc_lvl.h" |
|
39 |
|
#include "smc_mc_reg_tbl.h" |
39 |
40 |
|
|
40 |
41 |
long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl) |
long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl) |
41 |
42 |
{ |
{ |
|
... |
... |
void smc_sw_regs_ulv_init(struct ctx *ctx) |
84 |
85 |
smc_sw_wr32(ctx->dev, ctx->pcie_lanes_n, |
smc_sw_wr32(ctx->dev, ctx->pcie_lanes_n, |
85 |
86 |
SMC_SW_NON_ULV_PCIE_LINK_WIDTH); |
SMC_SW_NON_ULV_PCIE_LINK_WIDTH); |
86 |
87 |
} |
} |
|
88 |
|
|
|
89 |
|
static u8 mc_reg_set_find(struct ctx *ctx, u32 mem_clk) |
|
90 |
|
{ |
|
91 |
|
u8 mc_reg_set_idx; |
|
92 |
|
|
|
93 |
|
/* select a set of mc regs which can support the pwr lvl mem clk */ |
|
94 |
|
for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n; |
|
95 |
|
++mc_reg_set_idx) { |
|
96 |
|
struct atb_mc_reg_set *mc_reg_set; |
|
97 |
|
|
|
98 |
|
mc_reg_set = &ctx->atb_mc_reg_tbl.sets[mc_reg_set_idx]; |
|
99 |
|
|
|
100 |
|
if (mem_clk <= mc_reg_set->mem_clk_max) |
|
101 |
|
break; |
|
102 |
|
} |
|
103 |
|
|
|
104 |
|
/* |
|
105 |
|
* Not found, then try the last one as a work around which should |
|
106 |
|
* accomodate the highest mem clk. The tbl seems to be sorted |
|
107 |
|
* from lowest mem clk to highest mem clk. |
|
108 |
|
*/ |
|
109 |
|
if (mc_reg_set_idx == ctx->atb_mc_reg_tbl.sets_n) |
|
110 |
|
--mc_reg_set_idx; /* we presume we have at least one set */ |
|
111 |
|
return mc_reg_set_idx; |
|
112 |
|
} |
|
113 |
|
|
|
114 |
|
void smc_mc_reg_tbl_ulv_init(struct ctx *ctx, |
|
115 |
|
struct smc_mc_reg_tbl *smc_mc_reg_tbl) |
|
116 |
|
{ |
|
117 |
|
u8 mc_reg_set_idx; |
|
118 |
|
|
|
119 |
|
/* |
|
120 |
|
* for the ulv state, if the atombios define an ulv pwr lvl, do |
|
121 |
|
* use the mem clk from here, if not, use the firt set of mc reg, which |
|
122 |
|
* should be targetted for the lowest mem clk since sets are sorted |
|
123 |
|
* from lowest mem clk to highest mem clk |
|
124 |
|
*/ |
|
125 |
|
if (ctx->atb_ulv.lvls_n) { |
|
126 |
|
u32 mem_clk; |
|
127 |
|
|
|
128 |
|
mem_clk = ctx->atb_ulv.lvls[0].mem_clk; |
|
129 |
|
|
|
130 |
|
mc_reg_set_idx = mc_reg_set_find(ctx, mem_clk); |
|
131 |
|
} else |
|
132 |
|
mc_reg_set_idx = 0; |
|
133 |
|
|
|
134 |
|
smc_mc_reg_set_load(ctx, mc_reg_set_idx, |
|
135 |
|
&smc_mc_reg_tbl->sets[SMC_MC_REG_TBL_ULV_SLOT]); |
|
136 |
|
} |
|
137 |
|
|
File drivers/gpu/alga/amd/si/dyn_pm/ulv.h changed (mode: 100644) (index 74a1cc1..8c8be4b) |
8 |
8 |
long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl); |
long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl); |
9 |
9 |
void ulv_program(struct pci_dev *dev); |
void ulv_program(struct pci_dev *dev); |
10 |
10 |
void smc_sw_regs_ulv_init(struct ctx *ctx); |
void smc_sw_regs_ulv_init(struct ctx *ctx); |
|
11 |
|
void smc_mc_reg_tbl_ulv_init(struct ctx *ctx, |
|
12 |
|
struct smc_mc_reg_tbl *smc_mc_reg_tbl); |
11 |
13 |
#endif |
#endif |