List of commits:
Subject Hash Author Date (UTC)
mc reg tbl init for the ulv state 97d55c06f7eeb31dd6f6a95fb13b30ddd22be157 Sylvain BERTRAND 2014-01-23 11:29:32
mc reg tbl init for the emergency state 7cf2fffd8bf166af90b20301652d03400feba029 Sylvain BERTRAND 2014-01-23 10:55:52
move smc sw related to mc reg tbl cbdb219935cc25639e5dca06ba99db995f87bef9 Sylvain BERTRAND 2014-01-23 10:15:53
smc mc reg tbl init for the initial state 1aa130d818c0aca415c0b76c80ec4bdb1e030a3f Sylvain BERTRAND 2014-01-22 18:01:49
clean way to deal with state and lvls 362777b13abdfacbeb0612e59c301e04dd2a7d65 Sylvain BERTRAND 2014-01-22 14:01:45
mc reg tbl reg address init 156ba053088bafba7a99fc2f1c2c0e2ca11d7f97 Sylvain BERTRAND 2014-01-22 13:15:15
mc register value valid bit set 4fabfcbad702789b9dbfd36d5fcaae8d0f9424f4 Sylvain BERTRAND 2014-01-22 02:31:53
addition of mc special registers ee876d15d34a720ebf4c26c57481d467fecbf1d5 Sylvain BERTRAND 2014-01-22 01:52:24
mc regs and fixes 6cbf7ddf6cc3ab42487d3ae040f3f8feeb9b5b99 Sylvain BERTRAND 2014-01-16 17:38:22
ulv state fde4ccf60791e6db319f98593318ac6ae0fa1961 Sylvain BERTRAND 2013-11-20 00:44:36
atombios:atb_eng_mem_pll_compute and more 633c0d754bc9d36902a3bf620cbb11282dc6a4a7 Sylvain BERTRAND 2013-11-13 12:48:15
atombios:atb_eng_mem_set added 792770998bdfbc1da15a3e4b8c585134134de5b2 Sylvain BERTRAND 2013-11-13 08:28:41
atombios data and dump 702d5ca1cb1d6d28ea33e5c550ece8a2f04976cc Sylvain BERTRAND 2013-11-13 07:56:18
tens of thousand of lines to refactor e6067d9bf38a4f6d71ecc8cfe3bb0c52f7a44834 Sylvain BERTRAND 2013-11-13 01:51:14
shame on me 8d3c8a1c1cb494c723603b7062a5b0cdaa4742be Sylvain BERTRAND 2013-11-04 00:37:42
writeX and readX already do the leX swapping 3b7d5a29f98160ed555309952a5e7f2a1f265684 Sylvain BERTRAND 2013-10-27 11:39:42
first part of dynamic clock/power management 732f467ca8db8ba676fdce6a5387b1fa9bc6964b Sylvain BERTRAND 2013-10-23 05:01:48
dce:upstream new addr conf reg f7d4efda311c439b3a084b935e563eab47216613 Sylvain BERTRAND 2013-10-21 02:33:41
atombios cleanup 74f7fae53d33509b2a160d8060f9906ca099772a Sylvain BERTRAND 2013-10-21 00:45:57
upstream: do not force the cp internal int state b9bdb0bd3ab4a2e2407720f077ff47dc7c0c6d32 Sylvain BERTRAND 2013-09-24 01:23:52
Commit 97d55c06f7eeb31dd6f6a95fb13b30ddd22be157 - mc reg tbl init for the ulv state
Author: Sylvain BERTRAND
Author date (UTC): 2014-01-23 11:29
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-01-23 11:29
Parent(s): 7cf2fffd8bf166af90b20301652d03400feba029
Signer:
Signing key:
Signing status: N
Tree: 3043d6235b8b8c0f1153c13a3a9744f6240d330a
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/ctx.h 1 1
drivers/gpu/alga/amd/si/dyn_pm/initial.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/smc_mc_reg_tbl.c 2 0
drivers/gpu/alga/amd/si/dyn_pm/ulv.c 51 0
drivers/gpu/alga/amd/si/dyn_pm/ulv.h 2 0
File drivers/gpu/alga/amd/si/dyn_pm/ctx.h changed (mode: 100644) (index d83e597..30b19d4)
... ... struct ctx {
53 53 struct atb_mc_reg_tbl atb_mc_reg_tbl; struct atb_mc_reg_tbl atb_mc_reg_tbl;
54 54 u32 atb_mc_regs_valid; u32 atb_mc_regs_valid;
55 55
56 /* upstream: "no room in bios, then added on the fly"... */
56 /* upstream: "no room in bios, then regs added on the fly"... */
57 57 u8 special_mc_regs_n; u8 special_mc_regs_n;
58 58 u8 special_mc_regs_valid; u8 special_mc_regs_valid;
59 59 u32 special_mc_regs_addrs[SPECIAL_MC_REGS_N_MAX]; u32 special_mc_regs_addrs[SPECIAL_MC_REGS_N_MAX];
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index ea2594d..fc401d9)
... ... void smc_mc_reg_tbl_initial_init(struct ctx *ctx,
192 192 initial_lvl_mem_clk = get_unaligned_be32( initial_lvl_mem_clk = get_unaligned_be32(
193 193 &smc_state_tbl->initial_lvl.mem_clk.clk); &smc_state_tbl->initial_lvl.mem_clk.clk);
194 194
195 /* select a set of mc regs which can support the pwr lvl */
195 /* select a set of mc regs which can support the pwr lvl mem clk */
196 196 for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n; for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n;
197 197 ++mc_reg_set_idx) { ++mc_reg_set_idx) {
198 198 struct atb_mc_reg_set *mc_reg_set; struct atb_mc_reg_set *mc_reg_set;
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_reg_tbl.c changed (mode: 100644) (index f552e0d..c9d3a53)
37 37 #include "private.h" #include "private.h"
38 38 #include "initial.h" #include "initial.h"
39 39 #include "emergency.h" #include "emergency.h"
40 #include "ulv.h"
40 41
41 42 static u8 all_valid_regs_n_cnt(struct ctx *ctx) static u8 all_valid_regs_n_cnt(struct ctx *ctx)
42 43 { {
 
... ... long smc_mc_reg_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
183 184
184 185 smc_mc_reg_tbl_initial_init(ctx, smc_state_tbl, smc_mc_reg_tbl); smc_mc_reg_tbl_initial_init(ctx, smc_state_tbl, smc_mc_reg_tbl);
185 186 smc_mc_reg_tbl_emergency_init(ctx, smc_mc_reg_tbl); smc_mc_reg_tbl_emergency_init(ctx, smc_mc_reg_tbl);
187 smc_mc_reg_tbl_ulv_init(ctx, smc_mc_reg_tbl);
186 188 return 0; return 0;
187 189 } }
188 190
File drivers/gpu/alga/amd/si/dyn_pm/ulv.c changed (mode: 100644) (index f78a2e4..a444fe2)
36 36 #include "private.h" #include "private.h"
37 37 #include "smc.h" #include "smc.h"
38 38 #include "smc_lvl.h" #include "smc_lvl.h"
39 #include "smc_mc_reg_tbl.h"
39 40
40 41 long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl) long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl)
41 42 { {
 
... ... void smc_sw_regs_ulv_init(struct ctx *ctx)
84 85 smc_sw_wr32(ctx->dev, ctx->pcie_lanes_n, smc_sw_wr32(ctx->dev, ctx->pcie_lanes_n,
85 86 SMC_SW_NON_ULV_PCIE_LINK_WIDTH); SMC_SW_NON_ULV_PCIE_LINK_WIDTH);
86 87 } }
88
89 static u8 mc_reg_set_find(struct ctx *ctx, u32 mem_clk)
90 {
91 u8 mc_reg_set_idx;
92
93 /* select a set of mc regs which can support the pwr lvl mem clk */
94 for (mc_reg_set_idx = 0; mc_reg_set_idx < ctx->atb_mc_reg_tbl.sets_n;
95 ++mc_reg_set_idx) {
96 struct atb_mc_reg_set *mc_reg_set;
97
98 mc_reg_set = &ctx->atb_mc_reg_tbl.sets[mc_reg_set_idx];
99
100 if (mem_clk <= mc_reg_set->mem_clk_max)
101 break;
102 }
103
104 /*
105 * Not found, then try the last one as a work around which should
106 * accomodate the highest mem clk. The tbl seems to be sorted
107 * from lowest mem clk to highest mem clk.
108 */
109 if (mc_reg_set_idx == ctx->atb_mc_reg_tbl.sets_n)
110 --mc_reg_set_idx; /* we presume we have at least one set */
111 return mc_reg_set_idx;
112 }
113
114 void smc_mc_reg_tbl_ulv_init(struct ctx *ctx,
115 struct smc_mc_reg_tbl *smc_mc_reg_tbl)
116 {
117 u8 mc_reg_set_idx;
118
119 /*
120 * for the ulv state, if the atombios define an ulv pwr lvl, do
121 * use the mem clk from here, if not, use the firt set of mc reg, which
122 * should be targetted for the lowest mem clk since sets are sorted
123 * from lowest mem clk to highest mem clk
124 */
125 if (ctx->atb_ulv.lvls_n) {
126 u32 mem_clk;
127
128 mem_clk = ctx->atb_ulv.lvls[0].mem_clk;
129
130 mc_reg_set_idx = mc_reg_set_find(ctx, mem_clk);
131 } else
132 mc_reg_set_idx = 0;
133
134 smc_mc_reg_set_load(ctx, mc_reg_set_idx,
135 &smc_mc_reg_tbl->sets[SMC_MC_REG_TBL_ULV_SLOT]);
136 }
137
File drivers/gpu/alga/amd/si/dyn_pm/ulv.h changed (mode: 100644) (index 74a1cc1..8c8be4b)
8 8 long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl); long smc_state_tbl_ulv_init(struct ctx *ctx, struct smc_state_tbl *tbl);
9 9 void ulv_program(struct pci_dev *dev); void ulv_program(struct pci_dev *dev);
10 10 void smc_sw_regs_ulv_init(struct ctx *ctx); void smc_sw_regs_ulv_init(struct ctx *ctx);
11 void smc_mc_reg_tbl_ulv_init(struct ctx *ctx,
12 struct smc_mc_reg_tbl *smc_mc_reg_tbl);
11 13 #endif #endif
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