sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
alga cosmetics a8b013ce129bb7218fbf5a331f09828322219ac6 Sylvain BERTRAND 2013-03-22 01:21:27
massive comestics f0ff31f57512bd63b707a34d8f6252091facb632 Sylvain BERTRAND 2013-03-22 01:02:42
sysfs discret_vram property cf1c115de509b4449d7e1af1e21bf26010904c46 Sylvain BERTRAND 2013-03-19 00:56:39
dce6 crtc attribute 8f7a977603c22668c56d36c59868b74426fcf371 Sylvain BERTRAND 2013-03-12 17:02:51
ioctl edid not big enough fa9570a5821514fdb281d81ce801c2c86592dc69 Sylvain BERTRAND 2013-03-11 22:14:17
edid override has ioctl d0e628fe0d9e43cdebb3ce32cf04e53f4e36239e Sylvain BERTRAND 2013-03-11 20:48:26
forgot to remove the edid binary attribute fe3bf78e0ef1919315c1ba4da75dd3a320140061 Sylvain BERTRAND 2013-03-07 16:48:36
finally switch to binary attr for edid 739827ff0f69bacbda2bc18c19ab3cf9a7b96a5b Sylvain BERTRAND 2013-03-07 16:30:46
display properties with edid patching e43106768022d2d37e2120f4748e1bbe294f2fb9 Sylvain BERTRAND 2013-03-07 03:33:05
first shot at sysfs for display hotplug 411ae25ba5390aa8cb43d104fc7942781c036758 Sylvain BERTRAND 2013-03-06 02:10:12
new tahiti pci id 6e6296898ab0e460aba5a5c16e28a50927f073f9 Sylvain BERTRAND 2013-03-04 22:39:41
atombios init, reset, oland 8b75a3e3dd4af96d09c4fdab8787e72b0046f59e Sylvain BERTRAND 2013-03-04 21:50:55
oland 0f5b78a2b2b542c564d778cc875c09b28a63567b Sylvain BERTRAND 2013-03-04 20:49:40
minor management c9d861c8bed7eb9e350245a3114ef6dd3cc37004 Sylvain BERTRAND 2013-03-04 17:27:04
linux 3.8.0 df5ce6b90332feec174c48c3947a3d635fb3cfdd Sylvain BERTRAND 2013-02-28 22:48:17
upstream: new pci ids 79cd8f97c27c895a4187b36f94fa1b432653555c Sylvain BERTRAND 2012-10-17 11:40:08
triangle basic pattern working 97faa34485d6d8b7b19dd54740d5f71fdae7691f Sylvain BERTRAND 2012-10-09 00:55:39
more regs b04101d3e2fcc6d5bac47c3b7999a63b8e70ec86 Sylvain BERTRAND 2012-10-06 13:49:36
add CPs interrupts 35f9940a0ac89e875d852b8ca32009954d92faa5 Sylvain BERTRAND 2012-10-06 13:23:06
tiling, hdp fixes aacf6796f68771f4f6b680844ae495147849ec64 Sylvain BERTRAND 2012-10-06 02:51:51
Commit a8b013ce129bb7218fbf5a331f09828322219ac6 - alga cosmetics
Author: Sylvain BERTRAND
Author date (UTC): 2013-03-22 01:21
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-03-22 01:21
Parent(s): f0ff31f57512bd63b707a34d8f6252091facb632
Signer:
Signing key:
Signing status: N
Tree: b7e9bb60678bcfe5f3dfdc55d4a9b843161e8e1b
File Lines added Lines deleted
drivers/gpu/alga/helpers/edid.c 15 15
drivers/gpu/alga/helpers/mod.c 2 2
drivers/gpu/alga/helpers/rng_mng.c 5 5
drivers/gpu/alga/helpers/vesa_dmts.h 178 178
include/alga/edid.h 4 3
File drivers/gpu/alga/helpers/edid.c changed (mode: 100644) (index 70e52c1..f5c3a7a)
21 21
22 22 #define I2C_FETCH_RETRIES 4 #define I2C_FETCH_RETRIES 4
23 23
24 static bool has_valid_hdr(void *edid)
24 static u8 has_valid_hdr(void *edid)
25 25 { {
26 26 static u8 valid_hdr[8] = { static u8 valid_hdr[8] = {
27 27 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
28 28 if (memcmp(edid, valid_hdr, sizeof(valid_hdr)) != 0) if (memcmp(edid, valid_hdr, sizeof(valid_hdr)) != 0)
29 return false;
30 return true;
29 return 0;
30 return 1;
31 31 } }
32 32
33 static bool is_v1_4(void *edid)
33 static u8 is_v1_4(void *edid)
34 34 { {
35 35 u8 version; u8 version;
36 36 u8 revision; u8 revision;
37 37
38 38 version = *(u8*)(edid + 0x12); version = *(u8*)(edid + 0x12);
39 39 if (version != 1) if (version != 1)
40 return false;
40 return 0;
41 41
42 42 revision = *(u8*)(edid + 0x13); revision = *(u8*)(edid + 0x13);
43 43 if (revision != 4) if (revision != 4)
44 return false;
45 return true;
44 return 0;
45 return 1;
46 46 } }
47 47
48 48 static void dtd_collect(void *dtd, struct alga_timing (*ts)[ALGA_TIMINGS_MAX]) static void dtd_collect(void *dtd, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
49 49 { {
50 50 struct alga_timing *t; struct alga_timing *t;
51 51 u8 *p; u8 *p;
52 unsigned tmp;
53 unsigned i;
52 u32 tmp;
53 u8 i;
54 54
55 55 /* get to the first available slot of timings */ /* get to the first available slot of timings */
56 56 for (i = 0; i < ALGA_TIMINGS_MAX; ++i) for (i = 0; i < ALGA_TIMINGS_MAX; ++i)
 
... ... static void dtd_collect(void *dtd, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
114 114
115 115 static void dtds_collect(void *edid, struct alga_timing (*ts)[ALGA_TIMINGS_MAX]) static void dtds_collect(void *edid, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
116 116 { {
117 unsigned i;
117 u8 i;
118 118 void *dtd; void *dtd;
119 119
120 120 for (i = 0, dtd = edid + 0x36; i < 4; ++i, dtd += 18) { for (i = 0, dtd = edid + 0x36; i < 4; ++i, dtd += 18) {
 
... ... static void timings(void *edid, struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
132 132 /* TODO: collect the timings defined in other ways */ /* TODO: collect the timings defined in other ways */
133 133 } }
134 134
135 int alga_edid_timings(struct device *dev, void *edid,
135 long alga_edid_timings(struct device *dev, void *edid,
136 136 struct alga_timing (*ts)[ALGA_TIMINGS_MAX]) struct alga_timing (*ts)[ALGA_TIMINGS_MAX])
137 137 { {
138 138 if (!is_v1_4(edid)) { if (!is_v1_4(edid)) {
 
... ... EXPORT_SYMBOL_GPL(alga_edid_timings);
150 150 * XXX:for now do not deal with the e-edid extension blocks * XXX:for now do not deal with the e-edid extension blocks
151 151 * must not support edid bigger than PAGE_SIZE - 1 for sysfs attribute * must not support edid bigger than PAGE_SIZE - 1 for sysfs attribute
152 152 */ */
153 int alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a, void **edid)
153 long alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a, void **edid)
154 154 { {
155 155 u8 out; u8 out;
156 int r;
157 int retry;
156 long r;
157 u8 retry;
158 158 struct i2c_msg msgs[] = { struct i2c_msg msgs[] = {
159 159 { {
160 160 .addr = 0x50, .addr = 0x50,
 
... ... err:
203 203 } }
204 204 EXPORT_SYMBOL_GPL(alga_i2c_edid_fetch); EXPORT_SYMBOL_GPL(alga_i2c_edid_fetch);
205 205
206 int alga_edid_bpc(struct device *dev, void *edid)
206 u8 alga_edid_bpc(struct device *dev, void *edid)
207 207 { {
208 208 u8 def; u8 def;
209 209
File drivers/gpu/alga/helpers/mod.c changed (mode: 100644) (index d5b9a28..d68402a)
4 4 See README at root of alga tree. See README at root of alga tree.
5 5 */ */
6 6 #include <linux/module.h> #include <linux/module.h>
7 static int __init init(void)
7 static int init(void)
8 8 { {
9 9 return 0; return 0;
10 10 } }
11 11
12 static void __exit cleanup(void)
12 static void cleanup(void)
13 13 { {
14 14 } }
15 15
File drivers/gpu/alga/helpers/rng_mng.c changed (mode: 100644) (index e83ab18..6ec004b)
12 12 #include <alga/alga.h> #include <alga/alga.h>
13 13 #include <alga/rng_mng.h> #include <alga/rng_mng.h>
14 14
15 static bool have_room_align(u64 *s_aligned, struct rng *mng, struct rng *r,
15 static u8 have_room_align(u64 *s_aligned, struct rng *mng, struct rng *r,
16 16 struct rng *next_r, u64 sz, u64 align) struct rng *next_r, u64 sz, u64 align)
17 17 { {
18 18 u64 gap_start; u64 gap_start;
 
... ... static bool have_room_align(u64 *s_aligned, struct rng *mng, struct rng *r,
28 28 *s_aligned = rng_align(gap_start, align); *s_aligned = rng_align(gap_start, align);
29 29
30 30 if ((*s_aligned + sz - 1) <= gap_end) if ((*s_aligned + sz - 1) <= gap_end)
31 return true;
32 return false;
31 return 1;
32 return 0;
33 33 } }
34 34
35 35 static bool first_range(u64 *s_aligned, struct rng *mng, u64 sz, u64 align) static bool first_range(u64 *s_aligned, struct rng *mng, u64 sz, u64 align)
 
... ... static bool first_range(u64 *s_aligned, struct rng *mng, u64 sz, u64 align)
37 37 *s_aligned = rng_align(mng->s, align); *s_aligned = rng_align(mng->s, align);
38 38
39 39 if ((*s_aligned + sz - 1) <= (mng->s + mng->sz - 1)) if ((*s_aligned + sz - 1) <= (mng->s + mng->sz - 1))
40 return true;
41 return false;
40 return 1;
41 return 0;
42 42 } }
43 43
44 44 void rng_mng_init(struct rng *mng, u64 s, u64 sz) void rng_mng_init(struct rng *mng, u64 s, u64 sz)
File drivers/gpu/alga/helpers/vesa_dmts.h changed (mode: 100644) (index 62b83b7..17b9b48)
8 8 #define VESA_DMTS_COUNT 0x51 #define VESA_DMTS_COUNT 0x51
9 9 struct dmt { struct dmt {
10 10 /* pixels */ /* pixels */
11 unsigned h;
12 unsigned h_bl;
13 unsigned h_so;
14 unsigned h_spw;
15 unsigned h_b;
16 unsigned h_sp; /* 0: high/positive, 1: low/negative */
11 uint32_t h;
12 uint32_t h_bl;
13 uint32_t h_so;
14 uint32_t h_spw;
15 uint32_t h_b;
16 uint32_t h_sp; /* 0: high/positive, 1: low/negative */
17 17
18 18 /* lines */ /* lines */
19 unsigned v;
20 unsigned v_bl;
21 unsigned v_so;
22 unsigned v_spw;
23 unsigned v_b;
24 unsigned v_sp; /* 0: high/positive, 1: low/negative */
19 uint32_t v;
20 uint32_t v_bl;
21 uint32_t v_so;
22 uint32_t v_spw;
23 uint32_t v_b;
24 uint32_t v_sp; /* 0: high/positive, 1: low/negative */
25 25
26 unsigned pixel_clk; /* kHz */
27 unsigned r; /* Hz for timing name only */
26 uint32_t pixel_clk; /* kHz */
27 uint32_t r; /* Hz for timing name only */
28 28
29 bool interlaced;
30 bool reduced_blanking;
29 uint8_t interlaced;
30 uint8_t reduced_blanking;
31 31 }; };
32 32
33 33 static struct dmt vesa_dmts[VESA_DMTS_COUNT] = { static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
46 46 .v_sp = 0, .v_sp = 0,
47 47 .pixel_clk = 0, .pixel_clk = 0,
48 48 .r = 0, .r = 0,
49 .interlaced = false,
50 .reduced_blanking = false
49 .interlaced = 0,
50 .reduced_blanking = 0
51 51 }, },
52 52 {/* DMT ID 0x01 */ {/* DMT ID 0x01 */
53 53 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
64 64 .v_sp = 1, .v_sp = 1,
65 65 .pixel_clk = 31500, .pixel_clk = 31500,
66 66 .r = 85, .r = 85,
67 .interlaced = false,
68 .reduced_blanking = false
67 .interlaced = 0,
68 .reduced_blanking = 0
69 69 }, },
70 70 {/* DMT ID 0x02 */ {/* DMT ID 0x02 */
71 71 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
82 82 .v_sp = 0, .v_sp = 0,
83 83 .pixel_clk = 31500, .pixel_clk = 31500,
84 84 .r = 85, .r = 85,
85 .interlaced = false,
86 .reduced_blanking = false
85 .interlaced = 0,
86 .reduced_blanking = 0
87 87 }, },
88 88 {/* DMT ID 0x03 */ {/* DMT ID 0x03 */
89 89 .h = 720, .h = 720,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
100 100 .v_sp = 0, .v_sp = 0,
101 101 .pixel_clk = 35500, .pixel_clk = 35500,
102 102 .r = 85, .r = 85,
103 .interlaced = false,
104 .reduced_blanking = false
103 .interlaced = 0,
104 .reduced_blanking = 0
105 105 }, },
106 106 {/* DMT ID 0x04 */ {/* DMT ID 0x04 */
107 107 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
118 118 .v_sp = 1, .v_sp = 1,
119 119 .pixel_clk = 25175, .pixel_clk = 25175,
120 120 .r = 60, .r = 60,
121 .interlaced = false,
122 .reduced_blanking = false
121 .interlaced = 0,
122 .reduced_blanking = 0
123 123 }, },
124 124 {/* DMT ID 0x05 */ {/* DMT ID 0x05 */
125 125 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
136 136 .v_sp = 1, .v_sp = 1,
137 137 .pixel_clk = 31500, .pixel_clk = 31500,
138 138 .r = 72, .r = 72,
139 .interlaced = false,
140 .reduced_blanking = false
139 .interlaced = 0,
140 .reduced_blanking = 0
141 141 }, },
142 142 {/* DMT ID 0x06 */ {/* DMT ID 0x06 */
143 143 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
154 154 .v_sp = 1, .v_sp = 1,
155 155 .pixel_clk = 31500, .pixel_clk = 31500,
156 156 .r = 75, .r = 75,
157 .interlaced = false,
158 .reduced_blanking = false
157 .interlaced = 0,
158 .reduced_blanking = 0
159 159 }, },
160 160 {/* DMT ID 0x07 */ {/* DMT ID 0x07 */
161 161 .h = 640, .h = 640,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
172 172 .v_sp = 1, .v_sp = 1,
173 173 .pixel_clk = 36000, .pixel_clk = 36000,
174 174 .r = 85, .r = 85,
175 .interlaced = false,
176 .reduced_blanking = false
175 .interlaced = 0,
176 .reduced_blanking = 0
177 177 }, },
178 178 {/* DMT ID 0x08 */ {/* DMT ID 0x08 */
179 179 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
190 190 .v_sp = 0, .v_sp = 0,
191 191 .pixel_clk = 36000, .pixel_clk = 36000,
192 192 .r = 56, .r = 56,
193 .interlaced = false,
194 .reduced_blanking = false
193 .interlaced = 0,
194 .reduced_blanking = 0
195 195 }, },
196 196 {/* DMT ID 0x09 */ {/* DMT ID 0x09 */
197 197 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
208 208 .v_sp = 0, .v_sp = 0,
209 209 .pixel_clk = 40000, .pixel_clk = 40000,
210 210 .r = 60, .r = 60,
211 .interlaced = false,
212 .reduced_blanking = false
211 .interlaced = 0,
212 .reduced_blanking = 0
213 213 }, },
214 214 {/* DMT ID 0x0a */ {/* DMT ID 0x0a */
215 215 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
226 226 .v_sp = 0, .v_sp = 0,
227 227 .pixel_clk = 50000, .pixel_clk = 50000,
228 228 .r = 72, .r = 72,
229 .interlaced = false,
230 .reduced_blanking = false
229 .interlaced = 0,
230 .reduced_blanking = 0
231 231 }, },
232 232 {/* DMT ID 0x0b */ {/* DMT ID 0x0b */
233 233 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
244 244 .v_sp = 0, .v_sp = 0,
245 245 .pixel_clk = 49500, .pixel_clk = 49500,
246 246 .r = 75, .r = 75,
247 .interlaced = false,
248 .reduced_blanking = false
247 .interlaced = 0,
248 .reduced_blanking = 0
249 249 }, },
250 250 {/* DMT ID 0x0c */ {/* DMT ID 0x0c */
251 251 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
262 262 .v_sp = 0, .v_sp = 0,
263 263 .pixel_clk = 56250, .pixel_clk = 56250,
264 264 .r = 85, .r = 85,
265 .interlaced = false,
266 .reduced_blanking = false
265 .interlaced = 0,
266 .reduced_blanking = 0
267 267 }, },
268 268 {/* DMT ID 0x0d */ {/* DMT ID 0x0d */
269 269 .h = 800, .h = 800,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
280 280 .v_sp = 1, .v_sp = 1,
281 281 .pixel_clk = 73250, .pixel_clk = 73250,
282 282 .r = 120, .r = 120,
283 .interlaced = false,
284 .reduced_blanking = true
283 .interlaced = 0,
284 .reduced_blanking = 1
285 285 }, },
286 286 {/* DMT ID 0x0e */ {/* DMT ID 0x0e */
287 287 .h = 848, .h = 848,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
298 298 .v_sp = 0, .v_sp = 0,
299 299 .pixel_clk = 33750, .pixel_clk = 33750,
300 300 .r = 60, .r = 60,
301 .interlaced = false,
302 .reduced_blanking = false
301 .interlaced = 0,
302 .reduced_blanking = 0
303 303 }, },
304 304 {/* DMT ID 0x0f */ {/* DMT ID 0x0f */
305 305 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
316 316 .v_sp = 0, .v_sp = 0,
317 317 .pixel_clk = 44900, .pixel_clk = 44900,
318 318 .r = 43, .r = 43,
319 .interlaced = true,
320 .reduced_blanking = false
319 .interlaced = 1,
320 .reduced_blanking = 0
321 321 }, },
322 322 {/* DMT ID 0x10 */ {/* DMT ID 0x10 */
323 323 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
334 334 .v_sp = 1, .v_sp = 1,
335 335 .pixel_clk = 65000, .pixel_clk = 65000,
336 336 .r = 60, .r = 60,
337 .interlaced = false,
338 .reduced_blanking = false
337 .interlaced = 0,
338 .reduced_blanking = 0
339 339 }, },
340 340 {/* DMT ID 0x11 */ {/* DMT ID 0x11 */
341 341 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
352 352 .v_sp = 1, .v_sp = 1,
353 353 .pixel_clk = 75000, .pixel_clk = 75000,
354 354 .r = 70, .r = 70,
355 .interlaced = false,
356 .reduced_blanking = false
355 .interlaced = 0,
356 .reduced_blanking = 0
357 357 }, },
358 358 {/* DMT ID 0x12 */ {/* DMT ID 0x12 */
359 359 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
370 370 .v_sp = 0, .v_sp = 0,
371 371 .pixel_clk = 78750, .pixel_clk = 78750,
372 372 .r = 75, .r = 75,
373 .interlaced = false,
374 .reduced_blanking = false
373 .interlaced = 0,
374 .reduced_blanking = 0
375 375 }, },
376 376 {/* DMT ID 0x13 */ {/* DMT ID 0x13 */
377 377 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
388 388 .v_sp = 0, .v_sp = 0,
389 389 .pixel_clk = 94500, .pixel_clk = 94500,
390 390 .r = 85, .r = 85,
391 .interlaced = false,
392 .reduced_blanking = false
391 .interlaced = 0,
392 .reduced_blanking = 0
393 393 }, },
394 394 {/* DMT ID 0x14 */ {/* DMT ID 0x14 */
395 395 .h = 1024, .h = 1024,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
406 406 .v_sp = 1, .v_sp = 1,
407 407 .pixel_clk = 115500, .pixel_clk = 115500,
408 408 .r = 120, .r = 120,
409 .interlaced = false,
410 .reduced_blanking = true
409 .interlaced = 0,
410 .reduced_blanking = 1
411 411 }, },
412 412 {/* DMT ID 0x15 */ {/* DMT ID 0x15 */
413 413 .h = 1152, .h = 1152,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
424 424 .v_sp = 0, .v_sp = 0,
425 425 .pixel_clk = 108000, .pixel_clk = 108000,
426 426 .r = 75, .r = 75,
427 .interlaced = false,
428 .reduced_blanking = false
427 .interlaced = 0,
428 .reduced_blanking = 0
429 429 }, },
430 430 {/* DMT ID 0x16 */ {/* DMT ID 0x16 */
431 431 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
442 442 .v_sp = 1, .v_sp = 1,
443 443 .pixel_clk = 68250, .pixel_clk = 68250,
444 444 .r = 60, .r = 60,
445 .interlaced = false,
446 .reduced_blanking = true
445 .interlaced = 0,
446 .reduced_blanking = 1
447 447 }, },
448 448 {/* DMT ID 0x17 */ {/* DMT ID 0x17 */
449 449 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
460 460 .v_sp = 0, .v_sp = 0,
461 461 .pixel_clk = 79500, .pixel_clk = 79500,
462 462 .r = 60, .r = 60,
463 .interlaced = false,
464 .reduced_blanking = true
463 .interlaced = 0,
464 .reduced_blanking = 1
465 465 }, },
466 466 {/* DMT ID 0x18 */ {/* DMT ID 0x18 */
467 467 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
478 478 .v_sp = 0, .v_sp = 0,
479 479 .pixel_clk = 102250, .pixel_clk = 102250,
480 480 .r = 75, .r = 75,
481 .interlaced = false,
482 .reduced_blanking = false
481 .interlaced = 0,
482 .reduced_blanking = 0
483 483 }, },
484 484 {/* DMT ID 0x19 */ {/* DMT ID 0x19 */
485 485 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
496 496 .v_sp = 0, .v_sp = 0,
497 497 .pixel_clk = 117500, .pixel_clk = 117500,
498 498 .r = 85, .r = 85,
499 .interlaced = false,
500 .reduced_blanking = false
499 .interlaced = 0,
500 .reduced_blanking = 0
501 501 }, },
502 502 {/* DMT ID 0x1a */ {/* DMT ID 0x1a */
503 503 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
514 514 .v_sp = 1, .v_sp = 1,
515 515 .pixel_clk = 140250, .pixel_clk = 140250,
516 516 .r = 120, .r = 120,
517 .interlaced = false,
518 .reduced_blanking = true
517 .interlaced = 0,
518 .reduced_blanking = 1
519 519 }, },
520 520 {/* DMT ID 0x1b */ {/* DMT ID 0x1b */
521 521 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
532 532 .v_sp = 1, .v_sp = 1,
533 533 .pixel_clk = 71000, .pixel_clk = 71000,
534 534 .r = 60, .r = 60,
535 .interlaced = false,
536 .reduced_blanking = true
535 .interlaced = 0,
536 .reduced_blanking = 1
537 537 }, },
538 538 {/* DMT ID 0x1c */ {/* DMT ID 0x1c */
539 539 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
550 550 .v_sp = 0, .v_sp = 0,
551 551 .pixel_clk = 83500, .pixel_clk = 83500,
552 552 .r = 60, .r = 60,
553 .interlaced = false,
554 .reduced_blanking = false
553 .interlaced = 0,
554 .reduced_blanking = 0
555 555 }, },
556 556 {/* DMT ID 0x1d */ {/* DMT ID 0x1d */
557 557 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
568 568 .v_sp = 0, .v_sp = 0,
569 569 .pixel_clk = 106500, .pixel_clk = 106500,
570 570 .r = 75, .r = 75,
571 .interlaced = false,
572 .reduced_blanking = false
571 .interlaced = 0,
572 .reduced_blanking = 0
573 573 }, },
574 574 {/* DMT ID 0x1e */ {/* DMT ID 0x1e */
575 575 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
586 586 .v_sp = 0, .v_sp = 0,
587 587 .pixel_clk = 122500, .pixel_clk = 122500,
588 588 .r = 85, .r = 85,
589 .interlaced = false,
590 .reduced_blanking = false
589 .interlaced = 0,
590 .reduced_blanking = 0
591 591 }, },
592 592 {/* DMT ID 0x1f */ {/* DMT ID 0x1f */
593 593 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
604 604 .v_sp = 1, .v_sp = 1,
605 605 .pixel_clk = 146250, .pixel_clk = 146250,
606 606 .r = 120, .r = 120,
607 .interlaced = false,
608 .reduced_blanking = true
607 .interlaced = 0,
608 .reduced_blanking = 1
609 609 }, },
610 610 {/* DMT ID 0x20 */ {/* DMT ID 0x20 */
611 611 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
622 622 .v_sp = 0, .v_sp = 0,
623 623 .pixel_clk = 108000, .pixel_clk = 108000,
624 624 .r = 60, .r = 60,
625 .interlaced = false,
626 .reduced_blanking = false
625 .interlaced = 0,
626 .reduced_blanking = 0
627 627 }, },
628 628 {/* DMT ID 0x21 */ {/* DMT ID 0x21 */
629 629 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
640 640 .v_sp = 0, .v_sp = 0,
641 641 .pixel_clk = 148500, .pixel_clk = 148500,
642 642 .r = 85, .r = 85,
643 .interlaced = false,
644 .reduced_blanking = false
643 .interlaced = 0,
644 .reduced_blanking = 0
645 645 }, },
646 646 {/* DMT ID 0x22 */ {/* DMT ID 0x22 */
647 647 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
658 658 .v_sp = 1, .v_sp = 1,
659 659 .pixel_clk = 175500, .pixel_clk = 175500,
660 660 .r = 120, .r = 120,
661 .interlaced = false,
662 .reduced_blanking = true
661 .interlaced = 0,
662 .reduced_blanking = 1
663 663 }, },
664 664 {/* DMT ID 0x23 */ {/* DMT ID 0x23 */
665 665 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
676 676 .v_sp = 0, .v_sp = 0,
677 677 .pixel_clk = 108000, .pixel_clk = 108000,
678 678 .r = 60, .r = 60,
679 .interlaced = false,
680 .reduced_blanking = false
679 .interlaced = 0,
680 .reduced_blanking = 0
681 681 }, },
682 682 {/* DMT ID 0x24 */ {/* DMT ID 0x24 */
683 683 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
694 694 .v_sp = 0, .v_sp = 0,
695 695 .pixel_clk = 135000, .pixel_clk = 135000,
696 696 .r = 75, .r = 75,
697 .interlaced = false,
698 .reduced_blanking = false
697 .interlaced = 0,
698 .reduced_blanking = 0
699 699 }, },
700 700 {/* DMT ID 0x25 */ {/* DMT ID 0x25 */
701 701 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
712 712 .v_sp = 0, .v_sp = 0,
713 713 .pixel_clk = 157500, .pixel_clk = 157500,
714 714 .r = 85, .r = 85,
715 .interlaced = false,
716 .reduced_blanking = false
715 .interlaced = 0,
716 .reduced_blanking = 0
717 717 }, },
718 718 {/* DMT ID 0x26 */ {/* DMT ID 0x26 */
719 719 .h = 1280, .h = 1280,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
730 730 .v_sp = 1, .v_sp = 1,
731 731 .pixel_clk = 187250, .pixel_clk = 187250,
732 732 .r = 120, .r = 120,
733 .interlaced = false,
734 .reduced_blanking = true
733 .interlaced = 0,
734 .reduced_blanking = 1
735 735 }, },
736 736 {/* DMT ID 0x27 */ {/* DMT ID 0x27 */
737 737 .h = 1360, .h = 1360,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
748 748 .v_sp = 0, .v_sp = 0,
749 749 .pixel_clk = 85500, .pixel_clk = 85500,
750 750 .r = 60, .r = 60,
751 .interlaced = false,
752 .reduced_blanking = false
751 .interlaced = 0,
752 .reduced_blanking = 0
753 753 }, },
754 754 {/* DMT ID 0x28 */ {/* DMT ID 0x28 */
755 755 .h = 1360, .h = 1360,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
766 766 .v_sp = 1, .v_sp = 1,
767 767 .pixel_clk = 148250, .pixel_clk = 148250,
768 768 .r = 120, .r = 120,
769 .interlaced = false,
770 .reduced_blanking = true
769 .interlaced = 0,
770 .reduced_blanking = 1
771 771 }, },
772 772 {/* DMT ID 0x29 */ {/* DMT ID 0x29 */
773 773 .h = 1400, .h = 1400,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
784 784 .v_sp = 1, .v_sp = 1,
785 785 .pixel_clk = 101000, .pixel_clk = 101000,
786 786 .r = 60, .r = 60,
787 .interlaced = false,
788 .reduced_blanking = true
787 .interlaced = 0,
788 .reduced_blanking = 1
789 789 }, },
790 790 {/* DMT ID 0x2a */ {/* DMT ID 0x2a */
791 791 .h = 1400, .h = 1400,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
802 802 .v_sp = 0, .v_sp = 0,
803 803 .pixel_clk = 121750, .pixel_clk = 121750,
804 804 .r = 60, .r = 60,
805 .interlaced = false,
806 .reduced_blanking = false
805 .interlaced = 0,
806 .reduced_blanking = 0
807 807 }, },
808 808 {/* DMT ID 0x2b */ {/* DMT ID 0x2b */
809 809 .h = 1400, .h = 1400,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
820 820 .v_sp = 0, .v_sp = 0,
821 821 .pixel_clk = 156000, .pixel_clk = 156000,
822 822 .r = 75, .r = 75,
823 .interlaced = false,
824 .reduced_blanking = false
823 .interlaced = 0,
824 .reduced_blanking = 0
825 825 }, },
826 826 {/* DMT ID 0x2c */ {/* DMT ID 0x2c */
827 827 .h = 1400, .h = 1400,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
838 838 .v_sp = 0, .v_sp = 0,
839 839 .pixel_clk = 179500, .pixel_clk = 179500,
840 840 .r = 85, .r = 85,
841 .interlaced = false,
842 .reduced_blanking = false
841 .interlaced = 0,
842 .reduced_blanking = 0
843 843 }, },
844 844 {/* DMT ID 0x2d */ {/* DMT ID 0x2d */
845 845 .h = 1400, .h = 1400,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
856 856 .v_sp = 1, .v_sp = 1,
857 857 .pixel_clk = 208000, .pixel_clk = 208000,
858 858 .r = 120, .r = 120,
859 .interlaced = false,
860 .reduced_blanking = true
859 .interlaced = 0,
860 .reduced_blanking = 1
861 861 }, },
862 862 {/* DMT ID 0x2e */ {/* DMT ID 0x2e */
863 863 .h = 1440, .h = 1440,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
874 874 .v_sp = 1, .v_sp = 1,
875 875 .pixel_clk = 88750, .pixel_clk = 88750,
876 876 .r = 60, .r = 60,
877 .interlaced = false,
878 .reduced_blanking = true
877 .interlaced = 0,
878 .reduced_blanking = 1
879 879 }, },
880 880 {/* DMT ID 0x2f */ {/* DMT ID 0x2f */
881 881 .h = 1440, .h = 1440,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
892 892 .v_sp = 0, .v_sp = 0,
893 893 .pixel_clk = 106500, .pixel_clk = 106500,
894 894 .r = 60, .r = 60,
895 .interlaced = false,
896 .reduced_blanking = false
895 .interlaced = 0,
896 .reduced_blanking = 0
897 897 }, },
898 898 {/* DMT ID 0x30 */ {/* DMT ID 0x30 */
899 899 .h = 1440, .h = 1440,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
910 910 .v_sp = 0, .v_sp = 0,
911 911 .pixel_clk = 136750, .pixel_clk = 136750,
912 912 .r = 75, .r = 75,
913 .interlaced = false,
914 .reduced_blanking = false
913 .interlaced = 0,
914 .reduced_blanking = 0
915 915 }, },
916 916 {/* DMT ID 0x31 */ {/* DMT ID 0x31 */
917 917 .h = 1440, .h = 1440,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
928 928 .v_sp = 0, .v_sp = 0,
929 929 .pixel_clk = 157000, .pixel_clk = 157000,
930 930 .r = 85, .r = 85,
931 .interlaced = false,
932 .reduced_blanking = false
931 .interlaced = 0,
932 .reduced_blanking = 0
933 933 }, },
934 934 {/* DMT ID 0x32 */ {/* DMT ID 0x32 */
935 935 .h = 1440, .h = 1440,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
946 946 .v_sp = 1, .v_sp = 1,
947 947 .pixel_clk = 182750, .pixel_clk = 182750,
948 948 .r = 120, .r = 120,
949 .interlaced = false,
950 .reduced_blanking = true
949 .interlaced = 0,
950 .reduced_blanking = 1
951 951 }, },
952 952 {/* DMT ID 0x33 */ {/* DMT ID 0x33 */
953 953 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
964 964 .v_sp = 0, .v_sp = 0,
965 965 .pixel_clk = 162000, .pixel_clk = 162000,
966 966 .r = 60, .r = 60,
967 .interlaced = false,
968 .reduced_blanking = false
967 .interlaced = 0,
968 .reduced_blanking = 0
969 969 }, },
970 970 {/* DMT ID 0x34 */ {/* DMT ID 0x34 */
971 971 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
982 982 .v_sp = 0, .v_sp = 0,
983 983 .pixel_clk = 175500, .pixel_clk = 175500,
984 984 .r = 65, .r = 65,
985 .interlaced = false,
986 .reduced_blanking = false
985 .interlaced = 0,
986 .reduced_blanking = 0
987 987 }, },
988 988 {/* DMT ID 0x35 */ {/* DMT ID 0x35 */
989 989 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1000 1000 .v_sp = 0, .v_sp = 0,
1001 1001 .pixel_clk = 189000, .pixel_clk = 189000,
1002 1002 .r = 70, .r = 70,
1003 .interlaced = false,
1004 .reduced_blanking = false
1003 .interlaced = 0,
1004 .reduced_blanking = 0
1005 1005 }, },
1006 1006 {/* DMT ID 0x36 */ {/* DMT ID 0x36 */
1007 1007 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1018 1018 .v_sp = 0, .v_sp = 0,
1019 1019 .pixel_clk = 202500, .pixel_clk = 202500,
1020 1020 .r = 75, .r = 75,
1021 .interlaced = false,
1022 .reduced_blanking = false
1021 .interlaced = 0,
1022 .reduced_blanking = 0
1023 1023 }, },
1024 1024 {/* DMT ID 0x37 */ {/* DMT ID 0x37 */
1025 1025 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1036 1036 .v_sp = 0, .v_sp = 0,
1037 1037 .pixel_clk = 229500, .pixel_clk = 229500,
1038 1038 .r = 85, .r = 85,
1039 .interlaced = false,
1040 .reduced_blanking = false
1039 .interlaced = 0,
1040 .reduced_blanking = 0
1041 1041 }, },
1042 1042 {/* DMT ID 0x38 */ {/* DMT ID 0x38 */
1043 1043 .h = 1600, .h = 1600,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1054 1054 .v_sp = 1, .v_sp = 1,
1055 1055 .pixel_clk = 268250, .pixel_clk = 268250,
1056 1056 .r = 120, .r = 120,
1057 .interlaced = false,
1058 .reduced_blanking = true
1057 .interlaced = 0,
1058 .reduced_blanking = 1
1059 1059 }, },
1060 1060 {/* DMT ID 0x39 */ {/* DMT ID 0x39 */
1061 1061 .h = 1680, .h = 1680,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1072 1072 .v_sp = 1, .v_sp = 1,
1073 1073 .pixel_clk = 119000, .pixel_clk = 119000,
1074 1074 .r = 120, .r = 120,
1075 .interlaced = false,
1076 .reduced_blanking = true
1075 .interlaced = 0,
1076 .reduced_blanking = 1
1077 1077 }, },
1078 1078 {/* DMT ID 0x3a */ {/* DMT ID 0x3a */
1079 1079 .h = 1680, .h = 1680,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1090 1090 .v_sp = 0, .v_sp = 0,
1091 1091 .pixel_clk = 146250, .pixel_clk = 146250,
1092 1092 .r = 60, .r = 60,
1093 .interlaced = false,
1094 .reduced_blanking = false
1093 .interlaced = 0,
1094 .reduced_blanking = 0
1095 1095 }, },
1096 1096 {/* DMT ID 0x3b */ {/* DMT ID 0x3b */
1097 1097 .h = 1680, .h = 1680,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1108 1108 .v_sp = 0, .v_sp = 0,
1109 1109 .pixel_clk = 187000, .pixel_clk = 187000,
1110 1110 .r = 75, .r = 75,
1111 .interlaced = false,
1112 .reduced_blanking = false
1111 .interlaced = 0,
1112 .reduced_blanking = 0
1113 1113 }, },
1114 1114 {/* DMT ID 0x3c */ {/* DMT ID 0x3c */
1115 1115 .h = 1680, .h = 1680,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1126 1126 .v_sp = 0, .v_sp = 0,
1127 1127 .pixel_clk = 214750, .pixel_clk = 214750,
1128 1128 .r = 85, .r = 85,
1129 .interlaced = false,
1130 .reduced_blanking = false
1129 .interlaced = 0,
1130 .reduced_blanking = 0
1131 1131 }, },
1132 1132 {/* DMT ID 0x3d */ {/* DMT ID 0x3d */
1133 1133 .h = 1680, .h = 1680,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1144 1144 .v_sp = 1, .v_sp = 1,
1145 1145 .pixel_clk = 245500, .pixel_clk = 245500,
1146 1146 .r = 120, .r = 120,
1147 .interlaced = false,
1148 .reduced_blanking = true
1147 .interlaced = 0,
1148 .reduced_blanking = 1
1149 1149 }, },
1150 1150 {/* DMT ID 0x3e */ {/* DMT ID 0x3e */
1151 1151 .h = 1792, .h = 1792,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1162 1162 .v_sp = 0, .v_sp = 0,
1163 1163 .pixel_clk = 204750, .pixel_clk = 204750,
1164 1164 .r = 60, .r = 60,
1165 .interlaced = false,
1166 .reduced_blanking = false
1165 .interlaced = 0,
1166 .reduced_blanking = 0
1167 1167 }, },
1168 1168 {/* DMT ID 0x3f */ {/* DMT ID 0x3f */
1169 1169 .h = 1792, .h = 1792,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1180 1180 .v_sp = 0, .v_sp = 0,
1181 1181 .pixel_clk = 261000, .pixel_clk = 261000,
1182 1182 .r = 75, .r = 75,
1183 .interlaced = false,
1184 .reduced_blanking = false
1183 .interlaced = 0,
1184 .reduced_blanking = 0
1185 1185 }, },
1186 1186 {/* DMT ID 0x40 */ {/* DMT ID 0x40 */
1187 1187 .h = 1792, .h = 1792,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1198 1198 .v_sp = 1, .v_sp = 1,
1199 1199 .pixel_clk = 333250, .pixel_clk = 333250,
1200 1200 .r = 120, .r = 120,
1201 .interlaced = false,
1202 .reduced_blanking = true
1201 .interlaced = 0,
1202 .reduced_blanking = 1
1203 1203 }, },
1204 1204 {/* DMT ID 0x41 */ {/* DMT ID 0x41 */
1205 1205 .h = 1856, .h = 1856,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1216 1216 .v_sp = 0, .v_sp = 0,
1217 1217 .pixel_clk = 218250, .pixel_clk = 218250,
1218 1218 .r = 60, .r = 60,
1219 .interlaced = false,
1220 .reduced_blanking = false
1219 .interlaced = 0,
1220 .reduced_blanking = 0
1221 1221 }, },
1222 1222 {/* DMT ID 0x42 */ {/* DMT ID 0x42 */
1223 1223 .h = 1856, .h = 1856,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1234 1234 .v_sp = 0, .v_sp = 0,
1235 1235 .pixel_clk = 288000, .pixel_clk = 288000,
1236 1236 .r = 75, .r = 75,
1237 .interlaced = false,
1238 .reduced_blanking = false
1237 .interlaced = 0,
1238 .reduced_blanking = 0
1239 1239 }, },
1240 1240 {/* DMT ID 0x43 */ {/* DMT ID 0x43 */
1241 1241 .h = 1856, .h = 1856,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1252 1252 .v_sp = 1, .v_sp = 1,
1253 1253 .pixel_clk = 356500, .pixel_clk = 356500,
1254 1254 .r = 120, .r = 120,
1255 .interlaced = false,
1256 .reduced_blanking = true
1255 .interlaced = 0,
1256 .reduced_blanking = 1
1257 1257 }, },
1258 1258 {/* DMT ID 0x44 */ {/* DMT ID 0x44 */
1259 1259 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1270 1270 .v_sp = 1, .v_sp = 1,
1271 1271 .pixel_clk = 154000, .pixel_clk = 154000,
1272 1272 .r = 60, .r = 60,
1273 .interlaced = false,
1274 .reduced_blanking = true
1273 .interlaced = 0,
1274 .reduced_blanking = 1
1275 1275 }, },
1276 1276 {/* DMT ID 0x45 */ {/* DMT ID 0x45 */
1277 1277 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1288 1288 .v_sp = 0, .v_sp = 0,
1289 1289 .pixel_clk = 193250, .pixel_clk = 193250,
1290 1290 .r = 60, .r = 60,
1291 .interlaced = false,
1292 .reduced_blanking = false
1291 .interlaced = 0,
1292 .reduced_blanking = 0
1293 1293 }, },
1294 1294 {/* DMT ID 0x46 */ {/* DMT ID 0x46 */
1295 1295 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1306 1306 .v_sp = 0, .v_sp = 0,
1307 1307 .pixel_clk = 245250, .pixel_clk = 245250,
1308 1308 .r = 75, .r = 75,
1309 .interlaced = false,
1310 .reduced_blanking = false
1309 .interlaced = 0,
1310 .reduced_blanking = 0
1311 1311 }, },
1312 1312 {/* DMT ID 0x47 */ {/* DMT ID 0x47 */
1313 1313 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1324 1324 .v_sp = 0, .v_sp = 0,
1325 1325 .pixel_clk = 281250, .pixel_clk = 281250,
1326 1326 .r = 85, .r = 85,
1327 .interlaced = false,
1328 .reduced_blanking = false
1327 .interlaced = 0,
1328 .reduced_blanking = 0
1329 1329 }, },
1330 1330 {/* DMT ID 0x48 */ {/* DMT ID 0x48 */
1331 1331 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1342 1342 .v_sp = 1, .v_sp = 1,
1343 1343 .pixel_clk = 317000, .pixel_clk = 317000,
1344 1344 .r = 120, .r = 120,
1345 .interlaced = false,
1346 .reduced_blanking = true
1345 .interlaced = 0,
1346 .reduced_blanking = 1
1347 1347 }, },
1348 1348 {/* DMT ID 0x49 */ {/* DMT ID 0x49 */
1349 1349 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1360 1360 .v_sp = 0, .v_sp = 0,
1361 1361 .pixel_clk = 234000, .pixel_clk = 234000,
1362 1362 .r = 60, .r = 60,
1363 .interlaced = false,
1364 .reduced_blanking = false
1363 .interlaced = 0,
1364 .reduced_blanking = 0
1365 1365 }, },
1366 1366 {/* DMT ID 0x4a */ {/* DMT ID 0x4a */
1367 1367 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1378 1378 .v_sp = 0, .v_sp = 0,
1379 1379 .pixel_clk = 297000, .pixel_clk = 297000,
1380 1380 .r = 75, .r = 75,
1381 .interlaced = false,
1382 .reduced_blanking = false
1381 .interlaced = 0,
1382 .reduced_blanking = 0
1383 1383 }, },
1384 1384 {/* DMT ID 0x4b */ {/* DMT ID 0x4b */
1385 1385 .h = 1920, .h = 1920,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1396 1396 .v_sp = 1, .v_sp = 1,
1397 1397 .pixel_clk = 380500, .pixel_clk = 380500,
1398 1398 .r = 120, .r = 120,
1399 .interlaced = false,
1400 .reduced_blanking = true
1399 .interlaced = 0,
1400 .reduced_blanking = 1
1401 1401 }, },
1402 1402 {/* DMT ID 0x4c */ {/* DMT ID 0x4c */
1403 1403 .h = 2560, .h = 2560,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1414 1414 .v_sp = 1, .v_sp = 1,
1415 1415 .pixel_clk = 268500, .pixel_clk = 268500,
1416 1416 .r = 120, .r = 120,
1417 .interlaced = false,
1418 .reduced_blanking = true
1417 .interlaced = 0,
1418 .reduced_blanking = 1
1419 1419 }, },
1420 1420 {/* DMT ID 0x4d */ {/* DMT ID 0x4d */
1421 1421 .h = 2560, .h = 2560,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1432 1432 .v_sp = 0, .v_sp = 0,
1433 1433 .pixel_clk = 348500, .pixel_clk = 348500,
1434 1434 .r = 120, .r = 120,
1435 .interlaced = false,
1436 .reduced_blanking = false
1435 .interlaced = 0,
1436 .reduced_blanking = 0
1437 1437 }, },
1438 1438 {/* DMT ID 0x4e */ {/* DMT ID 0x4e */
1439 1439 .h = 2560, .h = 2560,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1450 1450 .v_sp = 0, .v_sp = 0,
1451 1451 .pixel_clk = 443250, .pixel_clk = 443250,
1452 1452 .r = 75, .r = 75,
1453 .interlaced = false,
1454 .reduced_blanking = false
1453 .interlaced = 0,
1454 .reduced_blanking = 0
1455 1455 }, },
1456 1456 {/* DMT ID 0x4f */ {/* DMT ID 0x4f */
1457 1457 .h = 2560, .h = 2560,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1468 1468 .v_sp = 0, .v_sp = 0,
1469 1469 .pixel_clk = 505250, .pixel_clk = 505250,
1470 1470 .r = 85, .r = 85,
1471 .interlaced = false,
1472 .reduced_blanking = false
1471 .interlaced = 0,
1472 .reduced_blanking = 0
1473 1473 }, },
1474 1474 {/* DMT ID 0x50 */ {/* DMT ID 0x50 */
1475 1475 .h = 2560, .h = 2560,
 
... ... static struct dmt vesa_dmts[VESA_DMTS_COUNT] = {
1486 1486 .v_sp = 1, .v_sp = 1,
1487 1487 .pixel_clk = 552750, .pixel_clk = 552750,
1488 1488 .r = 120, .r = 120,
1489 .interlaced = false,
1490 .reduced_blanking = true
1489 .interlaced = 0,
1490 .reduced_blanking = 1
1491 1491 } }
1492 1492 }; };
1493 1493 #endif #endif
File include/alga/edid.h changed (mode: 100644) (index 2bae532..f6049e2)
11 11 #error "sysfs attribute on this architecture won't fit the edid block 0" #error "sysfs attribute on this architecture won't fit the edid block 0"
12 12 #endif #endif
13 13 #define EDID_DESCRIPTOR_STR_SZ_MAX (13 + 1) #define EDID_DESCRIPTOR_STR_SZ_MAX (13 + 1)
14 int alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a, void **edid);
15 int alga_edid_timings(struct device *dev, void *edid,
14 long alga_i2c_edid_fetch(struct device *dev, struct i2c_adapter *a,
15 void **edid);
16 long alga_edid_timings(struct device *dev, void *edid,
16 17 struct alga_timing (*ts)[ALGA_TIMINGS_MAX]); struct alga_timing (*ts)[ALGA_TIMINGS_MAX]);
17 int alga_edid_bpc(struct device *dev, void *edid);
18 u8 alga_edid_bpc(struct device *dev, void *edid);
18 19 u16 alga_edid_manufacturer(struct device *dev, void *edid); u16 alga_edid_manufacturer(struct device *dev, void *edid);
19 20 u16 alga_edid_product_code(struct device *dev, void *edid); u16 alga_edid_product_code(struct device *dev, void *edid);
20 21 void alga_edid_monitor_name(struct device *dev, void *edid, u8 *name); void alga_edid_monitor_name(struct device *dev, void *edid, u8 *name);
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