sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
power management continued e8e2e1e2a8dc438a1f15ec3d7ec72b2ecd431f08 Sylvain BERTRAND 2013-05-01 00:57:09
powerplay preliminary support e65cce387d8aed980f48b0f58092bea31175b79d Sylvain BERTRAND 2013-04-26 17:48:11
dce sysfs: remove obsolete crtc word 288dd69b5196b3848b90e993b4d45383d7d0c972 Sylvain BERTRAND 2013-04-26 13:54:02
dce:i te idx 74e29494f7283fa105fef53291053e3630b605bf Sylvain BERTRAND 2013-04-26 13:28:37
upstream: new pci ids dda82ff321c33e0d7123dd06b0466775d9f96141 Sylvain BERTRAND 2013-04-26 12:22:27
cleaner error handling f853e060408068567efa895448ebc5807b5e5485 Sylvain BERTRAND 2013-03-22 01:28:11
alga cosmetics a8b013ce129bb7218fbf5a331f09828322219ac6 Sylvain BERTRAND 2013-03-22 01:21:27
massive comestics f0ff31f57512bd63b707a34d8f6252091facb632 Sylvain BERTRAND 2013-03-22 01:02:42
sysfs discret_vram property cf1c115de509b4449d7e1af1e21bf26010904c46 Sylvain BERTRAND 2013-03-19 00:56:39
dce6 crtc attribute 8f7a977603c22668c56d36c59868b74426fcf371 Sylvain BERTRAND 2013-03-12 17:02:51
ioctl edid not big enough fa9570a5821514fdb281d81ce801c2c86592dc69 Sylvain BERTRAND 2013-03-11 22:14:17
edid override has ioctl d0e628fe0d9e43cdebb3ce32cf04e53f4e36239e Sylvain BERTRAND 2013-03-11 20:48:26
forgot to remove the edid binary attribute fe3bf78e0ef1919315c1ba4da75dd3a320140061 Sylvain BERTRAND 2013-03-07 16:48:36
finally switch to binary attr for edid 739827ff0f69bacbda2bc18c19ab3cf9a7b96a5b Sylvain BERTRAND 2013-03-07 16:30:46
display properties with edid patching e43106768022d2d37e2120f4748e1bbe294f2fb9 Sylvain BERTRAND 2013-03-07 03:33:05
first shot at sysfs for display hotplug 411ae25ba5390aa8cb43d104fc7942781c036758 Sylvain BERTRAND 2013-03-06 02:10:12
new tahiti pci id 6e6296898ab0e460aba5a5c16e28a50927f073f9 Sylvain BERTRAND 2013-03-04 22:39:41
atombios init, reset, oland 8b75a3e3dd4af96d09c4fdab8787e72b0046f59e Sylvain BERTRAND 2013-03-04 21:50:55
oland 0f5b78a2b2b542c564d778cc875c09b28a63567b Sylvain BERTRAND 2013-03-04 20:49:40
minor management c9d861c8bed7eb9e350245a3114ef6dd3cc37004 Sylvain BERTRAND 2013-03-04 17:27:04
Commit e8e2e1e2a8dc438a1f15ec3d7ec72b2ecd431f08 - power management continued
Author: Sylvain BERTRAND
Author date (UTC): 2013-05-01 00:57
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-05-01 00:57
Parent(s): e65cce387d8aed980f48b0f58092bea31175b79d
Signer:
Signing key:
Signing status: N
Tree: 006c0996c896db78d9fd2f3dd95f1dc8876048c3
File Lines added Lines deleted
drivers/gpu/alga/amd/atombios/dce.c 5 7
drivers/gpu/alga/amd/atombios/mod.c 3 24
drivers/gpu/alga/amd/atombios/pp.c 377 10
drivers/gpu/alga/amd/atombios/tables/cmd.h 8 4
drivers/gpu/alga/amd/atombios/tables/firmware_info.h 19 18
drivers/gpu/alga/amd/atombios/tables/i2c.h 8 6
drivers/gpu/alga/amd/atombios/tables/pp.h 104 12
drivers/gpu/alga/amd/si/drv.c 26 2
drivers/gpu/alga/amd/si/drv.h 10 1
include/alga/amd/atombios/atb.h 1 1
include/alga/amd/atombios/pp.h 14 0
File drivers/gpu/alga/amd/atombios/dce.c changed (mode: 100644) (index 18a7834..619f915)
... ... static long default_disp_clk_freq(struct atombios *atb, u32 *clk)
336 336 { {
337 337 u16 of; u16 of;
338 338 struct master_data_tbl *data_tbl; struct master_data_tbl *data_tbl;
339 struct firmware_info_v2_1 *info;
339 struct firmware_info_v2_2 *info;
340 340
341 341 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of); of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
342 342 data_tbl = atb->adev.rom + of; data_tbl = atb->adev.rom + of;
 
... ... static long default_disp_clk_freq(struct atombios *atb, u32 *clk)
344 344 of = get_unaligned_le16(&data_tbl->list.firmware_info); of = get_unaligned_le16(&data_tbl->list.firmware_info);
345 345 info = atb->adev.rom + of; info = atb->adev.rom + of;
346 346
347 if (info->subset.hdr.tbl_fmt_rev != 2
348 && info->subset.hdr.tbl_content_rev != 1) {
349 dev_err(atb->adev.dev, "atombios: firmware_info (0x%04x) "
350 "revision %u.%u not supported\n", of,
351 info->subset.hdr.tbl_fmt_rev,
352 info->subset.hdr.tbl_content_rev);
347 if (info->hdr.tbl_fmt_rev != 2 && info->hdr.tbl_content_rev != 2) {
348 dev_err(atb->adev.dev, "atombios:firmware_info (0x%04x)"
349 " revision %u.%u not supported\n", of,
350 info->hdr.tbl_fmt_rev, info->hdr.tbl_content_rev);
353 351 return -ATB_ERR; return -ATB_ERR;
354 352 } }
355 353 *clk = get_unaligned_le32(&info->default_disp_clk_freq); *clk = get_unaligned_le32(&info->default_disp_clk_freq);
File drivers/gpu/alga/amd/atombios/mod.c changed (mode: 100644) (index 3941eba..1594675)
26 26 #include "interpreter.h" #include "interpreter.h"
27 27 #include "iio_interpreter.h" #include "iio_interpreter.h"
28 28
29 long atb_asic_init(struct atombios *atb)
29 long atb_asic_init(struct atombios *atb, u32 eng_clk, u32 mem_clk)
30 30 { {
31 31 u16 of; u16 of;
32 struct master_data_tbl *data_tbl;
33 struct firmware_info_subset *info;
34 32 struct master_cmd_tbl *cmd_tbl; struct master_cmd_tbl *cmd_tbl;
35 33 struct common_cmd_tbl_hdr *asic_init; struct common_cmd_tbl_hdr *asic_init;
36 34 struct asic_init_params *ps; struct asic_init_params *ps;
 
... ... long atb_asic_init(struct atombios *atb)
38 36
39 37 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
40 38
41 /* engine and memory default clocks */
42 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
43 data_tbl = atb->adev.rom + of;
44
45 of = get_unaligned_le16(&data_tbl->list.firmware_info);
46 info = atb->adev.rom + of;
47
48 dev_info(atb->adev.dev, "atombios: firmware_info (0x%04x) revision "
49 "%u.%u\n", of, info->hdr.tbl_fmt_rev,
50 info->hdr.tbl_content_rev);
51 dev_info(atb->adev.dev, "atombios: firmware revision 0x%08x\n",
52 get_unaligned_le32(&info->firmware_rev));
53 dev_info(atb->adev.dev, "atombios: default engine clock %ukHz\n",
54 get_unaligned_le32(&info->default_eng_clk) * 10);
55 dev_info(atb->adev.dev, "atombios: default memory clock %ukHz\n",
56 get_unaligned_le32(&info->default_mem_clk) * 10);
57
58 39 /* asic_init call */ /* asic_init call */
59 40 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of); of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
60 41 cmd_tbl = atb->adev.rom + of; cmd_tbl = atb->adev.rom + of;
 
... ... long atb_asic_init(struct atombios *atb)
74 55 } }
75 56
76 57 ps = (struct asic_init_params *)atb->g_ctx.ps_top; ps = (struct asic_init_params *)atb->g_ctx.ps_top;
77 put_unaligned_le32(get_unaligned_le32(&info->default_eng_clk),
78 &ps->default_eng_clk);
79 put_unaligned_le32(get_unaligned_le32(&info->default_mem_clk),
80 &ps->default_mem_clk);
58 put_unaligned_le32(eng_clk, &ps->default_eng_clk);
59 put_unaligned_le32(mem_clk, &ps->default_mem_clk);
81 60
82 61 /* reset some global runtime workspace data */ /* reset some global runtime workspace data */
83 62 atb->g_ctx.fb_wnd = 0; atb->g_ctx.fb_wnd = 0;
File drivers/gpu/alga/amd/atombios/pp.c changed (mode: 100644) (index 471042f..a89bbd0)
7 7 #include <linux/device.h> #include <linux/device.h>
8 8 #include <asm/unaligned.h> #include <asm/unaligned.h>
9 9 #include <linux/mutex.h> #include <linux/mutex.h>
10 #include <linux/slab.h>
10 11
11 12 #include <alga/amd/atombios/atb.h> #include <alga/amd/atombios/atb.h>
13 #include <alga/amd/atombios/pp.h>
14
15 #include "interpreter.h"
12 16
13 17 #include "tables/atb.h" #include "tables/atb.h"
18 #include "tables/cmd.h"
14 19 #include "tables/data.h" #include "tables/data.h"
20 #include "tables/i2c.h"
15 21 #include "tables/pp.h" #include "tables/pp.h"
22 #include "tables/firmware_info.h"
16 23
17 24 #include "atb.h" #include "atb.h"
18 25
19 static long state_array_parse(struct atombios *atb, u16 pp_of, u16 array_of)
26 long atb_pp_defaults_get(struct atombios *atb, struct atb_pp_defaults *d)
27 {
28 u16 of;
29 struct master_data_tbl *data_tbl;
30 struct firmware_info_v2_2 *info;
31 long r;
32
33 mutex_lock(&atb->mutex);
34
35 /* engine and memory default clocks */
36 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
37 data_tbl = atb->adev.rom + of;
38
39 of = get_unaligned_le16(&data_tbl->list.firmware_info);
40 info = atb->adev.rom + of;
41
42 d->eng_clk = get_unaligned_le32(&info->default_eng_clk);
43 d->mem_clk = get_unaligned_le32(&info->default_mem_clk);
44 d->vddc = get_unaligned_le16(&info->default_vddc);
45 d->vddci = get_unaligned_le16(&info->default_vddci);
46
47 dev_info(atb->adev.dev, "atombios:firmware_info (0x%04x) revision "
48 "%u.%u\n", of, info->hdr.tbl_fmt_rev,
49 info->hdr.tbl_content_rev);
50 if (info->hdr.tbl_fmt_rev != 2 && info->hdr.tbl_content_rev != 2) {
51 dev_err(atb->adev.dev, "atombios:firmware_info revision not"
52 " supported");
53 r = -ATB_ERR;
54 goto unlock_mutex;
55 }
56 dev_info(atb->adev.dev, "atombios: firmware revision 0x%08x\n",
57 get_unaligned_le32(&info->firmware_rev));
58 dev_info(atb->adev.dev, "atombios: default engine clock %ukHz\n",
59 d->eng_clk * 10);
60 dev_info(atb->adev.dev, "atombios: default memory clock %ukHz\n",
61 d->mem_clk * 10);
62 dev_info(atb->adev.dev, "atombios: default vddc %umV\n",d->vddc);
63 dev_info(atb->adev.dev, "atombios: default vddci %umV\n",d->vddci);
64
65 r = 0;
66
67 unlock_mutex:
68 mutex_unlock(&atb->mutex);
69 return r;
70 }
71 EXPORT_SYMBOL_GPL(atb_pp_defaults_get);
72
73 static long voltage_get(struct atombios *atb, u8 type, u16 id, u16 *lvl)
74 {
75 u16 of;
76 struct master_cmd_tbl *cmd_tbl;
77 struct common_cmd_tbl_hdr *voltage;
78 struct voltage_params *ps;
79 long r;
80
81 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
82 cmd_tbl = atb->adev.rom + of;
83 of = get_unaligned_le16(&cmd_tbl->list.voltage);
84
85 voltage = atb->adev.rom + of;
86 dev_info(atb->adev.dev, "atombios:voltage (0x%04x) revision %u.%u\n",
87 of, voltage->hdr.tbl_fmt_rev,voltage->hdr.tbl_content_rev);
88 if (voltage->hdr.tbl_fmt_rev != 1
89 || voltage->hdr.tbl_content_rev != 3) {
90 dev_err(atb->adev.dev, "atombios:voltage revision not"
91 " supported");
92 r = -ATB_ERR;
93 goto exit;
94 }
95
96 atb->g_ctx.ps_dws = 0x80;/* max for ps index */
97 atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
98 if (!atb->g_ctx.ps_top) {
99 dev_err(atb->adev.dev, "atombios:unable to allocate parameter"
100 " space (stack)\n");
101 r = -ATB_ERR;
102 goto exit;
103 }
104 ps = (struct voltage_params *)atb->g_ctx.ps_top;
105 ps->type = type;
106 ps->action = VOLTAGE_ACTION_GET;
107 put_unaligned_le16(id, &ps->lvl);
108
109 atb->g_ctx.fb_wnd = 0;
110 atb->g_ctx.regs_blk = 0;
111 atb->g_ctx.io_mode = IO_MM;
112
113 r = interpret(atb, of, 0, 0);
114
115 if (r == 0)
116 *lvl = get_unaligned_le16(&ps->lvl);
117
118 kfree(atb->g_ctx.ps_top);
119
120 exit:
121 return r;
122 }
123
124 long atb_eng_clk_set(struct atombios *atb, u32 clk)
125 {
126 u16 of;
127 struct master_cmd_tbl *cmd_tbl;
128 struct common_cmd_tbl_hdr *eng_clk_set;
129 struct mem_eng_clk_params *ps;
130 long r;
131
132 mutex_lock(&atb->mutex);
133
134 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
135 cmd_tbl = atb->adev.rom + of;
136 of = get_unaligned_le16(&cmd_tbl->list.eng_clk_set);
137
138 eng_clk_set = atb->adev.rom + of;
139 dev_info(atb->adev.dev, "atombios:eng_clk_set (0x%04x) revision %u.%u\n",
140 of, eng_clk_set->hdr.tbl_fmt_rev,
141 eng_clk_set->hdr.tbl_content_rev);
142
143 atb->g_ctx.ps_dws = 0x80;/* max for ps index */
144 atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
145 if (!atb->g_ctx.ps_top) {
146 dev_err(atb->adev.dev, "atombios:unable to allocate parameter"
147 " space (stack)\n");
148 r = -ATB_ERR;
149 goto unlock_mutex;
150 }
151 ps = (struct mem_eng_clk_params *)atb->g_ctx.ps_top;
152 put_unaligned_le32(clk, &ps->clk);
153
154 atb->g_ctx.fb_wnd = 0;
155 atb->g_ctx.regs_blk = 0;
156 atb->g_ctx.io_mode = IO_MM;
157
158 r = interpret(atb, of, 0, 0);
159 kfree(atb->g_ctx.ps_top);
160
161 unlock_mutex:
162 mutex_unlock(&atb->mutex);
163 return r;
164 }
165 EXPORT_SYMBOL_GPL(atb_eng_clk_set);
166
167 long atb_mem_clk_set(struct atombios *atb, u32 clk)
168 {
169 u16 of;
170 struct master_cmd_tbl *cmd_tbl;
171 struct common_cmd_tbl_hdr *mem_clk_set;
172 struct mem_eng_clk_params *ps;
173 long r;
174
175 mutex_lock(&atb->mutex);
176
177 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
178 cmd_tbl = atb->adev.rom + of;
179 of = get_unaligned_le16(&cmd_tbl->list.mem_clk_set);
180
181 mem_clk_set = atb->adev.rom + of;
182 dev_info(atb->adev.dev, "atombios:mem_clk_set (0x%04x) revision %u.%u\n",
183 of, mem_clk_set->hdr.tbl_fmt_rev,
184 mem_clk_set->hdr.tbl_content_rev);
185
186 atb->g_ctx.ps_dws = 0x80;/* max for ps index */
187 atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
188 if (!atb->g_ctx.ps_top) {
189 dev_err(atb->adev.dev, "atombios:unable to allocate parameter"
190 " space (stack)\n");
191 r = -ATB_ERR;
192 goto unlock_mutex;
193 }
194 ps = (struct mem_eng_clk_params *)atb->g_ctx.ps_top;
195 put_unaligned_le32(clk, &ps->clk);
196
197 atb->g_ctx.fb_wnd = 0;
198 atb->g_ctx.regs_blk = 0;
199 atb->g_ctx.io_mode = IO_MM;
200
201 r = interpret(atb, of, 0, 0);
202 kfree(atb->g_ctx.ps_top);
203
204 unlock_mutex:
205 mutex_unlock(&atb->mutex);
206 return r;
207 }
208 EXPORT_SYMBOL_GPL(atb_mem_clk_set);
209
210 long atb_voltage_set(struct atombios *atb, u8 type, u16 lvl)
20 211 { {
212 u16 of;
213 struct master_cmd_tbl *cmd_tbl;
214 struct common_cmd_tbl_hdr *voltage;
215 struct voltage_params *ps;
216 long r;
217
218 mutex_lock(&atb->mutex);
219
220 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
221 cmd_tbl = atb->adev.rom + of;
222 of = get_unaligned_le16(&cmd_tbl->list.voltage);
223
224 voltage = atb->adev.rom + of;
225 dev_info(atb->adev.dev, "atombios:voltage (0x%04x) revision %u.%u\n",
226 of, voltage->hdr.tbl_fmt_rev,voltage->hdr.tbl_content_rev);
227 if (voltage->hdr.tbl_fmt_rev != 1
228 || voltage->hdr.tbl_content_rev != 3) {
229 dev_err(atb->adev.dev, "atombios:voltage revision not"
230 " supported");
231 r = -ATB_ERR;
232 goto unlock_mutex;
233 }
234
235 atb->g_ctx.ps_dws = 0x80;/* max for ps index */
236 atb->g_ctx.ps_top = kzalloc(atb->g_ctx.ps_dws * 4, GFP_KERNEL);
237 if (!atb->g_ctx.ps_top) {
238 dev_err(atb->adev.dev, "atombios:unable to allocate parameter"
239 " space (stack)\n");
240 r = -ATB_ERR;
241 goto unlock_mutex;
242 }
243 ps = (struct voltage_params *)atb->g_ctx.ps_top;
244 ps->type = type;
245 ps->action = VOLTAGE_ACTION_SET;
246 put_unaligned_le16(lvl, &ps->lvl);
247
248 atb->g_ctx.fb_wnd = 0;
249 atb->g_ctx.regs_blk = 0;
250 atb->g_ctx.io_mode = IO_MM;
251
252 r = interpret(atb, of, 0, 0);
253 kfree(atb->g_ctx.ps_top);
254
255 unlock_mutex:
256 mutex_unlock(&atb->mutex);
257 return r;
258 }
259 EXPORT_SYMBOL_GPL(atb_voltage_set);
260
261 struct pp_parse {
262 union pp *pp;
21 263 struct pp_state_array *state_array; struct pp_state_array *state_array;
264 struct pp_desc_array *desc_array;
265 struct pp_clk_array *clk_array;
266 };
267
268 static long lvl_process(struct atombios *atb, struct pp_parse *pp_parse,
269 u8 state, u32 state_of, u8 lvl)
270 {
271 struct pp_state *s;
272 u32 clk_of;
273 struct pp_clk *clk;
274 long r;
275 u32 eng_clk;
276 u32 mem_clk;
277 u16 vddc;
278
279 s = (struct pp_state*)(&pp_parse->state_array->states[0] + state_of);
280
281 if (s->clk_idxes[lvl] >= pp_parse->clk_array->n) {
282 dev_err(atb->adev.dev, "atombios:pp:%u:%u(%u):error:clock info"
283 " index not in range\n", state, lvl, s->clk_idxes[lvl]);
284 return -ATB_ERR;
285 }
286
287 clk_of = pp_parse->clk_array->entry_sz * s->clk_idxes[lvl];
288 clk = (struct pp_clk*)((u8*)&pp_parse->clk_array->clks[0] + clk_of);
289
290 eng_clk = get_unaligned_le16(&clk->eng_clk_low);
291 eng_clk |= clk->eng_clk_high << 16;
292 dev_info(atb->adev.dev, "atombios:pp:%u:%u(%u):engine clk:%ukHz\n",
293 state, lvl, s->clk_idxes[lvl], eng_clk * 10);
294 mem_clk = get_unaligned_le16(&clk->mem_clk_low);
295 mem_clk |= clk->mem_clk_high << 16;
296 dev_info(atb->adev.dev, "atombios:pp:%u:%u(%u):memory clk:%ukHz\n",
297 state, lvl, s->clk_idxes[lvl], mem_clk * 10);
298
299 vddc = get_unaligned_le16(&clk->vddc);
300 if((vddc & 0xff00) == 0xff00) {
301 u16 vddc_lvl;
302 r = voltage_get(atb, VOLTAGE_TYPE_VDDC, vddc, &vddc_lvl);
303
304 if (r == 0) {
305 dev_info(atb->adev.dev, "atombios:pp:%u:%u(%u):"
306 "converted vddc:%umV\n", state, lvl,
307 s->clk_idxes[lvl], vddc_lvl);
308 } else {
309 dev_err(atb->adev.dev, "atombios:pp:%u:%u(%u):error:"
310 "unable to convert vddc\n", state, lvl,
311 s->clk_idxes[lvl]);
312 return -ATB_ERR;
313 }
314 } else {
315 dev_info(atb->adev.dev, "atombios:pp:%u:%u(%u):vddc:%umV\n",
316 state, lvl, s->clk_idxes[lvl], vddc);
317 }
318 return 0;
319 }
320
321 static long state_process(struct atombios *atb, struct pp_parse *pp_parse,
322 u8 state, u32 state_of)
323 {
324 struct pp_state *s;
325 u8 lvl;
326 u32 d_of;
327 struct pp_desc *d;
328
329 s = (struct pp_state*)(&pp_parse->state_array->states[0] + state_of);
330 dev_info(atb->adev.dev, "atombios:pp:state %u has %u power levels\n",
331 state, s->lvls_n);
332 //XXX:this is a bug, you must use the state index to fetch the state
333 //description, *not* pp_state.desc_idx
334 d_of = state * pp_parse->desc_array->entry_sz;
335 d = (struct pp_desc*)((u8*)&pp_parse->desc_array->descs[0] + d_of);
336 dev_info(atb->adev.dev, "atombios:pp:%u:desc_of:0x%04x\n", state, d_of);
337 dev_info(atb->adev.dev, "atombios:pp:%u:desc:class:0x%04x\n", state,
338 get_unaligned_le16(&d->class));
339 dev_info(atb->adev.dev, "atombios:pp:%u:desc:class2:0x%04x\n", state,
340 get_unaligned_le16(&d->class2));
341
342 lvl = 0;
343 while(1) {
344 long r;
345 if (lvl == s->lvls_n)
346 break;
347
348 r = lvl_process(atb, pp_parse, state, state_of, lvl);
349 if (r != 0)
350 return r;
351 ++lvl;
352 }
353 return 0;
354 }
355
356 static long state_array_parse(struct atombios *atb, struct pp_parse *pp_parse)
357 {
358 u8 state;
359 u32 state_of;
22 360
23 state_array = atb->adev.rom + pp_of + array_of;
24 dev_info(atb->adev.dev, "atombios:pp:%u states\n",state_array->n);
361 dev_info(atb->adev.dev, "atombios:pp:%u states\n",
362 pp_parse->state_array->n);
363 state = 0;
364 state_of = 0;
365 while(1) {
366 struct pp_state *s;
367 long r;
368 if (state == pp_parse->state_array->n)
369 break;
370 r = state_process(atb, pp_parse, state, state_of);
371 if (r != 0)
372 return r;
373 ++state;
374 s = (struct pp_state*)(&pp_parse->state_array->states[0]
375 + state_of);
376 state_of += sizeof(*s) + s->lvls_n * sizeof(s->clk_idxes[0]);
377 }
25 378 return 0; return 0;
26 379 } }
27 380
 
... ... long atb_pp(struct atombios *atb)
29 382 { {
30 383 u16 of; u16 of;
31 384 struct master_data_tbl *data_tbl; struct master_data_tbl *data_tbl;
32 union pp *pp;
385 struct pp_parse pp_parse;
33 386 long r; long r;
34 387
35 388 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
 
... ... long atb_pp(struct atombios *atb)
38 391 data_tbl = atb->adev.rom + of; data_tbl = atb->adev.rom + of;
39 392
40 393 of = get_unaligned_le16(&data_tbl->list.pp_info); of = get_unaligned_le16(&data_tbl->list.pp_info);
41 pp = atb->adev.rom + of;
394 pp_parse.pp = atb->adev.rom + of;
42 395
43 396 dev_info(atb->adev.dev, "atombios:pp_info (0x%04x) revision %u.%u\n", dev_info(atb->adev.dev, "atombios:pp_info (0x%04x) revision %u.%u\n",
44 of, pp->pp1.hdr.tbl_fmt_rev,pp->pp1.hdr.tbl_content_rev);
397 of, pp_parse.pp->pp1.hdr.tbl_fmt_rev,
398 pp_parse.pp->pp1.hdr.tbl_content_rev);
45 399
46 if (pp->pp1.hdr.tbl_fmt_rev != 6 && pp->pp1.hdr.tbl_content_rev != 1) {
400 if (pp_parse.pp->pp1.hdr.tbl_fmt_rev != 6
401 && pp_parse.pp->pp1.hdr.tbl_content_rev != 1) {
47 402 dev_err(atb->adev.dev, "atombios:pp_info (0x%04x) revision" dev_err(atb->adev.dev, "atombios:pp_info (0x%04x) revision"
48 " %u.%u not supported\n", of, pp->pp1.hdr
49 .tbl_fmt_rev, pp->pp1.hdr
403 " %u.%u not supported\n", of, pp_parse.pp->pp1.hdr
404 .tbl_fmt_rev, pp_parse.pp->pp1.hdr
50 405 .tbl_content_rev); .tbl_content_rev);
51 406 r = -ATB_ERR; r = -ATB_ERR;
52 407 goto unlock_mutex; goto unlock_mutex;
53 408 } }
54 409
55 state_array_parse(atb,of,get_unaligned_le16(&pp->pp1.state_array_of));
410 pp_parse.state_array = atb->adev.rom + of
411 + get_unaligned_le16(&pp_parse.pp->
412 pp1.state_array_of);
413 pp_parse.desc_array = atb->adev.rom + of
414 + get_unaligned_le16(&pp_parse.pp->pp1
415 .desc_array_of);
416 pp_parse.clk_array = atb->adev.rom + of
417 + get_unaligned_le16(&pp_parse.pp->pp1
418 .clk_array_of);
419
420 r = state_array_parse(atb, &pp_parse);
421 if (r != 0)
422 goto unlock_mutex;
56 423
57 424 r = 0; r = 0;
58 425 unlock_mutex: unlock_mutex:
File drivers/gpu/alga/amd/atombios/tables/cmd.h changed (mode: 100644) (index 8af3577..d2d09d3)
... ... struct cmd_tbls_list
12 12 __le16 asic_init; __le16 asic_init;
13 13 u16 unused0[3]; u16 unused0[3];
14 14 __le16 enc_ctl; __le16 enc_ctl;
15 u16 unused1[7];
15 u16 unused1[5];
16 __le16 eng_clk_set;
17 __le16 mem_clk_set;
16 18 __le16 pixel_clk_set; __le16 pixel_clk_set;
17 19 __le16 crtc_pair_pwr_gate; __le16 crtc_pair_pwr_gate;
18 20 u16 unused2[19]; u16 unused2[19];
 
... ... struct cmd_tbls_list
27 29 __le16 crtc_db_regs; __le16 crtc_db_regs;
28 30 u16 unused6[4]; u16 unused6[4];
29 31 __le16 crtc_timing; __le16 crtc_timing;
30 u16 unused7[26];
32 u16 unused7[17];
33 __le16 voltage;
34 u16 unused8[8];
31 35 __le16 trans_ctl; __le16 trans_ctl;
32 u16 unused8;
33 __le16 dp_aux;
34 36 u16 unused9; u16 unused9;
37 __le16 dp_aux;
38 u16 unused10[2];
35 39 } __packed; } __packed;
36 40
37 41 struct master_cmd_tbl struct master_cmd_tbl
File drivers/gpu/alga/amd/atombios/tables/firmware_info.h changed (mode: 100644) (index a243c3d..65a8629)
5 5 * This fork is protected by the GNU affero GPLv3 with additionnal rights * This fork is protected by the GNU affero GPLv3 with additionnal rights
6 6 * Original code from Advanced Micro Devices, Inc. * Original code from Advanced Micro Devices, Inc.
7 7 */ */
8
9 /*
10 * common subset of all firmware_info revisions used of asic_init, as far as our
11 * specs are uptodate
12 */
13 struct firmware_info_subset {
8 struct firmware_info_v2_2 {
14 9 struct common_tbl_hdr hdr; struct common_tbl_hdr hdr;
15 10 __le32 firmware_rev; __le32 firmware_rev;
16 __le32 default_eng_clk; /* in 10kHz unit */
17 __le32 default_mem_clk; /* in 10kHz unit */
18 } __packed;
19
20 struct firmware_info_v2_1 {
21 struct firmware_info_subset subset;
22 __le32 rsvd0[2];
23 __le32 unused0[4];
11 __le32 default_eng_clk; /* in 10kHz unit */
12 __le32 default_mem_clk; /* in 10kHz unit */
13 __le32 rsvd0[4];
14 __le32 unused[2];
24 15 __le32 default_disp_clk_freq; /* in 10 kHz unit */ __le32 default_disp_clk_freq; /* in 10 kHz unit */
25 16 u8 rsvd1; u8 rsvd1;
26 17 u8 unused1; u8 unused1;
27 __le16 unused2[3];
18 __le16 default_vddc; /* in mV unit */
19 __le16 unused2[2];
28 20 __le32 rsvd2; __le32 rsvd2;
29 21 __le32 unused3; __le32 unused3;
30 __le16 unused4[13];
22 u8 unused4;
23 u8 rsvd3[3];
24 __le32 rsvd4[2];
25 __le16 rvsd5;
26 __le16 unused5[2];
27 __le16 default_vddci; /* in mV unit */
28 __le16 unused6[3];
31 29 __le16 uniphy_dp_mode_ext_clk_freq; /* in 10kHz unit, if 0; dp uses __le16 uniphy_dp_mode_ext_clk_freq; /* in 10kHz unit, if 0; dp uses
32 30 internal pll as input clock, internal pll as input clock,
33 31 else dp uses an external else dp uses an external
34 32 clock */ clock */
35 u8 unused5;
36 u8 rsvd3[3];
33 u8 unused7;
34 u8 rsvd6[3];
35 __le16 unused8;
36 __le16 rsvd7;
37 __le32 rsvd8[3];
37 38 } __packed; } __packed;
38 39 #endif /* _TABLES_FIRMWARE_INFO_H */ #endif /* _TABLES_FIRMWARE_INFO_H */
File drivers/gpu/alga/amd/atombios/tables/i2c.h changed (mode: 100644) (index 1b10f25..1c4960b)
1 #ifndef _TABLES_I2C_H
2 #define _TABLES_I2C_H
1 #ifndef TABLES_I2C_H
2 #define TABLES_I2C_H
3 3 /* /*
4 4 * Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com) * Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
5 5 * This fork is protected by the GNU affero GPLv3 with additionnal rights * This fork is protected by the GNU affero GPLv3 with additionnal rights
6 6 * Original code from Advanced Micro Devices, Inc. * Original code from Advanced Micro Devices, Inc.
7 7 */ */
8 8
9 struct gpio_i2c_assignment
10 {
9 struct gpio_i2c_assignment {
11 10 __le16 clk_mask_reg_idx; __le16 clk_mask_reg_idx;
12 11 __le16 clk_en_reg_idx; __le16 clk_en_reg_idx;
13 12 __le16 clk_y_reg_idx; __le16 clk_y_reg_idx;
 
... ... struct gpio_i2c_assignment
37 36
38 37 #define I2C_MM_ENG_ID 0x02 #define I2C_MM_ENG_ID 0x02
39 38
40 struct gpio_i2c_info
41 {
39 struct gpio_i2c_info {
42 40 struct common_tbl_hdr hdr; struct common_tbl_hdr hdr;
43 41 struct gpio_i2c_assignment info[]; struct gpio_i2c_assignment info[];
44 42 } __packed; } __packed;
43
44 struct hw_i2c_one_data_byte_wr_params {
45 u16 unused[6];
46 } __packed;
45 47 #endif /* _TABLES_I2C_H */ #endif /* _TABLES_I2C_H */
File drivers/gpu/alga/amd/atombios/tables/pp.h changed (mode: 100644) (index 8205729..8dd6f05)
6 6 * Original code from Advanced Micro Devices, Inc. * Original code from Advanced Micro Devices, Inc.
7 7 */ */
8 8
9 //------------------------------------------------------------------------------
9 10 struct pp_thermal_ctrler { struct pp_thermal_ctrler {
10 u8 type;
11 u8 i2c_line;
12 u8 i2c_addr;
13 u8 fan_params;
14 u8 fan_min_rpm;
15 u8 fan_max_rpm;
16 u8 rsvd;
17 u8 flgs;
11 u8 unused[8];
18 12 } __packed; } __packed;
19 13
20 14 struct pp1 { struct pp1 {
 
... ... struct pp1 {
25 19
26 20 u8 state_entry_sz; u8 state_entry_sz;
27 21 u8 clk_sz; u8 clk_sz;
28 u8 non_clk_sz;
22 u8 desc_sz;
29 23
30 24 __le16 state_array_of; __le16 state_array_of;
31 25 __le16 clk_array_of; __le16 clk_array_of;
32 __le16 non_clk_array_of;
26 __le16 desc_array_of;
33 27
34 28 __le16 back_bias_time; /* microseconds */ __le16 back_bias_time; /* microseconds */
35 29 __le16 voltage_time; /* microseconds */ __le16 voltage_time; /* microseconds */
 
... ... union pp {
50 44 /* array of sub pwr lvls for that a major state */ /* array of sub pwr lvls for that a major state */
51 45 struct pp_state { struct pp_state {
52 46 u8 lvls_n; u8 lvls_n;
53 u8 non_clk_idx;
47 u8 desc_idx; /* BUG:DO NOT USE!!! USE STATE INDEX */
54 48 u8 clk_idxes[]; u8 clk_idxes[];
55 49 } __packed; } __packed;
56 50
57 51 /* array of major pwr major states */ /* array of major pwr major states */
58 52 struct pp_state_array { struct pp_state_array {
59 53 u8 n; u8 n;
60 struct pp_state states[];
54 u8 states[];/* struct pp_state */
55 } __packed;
56
57 #define PP_DESC_CLASS_UI_MASK 0x0007
58 #define PP_DESC_CLASS_UI_NONE 0
59 #define PP_DESC_CLASS_UI_BATTERY 1
60 #define PP_DESC_CLASS_UI_BALANCED 3
61 #define PP_DESC_CLASS_UI_PERFORMANCE 5
62 /* 2, 4, 6, 7 are reserved */
63 #define PP_DESC_CLASS_BOOT 0x0008
64 #define PP_DESC_CLASS_THERMAL 0x0010
65 #define PP_DESC_CLASS_LIMITEDPOWERSOURCE 0x0020
66 #define PP_DESC_CLASS_REST 0x0040
67 #define PP_DESC_CLASS_FORCED 0x0080
68 #define PP_DESC_CLASS_3DPERFORMANCE 0x0100
69 #define PP_DESC_CLASS_OVERDRIVETEMPLATE 0x0200
70 #define PP_DESC_CLASS_UVDSTATE 0x0400
71 #define PP_DESC_CLASS_3DLOW 0x0800
72 #define PP_DESC_CLASS_ACPI 0x1000
73 #define PP_DESC_CLASS_HD2STATE 0x2000
74 #define PP_DESC_CLASS_HDSTATE 0x4000
75 #define PP_DESC_CLASS_SDSTATE 0x8000
76
77 #define PP_DESC_CAPS_SETTINGS_SINGLE_DISP_ONLY 0x00000001
78 #define PP_DESC_CAPS_SETTINGS_SUPPORTS_VIDEO_PLAYBACK 0x00000002
79 struct pp_desc {
80 __le16 class;
81 u8 temp_min;
82 u8 temp_max;
83 __le32 caps_settings;
84 u8 required_pwr;
85 __le16 class2;
86 __le32 v_clk;
87 __le32 d_clk;
88 u8 unused[5];
89 } __packed;
90
91 struct pp_desc_array {
92 u8 n;
93 u8 entry_sz;
94 u8 descs[];/* struct pp_desc */
95 } __packed;
96
97 /* used also in voltage command */
98 #define VIRTUAL_VOLTAGE_ID_0 0xff01
99 #define VIRTUAL_VOLTAGE_ID_1 0xff02
100 #define VIRTUAL_VOLTAGE_ID_2 0xff03
101 #define VIRTUAL_VOLTAGE_ID_3 0xff04
102 struct pp_clk {
103 __le16 eng_clk_low;
104 u8 eng_clk_high;
105
106 __le16 mem_clk_low;
107 u8 mem_clk_high;
108
109 __le16 vddc;
110 __le16 vddci;
111 u8 pcie_gen;
112 u8 unused;
113
114 __le32 flgs;
115 } __packed;
116
117 struct pp_clk_array {
118 u8 n;
119 u8 entry_sz;
120 u8 clks[];/* struct pp_clk */
121 } __packed;
122 //------------------------------------------------------------------------------
123
124 //------------------------------------------------------------------------------
125 #define VOLTAGE_TYPE_VDDC 1
126 #define VOLTAGE_TYPE_MVDDC 2
127 #define VOLTAGE_TYPE_MVDDQ 3
128 #define VOLTAGE_TYPE_VDDCI 4
129
130 #define VOLTAGE_ACTION_SET 0
131 #define VOLTAGE_ACTION_INIT_REGULATOR 3
132 #define VOLTAGE_ACTION_SET_PHASE 4
133 #define VOLTAGE_ACTION_GET 6/* get from virtual voltage id */
134 struct voltage_params {
135 u8 type;
136 u8 action;
137 __le16 lvl;
138 struct hw_i2c_one_data_byte_wr_params internal;
139 } __packed;
140 //------------------------------------------------------------------------------
141
142
143 //------------------------------------------------------------------------------
144 struct mem_eng_pll_params {
145 __le32 unused0;
146 u8 unused1[4];
147 } __packed;
148
149 struct mem_eng_clk_params {
150 __le32 clk;/* 10kHz units */
151 struct mem_eng_pll_params mem_eng_pll_params;
61 152 } __packed; } __packed;
153 //------------------------------------------------------------------------------
62 154 #endif #endif
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index a604e20..c8555bc)
... ... static int probe(struct pci_dev *dev, const struct pci_device_id *id)
265 265 struct dev_drv_data *dd; struct dev_drv_data *dd;
266 266 u32 addr_cfg; u32 addr_cfg;
267 267 u32 mem_row_sz_kb; u32 mem_row_sz_kb;
268 struct atb_pp_defaults atb_pp_defaults;
268 269
269 270 r = pci_enable_device(dev); r = pci_enable_device(dev);
270 271 if (r) { if (r) {
 
... ... static int probe(struct pci_dev *dev, const struct pci_device_id *id)
357 358 } }
358 359 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
359 360
361 /* get defaults clocks and voltages */
362 r = atb_pp_defaults_get(dd->atb, &atb_pp_defaults);
363 if (r) {
364 dev_err(&dev->dev, "atombios failed to get default clocks and"
365 " voltages/n");
366 goto err_dce_free;
367 }
368 dd->pp.default_eng_clk = atb_pp_defaults.eng_clk;
369 dd->pp.default_mem_clk = atb_pp_defaults.mem_clk;
370 dd->pp.default_vddc = atb_pp_defaults.vddc;
371 dd->pp.default_vddc = atb_pp_defaults.vddci;
372
360 373 /* posting will ensure the chip is in good shape */ /* posting will ensure the chip is in good shape */
361 374 dev_info(&dev->dev, "posting now...\n"); dev_info(&dev->dev, "posting now...\n");
362 r = atb_asic_init(dd->atb);
375 r = atb_asic_init(dd->atb, dd->pp.default_eng_clk,
376 dd->pp.default_mem_clk);
363 377 if (r) { if (r) {
364 378 dev_err(&dev->dev, "atombios failed to init the asic\n"); dev_err(&dev->dev, "atombios failed to init the asic\n");
365 379 goto err_dce_free; goto err_dce_free;
 
... ... static int probe(struct pci_dev *dev, const struct pci_device_id *id)
514 528 dce6_hpds_intr_ena(dd->dce); dce6_hpds_intr_ena(dd->dce);
515 529 cps_intr_ena(dev); cps_intr_ena(dev);
516 530
531 //TEST
517 532 atb_pp(dd->atb); atb_pp(dd->atb);
533 //atb_voltage_set(dd->atb, ATB_VOLTAGE_TYPE_VDDC, 1170);/* 1170 mV */
534 //atb_mem_clk_set(dd->atb, 137500);/* 1.375GHz */
535 //atb_eng_clk_set(dd->atb, 100000);/* 1GHz */
536 //msleep(10000);/* 10s */
537 atb_eng_clk_set(dd->atb, 30000);/* 300MHz */
538 atb_mem_clk_set(dd->atb, 15000);/* 150MHz */
539 atb_voltage_set(dd->atb, ATB_VOLTAGE_TYPE_VDDC, 850);/* 850 mV */
540
518 541
519 542 dev_info(&dev->dev, "ready\n"); dev_info(&dev->dev, "ready\n");
520 543 return 0; return 0;
 
... ... static void remove(struct pci_dev *dev)
619 642 rng_free(&dd->vram.mng, dd->vram.scratch_page); rng_free(&dd->vram.mng, dd->vram.scratch_page);
620 643
621 644 rng_mng_destroy(&dd->vram.mng); rng_mng_destroy(&dd->vram.mng);
622 atb_asic_init(dd->atb);/* do try to set it in a nice state */
645 /* do try to set the chip in a nice state */
646 atb_asic_init(dd->atb, dd->pp.default_eng_clk, dd->pp.default_mem_clk);
623 647 atb_cleanup(dd->atb); atb_cleanup(dd->atb);
624 648 kfree(dd->atb); kfree(dd->atb);
625 649 kfree(adev.rom); kfree(adev.rom);
File drivers/gpu/alga/amd/si/drv.h changed (mode: 100644) (index 6ba50ba..e27a947)
10 10 #define VERDE 2 #define VERDE 2
11 11 #define OLAND 3 #define OLAND 3
12 12
13 #define SI_ERR -900
13 #define SI_ERR 900
14 14 #define USEC_TIMEOUT 100000 /* 100000 us = 100 ms */ #define USEC_TIMEOUT 100000 /* 100000 us = 100 ms */
15 15
16 16 struct cfg { struct cfg {
 
... ... struct cfg {
19 19 struct gpu_cfg gpu; struct gpu_cfg gpu;
20 20 }; };
21 21
22 struct pp {
23 u32 default_eng_clk; /* 10 kHz units */
24 u32 default_mem_clk; /* 10 kHz units */
25 u16 default_vddc; /* mV units */
26 u16 default_vddci; /* mV units */
27 };
28
22 29 struct dev_drv_data { struct dev_drv_data {
23 30 u8 family; u8 family;
24 31 struct cfg cfg; struct cfg cfg;
25 32
26 33 struct atombios *atb; struct atombios *atb;
27 34
35 struct pp pp;
36
28 37 struct dce6 *dce; struct dce6 *dce;
29 38
30 39 void __iomem *regs; void __iomem *regs;
File include/alga/amd/atombios/atb.h changed (mode: 100644) (index b6024b8..3051de8)
... ... struct atombios *atb_alloc(struct atb_dev *adev);
13 13 long atb_init(struct atombios *atb); long atb_init(struct atombios *atb);
14 14 void atb_cleanup(struct atombios *atb); void atb_cleanup(struct atombios *atb);
15 15
16 long atb_asic_init(struct atombios *atb);
16 long atb_asic_init(struct atombios *atb, u32 eng_clk, u32 mem_clk);
17 17 #endif #endif
File include/alga/amd/atombios/pp.h changed (mode: 100644) (index ae8564d..e24e25e)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 struct atb_pp_defaults {
9 u32 eng_clk; /* 10 kHz units */
10 u32 mem_clk; /* 10 kHz units */
11 u16 vddc; /* mV units */
12 u16 vddci; /* mV units */
13 };
14 long atb_pp_defaults_get(struct atombios *atb, struct atb_pp_defaults *d);
8 15 long atb_pp(struct atombios *atb); long atb_pp(struct atombios *atb);
16 #define ATB_VOLTAGE_TYPE_VDDC 1
17 #define ATB_VOLTAGE_TYPE_MVDDC 2
18 #define ATB_VOLTAGE_TYPE_MVDDQ 3
19 #define ATB_VOLTAGE_TYPE_VDDCI 4
20 long atb_voltage_set(struct atombios *atb, u8 type, u16 lvl);
21 long atb_eng_clk_set(struct atombios *atb, u32 clk);
22 long atb_mem_clk_set(struct atombios *atb, u32 clk);
9 23 #endif #endif
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/linux-gpu-amd-si

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main