sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
significant gfx stack update 81b1641e4a68d13bdb3207958c1b61f5c9178110 Sylvain BERTRAND 2019-11-12 17:19:01
st with alpha 40c4dd0ba37efa471f371b5ebb2c700791cf2e41 Sylvain BERTRAND 2019-10-29 04:12:09
gfx stack update 2e34313ea063d321682a21a4d1b18b33fd1c08b2 Sylvain BERTRAND 2019-10-28 19:42:48
add a direct into steam startup 2f9f5cdf6cc52bd91252d3320e84a75b51e9ba29 Sylvain BERTRAND 2019-10-27 18:38:37
gfx stack update 7f8dbe3e5666565b1d7dbd593894440dce671843 Sylvain BERTRAND 2019-10-24 23:08:53
alsa 1.1.9 1962471fe6f6cbf49db17de01d37a0eb312c351a Sylvain BERTRAND 2019-10-16 19:48:29
gfx stack update (xserver broken) 24366ffbb58e6ab17e36fd7857d1740ea00e5c3f Sylvain BERTRAND 2019-10-14 22:57:04
gfx stack update 83dc9bfacd6249162046aadbc77c968955fa5036 Sylvain BERTRAND 2019-10-07 20:54:30
add x11 compositing 9308f9158cac1fef16bb64b105e7c9583a55b2b8 Sylvain BERTRAND 2019-10-02 20:48:29
gfx stack update 0fc55d155b358c036a3032d045c78e6f3adab111 Sylvain BERTRAND 2019-09-30 20:46:52
gfx stack update c8c3e4d0abe14e601250bccc72d0cd3423f16805 Sylvain BERTRAND 2019-09-25 21:05:20
gfx stack update 4e84d92d1f9f30dd4c42347e1d92829f4563e1ab Sylvain BERTRAND 2019-09-16 16:54:42
fix openssh nasty bug due to linking to static libressl bddd58feb4ffd205f08430069840f0878775ec75 Sylvain BERTRAND 2019-09-13 23:28:10
update links and enable freetype/fontconfig b51e63a4d6ef5e78789d7246a5f1481ac62b68a0 Sylvain BERTRAND 2019-09-11 02:32:00
update openssh 56c06574ee36175891cd6ac8bca4405324f6dcf9 Sylvain BERTRAND 2019-09-11 01:49:32
update libressl 9b49618b8f194a4c5af4cca5ec2394d9de4a7a47 Sylvain BERTRAND 2019-09-11 01:49:03
update freetype shared dynamic lib 345eb8bd48c61a50c467475704f00f62dec21890 Sylvain BERTRAND 2019-09-11 01:45:49
gfx stack update 6fe5530231ab855ba9cd027ce01cefb8ee6f21d3 Sylvain BERTRAND 2019-09-09 17:31:01
move the comment 5c8f4662c6adb71cedd8e0ecb8f619e3ec0eb235 Sylvain BERTRAND 2019-09-06 11:24:26
gfx stack update ad4649440de4767f6c8e19d3fef195f83f5692df Sylvain BERTRAND 2019-09-02 18:44:20
Commit 81b1641e4a68d13bdb3207958c1b61f5c9178110 - significant gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2019-11-12 17:19
Committer name: Sylvain BERTRAND
Committer date (UTC): 2019-11-12 17:19
Parent(s): 40c4dd0ba37efa471f371b5ebb2c700791cf2e41
Signer:
Signing key:
Signing status: N
Tree: 7c0085707d77803a36db4e3c913e90cf21858302
File Lines added Lines deleted
builders/Vulkan-LoaderAndValidationLayers-0/builder-target.sh 0 48
builders/Vulkan-LoaderAndValidationLayers-0/test.asm 0 6
builders/drm-1/builder.sh 1 1
builders/ffmpeg-0/builder.sh 1 1
builders/ffmpeg-1/builder.sh 1 1
builders/libepoxy-0/builder.sh 5 3
builders/llvm-0/builder.sh 30 24
builders/llvm-1/builder.sh 1 1
builders/mesa-gl-0/builder.sh 1 1
builders/mesa-gl-0/contrib/util.sh 1 0
builders/mesa-gl-1/builder.sh 1 1
builders/mesa-gl-1/contrib/util.sh 1 0
builders/mesa-vulkan-0/builder.sh 1 1
builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str.c 0 0
builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str_commands.c 0 0
builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str_enums.c 0 0
builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/log 0 0
builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/.gen_enum_to_str.c.swo 0 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/amd/amd.c 41 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/amd/system_values.c 9 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/generic.c 18 607
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/image.c 0 15
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/load.c 0 20
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/store.c 0 21
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/system_values.c 0 47
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/intel/image.c 14 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/ir3.c 153 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/load.c 44 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/store.c 43 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/system_values.c 71 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/v3d/v3d.c 45 0
builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c 24 1918
builders/mesa-vulkan-0/contrib/vk_enum_to_str.c 9 0
builders/mesa-vulkan-0/contrib/vk_enum_to_str.h 5 0
builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 110 12
builders/mesa-vulkan-1/builder.sh 2 2
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c 60 2
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_system_values.c 8 0
builders/mesa-vulkan-1/contrib/generators/nir/nir_intrinsics_c.c 3 0
builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 91 51
builders/mplayer-0/builder.sh 2 2
builders/mplayer-1/builder.sh 2 2
builders/vulkan-headers-0/builder.sh 28 0
builders/vulkan-loader-0/builder.sh 42 0
builders/vulkan-loader-0/contrib/loader_cmake_config.h 2 0
builders/vulkan-loader-0/contrib/x86_64_linux_gnu_xlib_xcb.sh 242 0
builders/xserver-0/builder.sh 1 1
builders/xserver-1/builder.sh 1 1
File builders/Vulkan-LoaderAndValidationLayers-0/builder-target.sh deleted (index e444473..0000000)
1 src_name=Vulkan-LoaderAndValidationLayers
2 git_commit=b4549ff9683b4f422e689f0d7d5dec4b561b4402
3 git_url0=https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers
4
5 src_dir=$src_dir_root/$src_name
6 pkg_dir=$pkgs_dir_root/$pkg_name
7 rm -Rf $pkg_dir
8 mkdir -p $pkgs_dir_root
9 cp -r $src_dir $pkg_dir
10
11 cd $pkg_dir
12
13 git checkout --force $git_commit
14 git reset --hard
15
16 build_dir=$builds_dir_root/$pkg_name-$target_gnu_triple
17 rm -Rf $build_dir
18 mkdir -p $build_dir
19 cd $build_dir
20
21 OLD_PATH=$PATH
22 export PATH=$cross_toolchain_dir_root/bin:$sdk_cmake_path/bin:$PATH
23
24 # use the unix makefile generator
25 cmake \
26 "-DCMAKE_SYSTEM_NAME=Linux" \
27 "-DCMAKE_C_COMPILER=$target_gnu_triple-gcc" \
28 "-DCMAKE_C_FLAGS=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B$target_sysroot/nyan/glibc/current/lib -L$target_sysroot/nyan/glibc/current/lib -Wl,-rpath-link,$target_sysroot/nyan/glibc/current/lib -I$target_sysroot/nyan/libxcb/0/include" \
29 "-DCMAKE_CXX_COMPILER=$target_gnu_triple-g++" \
30 "-DCMAKE_CXX_FLAGS=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B$target_sysroot/nyan/glibc/current/lib -L$target_sysroot/nyan/glibc/current/lib -Wl,-rpath-link,$target_sysroot/nyan/glibc/current/lib -I$target_sysroot/nyan/libxcb/0/include" \
31 -DPYTHON_EXECUTABLE=$sdk_python3_path/bin/python3 \
32 -DBUILD_WSI_XLIB_SUPPORT=off \
33 -DBUILD_WSI_WAYLAND_SUPPORT=off \
34 -DBUILD_LAYERS=off \
35 -DBUILD_TESTS=off \
36 -DBUILD_DEMOS=off \
37 -DCMAKE_INSTALL_PREFIX=/nyan/Vulkan-LoaderAndValidationLayers/0 \
38 -DCMAKE_BUILD_TYPE=Release \
39 $pkg_dir
40
41 cmake --build .
42 DESTDIR=$target_sysroot cmake --build . --target install
43
44 # cleanup and tidying
45 find $target_sysroot/nyan/$src_name/0/lib -type f | while read f; do if file $f | egrep 'ELF.+(shared|executable)' >/dev/null; then $target_gnu_triple-strip -s $f; fi; done
46
47 rm -Rf $build_dir $pkg_dir
48 export PATH=$OLD_PATH
File builders/Vulkan-LoaderAndValidationLayers-0/test.asm deleted (index 45ac889..0000000)
1 .intel_syntax noprefix
2 .text
3 .global sample
4 sample:
5 mov ecx, [eax + 16]
6
File builders/drm-1/builder.sh changed (mode: 100644) (index b86f17b..f854f6b)
1 1 src_name=drm src_name=drm
2 git_commit=c69c9c4f4eaaea302e41e3ffd5f7b6d4bcc6a37a
2 git_commit=0a7ad7df1472a3002cc1baa8e9879350bc59acfa
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 slot=1 slot=1
File builders/ffmpeg-0/builder.sh changed (mode: 100644) (index fca18ac..c53581e)
1 1 src_name=ffmpeg src_name=ffmpeg
2 git_commit=68f623d64451a6ee8c81b6071ec68d6097c0f213
2 git_commit=b25b6432a7345791c488fadba3bd1ac75ebb2cbb
3 3 git_url0=https://git.ffmpeg.org/$src_name.git git_url0=https://git.ffmpeg.org/$src_name.git
4 4
5 5 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
File builders/ffmpeg-1/builder.sh changed (mode: 100644) (index 139d428..8746539)
1 1 src_name=ffmpeg src_name=ffmpeg
2 git_commit=37d8ae9da8ac9f3dd01d30996b538c82ba4d8085
2 git_commit=ec3d3fc65d06a9f7bc4d32b12b14a7c75e00484d
3 3 git_url0=https://git.ffmpeg.org/$src_name.git git_url0=https://git.ffmpeg.org/$src_name.git
4 4
5 5 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
File builders/libepoxy-0/builder.sh changed (mode: 100644) (index 20e6da3..f1b1ca9)
1 1 src_name=libepoxy src_name=libepoxy
2 git_commit=2edc4973743a6e9bc5705cee8ea6a64748cc673c
2 git_commit=09edbe01d901c0f01e866aa08455c6d9ee6fd0ac
3 3 git_url0=git://github.com/anholt/$src_name git_url0=git://github.com/anholt/$src_name
4 4
5 slot=0
6
5 7 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
6 8 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
7 9 rm -Rf $pkg_dir rm -Rf $pkg_dir
 
... ... export "PKG_CONFIG_LIBDIR=\
35 37 /nyan/xorgproto/current/share/pkgconfig" /nyan/xorgproto/current/share/pkgconfig"
36 38
37 39 $pkg_dir/contrib/make.gnulinux \ $pkg_dir/contrib/make.gnulinux \
38 --prefix=/nyan/libepoxy/0 \
40 --prefix=/nyan/libepoxy/$slot \
39 41 --python3=$sdk_python3_path/bin/python3 \ --python3=$sdk_python3_path/bin/python3 \
40 42 "--dslibepoxy-cc=gcc -static-libgcc -O2 -pipe -fPIC -fvisibility=hidden -c" \ "--dslibepoxy-cc=gcc -static-libgcc -O2 -pipe -fPIC -fvisibility=hidden -c" \
41 43 "--dslibepoxy-ccld=gcc -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib -static-libgcc -shared -Wl,-soname,libepoxy.so.0 -Bsymbolic -Wl,--no-undefined" "--dslibepoxy-ccld=gcc -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib -static-libgcc -shared -Wl,-soname,libepoxy.so.0 -Bsymbolic -Wl,--no-undefined"
 
... ... $pkg_dir/contrib/make.gnulinux \
43 45 cp -f -r ./fake_root/* / cp -f -r ./fake_root/* /
44 46
45 47 # cleanup and tidying # cleanup and tidying
46 find /nyan/$src_name/0/lib -type f | while read f; do if file $f | egrep 'ELF.+(shared|executable)' >/dev/null; then strip -s $f; fi; done
48 find /nyan/$src_name/$slot/lib -type f | while read f; do if file $f | egrep 'ELF.+(shared|executable)' >/dev/null; then strip -s $f; fi; done
47 49
48 50 rm -Rf $build_dir $pkg_dir rm -Rf $build_dir $pkg_dir
File builders/llvm-0/builder.sh changed (mode: 100644) (index 74f9b3e..932035c)
1 src_name=llvm
2 git_commit=2c4ca6832fa6b306ee6a7010bfb80a3f2596f824
3 git_url0=http://llvm.org/git/llvm.git
1 src_name=llvm-project
2 git_commit=44e5879f0fb7c28b90e8042fde81bba30b4090a3
3 git_url0=git://github.com/llvm/$src_name
4
5 slot=0
4 6
5 7 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
6 8 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
 
... ... OLD_PATH=$PATH
22 24 # wants sh in path # wants sh in path
23 25 export PATH=$sdk_cmake_path/bin:$sdk_ninja_path/bin:/bin:$PATH export PATH=$sdk_cmake_path/bin:$sdk_ninja_path/bin:/bin:$PATH
24 26
25 cmake -G Ninja \
26 "-DCMAKE_C_COMPILER=gcc" \
27 "-DCMAKE_C_FLAGS=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib" \
28 "-DCMAKE_CXX_COMPILER=g++" \
29 "-DCMAKE_CXX_FLAGS:STRING=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib" \
30 -DPYTHON_EXECUTABLE=$sdk_python3_path/bin/python3 \
31 -DCMAKE_INSTALL_PREFIX=/nyan/llvm/0 \
32 -DCMAKE_BUILD_TYPE=Release \
33 -DLLVM_TARGETS_TO_BUILD=AMDGPU \
34 -DLLVM_INCLUDE_TESTS=off \
35 -DLLVM_ENABLE_PEDANTIC=off \
36 -DLLVM_PARALLEL_COMPILE_JOBS=2000 \
37 -DLLVM_PARALLEL_LINK_JOBS=2000 \
38 -DLLVM_BUILD_UTILS=off \
39 $pkg_dir
27 cmake -G Ninja \
28 "-DCMAKE_C_COMPILER=gcc" \
29 "-DCMAKE_C_FLAGS=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib" \
30 "-DCMAKE_CXX_COMPILER=g++" \
31 "-DCMAKE_CXX_FLAGS:STRING=-pipe -O2 -fPIC -static-libgcc -static-libstdc++ -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib" \
32 -DPYTHON_EXECUTABLE=$sdk_python3_path/bin/python3 \
33 -DCMAKE_INSTALL_PREFIX=/nyan/llvm/$slot \
34 -DCMAKE_BUILD_TYPE=Release \
35 -DLLVM_TARGETS_TO_BUILD=AMDGPU \
36 -DLLVM_INCLUDE_TESTS=off \
37 -DLLVM_ENABLE_PEDANTIC=off \
38 -DLLVM_PARALLEL_COMPILE_JOBS=$threads_n \
39 -DLLVM_PARALLEL_LINK_JOBS=$threads_n \
40 -DLLVM_BUILD_UTILS=off \
41 $pkg_dir/llvm
40 42
41 43 cmake --build . -- -j $threads_n cmake --build . -- -j $threads_n
42 44 # ninja does not know of DESTDIR, the llvm-config does ignore the sysroot anyway and will be useless on the target machine # ninja does not know of DESTDIR, the llvm-config does ignore the sysroot anyway and will be useless on the target machine
43 cmake -DCMAKE_INSTALL_PREFIX=/nyan/llvm/0 -P ./cmake_install.cmake
45 cmake -DCMAKE_INSTALL_PREFIX=/nyan/llvm/$slot -P ./cmake_install.cmake
44 46
45 47 # cleanup and tidying # cleanup and tidying
48 #--------
49 # since we don't use meson/gnu autotools/cmake, the following should not be usefull
46 50 # we get rid of llvm binaries and install our version of llvm-config for static linking hack (only mesa) with sysroot friendlyness # we get rid of llvm binaries and install our version of llvm-config for static linking hack (only mesa) with sysroot friendlyness
47 rm -Rf /nyan/$src_name/0/share
48 rm -f /nyan/$src_name/0/bin/*
49 cp -f $nyan_root/builders/$pkg_name/llvm-config /nyan/$src_name/0/bin/
50 find /nyan/$src_name/0 -type f -name '*.la' | xargs rm -f
51 find /nyan/$src_name/0 -type f | while read f; do if file $f | egrep 'ELF.+(shared|executable)' >/dev/null; then strip -s $f; fi; done
51 rm -Rf /nyan/llvm/$slot/share
52 rm -Rf /nyan/llvm/$slot/bin
53 #rm -f /nyan/llvm/$slot/bin/*
54 #cp -f $nyan_root/builders/$pkg_name/llvm-config /nyan/llvm/$slot/bin/
55 #--------
56 find /nyan/llvm/$slot -type f -name '*.la' | xargs rm -f
57 find /nyan/llvm/$slot -type f | while read f; do if file $f | egrep 'ELF.+(shared|executable)' >/dev/null; then strip -s $f; fi; done
52 58
53 59 rm -Rf $build_dir $pkg_dir rm -Rf $build_dir $pkg_dir
54 60 export PATH=$OLD_PATH export PATH=$OLD_PATH
File builders/llvm-1/builder.sh changed (mode: 100644) (index de93468..970cd23)
1 1 src_name=llvm src_name=llvm
2 git_commit=d1d5cb769843c1328f39f565288bf463af8a73d0
2 git_commit=2c4ca6832fa6b306ee6a7010bfb80a3f2596f824
3 3 git_url0=http://llvm.org/git/llvm.git git_url0=http://llvm.org/git/llvm.git
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/mesa-gl-0/builder.sh changed (mode: 100644) (index ecc9f2b..4c984fd)
1 1 src_name=mesa src_name=mesa
2 git_commit=a0c003007515e31c63e18f4a3c8abc86814143bf
2 git_commit=9e440b8d0b982933650c7b600de1e4b6e33f9c7d
3 3 git_url0=git://anongit.freedesktop.org/mesa/$pkg_name git_url0=git://anongit.freedesktop.org/mesa/$pkg_name
4 4
5 5 slot=0 slot=0
File builders/mesa-gl-0/contrib/util.sh changed (mode: 100644) (index f2c25b7..f4f561c)
... ... $src_dir/src/util/rgtc.c \
38 38 $src_dir/src/util/set.c \ $src_dir/src/util/set.c \
39 39 $src_dir/src/util/slab.c \ $src_dir/src/util/slab.c \
40 40 $src_dir/src/util/softfloat.c \ $src_dir/src/util/softfloat.c \
41 $src_dir/src/util/sparse_array.c \
41 42 $src_dir/src/util/string_buffer.c \ $src_dir/src/util/string_buffer.c \
42 43 $src_dir/src/util/strtod.c \ $src_dir/src/util/strtod.c \
43 44 $src_dir/src/util/u_atomic.c \ $src_dir/src/util/u_atomic.c \
File builders/mesa-gl-1/builder.sh changed (mode: 100644) (index 5387643..b28ed70)
1 1 src_name=mesa src_name=mesa
2 git_commit=4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc
2 git_commit=538d2c33b86dd9e66a6e900ac8e1cda10a5bfc4d
3 3 git_url0=git://anongit.freedesktop.org/mesa/$pkg_name git_url0=git://anongit.freedesktop.org/mesa/$pkg_name
4 4
5 5 slot=1 slot=1
File builders/mesa-gl-1/contrib/util.sh changed (mode: 100644) (index f2c25b7..f4f561c)
... ... $src_dir/src/util/rgtc.c \
38 38 $src_dir/src/util/set.c \ $src_dir/src/util/set.c \
39 39 $src_dir/src/util/slab.c \ $src_dir/src/util/slab.c \
40 40 $src_dir/src/util/softfloat.c \ $src_dir/src/util/softfloat.c \
41 $src_dir/src/util/sparse_array.c \
41 42 $src_dir/src/util/string_buffer.c \ $src_dir/src/util/string_buffer.c \
42 43 $src_dir/src/util/strtod.c \ $src_dir/src/util/strtod.c \
43 44 $src_dir/src/util/u_atomic.c \ $src_dir/src/util/u_atomic.c \
File builders/mesa-vulkan-0/builder.sh changed (mode: 100644) (index eea5135..f0d5780)
1 1 src_name=mesa src_name=mesa
2 git_commit=a0c003007515e31c63e18f4a3c8abc86814143bf
2 git_commit=9e440b8d0b982933650c7b600de1e4b6e33f9c7d
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 slot=0 slot=0
File builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str.c renamed from builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/gen_enum_to_str.c (similarity 100%)
File builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str_commands.c renamed from builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/gen_enum_to_str_commands.c (similarity 100%)
File builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/gen_enum_to_str_enums.c renamed from builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/gen_enum_to_str_enums.c (similarity 100%)
File builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str.deprecated/log renamed from builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/log (similarity 100%)
File builders/mesa-vulkan-0/contrib/generators/gen_enum_to_str/.gen_enum_to_str.c.swo deleted (index 900846c..0000000)
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/amd/amd.c added (mode: 100644) (index 0000000..b0709eb)
1 /*----------------------------------------------------------------------------*/
2 /* AMD Shader ballot operations */
3 struct nir_intrinsic nir_quad_swizzle_amd = {
4 .name = "quad_swizzle_amd",
5 .has_dest = true,
6 .idxs_n = 1,
7 .idxs_map = {
8 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
9 },
10 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
11 };
12 struct nir_intrinsic nir_masked_swizzle_amd = {
13 .name = "masked_swizzle_amd",
14 .has_dest = true,
15 .idxs_n = 1,
16 .idxs_map = {
17 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
18 },
19 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
20 };
21 struct nir_intrinsic nir_write_invocation_amd = {
22 .name = "write_invocation_amd",
23 .srcs_n = 3,
24 .src_components_n = {
25 0,0,1
26 },
27 .has_dest = true,
28 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
29 };
30 struct nir_intrinsic nir_mbcnt_amd = {
31 .name = "mbcnt_amd",
32 .srcs_n = 1,
33 .src_components_n = {
34 1
35 },
36 .has_dest = true,
37 .dest_components_n = 1,
38 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
39 };
40 /* AMD Shader ballot operations */
41 /*----------------------------------------------------------------------------*/
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/amd/system_values.c added (mode: 100644) (index 0000000..3d1244c)
1 /* System value for internal compute shaders in radeonsi. */
2 static struct nir_intrinsic nir_load_user_data_amd = {
3 .name = "load_user_data_amd",
4 .has_dest = true,
5 .dest_components_n = 4,
6 .bit_szs = 0x20,
7 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
8 .system_value = true
9 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/generic.c copied from file builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c (similarity 68%) (mode: 100644) (index fca205d..aa28770)
1 #define NIR_INTRINSIC_SRCS_N_MAX 5
2
3 #define NIR_INTRINSIC_IDX_BASE 1
4 #define NIR_INTRINSIC_IDX_WRMASK 2
5 #define NIR_INTRINSIC_IDX_STREAM_ID 3
6 #define NIR_INTRINSIC_IDX_UCP_ID 4
7 #define NIR_INTRINSIC_IDX_RANGE 5
8 #define NIR_INTRINSIC_IDX_DESC_SET 6
9 #define NIR_INTRINSIC_IDX_BINDING 7
10 #define NIR_INTRINSIC_IDX_COMPONENT 8
11 #define NIR_INTRINSIC_IDX_INTERP_MODE 9
12 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10
13 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11
14 #define NIR_INTRINSIC_IDX_PARAM_IDX 12
15 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13
16 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14
17 #define NIR_INTRINSIC_IDX_FORMAT 15
18 #define NIR_INTRINSIC_IDX_ACCESS 16
19 #define NIR_INTRINSIC_IDX_DST_ACCESS 17
20 #define NIR_INTRINSIC_IDX_SRC_ACCESS 18
21 #define NIR_INTRINSIC_IDX_ALIGN_MUL 19
22 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 20
23 #define NIR_INTRINSIC_IDX_DESC_TYPE 21
24 #define NIR_INTRINSIC_IDX_TYPE 22
25 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 23
26 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 24
27 #define NIR_INTRINSIC_IDXS_N_MAX 25
28
29 #define NIR_INTRINSIC_FLAGS_CAN_ELIMINATE 0x01
30 #define NIR_INTRINSIC_FLAGS_CAN_REORDER 0x02
31
32 struct nir_intrinsic {
33 char *name;
34 u8 srcs_n;
35 s8 src_components_n[NIR_INTRINSIC_SRCS_N_MAX];
36 /*
37 * dest_components_n being 0 does not mean there is no dest components.
38 * in the old code, dest_components_n defaults to -1, hence if not
39 * explicitely set to 0 or above, this bool is false
40 */
41 bool has_dest;
42 u8 dest_components_n;
43 u8 idxs_n;
44 u32 idxs_map[NIR_INTRINSIC_IDXS_N_MAX];
45 u32 bit_szs; /* only valid szs are power of 2 bit szs */
46 u8 flags;
47 bool system_value;
48 };
49
50 1 struct nir_intrinsic nir_atomic_counter_add = { struct nir_intrinsic nir_atomic_counter_add = {
51 2 .name = "atomic_counter_add", .name = "atomic_counter_add",
52 3 .srcs_n = 2, .srcs_n = 2,
 
... ... struct nir_intrinsic nir_load_vulkan_descriptor = {
1075 1026 }, },
1076 1027 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1077 1028 }; };
1029 /*
1030 * Memory barrier with semantics analogous to the memoryBarrier() GLSL
1031 * intrinsic.
1032 */
1078 1033 struct nir_intrinsic nir_memory_barrier = { struct nir_intrinsic nir_memory_barrier = {
1079 1034 .name = "memory_barrier" .name = "memory_barrier"
1080 1035 }; };
1036 /*
1037 * Memory barrier with explicit scope. Follows the semantics of SPIR-V
1038 * OpMemoryBarrier, used to implement Vulkan Memory Model. Storage that the
1039 * barrierr applies is represented using NIR variable modes.
1040 */
1041 struct nir_intrinsic nir_scoped_memory_barrier = {
1042 .name = "scoped_memory_barrier",
1043 .idxs_n = 3,
1044 .idxs_map = {
1045 [NIR_INTRINSIC_IDX_MEMORY_SEMANTICS] = 1,
1046 [NIR_INTRINSIC_IDX_MEMORY_MODES] = 2,
1047 [NIR_INTRINSIC_IDX_MEMORY_SCOPE] = 3
1048 }
1049 };
1081 1050 struct nir_intrinsic nir_memory_barrier_atomic_counter = { struct nir_intrinsic nir_memory_barrier_atomic_counter = {
1082 1051 .name = "memory_barrier_atomic_counter" .name = "memory_barrier_atomic_counter"
1083 1052 }; };
 
... ... struct nir_intrinsic nir_deref_buffer_array_length = {
1670 1639 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1671 1640 }; };
1672 1641
1673 /*----------------------------------------------------------------------------*/
1674 /*
1675 * IR3-specific version of most SSBO intrinsics. The only different
1676 * compare to the originals is that they add an extra source to hold
1677 * the dword-offset, which is needed by the backend code apart from
1678 * the byte-offset already provided by NIR in one of the sources.
1679 *
1680 * NIR lowering pass 'ir3_nir_lower_io_offset' will replace the
1681 * original SSBO intrinsics by these, placing the computed
1682 * dword-offset always in the last source.
1683 *
1684 * The float versions are not handled because those are not supported
1685 * by the backend.
1686 */
1687 struct nir_intrinsic nir_store_ssbo_ir3 = {
1688 .name = "store_ssbo_ir3",
1689 .srcs_n = 4,
1690 .src_components_n = {
1691 0,1,1,1
1692 },
1693 .idxs_n = 4,
1694 .idxs_map = {
1695 [NIR_INTRINSIC_IDX_WRMASK] = 1,
1696 [NIR_INTRINSIC_IDX_ACCESS] = 2,
1697 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
1698 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
1699 }
1700 };
1701 struct nir_intrinsic nir_load_ssbo_ir3 = {
1702 .name = "load_ssbo_ir3",
1703 .srcs_n = 3,
1704 .src_components_n = {
1705 1,1,1
1706 },
1707 .has_dest = true,
1708 .idxs_n = 3,
1709 .idxs_map = {
1710 [NIR_INTRINSIC_IDX_ACCESS] = 1,
1711 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1712 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1713 },
1714 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1715 };
1716 struct nir_intrinsic nir_ssbo_atomic_add_ir3 = {
1717 .name = "ssbo_atomic_add_ir3",
1718 .srcs_n = 4,
1719 .src_components_n = {
1720 1,1,1,1
1721 },
1722 .has_dest = true,
1723 .dest_components_n = 1
1724 };
1725 struct nir_intrinsic nir_ssbo_atomic_imin_ir3 = {
1726 .name = "ssbo_atomic_imin_ir3",
1727 .srcs_n = 4,
1728 .src_components_n = {
1729 1,1,1,1
1730 },
1731 .has_dest = true,
1732 .dest_components_n = 1
1733 };
1734 struct nir_intrinsic nir_ssbo_atomic_umin_ir3 = {
1735 .name = "ssbo_atomic_umin_ir3",
1736 .srcs_n = 4,
1737 .src_components_n = {
1738 1,1,1,1
1739 },
1740 .has_dest = true,
1741 .dest_components_n = 1
1742 };
1743 struct nir_intrinsic nir_ssbo_atomic_imax_ir3 = {
1744 .name = "ssbo_atomic_imax_ir3",
1745 .srcs_n = 4,
1746 .src_components_n = {
1747 1,1,1,1
1748 },
1749 .has_dest = true,
1750 .dest_components_n = 1
1751 };
1752 struct nir_intrinsic nir_ssbo_atomic_umax_ir3 = {
1753 .name = "ssbo_atomic_umax_ir3",
1754 .srcs_n = 4,
1755 .src_components_n = {
1756 1,1,1,1
1757 },
1758 .has_dest = true,
1759 .dest_components_n = 1
1760 };
1761 struct nir_intrinsic nir_ssbo_atomic_and_ir3 = {
1762 .name = "ssbo_atomic_and_ir3",
1763 .srcs_n = 4,
1764 .src_components_n = {
1765 1,1,1,1
1766 },
1767 .has_dest = true,
1768 .dest_components_n = 1
1769 };
1770 struct nir_intrinsic nir_ssbo_atomic_or_ir3 = {
1771 .name = "ssbo_atomic_or_ir3",
1772 .srcs_n = 4,
1773 .src_components_n = {
1774 1,1,1,1
1775 },
1776 .has_dest = true,
1777 .dest_components_n = 1
1778 };
1779 struct nir_intrinsic nir_ssbo_atomic_xor_ir3 = {
1780 .name = "ssbo_atomic_xor_ir3",
1781 .srcs_n = 4,
1782 .src_components_n = {
1783 1,1,1,1
1784 },
1785 .has_dest = true,
1786 .dest_components_n = 1
1787 };
1788 struct nir_intrinsic nir_ssbo_atomic_exchange_ir3 = {
1789 .name = "ssbo_atomic_exchange_ir3",
1790 .srcs_n = 4,
1791 .src_components_n = {
1792 1,1,1,1
1793 },
1794 .has_dest = true,
1795 .dest_components_n = 1
1796 };
1797 struct nir_intrinsic nir_ssbo_atomic_swap_ir3 = {
1798 .name = "ssbo_atomic_swap_ir3",
1799 .srcs_n = 5,
1800 .src_components_n = {
1801 1,1,1,1,1
1802 },
1803 .has_dest = true,
1804 .dest_components_n = 1
1805 };
1806
1807 /******************************************************************************/
1808 /* AMD Shader ballot operations */
1809 struct nir_intrinsic nir_quad_swizzle_amd = {
1810 .name = "quad_swizzle_amd",
1811 .has_dest = true,
1812 .idxs_n = 1,
1813 .idxs_map = {
1814 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
1815 },
1816 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1817 };
1818 struct nir_intrinsic nir_masked_swizzle_amd = {
1819 .name = "masked_swizzle_amd",
1820 .has_dest = true,
1821 .idxs_n = 1,
1822 .idxs_map = {
1823 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
1824 },
1825 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1826 };
1827 struct nir_intrinsic nir_write_invocation_amd = {
1828 .name = "write_invocation_amd",
1829 .srcs_n = 3,
1830 .src_components_n = {
1831 0,0,1
1832 },
1833 .has_dest = true,
1834 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1835 };
1836 struct nir_intrinsic nir_mbcnt_amd = {
1837 .name = "mbcnt_amd",
1838 .srcs_n = 1,
1839 .src_components_n = {
1840 1
1841 },
1842 .has_dest = true,
1843 .dest_components_n = 1,
1844 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1845 };
1846 /* AMD Shader ballot operations */
1847 /******************************************************************************/
1848
1849 1642 /******************************************************************************/ /******************************************************************************/
1850 1643 /* /*
1851 1644 * Demote fragment shader invocation to a helper invocation. Any stores to * Demote fragment shader invocation to a helper invocation. Any stores to
 
... ... struct nir_intrinsic nir_load_raw_output_pan = {
1897 1690 }; };
1898 1691
1899 1692 /******************************************************************************/ /******************************************************************************/
1900 /*
1901 * V3D-specific instrinc for tile buffer color reads.
1902 *
1903 * The hardware requires that we read the samples and components of a pixel
1904 * in order, so we cannot eliminate or remove any loads in a sequence.
1905 *
1906 * src[] = { render_target }
1907 * BASE = sample index
1908 */
1909 struct nir_intrinsic nir_load_tlb_color_v3d = {
1910 .name = "load_tlb_color_v3d",
1911 .srcs_n = 1,
1912 .src_components_n = {
1913 1
1914 },
1915 .has_dest = true,
1916 .idxs_n = 2,
1917 .idxs_map = {
1918 [NIR_INTRINSIC_IDX_BASE] = 1,
1919 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
1920 }
1921 };
1922
1923 /*
1924 * V3D-specific instrinc for per-sample tile buffer color writes.
1925 *
1926 * The driver backend needs to identify per-sample color writes and emit
1927 * specific code for them.
1928 *
1929 * src[] = { value, render_target }
1930 * BASE = sample index
1931 */
1932 struct nir_intrinsic nir_store_tlb_sample_color_v3d = {
1933 .name = "store_tlb_sample_color_v3d",
1934 .srcs_n = 2,
1935 .src_components_n = {
1936 0,1
1937 },
1938 .idxs_n = 3,
1939 .idxs_map = {
1940 [NIR_INTRINSIC_IDX_BASE] = 1,
1941 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
1942 [NIR_INTRINSIC_IDX_TYPE] = 3
1943 }
1944 };
1945 /* v3d */
1946 /******************************************************************************/
1947
1948 #include "nir_database_intrinsic_system_values.c"
1949 #include "nir_database_intrinsic_image.c"
1950 #include "nir_database_intrinsic_store.c"
1951 #include "nir_database_intrinsic_load.c"
1952
1953 struct nir_intrinsic *nir_intrinsics[] = {
1954 &nir_atomic_counter_add,
1955 &nir_atomic_counter_add_deref,
1956 &nir_atomic_counter_and,
1957 &nir_atomic_counter_and_deref,
1958 &nir_atomic_counter_comp_swap,
1959 &nir_atomic_counter_comp_swap_deref,
1960 &nir_atomic_counter_exchange,
1961 &nir_atomic_counter_exchange_deref,
1962 &nir_atomic_counter_inc,
1963 &nir_atomic_counter_inc_deref,
1964 &nir_atomic_counter_max,
1965 &nir_atomic_counter_max_deref,
1966 &nir_atomic_counter_min,
1967 &nir_atomic_counter_min_deref,
1968 &nir_atomic_counter_or,
1969 &nir_atomic_counter_or_deref,
1970 &nir_atomic_counter_post_dec,
1971 &nir_atomic_counter_post_dec_deref,
1972 &nir_atomic_counter_pre_dec,
1973 &nir_atomic_counter_pre_dec_deref,
1974 &nir_atomic_counter_read,
1975 &nir_atomic_counter_read_deref,
1976 &nir_atomic_counter_xor,
1977 &nir_atomic_counter_xor_deref,
1978 &nir_ballot,
1979 &nir_ballot_bit_count_exclusive,
1980 &nir_ballot_bit_count_inclusive,
1981 &nir_ballot_bit_count_reduce,
1982 &nir_ballot_bitfield_extract,
1983 &nir_ballot_find_lsb,
1984 &nir_ballot_find_msb,
1985 &nir_barrier,
1986 &nir_begin_invocation_interlock,
1987 &nir_copy_deref,
1988 &nir_deref_atomic_add,
1989 &nir_deref_atomic_and,
1990 &nir_deref_atomic_comp_swap,
1991 &nir_deref_atomic_exchange,
1992 &nir_deref_atomic_fadd,
1993 &nir_deref_atomic_fcomp_swap,
1994 &nir_deref_atomic_fmax,
1995 &nir_deref_atomic_fmin,
1996 &nir_deref_atomic_imax,
1997 &nir_deref_atomic_imin,
1998 &nir_deref_atomic_or,
1999 &nir_deref_atomic_umax,
2000 &nir_deref_atomic_umin,
2001 &nir_deref_atomic_xor,
2002 &nir_discard,
2003 &nir_discard_if,
2004 &nir_elect,
2005 &nir_emit_vertex,
2006 &nir_emit_vertex_with_counter,
2007 &nir_end_invocation_interlock,
2008 &nir_end_primitive,
2009 &nir_end_primitive_with_counter,
2010 &nir_exclusive_scan,
2011 &nir_first_invocation,
2012 &nir_get_buffer_size,
2013 &nir_global_atomic_add,
2014 &nir_global_atomic_and,
2015 &nir_global_atomic_comp_swap,
2016 &nir_global_atomic_exchange,
2017 &nir_global_atomic_fadd,
2018 &nir_global_atomic_fcomp_swap,
2019 &nir_global_atomic_fmax,
2020 &nir_global_atomic_fmin,
2021 &nir_global_atomic_imax,
2022 &nir_global_atomic_imin,
2023 &nir_global_atomic_or,
2024 &nir_global_atomic_umax,
2025 &nir_global_atomic_umin,
2026 &nir_global_atomic_xor,
2027 &nir_group_memory_barrier,
2028 &nir_image_atomic_add,
2029 &nir_image_atomic_and,
2030 &nir_image_atomic_comp_swap,
2031 &nir_image_atomic_exchange,
2032 &nir_image_atomic_fadd,
2033 &nir_image_atomic_or,
2034 &nir_image_atomic_xor,
2035 &nir_image_deref_atomic_add,
2036 &nir_image_deref_atomic_and,
2037 &nir_image_deref_atomic_comp_swap,
2038 &nir_image_deref_atomic_exchange,
2039 &nir_image_deref_atomic_fadd,
2040 &nir_image_deref_atomic_or,
2041 &nir_image_deref_atomic_xor,
2042 &nir_image_deref_load,
2043 &nir_image_deref_load_param_intel,
2044 &nir_image_deref_load_raw_intel,
2045 &nir_image_deref_samples,
2046 &nir_image_deref_size,
2047 &nir_image_deref_store,
2048 &nir_image_deref_store_raw_intel,
2049 &nir_image_load,
2050 &nir_image_load_raw_intel,
2051 &nir_image_samples,
2052 &nir_image_size,
2053 &nir_image_store,
2054 &nir_image_store_raw_intel,
2055 &nir_inclusive_scan,
2056 &nir_interp_deref_at_centroid,
2057 &nir_interp_deref_at_offset,
2058 &nir_interp_deref_at_sample,
2059 &nir_load_barycentric_at_offset,
2060 &nir_load_barycentric_at_sample,
2061 &nir_load_barycentric_centroid,
2062 &nir_load_barycentric_pixel,
2063 &nir_load_barycentric_sample,
2064 &nir_load_base_instance,
2065 &nir_load_base_vertex,
2066 &nir_load_blend_const_color_a_float,
2067 &nir_load_blend_const_color_aaaa8888_unorm,
2068 &nir_load_blend_const_color_b_float,
2069 &nir_load_blend_const_color_g_float,
2070 &nir_load_blend_const_color_r_float,
2071 &nir_load_blend_const_color_rgba8888_unorm,
2072 &nir_load_constant,
2073 &nir_load_deref,
2074 &nir_load_draw_id,
2075 &nir_load_first_vertex,
2076 &nir_load_frag_coord,
2077 &nir_load_front_face,
2078 &nir_load_global,
2079 &nir_load_global_invocation_id,
2080 &nir_load_global_invocation_index,
2081 &nir_load_helper_invocation,
2082 &nir_load_input,
2083 &nir_load_instance_id,
2084 &nir_load_interpolated_input,
2085 &nir_load_invocation_id,
2086 &nir_load_is_indexed_draw,
2087 &nir_load_layer_id,
2088 &nir_load_local_group_size,
2089 &nir_load_local_invocation_id,
2090 &nir_load_local_invocation_index,
2091 &nir_load_num_subgroups,
2092 &nir_load_num_work_groups,
2093 &nir_load_output,
2094 &nir_load_param,
2095 &nir_load_patch_vertices_in,
2096 &nir_load_per_vertex_input,
2097 &nir_load_per_vertex_output,
2098 &nir_load_primitive_id,
2099 &nir_load_push_constant,
2100 &nir_load_sample_id,
2101 &nir_load_sample_id_no_per_sample,
2102 &nir_load_sample_mask_in,
2103 &nir_load_sample_pos,
2104 &nir_load_shared,
2105 &nir_load_ssbo,
2106 &nir_load_subgroup_eq_mask,
2107 &nir_load_subgroup_ge_mask,
2108 &nir_load_subgroup_gt_mask,
2109 &nir_load_subgroup_id,
2110 &nir_load_subgroup_invocation,
2111 &nir_load_subgroup_le_mask,
2112 &nir_load_subgroup_lt_mask,
2113 &nir_load_subgroup_size,
2114 &nir_load_tess_coord,
2115 &nir_load_tess_level_inner,
2116 &nir_load_tess_level_outer,
2117 &nir_load_ubo,
2118 &nir_load_uniform,
2119 &nir_load_user_clip_plane,
2120 &nir_load_vertex_id,
2121 &nir_load_vertex_id_zero_base,
2122 &nir_load_view_index,
2123 &nir_load_vulkan_descriptor,
2124 &nir_load_work_dim,
2125 &nir_load_work_group_id,
2126 &nir_memory_barrier,
2127 &nir_memory_barrier_atomic_counter,
2128 &nir_memory_barrier_buffer,
2129 &nir_memory_barrier_image,
2130 &nir_memory_barrier_shared,
2131 &nir_nop,
2132 &nir_quad_broadcast,
2133 &nir_quad_swap_diagonal,
2134 &nir_quad_swap_horizontal,
2135 &nir_quad_swap_vertical,
2136 &nir_read_first_invocation,
2137 &nir_read_invocation,
2138 &nir_reduce,
2139 &nir_set_vertex_count,
2140 &nir_shader_clock,
2141 &nir_shared_atomic_add,
2142 &nir_shared_atomic_and,
2143 &nir_shared_atomic_comp_swap,
2144 &nir_shared_atomic_exchange,
2145 &nir_shared_atomic_fadd,
2146 &nir_shared_atomic_fcomp_swap,
2147 &nir_shared_atomic_fmax,
2148 &nir_shared_atomic_fmin,
2149 &nir_shared_atomic_imax,
2150 &nir_shared_atomic_imin,
2151 &nir_shared_atomic_or,
2152 &nir_shared_atomic_umax,
2153 &nir_shared_atomic_umin,
2154 &nir_shared_atomic_xor,
2155 &nir_shuffle,
2156 &nir_shuffle_down,
2157 &nir_shuffle_up,
2158 &nir_shuffle_xor,
2159 &nir_ssbo_atomic_add,
2160 &nir_ssbo_atomic_and,
2161 &nir_ssbo_atomic_comp_swap,
2162 &nir_ssbo_atomic_exchange,
2163 &nir_ssbo_atomic_fadd,
2164 &nir_ssbo_atomic_fcomp_swap,
2165 &nir_ssbo_atomic_fmax,
2166 &nir_ssbo_atomic_fmin,
2167 &nir_ssbo_atomic_imax,
2168 &nir_ssbo_atomic_imin,
2169 &nir_ssbo_atomic_or,
2170 &nir_ssbo_atomic_umax,
2171 &nir_ssbo_atomic_umin,
2172 &nir_ssbo_atomic_xor,
2173 &nir_store_deref,
2174 &nir_store_global,
2175 &nir_store_output,
2176 &nir_store_per_vertex_output,
2177 &nir_store_shared,
2178 &nir_store_ssbo,
2179 &nir_vote_all,
2180 &nir_vote_any,
2181 &nir_vote_feq,
2182 &nir_vote_ieq,
2183 &nir_vulkan_resource_index,
2184 &nir_vulkan_resource_reindex,
2185 /* git db944999a1bad94471966862cc38212019165937..58376c6b9be80c2cb74c7638d961d5af64f7143f */
2186 &nir_deref_buffer_array_length,
2187 &nir_store_ssbo_ir3,
2188 &nir_load_ssbo_ir3,
2189 &nir_ssbo_atomic_add_ir3,
2190 &nir_ssbo_atomic_imin_ir3,
2191 &nir_ssbo_atomic_umin_ir3,
2192 &nir_ssbo_atomic_imax_ir3,
2193 &nir_ssbo_atomic_umax_ir3,
2194 &nir_ssbo_atomic_and_ir3,
2195 &nir_ssbo_atomic_or_ir3,
2196 &nir_ssbo_atomic_xor_ir3,
2197 &nir_ssbo_atomic_exchange_ir3,
2198 &nir_ssbo_atomic_swap_ir3,
2199 /* git 58376c6b9be80c2cb74c7638d961d5af64f7143f..15012077bceda24cbf38afeda7723c47e1b0d3c3 */
2200 &nir_load_kernel_input,
2201 /* git 15012077bceda24cbf38afeda7723c47e1b0d3c3..e4e6a3deaff4f84f0fb99b4dec950dc498d507ed */
2202 &nir_bindless_image_load,
2203 &nir_bindless_image_store,
2204 &nir_bindless_image_atomic_add,
2205 &nir_bindless_image_atomic_and,
2206 &nir_bindless_image_atomic_or,
2207 &nir_bindless_image_atomic_xor,
2208 &nir_bindless_image_atomic_exchange,
2209 &nir_bindless_image_atomic_comp_swap,
2210 &nir_bindless_image_atomic_fadd,
2211 &nir_bindless_image_size,
2212 &nir_bindless_image_samples,
2213 &nir_bindless_image_load_raw_intel,
2214 &nir_bindless_image_store_raw_intel,
2215 /* git e4e6a3deaff4f84f0fb99b4dec950dc498d507ed..10a2fdacfa3f96a57fec304cf54d1c298e4f0943 */
2216 &nir_load_viewport_x_scale,
2217 &nir_load_viewport_y_scale,
2218 &nir_load_viewport_z_scale,
2219 &nir_load_viewport_z_offset,
2220 &nir_load_viewport_scale,
2221 &nir_load_viewport_offset,
2222 /* git 10a2fdacfa3f96a57fec304cf54d1c298e4f0943..1af7701666bea2d6f4d0d226f5efc2fa65103872 */
2223 &nir_load_scratch,
2224 &nir_store_scratch,
2225 /* git a6ccc4c0c893cfd978068f1d75ad0e001182b381..07745f94948874c875dac924e055a11ee96beb5b */
2226 &nir_load_sample_pos_from_id,
2227 &nir_load_size_ir3,
2228 /* git 07745f94948874c875dac924e055a11ee96beb5b..974c4d679c23373dbed386c696e3e3bc1bfa23ae */
2229 &nir_load_blend_const_color_rgb,
2230 /* git e9703fb4162e85943c52b6559d3554b521125da4..1a7caac9e96f5ef5600edcaf982c5e113c3e62fd */
2231 &nir_quad_swizzle_amd,
2232 &nir_masked_swizzle_amd,
2233 &nir_write_invocation_amd,
2234 &nir_mbcnt_amd,
2235 /* git 8d74749f812e64968d37266061293e204fea252c..9b116173b6a5e96c54ef3962546aabd505e00cfb */
2236 &nir_load_color0,
2237 &nir_load_color1,
2238 &nir_load_fs_input_interp_deltas,
2239 /* git 9b116173b6a5e96c54ef3962546aabd505e00cfb..7a19e05e8c84152af3a15868f5ef781142ac8e23 */
2240 &nir_demote,
2241 &nir_is_helper_invocation,
2242 &nir_store_raw_output_pan,
2243 &nir_load_raw_output_pan,
2244 &nir_load_tlb_color_v3d,
2245 /* git 7a19e05e8c84152af3a15868f5ef781142ac8e23..f7224014df0d366453739356b9968ca94ad43979 */
2246 &nir_load_point_coord,
2247 &nir_store_tlb_sample_color_v3d,
2248 /* git f7224014df0d366453739356b9968ca94ad43979..de17922b8a3c382cf89833cf8975cadc00142313 */
2249 &nir_demote_if,
2250 /* git 486b33558a5d5fe18fb87e98f75c34ef992428af..5ed4e31c08dc079473dd2e459c973355d49cd529 */
2251 &nir_image_deref_atomic_inc_wrap,
2252 &nir_image_atomic_inc_wrap,
2253 &nir_bindless_image_atomic_inc_wrap,
2254 &nir_image_deref_atomic_dec_wrap,
2255 &nir_image_atomic_dec_wrap,
2256 &nir_bindless_image_atomic_dec_wrap,
2257 /* git 5ed4e31c08dc079473dd2e459c973355d49cd529..c550d367a747472ee71ed4c99e210174730aa82b */
2258 &nir_load_user_data_amd,
2259 &nir_load_tess_level_outer_default,
2260 &nir_load_tess_level_inner_default,
2261 /* git c550d367a747472ee71ed4c99e210174730aa82b..f58e0405b6ca15d9b82122d82311e8b82f4a0939 */
2262 &nir_image_deref_atomic_imin,
2263 &nir_image_deref_atomic_imax,
2264 &nir_image_deref_atomic_umin,
2265 &nir_image_deref_atomic_umax,
2266 &nir_image_atomic_imin,
2267 &nir_image_atomic_imax,
2268 &nir_image_atomic_umin,
2269 &nir_image_atomic_umax,
2270 &nir_bindless_image_atomic_imin,
2271 &nir_bindless_image_atomic_imax,
2272 &nir_bindless_image_atomic_umin,
2273 &nir_bindless_image_atomic_umax,
2274 /* git 35e92a11ddb1450571afc2d66286b97098d486a1..4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc */
2275 &nir_load_vs_primitive_stride_ir3,
2276 &nir_load_vs_vertex_stride_ir3,
2277 &nir_load_gs_header_ir3,
2278 &nir_load_primitive_location_ir3,
2279 &nir_store_shared_ir3,
2280 &nir_load_shared_ir3
2281 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/image.c renamed from builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_image.c (similarity 98%) (mode: 100644) (index 8981bb2..a91852e)
... ... struct nir_intrinsic nir_bindless_image_atomic_dec_wrap = {
874 874 }; };
875 875 /* bindless version */ /* bindless version */
876 876 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
877 /* the following is solo */
878 struct nir_intrinsic nir_image_deref_load_param_intel = {
879 .name = "image_deref_load_param_intel",
880 .srcs_n = 1,
881 .src_components_n = {
882 1
883 },
884 .has_dest = true,
885 .dest_components_n = 0,
886 .idxs_n = 1,
887 .idxs_map = {
888 [NIR_INTRINSIC_IDX_BASE] = 1
889 },
890 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
891 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/load.c renamed from builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_load.c (similarity 91%) (mode: 100644) (index 80d4222..ae633c9)
... ... struct nir_intrinsic nir_load_scratch = {
237 237 }, },
238 238 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
239 239 }; };
240 /*---------------------------------------------------------------------------*/
241 /*
242 * IR3-specific load/store intrinsics. These access a buffer used to pass data
243 * between geometry stages - perhaps it's explicit access to the vertex cache.
244 */
245 struct nir_intrinsic nir_load_shared_ir3 = {
246 .name = "load_shared_ir3",
247 .srcs_n = 1,
248 .src_components_n = {
249 1
250 },
251 .has_dest = true,
252 .idxs_n = 3,
253 .idxs_map = {
254 [NIR_INTRINSIC_IDX_BASE] = 1,
255 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
256 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
257 },
258 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
259 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/store.c renamed from builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_store.c (similarity 76%) (mode: 100644) (index b32ef0e..edb45e6)
... ... struct nir_intrinsic nir_store_scratch = {
92 92 [NIR_INTRINSIC_IDX_WRMASK] = 3 [NIR_INTRINSIC_IDX_WRMASK] = 3
93 93 } }
94 94 }; };
95 /*---------------------------------------------------------------------------*/
96 /*
97 * IR3-specific load/store intrinsics. These access a buffer used to pass data
98 * between geometry stages - perhaps it's explicit access to the vertex cache.
99 */
100 /* src[] = { value, offset }. */
101 struct nir_intrinsic nir_store_shared_ir3 = {
102 .name = "store_shared_ir3",
103 .srcs_n = 2,
104 .src_components_n = {
105 0,1
106 },
107 .idxs_n = 4,
108 .idxs_map = {
109 [NIR_INTRINSIC_IDX_BASE] = 1,
110 [NIR_INTRINSIC_IDX_WRMASK] = 2,
111 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
112 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
113 }
114 };
115 /*---------------------------------------------------------------------------*/
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/system_values.c renamed from builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_system_values.c (similarity 91%) (mode: 100644) (index 0376800..bb96237)
... ... static struct nir_intrinsic nir_load_color1 = {
509 509 .system_value = true .system_value = true
510 510 }; };
511 511 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
512 /* System value for internal compute shaders in radeonsi. */
513 static struct nir_intrinsic nir_load_user_data_amd = {
514 .name = "load_user_data_amd",
515 .has_dest = true,
516 .dest_components_n = 4,
517 .bit_szs = 0x20,
518 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
519 .system_value = true
520 };
521 /*----------------------------------------------------------------------------*/
522 /* System values for freedreno geometry shaders. */
523 static struct nir_intrinsic nir_load_vs_primitive_stride_ir3 = {
524 .name = "load_vs_primitive_stride_ir3",
525 .has_dest = true,
526 .dest_components_n = 1,
527 .bit_szs = 0x20,
528 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
529 .system_value = true
530 };
531 static struct nir_intrinsic nir_load_vs_vertex_stride_ir3 = {
532 .name = "load_vs_vertex_stride_ir3",
533 .has_dest = true,
534 .dest_components_n = 1,
535 .bit_szs = 0x20,
536 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
537 .system_value = true
538 };
539 static struct nir_intrinsic nir_load_gs_header_ir3 = {
540 .name = "load_gs_header_ir3",
541 .has_dest = true,
542 .dest_components_n = 1,
543 .bit_szs = 0x20,
544 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
545 .system_value = true
546 };
547 static struct nir_intrinsic nir_load_primitive_location_ir3 = {
548 .name = "load_primitive_location_ir3",
549 .has_dest = true,
550 .dest_components_n = 1,
551 .idxs_n = 1,
552 .idxs_map = {
553 [NIR_INTRINSIC_IDX_DRIVER_LOCATION] = 1,
554 },
555 .bit_szs = 0x20,
556 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
557 .system_value = true
558 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/intel/image.c added (mode: 100644) (index 0000000..47a4232)
1 struct nir_intrinsic nir_image_deref_load_param_intel = {
2 .name = "image_deref_load_param_intel",
3 .srcs_n = 1,
4 .src_components_n = {
5 1
6 },
7 .has_dest = true,
8 .dest_components_n = 0,
9 .idxs_n = 1,
10 .idxs_map = {
11 [NIR_INTRINSIC_IDX_BASE] = 1
12 },
13 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
14 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/ir3.c added (mode: 100644) (index 0000000..db2e01d)
1 /*
2 * IR3-specific version of most SSBO intrinsics. The only different
3 * compare to the originals is that they add an extra source to hold
4 * the dword-offset, which is needed by the backend code apart from
5 * the byte-offset already provided by NIR in one of the sources.
6 *
7 * NIR lowering pass 'ir3_nir_lower_io_offset' will replace the
8 * original SSBO intrinsics by these, placing the computed
9 * dword-offset always in the last source.
10 *
11 * The float versions are not handled because those are not supported
12 * by the backend.
13 */
14 struct nir_intrinsic nir_store_ssbo_ir3 = {
15 .name = "store_ssbo_ir3",
16 .srcs_n = 4,
17 .src_components_n = {
18 0,1,1,1
19 },
20 .idxs_n = 4,
21 .idxs_map = {
22 [NIR_INTRINSIC_IDX_WRMASK] = 1,
23 [NIR_INTRINSIC_IDX_ACCESS] = 2,
24 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
25 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
26 }
27 };
28 struct nir_intrinsic nir_load_ssbo_ir3 = {
29 .name = "load_ssbo_ir3",
30 .srcs_n = 3,
31 .src_components_n = {
32 1,1,1
33 },
34 .has_dest = true,
35 .idxs_n = 3,
36 .idxs_map = {
37 [NIR_INTRINSIC_IDX_ACCESS] = 1,
38 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
39 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
40 },
41 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
42 };
43 struct nir_intrinsic nir_ssbo_atomic_add_ir3 = {
44 .name = "ssbo_atomic_add_ir3",
45 .srcs_n = 4,
46 .src_components_n = {
47 1,1,1,1
48 },
49 .has_dest = true,
50 .dest_components_n = 1
51 };
52 struct nir_intrinsic nir_ssbo_atomic_imin_ir3 = {
53 .name = "ssbo_atomic_imin_ir3",
54 .srcs_n = 4,
55 .src_components_n = {
56 1,1,1,1
57 },
58 .has_dest = true,
59 .dest_components_n = 1
60 };
61 struct nir_intrinsic nir_ssbo_atomic_umin_ir3 = {
62 .name = "ssbo_atomic_umin_ir3",
63 .srcs_n = 4,
64 .src_components_n = {
65 1,1,1,1
66 },
67 .has_dest = true,
68 .dest_components_n = 1
69 };
70 struct nir_intrinsic nir_ssbo_atomic_imax_ir3 = {
71 .name = "ssbo_atomic_imax_ir3",
72 .srcs_n = 4,
73 .src_components_n = {
74 1,1,1,1
75 },
76 .has_dest = true,
77 .dest_components_n = 1
78 };
79 struct nir_intrinsic nir_ssbo_atomic_umax_ir3 = {
80 .name = "ssbo_atomic_umax_ir3",
81 .srcs_n = 4,
82 .src_components_n = {
83 1,1,1,1
84 },
85 .has_dest = true,
86 .dest_components_n = 1
87 };
88 struct nir_intrinsic nir_ssbo_atomic_and_ir3 = {
89 .name = "ssbo_atomic_and_ir3",
90 .srcs_n = 4,
91 .src_components_n = {
92 1,1,1,1
93 },
94 .has_dest = true,
95 .dest_components_n = 1
96 };
97 struct nir_intrinsic nir_ssbo_atomic_or_ir3 = {
98 .name = "ssbo_atomic_or_ir3",
99 .srcs_n = 4,
100 .src_components_n = {
101 1,1,1,1
102 },
103 .has_dest = true,
104 .dest_components_n = 1
105 };
106 struct nir_intrinsic nir_ssbo_atomic_xor_ir3 = {
107 .name = "ssbo_atomic_xor_ir3",
108 .srcs_n = 4,
109 .src_components_n = {
110 1,1,1,1
111 },
112 .has_dest = true,
113 .dest_components_n = 1
114 };
115 struct nir_intrinsic nir_ssbo_atomic_exchange_ir3 = {
116 .name = "ssbo_atomic_exchange_ir3",
117 .srcs_n = 4,
118 .src_components_n = {
119 1,1,1,1
120 },
121 .has_dest = true,
122 .dest_components_n = 1
123 };
124 struct nir_intrinsic nir_ssbo_atomic_swap_ir3 = {
125 .name = "ssbo_atomic_swap_ir3",
126 .srcs_n = 5,
127 .src_components_n = {
128 1,1,1,1,1
129 },
130 .has_dest = true,
131 .dest_components_n = 1
132 };
133 /* ir3 ssbo */
134 /*----------------------------------------------------------------------------*/
135 /*
136 * IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end
137 * the shader when src0 is false and is used to narrow down the TCS shader to
138 * just thread 0 before writing out tessellation levels.
139 */
140 struct nir_intrinsic nir_cond_end_ir3 = {
141 .name = "cond_end_ir3",
142 .srcs_n = 1,
143 .src_components_n = {
144 1
145 }
146 };
147 /*
148 * end_patch_ir3 is used just before thread 0 exist the TCS and presumably
149 * signals the TE that the patch is complete and can be tessellated.
150 */
151 struct nir_intrinsic nir_end_patch_ir3 = {
152 .name = "end_patch_ir3"
153 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/load.c added (mode: 100644) (index 0000000..9372618)
1 /*
2 * IR3-specific load/store intrinsics. These access a buffer used to pass data
3 * between geometry stages - perhaps it's explicit access to the vertex cache.
4 */
5 struct nir_intrinsic nir_load_shared_ir3 = {
6 .name = "load_shared_ir3",
7 .srcs_n = 1,
8 .src_components_n = {
9 1
10 },
11 .has_dest = true,
12 .idxs_n = 3,
13 .idxs_map = {
14 [NIR_INTRINSIC_IDX_BASE] = 1,
15 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
16 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
17 },
18 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
19 };
20 /*---------------------------------------------------------------------------*/
21 /*
22 * IR3-specific load/store global intrinsics. They take a 64-bit base address
23 * and a 32-bit offset. The hardware will add the base and the offset, which
24 * saves us from doing 64-bit math on the base address.
25 */
26 /*
27 * src[] = { address(vec2 of hi+lo uint32_t), offset }.
28 * const_index[] = { access, align_mul, align_offset }
29 */
30 struct nir_intrinsic nir_load_global_ir3 = {
31 .name = "load_global_ir3",
32 .srcs_n = 2,
33 .src_components_n = {
34 2, 1
35 },
36 .has_dest = true,
37 .idxs_n = 3,
38 .idxs_map = {
39 [NIR_INTRINSIC_IDX_ACCESS] = 1,
40 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
41 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
42 },
43 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
44 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/store.c added (mode: 100644) (index 0000000..2ce032f)
1 /*
2 * IR3-specific load/store intrinsics. These access a buffer used to pass data
3 * between geometry stages - perhaps it's explicit access to the vertex cache.
4 */
5 /* src[] = { value, offset }. */
6 struct nir_intrinsic nir_store_shared_ir3 = {
7 .name = "store_shared_ir3",
8 .srcs_n = 2,
9 .src_components_n = {
10 0,1
11 },
12 .idxs_n = 4,
13 .idxs_map = {
14 [NIR_INTRINSIC_IDX_BASE] = 1,
15 [NIR_INTRINSIC_IDX_WRMASK] = 2,
16 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
17 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
18 }
19 };
20 /*---------------------------------------------------------------------------*/
21 /*
22 * IR3-specific load/store global intrinsics. They take a 64-bit base address
23 * and a 32-bit offset. The hardware will add the base and the offset, which
24 * saves us from doing 64-bit math on the base address.
25 */
26 /*
27 * src[] = { value, address(vec2 of hi+lo uint32_t), offset }.
28 * const_index[] = { write_mask, align_mul, align_offset }
29 */
30 struct nir_intrinsic nir_store_global_ir3 = {
31 .name = "store_global_ir3",
32 .srcs_n = 3,
33 .src_components_n = {
34 0,2,1
35 },
36 .idxs_n = 4,
37 .idxs_map = {
38 [NIR_INTRINSIC_IDX_WRMASK] = 1,
39 [NIR_INTRINSIC_IDX_ACCESS] = 2,
40 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
41 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
42 }
43 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/ir3/system_values.c added (mode: 100644) (index 0000000..8982bf2)
1 /* System values for freedreno geometry shaders. */
2 static struct nir_intrinsic nir_load_vs_primitive_stride_ir3 = {
3 .name = "load_vs_primitive_stride_ir3",
4 .has_dest = true,
5 .dest_components_n = 1,
6 .bit_szs = 0x20,
7 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
8 .system_value = true
9 };
10 static struct nir_intrinsic nir_load_vs_vertex_stride_ir3 = {
11 .name = "load_vs_vertex_stride_ir3",
12 .has_dest = true,
13 .dest_components_n = 1,
14 .bit_szs = 0x20,
15 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
16 .system_value = true
17 };
18 static struct nir_intrinsic nir_load_gs_header_ir3 = {
19 .name = "load_gs_header_ir3",
20 .has_dest = true,
21 .dest_components_n = 1,
22 .bit_szs = 0x20,
23 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
24 .system_value = true
25 };
26 static struct nir_intrinsic nir_load_primitive_location_ir3 = {
27 .name = "load_primitive_location_ir3",
28 .has_dest = true,
29 .dest_components_n = 1,
30 .idxs_n = 1,
31 .idxs_map = {
32 [NIR_INTRINSIC_IDX_DRIVER_LOCATION] = 1,
33 },
34 .bit_szs = 0x20,
35 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
36 .system_value = true
37 };
38 /*----------------------------------------------------------------------------*/
39 /* System values for freedreno tessellation shaders. */
40 static struct nir_intrinsic nir_load_hs_patch_stride_ir3 = {
41 .name = "load_patch_stride_ir3",
42 .has_dest = true,
43 .dest_components_n = 1,
44 .bit_szs = 0x20,
45 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
46 .system_value = true
47 };
48 static struct nir_intrinsic nir_load_tess_factor_base_ir3 = {
49 .name = "load_load_tess_factor_base_ir3",
50 .has_dest = true,
51 .dest_components_n = 2,
52 .bit_szs = 0x20,
53 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
54 .system_value = true
55 };
56 static struct nir_intrinsic nir_load_tess_param_base_ir3 = {
57 .name = "load_load_tess_param_base_ir3",
58 .has_dest = true,
59 .dest_components_n = 2,
60 .bit_szs = 0x20,
61 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
62 .system_value = true
63 };
64 static struct nir_intrinsic nir_load_tcs_header_ir3 = {
65 .name = "load_load_tcs_header_ir3",
66 .has_dest = true,
67 .dest_components_n = 1,
68 .bit_szs = 0x20,
69 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
70 .system_value = true
71 };
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/v3d/v3d.c added (mode: 100644) (index 0000000..8d6d494)
1 /*
2 * V3D-specific instrinc for tile buffer color reads.
3 *
4 * The hardware requires that we read the samples and components of a pixel
5 * in order, so we cannot eliminate or remove any loads in a sequence.
6 *
7 * src[] = { render_target }
8 * BASE = sample index
9 */
10 struct nir_intrinsic nir_load_tlb_color_v3d = {
11 .name = "load_tlb_color_v3d",
12 .srcs_n = 1,
13 .src_components_n = {
14 1
15 },
16 .has_dest = true,
17 .idxs_n = 2,
18 .idxs_map = {
19 [NIR_INTRINSIC_IDX_BASE] = 1,
20 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
21 }
22 };
23
24 /*
25 * V3D-specific instrinc for per-sample tile buffer color writes.
26 *
27 * The driver backend needs to identify per-sample color writes and emit
28 * specific code for them.
29 *
30 * src[] = { value, render_target }
31 * BASE = sample index
32 */
33 struct nir_intrinsic nir_store_tlb_sample_color_v3d = {
34 .name = "store_tlb_sample_color_v3d",
35 .srcs_n = 2,
36 .src_components_n = {
37 0,1
38 },
39 .idxs_n = 3,
40 .idxs_map = {
41 [NIR_INTRINSIC_IDX_BASE] = 1,
42 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
43 [NIR_INTRINSIC_IDX_TYPE] = 3
44 }
45 };
File builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index ffb671d..29dd739)
... ... struct nir_intrinsic {
84 84 bool system_value; bool system_value;
85 85 }; };
86 86
87 struct nir_intrinsic nir_atomic_counter_add = {
88 .name = "atomic_counter_add",
89 .srcs_n = 2,
90 .src_components_n = {
91 1,1
92 },
93 .has_dest = true,
94 .dest_components_n = 1,
95 .idxs_n = 1,
96 .idxs_map = {
97 [NIR_INTRINSIC_IDX_BASE] = 1
98 }
99 };
100 struct nir_intrinsic nir_atomic_counter_add_deref = {
101 .name = "atomic_counter_add_deref",
102 .srcs_n = 2,
103 .src_components_n = {
104 -1,1
105 },
106 .has_dest = true,
107 .dest_components_n = 1
108 };
109 struct nir_intrinsic nir_atomic_counter_and = {
110 .name = "atomic_counter_and",
111 .srcs_n = 2,
112 .src_components_n = {
113 1,1
114 },
115 .has_dest = true,
116 .dest_components_n = 1,
117 .idxs_n = 1,
118 .idxs_map = {
119 [NIR_INTRINSIC_IDX_BASE] = 1
120 }
121 };
122 struct nir_intrinsic nir_atomic_counter_and_deref = {
123 .name = "atomic_counter_and_deref",
124 .srcs_n = 2,
125 .src_components_n = {
126 -1,1
127 },
128 .has_dest = true,
129 .dest_components_n = 1
130 };
131 struct nir_intrinsic nir_atomic_counter_comp_swap = {
132 .name = "atomic_counter_comp_swap",
133 .srcs_n = 3,
134 .src_components_n = {
135 1,1,1
136 },
137 .has_dest = true,
138 .dest_components_n = 1,
139 .idxs_n = 1,
140 .idxs_map = {
141 [NIR_INTRINSIC_IDX_BASE] = 1
142 }
143 };
144 struct nir_intrinsic nir_atomic_counter_comp_swap_deref = {
145 .name = "atomic_counter_comp_swap_deref",
146 .srcs_n = 3,
147 .src_components_n = {
148 -1,1,1
149 },
150 .has_dest = true,
151 .dest_components_n = 1
152 };
153 struct nir_intrinsic nir_atomic_counter_exchange = {
154 .name = "atomic_counter_exchange",
155 .srcs_n = 2,
156 .src_components_n = {
157 1,1
158 },
159 .has_dest = true,
160 .dest_components_n = 1,
161 .idxs_n = 1,
162 .idxs_map = {
163 [NIR_INTRINSIC_IDX_BASE] = 1
164 }
165 };
166 struct nir_intrinsic nir_atomic_counter_exchange_deref = {
167 .name = "atomic_counter_exchange_deref",
168 .srcs_n = 2,
169 .src_components_n = {
170 -1,1
171 },
172 .has_dest = true,
173 .dest_components_n = 1
174 };
175 struct nir_intrinsic nir_atomic_counter_inc = {
176 .name = "atomic_counter_inc",
177 .srcs_n = 1,
178 .src_components_n = {
179 1
180 },
181 .has_dest = true,
182 .dest_components_n = 1,
183 .idxs_n = 1,
184 .idxs_map = {
185 [NIR_INTRINSIC_IDX_BASE] = 1
186 }
187 };
188 struct nir_intrinsic nir_atomic_counter_inc_deref = {
189 .name = "atomic_counter_inc_deref",
190 .srcs_n = 1,
191 .src_components_n = {
192 -1
193 },
194 .has_dest = true,
195 .dest_components_n = 1
196 };
197 struct nir_intrinsic nir_atomic_counter_max = {
198 .name = "atomic_counter_max",
199 .srcs_n = 2,
200 .src_components_n = {
201 1,1
202 },
203 .has_dest = true,
204 .dest_components_n = 1,
205 .idxs_n = 1,
206 .idxs_map = {
207 [NIR_INTRINSIC_IDX_BASE] = 1
208 }
209 };
210 struct nir_intrinsic nir_atomic_counter_max_deref = {
211 .name = "atomic_counter_max_deref",
212 .srcs_n = 2,
213 .src_components_n = {
214 -1,1
215 },
216 .has_dest = true,
217 .dest_components_n = 1
218 };
219 struct nir_intrinsic nir_atomic_counter_min = {
220 .name = "atomic_counter_min",
221 .srcs_n = 2,
222 .src_components_n = {
223 1,1
224 },
225 .has_dest = true,
226 .dest_components_n = 1,
227 .idxs_n = 1,
228 .idxs_map = {
229 [NIR_INTRINSIC_IDX_BASE] = 1
230 }
231 };
232 struct nir_intrinsic nir_atomic_counter_min_deref = {
233 .name = "atomic_counter_min_deref",
234 .srcs_n = 2,
235 .src_components_n = {
236 -1,1
237 },
238 .has_dest = true,
239 .dest_components_n = 1
240 };
241 struct nir_intrinsic nir_atomic_counter_or = {
242 .name = "atomic_counter_or",
243 .srcs_n = 2,
244 .src_components_n = {
245 1,1
246 },
247 .has_dest = true,
248 .dest_components_n = 1,
249 .idxs_n = 1,
250 .idxs_map = {
251 [NIR_INTRINSIC_IDX_BASE] = 1
252 }
253 };
254 struct nir_intrinsic nir_atomic_counter_or_deref = {
255 .name = "atomic_counter_or_deref",
256 .srcs_n = 2,
257 .src_components_n = {
258 -1,1
259 },
260 .has_dest = true,
261 .dest_components_n = 1
262 };
263 struct nir_intrinsic nir_atomic_counter_post_dec = {
264 .name = "atomic_counter_post_dec",
265 .srcs_n = 1,
266 .src_components_n = {
267 1
268 },
269 .has_dest = true,
270 .dest_components_n = 1,
271 .idxs_n = 1,
272 .idxs_map = {
273 [NIR_INTRINSIC_IDX_BASE] = 1
274 }
275 };
276 struct nir_intrinsic nir_atomic_counter_post_dec_deref = {
277 .name = "atomic_counter_post_dec_deref",
278 .srcs_n = 1,
279 .src_components_n = {
280 -1
281 },
282 .has_dest = true,
283 .dest_components_n = 1
284 };
285 struct nir_intrinsic nir_atomic_counter_pre_dec = {
286 .name = "atomic_counter_pre_dec",
287 .srcs_n = 1,
288 .src_components_n = {
289 1
290 },
291 .has_dest = true,
292 .dest_components_n = 1,
293 .idxs_n = 1,
294 .idxs_map = {
295 [NIR_INTRINSIC_IDX_BASE] = 1
296 }
297 };
298 struct nir_intrinsic nir_atomic_counter_pre_dec_deref = {
299 .name = "atomic_counter_pre_dec_deref",
300 .srcs_n = 1,
301 .src_components_n = {
302 -1
303 },
304 .has_dest = true,
305 .dest_components_n = 1
306 };
307 struct nir_intrinsic nir_atomic_counter_read = {
308 .name = "atomic_counter_read",
309 .srcs_n = 1,
310 .src_components_n = {
311 1
312 },
313 .has_dest = true,
314 .dest_components_n = 1,
315 .idxs_n = 1,
316 .idxs_map = {
317 [NIR_INTRINSIC_IDX_BASE] = 1
318 },
319 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
320 };
321 struct nir_intrinsic nir_atomic_counter_read_deref = {
322 .name = "atomic_counter_read_deref",
323 .srcs_n = 1,
324 .src_components_n = {
325 -1
326 },
327 .has_dest = true,
328 .dest_components_n = 1,
329 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
330 };
331 struct nir_intrinsic nir_atomic_counter_xor = {
332 .name = "atomic_counter_xor",
333 .srcs_n = 2,
334 .src_components_n = {
335 1,1
336 },
337 .has_dest = true,
338 .dest_components_n = 1,
339 .idxs_n = 1,
340 .idxs_map = {
341 [NIR_INTRINSIC_IDX_BASE] = 1
342 }
343 };
344 struct nir_intrinsic nir_atomic_counter_xor_deref = {
345 .name = "atomic_counter_xor_deref",
346 .srcs_n = 2,
347 .src_components_n = {
348 -1,1
349 },
350 .has_dest = true,
351 .dest_components_n = 1
352 };
353 struct nir_intrinsic nir_ballot = {
354 .name = "ballot",
355 .srcs_n = 1,
356 .src_components_n = {
357 1
358 },
359 .has_dest = true,
360 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
361 };
362 struct nir_intrinsic nir_ballot_bit_count_exclusive = {
363 .name = "ballot_bit_count_exclusive",
364 .srcs_n = 1,
365 .src_components_n = {
366 4
367 },
368 .has_dest = true,
369 .dest_components_n = 1,
370 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
371 };
372 struct nir_intrinsic nir_ballot_bit_count_inclusive = {
373 .name = "ballot_bit_count_inclusive",
374 .srcs_n = 1,
375 .src_components_n = {
376 4
377 },
378 .has_dest = true,
379 .dest_components_n = 1,
380 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
381 };
382 struct nir_intrinsic nir_ballot_bit_count_reduce = {
383 .name = "ballot_bit_count_reduce",
384 .srcs_n = 1,
385 .src_components_n = {
386 4
387 },
388 .has_dest = true,
389 .dest_components_n = 1,
390 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
391 };
392 struct nir_intrinsic nir_ballot_bitfield_extract = {
393 .name = "ballot_bitfield_extract",
394 .srcs_n = 2,
395 .src_components_n = {
396 4,1
397 },
398 .has_dest = true,
399 .dest_components_n = 1,
400 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
401 };
402 struct nir_intrinsic nir_ballot_find_lsb = {
403 .name = "ballot_find_lsb",
404 .srcs_n = 1,
405 .src_components_n = {
406 4
407 },
408 .has_dest = true,
409 .dest_components_n = 1,
410 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
411 };
412 struct nir_intrinsic nir_ballot_find_msb = {
413 .name = "ballot_find_msb",
414 .srcs_n = 1,
415 .src_components_n = {
416 4
417 },
418 .has_dest = true,
419 .dest_components_n = 1,
420 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
421 };
422 struct nir_intrinsic nir_barrier = {
423 .name = "barrier"
424 };
425 struct nir_intrinsic nir_begin_invocation_interlock = {
426 .name = "begin_invocation_interlock"
427 };
428 struct nir_intrinsic nir_copy_deref = {
429 .name = "copy_deref",
430 .srcs_n = 2,
431 .src_components_n = {
432 -1,-1
433 },
434 .idxs_n = 2,
435 .idxs_map = {
436 [NIR_INTRINSIC_IDX_DST_ACCESS] = 1,
437 [NIR_INTRINSIC_IDX_SRC_ACCESS] = 2
438 }
439 };
440 struct nir_intrinsic nir_deref_atomic_add = {
441 .name = "deref_atomic_add",
442 .srcs_n = 2,
443 .src_components_n = {
444 -1,1
445 },
446 .has_dest = true,
447 .dest_components_n = 1,
448 .idxs_n = 1,
449 .idxs_map = {
450 [NIR_INTRINSIC_IDX_ACCESS] = 1
451 }
452 };
453 struct nir_intrinsic nir_deref_atomic_and = {
454 .name = "deref_atomic_and",
455 .srcs_n = 2,
456 .src_components_n = {
457 -1,1
458 },
459 .has_dest = true,
460 .dest_components_n = 1,
461 .idxs_n = 1,
462 .idxs_map = {
463 [NIR_INTRINSIC_IDX_ACCESS] = 1
464 }
465 };
466 struct nir_intrinsic nir_deref_atomic_comp_swap = {
467 .name = "deref_atomic_comp_swap",
468 .srcs_n = 3,
469 .src_components_n = {
470 -1,1,1
471 },
472 .has_dest = true,
473 .dest_components_n = 1,
474 .idxs_n = 1,
475 .idxs_map = {
476 [NIR_INTRINSIC_IDX_ACCESS] = 1
477 }
478 };
479 struct nir_intrinsic nir_deref_atomic_exchange = {
480 .name = "deref_atomic_exchange",
481 .srcs_n = 2,
482 .src_components_n = {
483 -1,1
484 },
485 .has_dest = true,
486 .dest_components_n = 1,
487 .idxs_n = 1,
488 .idxs_map = {
489 [NIR_INTRINSIC_IDX_ACCESS] = 1
490 }
491 };
492 struct nir_intrinsic nir_deref_atomic_fadd = {
493 .name = "deref_atomic_fadd",
494 .srcs_n = 2,
495 .src_components_n = {
496 -1,1
497 },
498 .has_dest = true,
499 .dest_components_n = 1,
500 .idxs_n = 1,
501 .idxs_map = {
502 [NIR_INTRINSIC_IDX_ACCESS] = 1
503 }
504 };
505 struct nir_intrinsic nir_deref_atomic_fcomp_swap = {
506 .name = "deref_atomic_fcomp_swap",
507 .srcs_n = 3,
508 .src_components_n = {
509 -1,1,1
510 },
511 .has_dest = true,
512 .dest_components_n = 1,
513 .idxs_n = 1,
514 .idxs_map = {
515 [NIR_INTRINSIC_IDX_ACCESS] = 1
516 }
517 };
518 struct nir_intrinsic nir_deref_atomic_fmax = {
519 .name = "deref_atomic_fmax",
520 .srcs_n = 2,
521 .src_components_n = {
522 -1,1
523 },
524 .has_dest = true,
525 .dest_components_n = 1,
526 .idxs_n = 1,
527 .idxs_map = {
528 [NIR_INTRINSIC_IDX_ACCESS] = 1
529 }
530 };
531 struct nir_intrinsic nir_deref_atomic_fmin = {
532 .name = "deref_atomic_fmin",
533 .srcs_n = 2,
534 .src_components_n = {
535 -1,1
536 },
537 .has_dest = true,
538 .dest_components_n = 1,
539 .idxs_n = 1,
540 .idxs_map = {
541 [NIR_INTRINSIC_IDX_ACCESS] = 1
542 }
543 };
544 struct nir_intrinsic nir_deref_atomic_imax = {
545 .name = "deref_atomic_imax",
546 .srcs_n = 2,
547 .src_components_n = {
548 -1,1
549 },
550 .has_dest = true,
551 .dest_components_n = 1,
552 .idxs_n = 1,
553 .idxs_map = {
554 [NIR_INTRINSIC_IDX_ACCESS] = 1
555 }
556 };
557 struct nir_intrinsic nir_deref_atomic_imin = {
558 .name = "deref_atomic_imin",
559 .srcs_n = 2,
560 .src_components_n = {
561 -1,1
562 },
563 .has_dest = true,
564 .dest_components_n = 1,
565 .idxs_n = 1,
566 .idxs_map = {
567 [NIR_INTRINSIC_IDX_ACCESS] = 1
568 }
569 };
570 struct nir_intrinsic nir_deref_atomic_or = {
571 .name = "deref_atomic_or",
572 .srcs_n = 2,
573 .src_components_n = {
574 -1,1
575 },
576 .has_dest = true,
577 .dest_components_n = 1,
578 .idxs_n = 1,
579 .idxs_map = {
580 [NIR_INTRINSIC_IDX_ACCESS] = 1
581 }
582 };
583 struct nir_intrinsic nir_deref_atomic_umax = {
584 .name = "deref_atomic_umax",
585 .srcs_n = 2,
586 .src_components_n = {
587 -1,1
588 },
589 .has_dest = true,
590 .dest_components_n = 1,
591 .idxs_n = 1,
592 .idxs_map = {
593 [NIR_INTRINSIC_IDX_ACCESS] = 1
594 }
595 };
596 struct nir_intrinsic nir_deref_atomic_umin = {
597 .name = "deref_atomic_umin",
598 .srcs_n = 2,
599 .src_components_n = {
600 -1,1
601 },
602 .has_dest = true,
603 .dest_components_n = 1,
604 .idxs_n = 1,
605 .idxs_map = {
606 [NIR_INTRINSIC_IDX_ACCESS] = 1
607 }
608 };
609 struct nir_intrinsic nir_deref_atomic_xor = {
610 .name = "deref_atomic_xor",
611 .srcs_n = 2,
612 .src_components_n = {
613 -1,1
614 },
615 .has_dest = true,
616 .dest_components_n = 1,
617 .idxs_n = 1,
618 .idxs_map = {
619 [NIR_INTRINSIC_IDX_ACCESS] = 1
620 }
621 };
622 struct nir_intrinsic nir_discard = {
623 .name = "discard"
624 };
625
626 /******************************************************************************/
627 /* A conditional discard/demote, with a single boolean source. */
628 struct nir_intrinsic nir_discard_if = {
629 .name = "discard_if",
630 .srcs_n = 1,
631 .src_components_n = {
632 1
633 }
634 };
635 struct nir_intrinsic nir_demote_if = {
636 .name = "demote_if",
637 .srcs_n = 1,
638 .src_components_n = {
639 1
640 }
641 };
642 /******************************************************************************/
643 struct nir_intrinsic nir_elect = {
644 .name = "elect",
645 .has_dest = true,
646 .dest_components_n = 1,
647 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
648 };
649 struct nir_intrinsic nir_emit_vertex = {
650 .name = "emit_vertex",
651 .idxs_n = 1,
652 .idxs_map = {
653 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
654 }
655 };
656 struct nir_intrinsic nir_emit_vertex_with_counter = {
657 .name = "emit_vertex_with_counter",
658 .srcs_n = 1,
659 .src_components_n = {
660 1
661 },
662 .idxs_n = 1,
663 .idxs_map = {
664 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
665 }
666 };
667 struct nir_intrinsic nir_end_invocation_interlock = {
668 .name = "end_invocation_interlock"
669 };
670 struct nir_intrinsic nir_end_primitive = {
671 .name = "end_primitive",
672 .idxs_n = 1,
673 .idxs_map = {
674 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
675 }
676 };
677 struct nir_intrinsic nir_end_primitive_with_counter = {
678 .name = "end_primitive_with_counter",
679 .srcs_n = 1,
680 .src_components_n = {
681 1
682 },
683 .idxs_n = 1,
684 .idxs_map = {
685 [NIR_INTRINSIC_IDX_STREAM_ID] = 1
686 }
687 };
688 struct nir_intrinsic nir_exclusive_scan = {
689 .name = "exclusive_scan",
690 .srcs_n = 1,
691 .src_components_n = {
692 0
693 },
694 .has_dest = true,
695 .idxs_n = 1,
696 .idxs_map = {
697 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1
698 },
699 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
700 };
701 struct nir_intrinsic nir_first_invocation = {
702 .name = "first_invocation",
703 .has_dest = true,
704 .dest_components_n = 1,
705 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
706 };
707 struct nir_intrinsic nir_get_buffer_size = {
708 .name = "get_buffer_size",
709 .srcs_n = 1,
710 .src_components_n = {
711 1
712 },
713 .has_dest = true,
714 .dest_components_n = 1,
715 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
716 };
717 struct nir_intrinsic nir_global_atomic_add = {
718 .name = "global_atomic_add",
719 .srcs_n = 2,
720 .src_components_n = {
721 1,1
722 },
723 .has_dest = true,
724 .dest_components_n = 1,
725 .idxs_n = 1,
726 .idxs_map = {
727 [NIR_INTRINSIC_IDX_BASE] = 1
728 }
729 };
730 struct nir_intrinsic nir_global_atomic_and = {
731 .name = "global_atomic_and",
732 .srcs_n = 2,
733 .src_components_n = {
734 1,1
735 },
736 .has_dest = true,
737 .dest_components_n = 1,
738 .idxs_n = 1,
739 .idxs_map = {
740 [NIR_INTRINSIC_IDX_BASE] = 1
741 }
742 };
743 struct nir_intrinsic nir_global_atomic_comp_swap = {
744 .name = "global_atomic_comp_swap",
745 .srcs_n = 3,
746 .src_components_n = {
747 1,1,1
748 },
749 .has_dest = true,
750 .dest_components_n = 1,
751 .idxs_n = 1,
752 .idxs_map = {
753 [NIR_INTRINSIC_IDX_BASE] = 1
754 }
755 };
756 struct nir_intrinsic nir_global_atomic_exchange = {
757 .name = "global_atomic_exchange",
758 .srcs_n = 2,
759 .src_components_n = {
760 1,1
761 },
762 .has_dest = true,
763 .dest_components_n = 1,
764 .idxs_n = 1,
765 .idxs_map = {
766 [NIR_INTRINSIC_IDX_BASE] = 1
767 }
768 };
769 struct nir_intrinsic nir_global_atomic_fadd = {
770 .name = "global_atomic_fadd",
771 .srcs_n = 2,
772 .src_components_n = {
773 1,1
774 },
775 .has_dest = true,
776 .dest_components_n = 1,
777 .idxs_n = 1,
778 .idxs_map = {
779 [NIR_INTRINSIC_IDX_BASE] = 1
780 }
781 };
782 struct nir_intrinsic nir_global_atomic_fcomp_swap = {
783 .name = "global_atomic_fcomp_swap",
784 .srcs_n = 3,
785 .src_components_n = {
786 1,1,1
787 },
788 .has_dest = true,
789 .dest_components_n = 1,
790 .idxs_n = 1,
791 .idxs_map = {
792 [NIR_INTRINSIC_IDX_BASE] = 1
793 }
794 };
795 struct nir_intrinsic nir_global_atomic_fmax = {
796 .name = "global_atomic_fmax",
797 .srcs_n = 2,
798 .src_components_n = {
799 1,1
800 },
801 .has_dest = true,
802 .dest_components_n = 1,
803 .idxs_n = 1,
804 .idxs_map = {
805 [NIR_INTRINSIC_IDX_BASE] = 1
806 }
807 };
808 struct nir_intrinsic nir_global_atomic_fmin = {
809 .name = "global_atomic_fmin",
810 .srcs_n = 2,
811 .src_components_n = {
812 1,1
813 },
814 .has_dest = true,
815 .dest_components_n = 1,
816 .idxs_n = 1,
817 .idxs_map = {
818 [NIR_INTRINSIC_IDX_BASE] = 1
819 }
820 };
821 struct nir_intrinsic nir_global_atomic_imax = {
822 .name = "global_atomic_imax",
823 .srcs_n = 2,
824 .src_components_n = {
825 1,1
826 },
827 .has_dest = true,
828 .dest_components_n = 1,
829 .idxs_n = 1,
830 .idxs_map = {
831 [NIR_INTRINSIC_IDX_BASE] = 1
832 }
833 };
834 struct nir_intrinsic nir_global_atomic_imin = {
835 .name = "global_atomic_imin",
836 .srcs_n = 2,
837 .src_components_n = {
838 1,1
839 },
840 .has_dest = true,
841 .dest_components_n = 1,
842 .idxs_n = 1,
843 .idxs_map = {
844 [NIR_INTRINSIC_IDX_BASE] = 1
845 }
846 };
847 struct nir_intrinsic nir_global_atomic_or = {
848 .name = "global_atomic_or",
849 .srcs_n = 2,
850 .src_components_n = {
851 1,1
852 },
853 .has_dest = true,
854 .dest_components_n = 1,
855 .idxs_n = 1,
856 .idxs_map = {
857 [NIR_INTRINSIC_IDX_BASE] = 1
858 }
859 };
860 struct nir_intrinsic nir_global_atomic_umax = {
861 .name = "global_atomic_umax",
862 .srcs_n = 2,
863 .src_components_n = {
864 1,1
865 },
866 .has_dest = true,
867 .dest_components_n = 1,
868 .idxs_n = 1,
869 .idxs_map = {
870 [NIR_INTRINSIC_IDX_BASE] = 1
871 }
872 };
873 struct nir_intrinsic nir_global_atomic_umin = {
874 .name = "global_atomic_umin",
875 .srcs_n = 2,
876 .src_components_n = {
877 1,1
878 },
879 .has_dest = true,
880 .dest_components_n = 1,
881 .idxs_n = 1,
882 .idxs_map = {
883 [NIR_INTRINSIC_IDX_BASE] = 1
884 }
885 };
886 struct nir_intrinsic nir_global_atomic_xor = {
887 .name = "global_atomic_xor",
888 .srcs_n = 2,
889 .src_components_n = {
890 1,1
891 },
892 .has_dest = true,
893 .dest_components_n = 1,
894 .idxs_n = 1,
895 .idxs_map = {
896 [NIR_INTRINSIC_IDX_BASE] = 1
897 }
898 };
899 struct nir_intrinsic nir_group_memory_barrier = {
900 .name = "group_memory_barrier"
901 };
902 struct nir_intrinsic nir_inclusive_scan = {
903 .name = "inclusive_scan",
904 .srcs_n = 1,
905 .src_components_n = {
906 0
907 },
908 .has_dest = true,
909 .idxs_n = 1,
910 .idxs_map = {
911 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1
912 },
913 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
914 };
915 struct nir_intrinsic nir_interp_deref_at_centroid = {
916 .name = "interp_deref_at_centroid",
917 .srcs_n = 1,
918 .src_components_n = {
919 1
920 },
921 .has_dest = true,
922 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
923 };
924 struct nir_intrinsic nir_interp_deref_at_offset = {
925 .name = "interp_deref_at_offset",
926 .srcs_n = 2,
927 .src_components_n = {
928 1,2
929 },
930 .has_dest = true,
931 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
932 };
933 struct nir_intrinsic nir_interp_deref_at_sample = {
934 .name = "interp_deref_at_sample",
935 .srcs_n = 2,
936 .src_components_n = {
937 1,1
938 },
939 .has_dest = true,
940 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
941 };
942 /******************************************************************************/
943 /*
944 * Barycentric coordinate intrinsics.
945 *
946 * These set up the barycentric coordinates for a particular interpolation.
947 * The first three are for the simple cases: pixel, centroid, or per-sample
948 * (at gl_SampleID). The next two handle interpolating at a specified
949 * sample location, or interpolating with a vec2 offset,
950 *
951 * The interp_mode index should be either the INTERP_MODE_SMOOTH or
952 * INTERP_MODE_NOPERSPECTIVE enum values.
953 *
954 * The vec2 value produced by these intrinsics is intended for use as the
955 * barycoord source of a load_interpolated_input intrinsic.
956 */
87 #include "intrinsics/generic/generic.c"
88 #include "intrinsics/generic/system_values.c"
89 #include "intrinsics/generic/load.c"
90 #include "intrinsics/generic/store.c"
91 #include "intrinsics/generic/image.c"
957 92 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
958 /* no source */
959 struct nir_intrinsic nir_load_barycentric_pixel = {
960 .name = "load_barycentric_pixel",
961 .srcs_n = 0,
962 .has_dest = true,
963 .dest_components_n = 2,
964 .idxs_n = 1,
965 .idxs_map = {
966 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
967 },
968 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
969 };
970 struct nir_intrinsic nir_load_barycentric_centroid = {
971 .name = "load_barycentric_centroid",
972 .srcs_n = 0,
973 .has_dest = true,
974 .dest_components_n = 2,
975 .idxs_n = 1,
976 .idxs_map = {
977 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
978 },
979 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
980 };
981 struct nir_intrinsic nir_load_barycentric_sample = {
982 .name = "load_barycentric_sample",
983 .srcs_n = 0,
984 .has_dest = true,
985 .dest_components_n = 2,
986 .idxs_n = 1,
987 .idxs_map = {
988 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
989 },
990 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
991 };
992 /* no source */
93 #include "intrinsics/amd/amd.c"
94 #include "intrinsics/amd/system_values.c"
993 95 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
994 /* src[] = { offset.xy } */
995 struct nir_intrinsic nir_load_barycentric_at_offset = {
996 .name = "load_barycentric_at_offset",
997 .srcs_n = 1,
998 .src_components_n = {
999 2
1000 },
1001 .has_dest = true,
1002 .dest_components_n = 2,
1003 .idxs_n = 1,
1004 .idxs_map = {
1005 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1006 },
1007 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1008 };
1009 /* src[] = { sample_id } */
1010 struct nir_intrinsic nir_load_barycentric_at_sample = {
1011 .name = "load_barycentric_at_sample",
1012 .srcs_n = 1,
1013 .src_components_n = {
1014 1
1015 },
1016 .has_dest = true,
1017 .dest_components_n = 2,
1018 .idxs_n = 1,
1019 .idxs_map = {
1020 [NIR_INTRINSIC_IDX_INTERP_MODE] = 1
1021 },
1022 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1023 };
1024 /* Barycentric coordinate intrinsics. */
1025 /******************************************************************************/
1026
1027 struct nir_intrinsic nir_load_deref = {
1028 .name = "load_deref",
1029 .srcs_n = 1,
1030 .src_components_n = {
1031 -1
1032 },
1033 .has_dest = true,
1034 .idxs_n = 1,
1035 .idxs_map = {
1036 [NIR_INTRINSIC_IDX_ACCESS] = 1
1037 },
1038 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1039 };
1040
1041 /*
1042 * Load sample position:
1043 *
1044 * Takes a sample # and returns a sample position. Used for lowering
1045 * interpolateAtSample() to interpolateAtOffset()
1046 */
1047 struct nir_intrinsic nir_load_sample_pos_from_id = {
1048 .name = "load_sample_pos_from_id",
1049 .srcs_n = 1,
1050 .src_components_n = {
1051 1
1052 },
1053 .has_dest = true,
1054 .dest_components_n = 2,
1055 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1056 };
1057
1058 /* Loads what I believe is the primitive size, for scaling ij to pixel size: */
1059 struct nir_intrinsic nir_load_size_ir3 = {
1060 .name = "load_size_ir3",
1061 .has_dest = true,
1062 .dest_components_n = 1,
1063 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1064 };
1065
1066 /*
1067 * Fragment shader input interpolation delta intrinsic.
1068 *
1069 * For hw where fragment shader input interpolation is handled in shader, the
1070 * load_fs_input_interp deltas intrinsics can be used to load the input deltas
1071 * used for interpolation as follows:
1072 *
1073 * vec3 iid = load_fs_input_interp_deltas(varying_slot)
1074 * vec2 bary = load_barycentric_*(...)
1075 * float result = iid.x + iid.y * bary.y + iid.z * bary.x
1076 */
1077 struct nir_intrinsic nir_load_fs_input_interp_deltas = {
1078 .name = "load_fs_input_interp_deltas",
1079 .srcs_n = 1,
1080 .src_components_n = {
1081 1
1082 },
1083 .has_dest = true,
1084 .dest_components_n = 3,
1085 .idxs_n = 2,
1086 .idxs_map = {
1087 [NIR_INTRINSIC_IDX_BASE] = 1,
1088 [NIR_INTRINSIC_IDX_COMPONENT] = 2
1089 },
1090 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1091 };
1092 struct nir_intrinsic nir_load_param = {
1093 .name = "load_param",
1094 .srcs_n = 0,
1095 .has_dest = true,
1096 .idxs_n = 1,
1097 .idxs_map = {
1098 [NIR_INTRINSIC_IDX_PARAM_IDX] = 1
1099 },
1100 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1101 };
1102 struct nir_intrinsic nir_load_vulkan_descriptor = {
1103 .name = "load_vulkan_descriptor",
1104 .srcs_n = 1,
1105 .src_components_n = {
1106 1
1107 },
1108 .has_dest = true,
1109 .idxs_n = 1,
1110 .idxs_map = {
1111 [NIR_INTRINSIC_IDX_DESC_TYPE] = 1
1112 },
1113 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1114 };
1115 /*
1116 * Memory barrier with semantics analogous to the memoryBarrier() GLSL
1117 * intrinsic.
1118 */
1119 struct nir_intrinsic nir_memory_barrier = {
1120 .name = "memory_barrier"
1121 };
1122 /*
1123 * Memory barrier with explicit scope. Follows the semantics of SPIR-V
1124 * OpMemoryBarrier, used to implement Vulkan Memory Model. Storage that the
1125 * barrierr applies is represented using NIR variable modes.
1126 */
1127 struct nir_intrinsic nir_scoped_memory_barrier = {
1128 .name = "scoped_memory_barrier",
1129 .idxs_n = 3,
1130 .idxs_map = {
1131 [NIR_INTRINSIC_IDX_MEMORY_SEMANTICS] = 1,
1132 [NIR_INTRINSIC_IDX_MEMORY_MODES] = 2,
1133 [NIR_INTRINSIC_IDX_MEMORY_SCOPE] = 3
1134 }
1135 };
1136 struct nir_intrinsic nir_memory_barrier_atomic_counter = {
1137 .name = "memory_barrier_atomic_counter"
1138 };
1139 struct nir_intrinsic nir_memory_barrier_buffer = {
1140 .name = "memory_barrier_buffer"
1141 };
1142 struct nir_intrinsic nir_memory_barrier_image = {
1143 .name = "memory_barrier_image"
1144 };
1145 struct nir_intrinsic nir_memory_barrier_shared = {
1146 .name = "memory_barrier_shared"
1147 };
1148 struct nir_intrinsic nir_nop = {
1149 .name = "nop",
1150 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1151 };
1152 struct nir_intrinsic nir_quad_broadcast = {
1153 .name = "quad_broadcast",
1154 .srcs_n = 2,
1155 .src_components_n = {
1156 0,1
1157 },
1158 .has_dest = true,
1159 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1160 };
1161 struct nir_intrinsic nir_quad_swap_diagonal = {
1162 .name = "quad_swap_diagonal",
1163 .srcs_n = 1,
1164 .src_components_n = {
1165 0
1166 },
1167 .has_dest = true,
1168 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1169 };
1170 struct nir_intrinsic nir_quad_swap_horizontal = {
1171 .name = "quad_swap_horizontal",
1172 .srcs_n = 1,
1173 .src_components_n = {
1174 0
1175 },
1176 .has_dest = true,
1177 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1178 };
1179 struct nir_intrinsic nir_quad_swap_vertical = {
1180 .name = "quad_swap_vertical",
1181 .srcs_n = 1,
1182 .src_components_n = {
1183 0
1184 },
1185 .has_dest = true,
1186 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1187 };
1188 struct nir_intrinsic nir_read_first_invocation = {
1189 .name = "read_first_invocation",
1190 .srcs_n = 1,
1191 .src_components_n = {
1192 0
1193 },
1194 .has_dest = true,
1195 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1196 };
1197 struct nir_intrinsic nir_read_invocation = {
1198 .name = "read_invocation",
1199 .srcs_n = 2,
1200 .src_components_n = {
1201 0,1
1202 },
1203 .has_dest = true,
1204 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1205 };
1206 struct nir_intrinsic nir_reduce = {
1207 .name = "reduce",
1208 .srcs_n = 1,
1209 .src_components_n = {
1210 0
1211 },
1212 .has_dest = true,
1213 .idxs_n = 2,
1214 .idxs_map = {
1215 [NIR_INTRINSIC_IDX_REDUCTION_OP] = 1,
1216 [NIR_INTRINSIC_IDX_CLUSTER_SIZE] = 2
1217 },
1218 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1219 };
1220 struct nir_intrinsic nir_set_vertex_count = {
1221 .name = "set_vertex_count",
1222 .srcs_n = 1,
1223 .src_components_n = {
1224 1
1225 }
1226 };
1227 struct nir_intrinsic nir_shader_clock = {
1228 .name = "shader_clock",
1229 .has_dest = true,
1230 .dest_components_n = 2,
1231 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1232 };
1233 struct nir_intrinsic nir_shared_atomic_add = {
1234 .name = "shared_atomic_add",
1235 .srcs_n = 2,
1236 .src_components_n = {
1237 1,1
1238 },
1239 .has_dest = true,
1240 .dest_components_n = 1,
1241 .idxs_n = 1,
1242 .idxs_map = {
1243 [NIR_INTRINSIC_IDX_BASE] = 1
1244 }
1245 };
1246 struct nir_intrinsic nir_shared_atomic_and = {
1247 .name = "shared_atomic_and",
1248 .srcs_n = 2,
1249 .src_components_n = {
1250 1,1
1251 },
1252 .has_dest = true,
1253 .dest_components_n = 1,
1254 .idxs_n = 1,
1255 .idxs_map = {
1256 [NIR_INTRINSIC_IDX_BASE] = 1
1257 }
1258 };
1259 struct nir_intrinsic nir_shared_atomic_comp_swap = {
1260 .name = "shared_atomic_comp_swap",
1261 .srcs_n = 3,
1262 .src_components_n = {
1263 1,1,1
1264 },
1265 .has_dest = true,
1266 .dest_components_n = 1,
1267 .idxs_n = 1,
1268 .idxs_map = {
1269 [NIR_INTRINSIC_IDX_BASE] = 1
1270 }
1271 };
1272 struct nir_intrinsic nir_shared_atomic_exchange = {
1273 .name = "shared_atomic_exchange",
1274 .srcs_n = 2,
1275 .src_components_n = {
1276 1,1
1277 },
1278 .has_dest = true,
1279 .dest_components_n = 1,
1280 .idxs_n = 1,
1281 .idxs_map = {
1282 [NIR_INTRINSIC_IDX_BASE] = 1
1283 }
1284 };
1285 struct nir_intrinsic nir_shared_atomic_fadd = {
1286 .name = "shared_atomic_fadd",
1287 .srcs_n = 2,
1288 .src_components_n = {
1289 1,1
1290 },
1291 .has_dest = true,
1292 .dest_components_n = 1,
1293 .idxs_n = 1,
1294 .idxs_map = {
1295 [NIR_INTRINSIC_IDX_BASE] = 1
1296 }
1297 };
1298 struct nir_intrinsic nir_shared_atomic_fcomp_swap = {
1299 .name = "shared_atomic_fcomp_swap",
1300 .srcs_n = 3,
1301 .src_components_n = {
1302 1,1,1
1303 },
1304 .has_dest = true,
1305 .dest_components_n = 1,
1306 .idxs_n = 1,
1307 .idxs_map = {
1308 [NIR_INTRINSIC_IDX_BASE] = 1
1309 }
1310 };
1311 struct nir_intrinsic nir_shared_atomic_fmax = {
1312 .name = "shared_atomic_fmax",
1313 .srcs_n = 2,
1314 .src_components_n = {
1315 1,1
1316 },
1317 .has_dest = true,
1318 .dest_components_n = 1,
1319 .idxs_n = 1,
1320 .idxs_map = {
1321 [NIR_INTRINSIC_IDX_BASE] = 1
1322 }
1323 };
1324 struct nir_intrinsic nir_shared_atomic_fmin = {
1325 .name = "shared_atomic_fmin",
1326 .srcs_n = 2,
1327 .src_components_n = {
1328 1,1
1329 },
1330 .has_dest = true,
1331 .dest_components_n = 1,
1332 .idxs_n = 1,
1333 .idxs_map = {
1334 [NIR_INTRINSIC_IDX_BASE] = 1
1335 }
1336 };
1337 struct nir_intrinsic nir_shared_atomic_imax = {
1338 .name = "shared_atomic_imax",
1339 .srcs_n = 2,
1340 .src_components_n = {
1341 1,1
1342 },
1343 .has_dest = true,
1344 .dest_components_n = 1,
1345 .idxs_n = 1,
1346 .idxs_map = {
1347 [NIR_INTRINSIC_IDX_BASE] = 1
1348 }
1349 };
1350 struct nir_intrinsic nir_shared_atomic_imin = {
1351 .name = "shared_atomic_imin",
1352 .srcs_n = 2,
1353 .src_components_n = {
1354 1,1
1355 },
1356 .has_dest = true,
1357 .dest_components_n = 1,
1358 .idxs_n = 1,
1359 .idxs_map = {
1360 [NIR_INTRINSIC_IDX_BASE] = 1
1361 }
1362 };
1363 struct nir_intrinsic nir_shared_atomic_or = {
1364 .name = "shared_atomic_or",
1365 .srcs_n = 2,
1366 .src_components_n = {
1367 1,1
1368 },
1369 .has_dest = true,
1370 .dest_components_n = 1,
1371 .idxs_n = 1,
1372 .idxs_map = {
1373 [NIR_INTRINSIC_IDX_BASE] = 1
1374 }
1375 };
1376 struct nir_intrinsic nir_shared_atomic_umax = {
1377 .name = "shared_atomic_umax",
1378 .srcs_n = 2,
1379 .src_components_n = {
1380 1,1
1381 },
1382 .has_dest = true,
1383 .dest_components_n = 1,
1384 .idxs_n = 1,
1385 .idxs_map = {
1386 [NIR_INTRINSIC_IDX_BASE] = 1
1387 }
1388 };
1389 struct nir_intrinsic nir_shared_atomic_umin = {
1390 .name = "shared_atomic_umin",
1391 .srcs_n = 2,
1392 .src_components_n = {
1393 1,1
1394 },
1395 .has_dest = true,
1396 .dest_components_n = 1,
1397 .idxs_n = 1,
1398 .idxs_map = {
1399 [NIR_INTRINSIC_IDX_BASE] = 1
1400 }
1401 };
1402 struct nir_intrinsic nir_shared_atomic_xor = {
1403 .name = "shared_atomic_xor",
1404 .srcs_n = 2,
1405 .src_components_n = {
1406 1,1
1407 },
1408 .has_dest = true,
1409 .dest_components_n = 1,
1410 .idxs_n = 1,
1411 .idxs_map = {
1412 [NIR_INTRINSIC_IDX_BASE] = 1
1413 }
1414 };
1415 struct nir_intrinsic nir_shuffle = {
1416 .name = "shuffle",
1417 .srcs_n = 2,
1418 .src_components_n = {
1419 0,1
1420 },
1421 .has_dest = true,
1422 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1423 };
1424 struct nir_intrinsic nir_shuffle_down = {
1425 .name = "shuffle_down",
1426 .srcs_n = 2,
1427 .src_components_n = {
1428 0,1
1429 },
1430 .has_dest = true,
1431 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1432 };
1433 struct nir_intrinsic nir_shuffle_up = {
1434 .name = "shuffle_up",
1435 .srcs_n = 2,
1436 .src_components_n = {
1437 0,1
1438 },
1439 .has_dest = true,
1440 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1441 };
1442 struct nir_intrinsic nir_shuffle_xor = {
1443 .name = "shuffle_xor",
1444 .srcs_n = 2,
1445 .src_components_n = {
1446 0,1
1447 },
1448 .has_dest = true,
1449 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1450 };
1451 struct nir_intrinsic nir_ssbo_atomic_add = {
1452 .name = "ssbo_atomic_add",
1453 .srcs_n = 3,
1454 .src_components_n = {
1455 1,1,1
1456 },
1457 .has_dest = true,
1458 .dest_components_n = 1,
1459 .idxs_n = 1,
1460 .idxs_map = {
1461 [NIR_INTRINSIC_IDX_ACCESS] = 1
1462 }
1463 };
1464 struct nir_intrinsic nir_ssbo_atomic_and = {
1465 .name = "ssbo_atomic_and",
1466 .srcs_n = 3,
1467 .src_components_n = {
1468 1,1,1
1469 },
1470 .has_dest = true,
1471 .dest_components_n = 1,
1472 .idxs_n = 1,
1473 .idxs_map = {
1474 [NIR_INTRINSIC_IDX_ACCESS] = 1
1475 }
1476 };
1477 struct nir_intrinsic nir_ssbo_atomic_comp_swap = {
1478 .name = "ssbo_atomic_comp_swap",
1479 .srcs_n = 4,
1480 .src_components_n = {
1481 1,1,1,1
1482 },
1483 .has_dest = true,
1484 .dest_components_n = 1,
1485 .idxs_n = 1,
1486 .idxs_map = {
1487 [NIR_INTRINSIC_IDX_ACCESS] = 1
1488 }
1489 };
1490 struct nir_intrinsic nir_ssbo_atomic_exchange = {
1491 .name = "ssbo_atomic_exchange",
1492 .srcs_n = 3,
1493 .src_components_n = {
1494 1,1,1
1495 },
1496 .has_dest = true,
1497 .dest_components_n = 1,
1498 .idxs_n = 1,
1499 .idxs_map = {
1500 [NIR_INTRINSIC_IDX_ACCESS] = 1
1501 }
1502 };
1503 struct nir_intrinsic nir_ssbo_atomic_fadd = {
1504 .name = "ssbo_atomic_fadd",
1505 .srcs_n = 3,
1506 .src_components_n = {
1507 1,1,1
1508 },
1509 .has_dest = true,
1510 .dest_components_n = 1,
1511 .idxs_n = 1,
1512 .idxs_map = {
1513 [NIR_INTRINSIC_IDX_ACCESS] = 1
1514 }
1515 };
1516 struct nir_intrinsic nir_ssbo_atomic_fcomp_swap = {
1517 .name = "ssbo_atomic_fcomp_swap",
1518 .srcs_n = 4,
1519 .src_components_n = {
1520 1,1,1,1
1521 },
1522 .has_dest = true,
1523 .dest_components_n = 1,
1524 .idxs_n = 1,
1525 .idxs_map = {
1526 [NIR_INTRINSIC_IDX_ACCESS] = 1
1527 }
1528 };
1529 struct nir_intrinsic nir_ssbo_atomic_fmax = {
1530 .name = "ssbo_atomic_fmax",
1531 .srcs_n = 3,
1532 .src_components_n = {
1533 1,1,1
1534 },
1535 .has_dest = true,
1536 .dest_components_n = 1,
1537 .idxs_n = 1,
1538 .idxs_map = {
1539 [NIR_INTRINSIC_IDX_ACCESS] = 1
1540 }
1541 };
1542 struct nir_intrinsic nir_ssbo_atomic_fmin = {
1543 .name = "ssbo_atomic_fmin",
1544 .srcs_n = 3,
1545 .src_components_n = {
1546 1,1,1
1547 },
1548 .has_dest = true,
1549 .dest_components_n = 1,
1550 .idxs_n = 1,
1551 .idxs_map = {
1552 [NIR_INTRINSIC_IDX_ACCESS] = 1
1553 }
1554 };
1555 struct nir_intrinsic nir_ssbo_atomic_imax = {
1556 .name = "ssbo_atomic_imax",
1557 .srcs_n = 3,
1558 .src_components_n = {
1559 1,1,1
1560 },
1561 .has_dest = true,
1562 .dest_components_n = 1,
1563 .idxs_n = 1,
1564 .idxs_map = {
1565 [NIR_INTRINSIC_IDX_ACCESS] = 1
1566 }
1567 };
1568 struct nir_intrinsic nir_ssbo_atomic_imin = {
1569 .name = "ssbo_atomic_imin",
1570 .srcs_n = 3,
1571 .src_components_n = {
1572 1,1,1
1573 },
1574 .has_dest = true,
1575 .dest_components_n = 1,
1576 .idxs_n = 1,
1577 .idxs_map = {
1578 [NIR_INTRINSIC_IDX_ACCESS] = 1
1579 }
1580 };
1581 struct nir_intrinsic nir_ssbo_atomic_or = {
1582 .name = "ssbo_atomic_or",
1583 .srcs_n = 3,
1584 .src_components_n = {
1585 1,1,1
1586 },
1587 .has_dest = true,
1588 .dest_components_n = 1,
1589 .idxs_n = 1,
1590 .idxs_map = {
1591 [NIR_INTRINSIC_IDX_ACCESS] = 1
1592 }
1593 };
1594 struct nir_intrinsic nir_ssbo_atomic_umax = {
1595 .name = "ssbo_atomic_umax",
1596 .srcs_n = 3,
1597 .src_components_n = {
1598 1,1,1
1599 },
1600 .has_dest = true,
1601 .dest_components_n = 1,
1602 .idxs_n = 1,
1603 .idxs_map = {
1604 [NIR_INTRINSIC_IDX_ACCESS] = 1
1605 }
1606 };
1607 struct nir_intrinsic nir_ssbo_atomic_umin = {
1608 .name = "ssbo_atomic_umin",
1609 .srcs_n = 3,
1610 .src_components_n = {
1611 1,1,1
1612 },
1613 .has_dest = true,
1614 .dest_components_n = 1,
1615 .idxs_n = 1,
1616 .idxs_map = {
1617 [NIR_INTRINSIC_IDX_ACCESS] = 1
1618 }
1619 };
1620 struct nir_intrinsic nir_ssbo_atomic_xor = {
1621 .name = "ssbo_atomic_xor",
1622 .srcs_n = 3,
1623 .src_components_n = {
1624 1,1,1
1625 },
1626 .has_dest = true,
1627 .dest_components_n = 1,
1628 .idxs_n = 1,
1629 .idxs_map = {
1630 [NIR_INTRINSIC_IDX_ACCESS] = 1
1631 }
1632 };
1633 struct nir_intrinsic nir_store_deref = {
1634 .name = "store_deref",
1635 .srcs_n = 2,
1636 .src_components_n = {
1637 -1,0
1638 },
1639 .idxs_n = 2,
1640 .idxs_map = {
1641 [NIR_INTRINSIC_IDX_WRMASK] = 1,
1642 [NIR_INTRINSIC_IDX_ACCESS] = 2
1643 }
1644 };
1645 struct nir_intrinsic nir_vote_all = {
1646 .name = "vote_all",
1647 .srcs_n = 1,
1648 .src_components_n = {
1649 1
1650 },
1651 .has_dest = true,
1652 .dest_components_n = 1,
1653 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1654 };
1655 struct nir_intrinsic nir_vote_any = {
1656 .name = "vote_any",
1657 .srcs_n = 1,
1658 .src_components_n = {
1659 1
1660 },
1661 .has_dest = true,
1662 .dest_components_n = 1,
1663 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1664 };
1665 struct nir_intrinsic nir_vote_feq = {
1666 .name = "vote_feq",
1667 .srcs_n = 1,
1668 .src_components_n = {
1669 0
1670 },
1671 .has_dest = true,
1672 .dest_components_n = 1,
1673 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1674 };
1675 struct nir_intrinsic nir_vote_ieq = {
1676 .name = "vote_ieq",
1677 .srcs_n = 1,
1678 .src_components_n = {
1679 0
1680 },
1681 .has_dest = true,
1682 .dest_components_n = 1,
1683 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1684 };
1685 struct nir_intrinsic nir_vulkan_resource_index = {
1686 .name = "vulkan_resource_index",
1687 .srcs_n = 1,
1688 .src_components_n = {
1689 1
1690 },
1691 .has_dest = true,
1692 .dest_components_n = 1,
1693 .idxs_n = 3,
1694 .idxs_map = {
1695 [NIR_INTRINSIC_IDX_DESC_SET] = 1,
1696 [NIR_INTRINSIC_IDX_BINDING] = 2,
1697 [NIR_INTRINSIC_IDX_DESC_TYPE] = 3
1698 },
1699 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1700 };
1701 struct nir_intrinsic nir_vulkan_resource_reindex = {
1702 .name = "vulkan_resource_reindex",
1703 .srcs_n = 2,
1704 .src_components_n = {
1705 1,1
1706 },
1707 .has_dest = true,
1708 .dest_components_n = 1,
1709 .idxs_n = 1,
1710 .idxs_map = {
1711 [NIR_INTRINSIC_IDX_DESC_TYPE] = 1
1712 },
1713 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1714 };
1715
1716 /* Gets the length of an unsized array at the end of a buffer */
1717 struct nir_intrinsic nir_deref_buffer_array_length = {
1718 .name = "deref_buffer_array_length",
1719 .srcs_n = 1,
1720 .src_components_n = {
1721 -1
1722 },
1723 .has_dest = true,
1724 .dest_components_n = 1,
1725 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1726 };
1727
96 #include "intrinsics/ir3/ir3.c"
97 #include "intrinsics/ir3/system_values.c"
98 #include "intrinsics/ir3/load.c"
99 #include "intrinsics/ir3/store.c"
1728 100 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
1729 /*
1730 * IR3-specific version of most SSBO intrinsics. The only different
1731 * compare to the originals is that they add an extra source to hold
1732 * the dword-offset, which is needed by the backend code apart from
1733 * the byte-offset already provided by NIR in one of the sources.
1734 *
1735 * NIR lowering pass 'ir3_nir_lower_io_offset' will replace the
1736 * original SSBO intrinsics by these, placing the computed
1737 * dword-offset always in the last source.
1738 *
1739 * The float versions are not handled because those are not supported
1740 * by the backend.
1741 */
1742 struct nir_intrinsic nir_store_ssbo_ir3 = {
1743 .name = "store_ssbo_ir3",
1744 .srcs_n = 4,
1745 .src_components_n = {
1746 0,1,1,1
1747 },
1748 .idxs_n = 4,
1749 .idxs_map = {
1750 [NIR_INTRINSIC_IDX_WRMASK] = 1,
1751 [NIR_INTRINSIC_IDX_ACCESS] = 2,
1752 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 3,
1753 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 4
1754 }
1755 };
1756 struct nir_intrinsic nir_load_ssbo_ir3 = {
1757 .name = "load_ssbo_ir3",
1758 .srcs_n = 3,
1759 .src_components_n = {
1760 1,1,1
1761 },
1762 .has_dest = true,
1763 .idxs_n = 3,
1764 .idxs_map = {
1765 [NIR_INTRINSIC_IDX_ACCESS] = 1,
1766 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
1767 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
1768 },
1769 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1770 };
1771 struct nir_intrinsic nir_ssbo_atomic_add_ir3 = {
1772 .name = "ssbo_atomic_add_ir3",
1773 .srcs_n = 4,
1774 .src_components_n = {
1775 1,1,1,1
1776 },
1777 .has_dest = true,
1778 .dest_components_n = 1
1779 };
1780 struct nir_intrinsic nir_ssbo_atomic_imin_ir3 = {
1781 .name = "ssbo_atomic_imin_ir3",
1782 .srcs_n = 4,
1783 .src_components_n = {
1784 1,1,1,1
1785 },
1786 .has_dest = true,
1787 .dest_components_n = 1
1788 };
1789 struct nir_intrinsic nir_ssbo_atomic_umin_ir3 = {
1790 .name = "ssbo_atomic_umin_ir3",
1791 .srcs_n = 4,
1792 .src_components_n = {
1793 1,1,1,1
1794 },
1795 .has_dest = true,
1796 .dest_components_n = 1
1797 };
1798 struct nir_intrinsic nir_ssbo_atomic_imax_ir3 = {
1799 .name = "ssbo_atomic_imax_ir3",
1800 .srcs_n = 4,
1801 .src_components_n = {
1802 1,1,1,1
1803 },
1804 .has_dest = true,
1805 .dest_components_n = 1
1806 };
1807 struct nir_intrinsic nir_ssbo_atomic_umax_ir3 = {
1808 .name = "ssbo_atomic_umax_ir3",
1809 .srcs_n = 4,
1810 .src_components_n = {
1811 1,1,1,1
1812 },
1813 .has_dest = true,
1814 .dest_components_n = 1
1815 };
1816 struct nir_intrinsic nir_ssbo_atomic_and_ir3 = {
1817 .name = "ssbo_atomic_and_ir3",
1818 .srcs_n = 4,
1819 .src_components_n = {
1820 1,1,1,1
1821 },
1822 .has_dest = true,
1823 .dest_components_n = 1
1824 };
1825 struct nir_intrinsic nir_ssbo_atomic_or_ir3 = {
1826 .name = "ssbo_atomic_or_ir3",
1827 .srcs_n = 4,
1828 .src_components_n = {
1829 1,1,1,1
1830 },
1831 .has_dest = true,
1832 .dest_components_n = 1
1833 };
1834 struct nir_intrinsic nir_ssbo_atomic_xor_ir3 = {
1835 .name = "ssbo_atomic_xor_ir3",
1836 .srcs_n = 4,
1837 .src_components_n = {
1838 1,1,1,1
1839 },
1840 .has_dest = true,
1841 .dest_components_n = 1
1842 };
1843 struct nir_intrinsic nir_ssbo_atomic_exchange_ir3 = {
1844 .name = "ssbo_atomic_exchange_ir3",
1845 .srcs_n = 4,
1846 .src_components_n = {
1847 1,1,1,1
1848 },
1849 .has_dest = true,
1850 .dest_components_n = 1
1851 };
1852 struct nir_intrinsic nir_ssbo_atomic_swap_ir3 = {
1853 .name = "ssbo_atomic_swap_ir3",
1854 .srcs_n = 5,
1855 .src_components_n = {
1856 1,1,1,1,1
1857 },
1858 .has_dest = true,
1859 .dest_components_n = 1
1860 };
1861
1862 /******************************************************************************/
1863 /* AMD Shader ballot operations */
1864 struct nir_intrinsic nir_quad_swizzle_amd = {
1865 .name = "quad_swizzle_amd",
1866 .has_dest = true,
1867 .idxs_n = 1,
1868 .idxs_map = {
1869 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
1870 },
1871 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1872 };
1873 struct nir_intrinsic nir_masked_swizzle_amd = {
1874 .name = "masked_swizzle_amd",
1875 .has_dest = true,
1876 .idxs_n = 1,
1877 .idxs_map = {
1878 [NIR_INTRINSIC_IDX_SWIZZLE_MASK] = 1
1879 },
1880 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1881 };
1882 struct nir_intrinsic nir_write_invocation_amd = {
1883 .name = "write_invocation_amd",
1884 .srcs_n = 3,
1885 .src_components_n = {
1886 0,0,1
1887 },
1888 .has_dest = true,
1889 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1890 };
1891 struct nir_intrinsic nir_mbcnt_amd = {
1892 .name = "mbcnt_amd",
1893 .srcs_n = 1,
1894 .src_components_n = {
1895 1
1896 },
1897 .has_dest = true,
1898 .dest_components_n = 1,
1899 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1900 };
1901 /* AMD Shader ballot operations */
1902 /******************************************************************************/
1903
1904 /******************************************************************************/
1905 /*
1906 * Demote fragment shader invocation to a helper invocation. Any stores to
1907 * memory after this instruction are suppressed and the fragment does not write
1908 * outputs to the framebuffer. Unlike discard, demote needs to ensure that
1909 * derivatives will still work for invocations that were not demoted.
1910 *
1911 * As specified by SPV_EXT_demote_to_helper_invocation.
1912 */
1913 struct nir_intrinsic nir_demote = {
1914 .name = "demote"
1915 };
1916 struct nir_intrinsic nir_is_helper_invocation= {
1917 .name = "is_helper_invocation",
1918 .has_dest = true,
1919 .dest_components_n = 1,
1920 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1921 };
1922 /* Demote related */
1923 /******************************************************************************/
1924
1925 /******************************************************************************/
1926 /*
1927 * Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined
1928 * within a blend shader to read/write the raw value from the tile buffer,
1929 * without applying any format conversion in the process. If the shader needs
1930 * usable pixel values, it must apply format conversions itself.
1931 *
1932 * These definitions are generic, but they are explicitly vendored to prevent
1933 * other drivers from using them, as their semantics is defined in terms of the
1934 * Midgard/Bifrost hardware tile buffer and may not line up with anything sane.
1935 * One notable divergence is sRGB, which is asymmetric: raw_input_pan requires
1936 * an sRGB->linear conversion, but linear values should be written to
1937 * raw_output_pan and the hardware handles linear->sRGB.
1938 */
1939
1940 /* src[] = { value } */
1941 struct nir_intrinsic nir_store_raw_output_pan = {
1942 .name = "store_raw_output_pan",
1943 .srcs_n = 1,
1944 .src_components_n = {
1945 0
1946 }
1947 };
1948 struct nir_intrinsic nir_load_raw_output_pan = {
1949 .name = "load_raw_output_pan",
1950 .has_dest = true,
1951 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1952 };
1953
1954 /******************************************************************************/
1955 /*
1956 * V3D-specific instrinc for tile buffer color reads.
1957 *
1958 * The hardware requires that we read the samples and components of a pixel
1959 * in order, so we cannot eliminate or remove any loads in a sequence.
1960 *
1961 * src[] = { render_target }
1962 * BASE = sample index
1963 */
1964 struct nir_intrinsic nir_load_tlb_color_v3d = {
1965 .name = "load_tlb_color_v3d",
1966 .srcs_n = 1,
1967 .src_components_n = {
1968 1
1969 },
1970 .has_dest = true,
1971 .idxs_n = 2,
1972 .idxs_map = {
1973 [NIR_INTRINSIC_IDX_BASE] = 1,
1974 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
1975 }
1976 };
1977
1978 /*
1979 * V3D-specific instrinc for per-sample tile buffer color writes.
1980 *
1981 * The driver backend needs to identify per-sample color writes and emit
1982 * specific code for them.
1983 *
1984 * src[] = { value, render_target }
1985 * BASE = sample index
1986 */
1987 struct nir_intrinsic nir_store_tlb_sample_color_v3d = {
1988 .name = "store_tlb_sample_color_v3d",
1989 .srcs_n = 2,
1990 .src_components_n = {
1991 0,1
1992 },
1993 .idxs_n = 3,
1994 .idxs_map = {
1995 [NIR_INTRINSIC_IDX_BASE] = 1,
1996 [NIR_INTRINSIC_IDX_COMPONENT] = 2,
1997 [NIR_INTRINSIC_IDX_TYPE] = 3
1998 }
1999 };
2000 /* v3d */
2001 /******************************************************************************/
2002
2003 #include "nir_database_intrinsic_system_values.c"
2004 #include "nir_database_intrinsic_image.c"
2005 #include "nir_database_intrinsic_store.c"
2006 #include "nir_database_intrinsic_load.c"
101 #include "intrinsics/v3d/v3d.c"
102 /*----------------------------------------------------------------------------*/
103 #include "intrinsics/intel/image.c"
2007 104
2008 105 struct nir_intrinsic *nir_intrinsics[] = { struct nir_intrinsic *nir_intrinsics[] = {
2009 106 &nir_atomic_counter_add, &nir_atomic_counter_add,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
2335 432 &nir_load_shared_ir3, &nir_load_shared_ir3,
2336 433 /* git 4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc..a0c003007515e31c63e18f4a3c8abc86814143bf */ /* git 4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc..a0c003007515e31c63e18f4a3c8abc86814143bf */
2337 434 &nir_load_alpha_ref_float, &nir_load_alpha_ref_float,
2338 &nir_scoped_memory_barrier
435 &nir_scoped_memory_barrier,
436 /* git 538d2c33b86dd9e66a6e900ac8e1cda10a5bfc4d..9e440b8d0b982933650c7b600de1e4b6e33f9c7d */
437 &nir_load_hs_patch_stride_ir3,
438 &nir_load_tess_factor_base_ir3,
439 &nir_load_tess_param_base_ir3,
440 &nir_load_tcs_header_ir3,
441 &nir_cond_end_ir3,
442 &nir_end_patch_ir3,
443 &nir_load_global_ir3,
444 &nir_store_global_ir3
2339 445 }; };
File builders/mesa-vulkan-0/contrib/vk_enum_to_str.c added (mode: 100644) (index 0000000..e530e9a)
1 #include <stdio.h>
2 #include <vulkan/vulkan_core.h>
3
4 const char * vk_Result_to_str(VkResult input)
5 {
6 static char buf[32];
7 sprintf(buf, "%ld", input);
8 return buf;
9 }
File builders/mesa-vulkan-0/contrib/vk_enum_to_str.h added (mode: 100644) (index 0000000..a5f86fd)
1 #ifndef MESA_VK_ENUM_TO_STR_H
2 #define MESA_VK_ENUM_TO_STR_H
3 #include <vulkan/vulkan_core.h>
4 const char * vk_Result_to_str(VkResult input);
5 #endif
File builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index b56c2bb..1bb30ed)
... ... if test "${version-unset}" = unset; then
59 59 if test -f $src_dir/VERSION; then if test -f $src_dir/VERSION; then
60 60 version=$(cat $src_dir/VERSION) version=$(cat $src_dir/VERSION)
61 61 else else
62 version=19.0.0-devel
62 version=20.0.0-devel
63 63 fi fi
64 64 fi fi
65 65 #=============================================================================== #===============================================================================
 
... ... fi
83 83 # (for the gl gallium dri driver, it's a gnu ld version script) # (for the gl gallium dri driver, it's a gnu ld version script)
84 84 if test "${cc-unset}" = unset; then if test "${cc-unset}" = unset; then
85 85 cc="gcc -pipe -fPIC -O2 -c -static-libgcc -fvisibility=hidden \ cc="gcc -pipe -fPIC -O2 -c -static-libgcc -fvisibility=hidden \
86 -fno-math-errno -fno-trapping-math \
86 87 -I/nyan/glibc/current/include-linux" -I/nyan/glibc/current/include-linux"
87 88 fi fi
88 89
89 90 if test "${cxx-unset}" = unset; then if test "${cxx-unset}" = unset; then
90 91 cxx="g++ -pipe -fPIC -O2 -c -static-libgcc -static-libstdc++ \ cxx="g++ -pipe -fPIC -O2 -c -static-libgcc -static-libstdc++ \
92 -fno-math-errno -fno-trapping-math \
91 93 -fno-rtti -fvisibility=hidden -I/nyan/glibc/current/include-linux" -fno-rtti -fvisibility=hidden -I/nyan/glibc/current/include-linux"
92 94 fi fi
93 95
 
... ... fi
149 151 # VK_USE_PLATFORM_XLIB_KHR: # VK_USE_PLATFORM_XLIB_KHR:
150 152 # vulkan macro enabling x11/xlib platform support, linked to # vulkan macro enabling x11/xlib platform support, linked to
151 153 # VK_USE_PLATFORM_XCB_KHR in the code # VK_USE_PLATFORM_XCB_KHR in the code
154 # VK_USE_PLATFORM_XLIB_XRANDR_EXT:
155 # xrandr stuff for vulkan
152 156 # #
153 157 # XXX: removed macros which seem not to be related # XXX: removed macros which seem not to be related
154 158 # - HAVE_X11_PLATFORM: gallium video layer (vl), and egl # - HAVE_X11_PLATFORM: gallium video layer (vl), and egl
 
... ... gcc_attributes_cppflags="\
215 219 -DHAVE_FUNC_ATTRIBUTE_VISIBILITY=1 \ -DHAVE_FUNC_ATTRIBUTE_VISIBILITY=1 \
216 220 -DHAVE_FUNC_ATTRIBUTE_ALIAS=1 \ -DHAVE_FUNC_ATTRIBUTE_ALIAS=1 \
217 221 -DHAVE_FUNC_ATTRIBUTE_NORETURN=1 \ -DHAVE_FUNC_ATTRIBUTE_NORETURN=1 \
222 -DHAVE_FUNC_ATTRIBUTE_UINT128=1 \
218 223 " "
219 224
220 225 linux_glibc_cppflags="\ linux_glibc_cppflags="\
221 226 -D_GNU_SOURCE \ -D_GNU_SOURCE \
222 227 -DHAVE_PTHREAD \ -DHAVE_PTHREAD \
228 -DHAVE_PTHREAD_SETAFFINITY \
223 229 -DHAVE_POSIX_MEMALIGN \ -DHAVE_POSIX_MEMALIGN \
224 230 -DHAVE_STRTOF \ -DHAVE_STRTOF \
225 231 -DHAVE_TIMESPEC_GET \ -DHAVE_TIMESPEC_GET \
 
... ... mesa_cppflags="\
237 243 " "
238 244
239 245 mesa_vulkan_cppflags="\ mesa_vulkan_cppflags="\
246 -DVK_USE_PLATFORM_DISPLAY_KHR \
240 247 -DVK_USE_PLATFORM_XCB_KHR \ -DVK_USE_PLATFORM_XCB_KHR \
241 248 -DVK_USE_PLATFORM_XLIB_KHR \ -DVK_USE_PLATFORM_XLIB_KHR \
249 -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
242 250 " "
243 251
244 252 cppflags_common="\ cppflags_common="\
 
... ... fi
308 316 #=============================================================================== #===============================================================================
309 317
310 318
319 #===============================================================================
320 if test "${libxrender_cppflags-unset}" = unset; then
321 libxrender_cppflags='-I/nyan/libXrender/current/include'
322 fi
323
324 if test "${libxrender_ldflags-unset}" = unset; then
325 libxrender_ldflags="/nyan/libXrender/current/lib/libXrender.so"
326 fi
327 #===============================================================================
328
329
330 #===============================================================================
331 if test "${libxrandr_cppflags-unset}" = unset; then
332 libxrandr_cppflags='-I/nyan/libXrandr/current/include'
333 fi
334
335 if test "${libxrandr_ldflags-unset}" = unset; then
336 libxrandr_ldflags="/nyan/libXrandr/current/lib/libXrandr.so"
337 fi
338 #===============================================================================
339
340
311 341 #=============================================================================== #===============================================================================
312 342 if test "${libx11_cppflags-unset}" = unset; then if test "${libx11_cppflags-unset}" = unset; then
313 343 libx11_cppflags='-I/nyan/libX11/current/include' libx11_cppflags='-I/nyan/libX11/current/include'
 
... ... fi
387 417
388 418 #=============================================================================== #===============================================================================
389 419 if test "${zlib_cppflags-unset}" = unset; then if test "${zlib_cppflags-unset}" = unset; then
390 zlib_cppflags='-I/nyan/zlib/current/include'
420 zlib_cppflags='-I/nyan/zlib/current/include -DHAVE_ZLIB'
391 421 fi fi
392 422
393 423 if test "${zlib_archives-unset}" = unset; then if test "${zlib_archives-unset}" = unset; then
 
... ... $cc -o $build_dir/xmlconfig.o $src_dir/src/util/xmlconfig.c \
588 618 #=============================================================================== #===============================================================================
589 619 # vulkan util # vulkan util
590 620 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
591 # vk_enum_to_str.h and vk_enum_to_str.c
592 $build_cc -I$src_dir/contrib/ezxml \
593 $src_dir/contrib/generators/gen_enum_to_str/gen_enum_to_str.c \
594 -o $build_dir/gen_enum_to_str.o
595
596 $build_ccld $build_dir/ezxml.o $build_dir/gen_enum_to_str.o \
597 -o $build_dir/gen_enum_to_str
598
599 $build_dir/gen_enum_to_str $vulkan_api_xml $build_dir
621 #-------------------------------------------------------------------------------
622 # XXX: deprecated
623 ##### keep that here since some upstream updates don't get properly traced by git
624 ##### and going out of sync will break vulkan
625 ####export PYTHONPATH=$mako
626 ####$python3 $src_dir/src/vulkan/util/gen_enum_to_str.py \
627 ####--xml $vulkan_api_xml \
628 ####--outdir $build_dir
629 ####unset PYTHONPATH
630 #-------------------------------------------------------------------------------
631 #-------------------------------------------------------------------------------
632 # XXX: deprecated
633 #### vk_enum_to_str.h and vk_enum_to_str.c
634 ###$build_cc -I$src_dir/contrib/ezxml \
635 ###$src_dir/contrib/generators/gen_enum_to_str/gen_enum_to_str.c \
636 ###-o $build_dir/gen_enum_to_str.o
637 ###
638 ###$build_ccld $build_dir/ezxml.o $build_dir/gen_enum_to_str.o \
639 ###-o $build_dir/gen_enum_to_str
640 ###
641 ###$build_dir/gen_enum_to_str $vulkan_api_xml $build_dir
642 #-------------------------------------------------------------------------------
643 # XXX: new thingy
644 cp -f $src_dir/contrib/vk_enum_to_str.c $src_dir/contrib/vk_enum_to_str.h \
645 $build_dir
600 646 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
601 647 cppflags="\ cppflags="\
602 648 $cppflags_common \ $cppflags_common \
 
... ... $cppflags_common \
606 652 -I$src_dir/include \ -I$src_dir/include \
607 653 $libxcb_cppflags \ $libxcb_cppflags \
608 654 $libx11_cppflags \ $libx11_cppflags \
655 $libxrandr_cppflags \
656 $libxrender_cppflags \
609 657 $xorgproto_cppflags \ $xorgproto_cppflags \
610 658 " "
611 659 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
 
... ... $cppflags_common \
636 684 -I$src_dir/include/drm-uapi \ -I$src_dir/include/drm-uapi \
637 685 $libxcb_cppflags \ $libxcb_cppflags \
638 686 $libx11_cppflags \ $libx11_cppflags \
687 $libxrandr_cppflags \
688 $libxrender_cppflags \
639 689 $xorgproto_cppflags \ $xorgproto_cppflags \
640 690 $libxshmfence_cppflags \ $libxshmfence_cppflags \
641 691 $libdrm_cppflags \ $libdrm_cppflags \
 
... ... $cc $cppflags $src_dir/src/vulkan/wsi/wsi_common.c \
645 695 -o $build_dir/wsi_common.o & -o $build_dir/wsi_common.o &
646 696 $cc $cppflags $src_dir/src/vulkan/wsi/wsi_common_x11.c \ $cc $cppflags $src_dir/src/vulkan/wsi/wsi_common_x11.c \
647 697 -o $build_dir/wsi_common_x11.o & -o $build_dir/wsi_common_x11.o &
698 $cc $cppflags $src_dir/src/vulkan/wsi/wsi_common_display.c \
699 -o $build_dir/wsi_common_display.o &
648 700 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
649 701 rm -f $build_dir/libvulkan_wsi.a rm -f $build_dir/libvulkan_wsi.a
650 702 wait wait
651 703 $ar $build_dir/libvulkan_wsi.a \ $ar $build_dir/libvulkan_wsi.a \
652 704 $build_dir/wsi_common.o \ $build_dir/wsi_common.o \
653 $build_dir/wsi_common_x11.o
705 $build_dir/wsi_common_x11.o \
706 $build_dir/wsi_common_display.o
654 707 #=============================================================================== #===============================================================================
655 708
656 709
 
... ... $python3 $src_dir/src/amd/registers/makeregheader.py \
674 727 --guard AMDGFXREGS_H \ --guard AMDGFXREGS_H \
675 728 >$build_dir/amdgfxregs.h & >$build_dir/amdgfxregs.h &
676 729 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
730 #-------------------------------------------------------------------------------
731 ##### keep that here since some upstream updates don't get properly traced by git
732 ##### and going out of sync will break nir
733 ####export PYTHONPATH=$mako
734 ####$python3 $src_dir/src/compiler/nir/nir_builder_opcodes_h.py \
735 ####>$build_dir/nir_builder_opcodes.h &
736 ####
737 ####$python3 $src_dir/src/compiler/nir/nir_opcodes_h.py \
738 ####>$build_dir/nir_opcodes.h &
739 ####
740 ####$python3 $src_dir/src/compiler/nir/nir_intrinsics_h.py \
741 ####--outdir $build_dir &
742 ####unset PYTHONPATH
743 #-------------------------------------------------------------------------------
744 #-------------------------------------------------------------------------------
677 745 $build_cc -I$src/contrib/generators/nir \ $build_cc -I$src/contrib/generators/nir \
678 746 $src_dir/contrib/generators/nir/nir_builder_opcodes_h.c \ $src_dir/contrib/generators/nir/nir_builder_opcodes_h.c \
679 747 -o $build_dir/nir_builder_opcodes_h.o -o $build_dir/nir_builder_opcodes_h.o
 
... ... $src_dir/src/amd/addrlib/src/r800/ciaddrlib.cpp \
833 901 $src_dir/src/amd/addrlib/src/r800/egbaddrlib.cpp \ $src_dir/src/amd/addrlib/src/r800/egbaddrlib.cpp \
834 902 $src_dir/src/amd/addrlib/src/r800/siaddrlib.cpp \ $src_dir/src/amd/addrlib/src/r800/siaddrlib.cpp \
835 903 " "
904
836 905 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
837 906 for f in $libamdgpu_addrlib_files for f in $libamdgpu_addrlib_files
838 907 do do
 
... ... $python3 $src_dir/src/compiler/nir/nir_constant_expressions.py \
898 967 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
899 968 $python3 $src_dir/src/compiler/nir/nir_opt_algebraic.py \ $python3 $src_dir/src/compiler/nir/nir_opt_algebraic.py \
900 969 >$build_dir/nir_opt_algebraic.c & >$build_dir/nir_opt_algebraic.c &
970 #-------------------------------------------------------------------------------
971 #-------------------------------------------------------------------------------
972 ##### keep that here since some upstream updates don't get properly traced by git
973 ##### and going out of sync will break nir
974 ####$python3 $src_dir/src/compiler/nir/nir_opcodes_c.py \
975 ####>$build_dir/nir_opcodes.c &
976 ####
977 ####$python3 $src_dir/src/compiler/nir/nir_intrinsics_c.py \
978 ####--outdir $build_dir &
979 #-------------------------------------------------------------------------------
980 #-------------------------------------------------------------------------------
901 981 unset PYTHONPATH unset PYTHONPATH
902 982 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
903 983 # nir_intrinsics.c # nir_intrinsics.c
 
... ... $build_ccld $build_dir/nir_intrinsics_c.o \
910 990
911 991 $build_dir/nir_intrinsics_c >$build_dir/nir_intrinsics.c & $build_dir/nir_intrinsics_c >$build_dir/nir_intrinsics.c &
912 992 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
993 # nir_opcodes.c
913 994 $build_cc -I$src/contrib/generators/nir \ $build_cc -I$src/contrib/generators/nir \
914 995 $src_dir/contrib/generators/nir/nir_opcodes_c.c \ $src_dir/contrib/generators/nir/nir_opcodes_c.c \
915 996 -o $build_dir/nir_opcodes_c.o -o $build_dir/nir_opcodes_c.o
 
... ... $src_dir/src/compiler/nir/nir_serialize.c \
1062 1143 $src_dir/src/compiler/nir/nir_split_per_member_structs.c \ $src_dir/src/compiler/nir/nir_split_per_member_structs.c \
1063 1144 $src_dir/src/compiler/nir/nir_split_var_copies.c \ $src_dir/src/compiler/nir/nir_split_var_copies.c \
1064 1145 $src_dir/src/compiler/nir/nir_split_vars.c \ $src_dir/src/compiler/nir/nir_split_vars.c \
1146 $src_dir/src/compiler/nir/nir_strip.c \
1065 1147 $src_dir/src/compiler/nir/nir_sweep.c \ $src_dir/src/compiler/nir/nir_sweep.c \
1066 1148 $src_dir/src/compiler/nir/nir_to_lcssa.c \ $src_dir/src/compiler/nir/nir_to_lcssa.c \
1067 1149 $src_dir/src/compiler/nir/nir_validate.c \ $src_dir/src/compiler/nir/nir_validate.c \
 
... ... $cppflags_common \
1118 1200 $llvm_cppflags \ $llvm_cppflags \
1119 1201 $libxcb_cppflags \ $libxcb_cppflags \
1120 1202 $libx11_cppflags \ $libx11_cppflags \
1203 $libxrandr_cppflags \
1204 $libxrender_cppflags \
1121 1205 $xorgproto_cppflags \ $xorgproto_cppflags \
1122 1206 " "
1123 1207
 
... ... $src_dir/src/amd/compiler/aco_reduce_assign.cpp \
1134 1218 $src_dir/src/amd/compiler/aco_register_allocation.cpp \ $src_dir/src/amd/compiler/aco_register_allocation.cpp \
1135 1219 $src_dir/src/amd/compiler/aco_live_var_analysis.cpp \ $src_dir/src/amd/compiler/aco_live_var_analysis.cpp \
1136 1220 $src_dir/src/amd/compiler/aco_lower_bool_phis.cpp \ $src_dir/src/amd/compiler/aco_lower_bool_phis.cpp \
1221 $src_dir/src/amd/compiler/aco_lower_to_cssa.cpp \
1137 1222 $src_dir/src/amd/compiler/aco_lower_to_hw_instr.cpp \ $src_dir/src/amd/compiler/aco_lower_to_hw_instr.cpp \
1138 1223 $build_dir/aco_opcodes.cpp \ $build_dir/aco_opcodes.cpp \
1139 1224 $src_dir/src/amd/compiler/aco_optimizer.cpp \ $src_dir/src/amd/compiler/aco_optimizer.cpp \
 
... ... $src_dir/src/util/bitscan.c \
1186 1271 $src_dir/src/util/blob.c \ $src_dir/src/util/blob.c \
1187 1272 $src_dir/src/util/build_id.c \ $src_dir/src/util/build_id.c \
1188 1273 $src_dir/src/util/crc32.c \ $src_dir/src/util/crc32.c \
1274 $src_dir/src/util/dag.c \
1189 1275 $src_dir/src/util/debug.c \ $src_dir/src/util/debug.c \
1190 1276 $src_dir/src/util/disk_cache.c \ $src_dir/src/util/disk_cache.c \
1191 1277 $src_dir/src/util/double.c \ $src_dir/src/util/double.c \
 
... ... $src_dir/src/util/half_float.c \
1194 1280 $src_dir/src/util/hash_table.c \ $src_dir/src/util/hash_table.c \
1195 1281 $src_dir/src/util/mesa-sha1.c \ $src_dir/src/util/mesa-sha1.c \
1196 1282 $src_dir/src/util/os_file.c \ $src_dir/src/util/os_file.c \
1283 $src_dir/src/util/os_misc.c \
1197 1284 $src_dir/src/util/os_time.c \ $src_dir/src/util/os_time.c \
1198 1285 $src_dir/src/util/sha1/sha1.c \ $src_dir/src/util/sha1/sha1.c \
1199 1286 $src_dir/src/util/ralloc.c \ $src_dir/src/util/ralloc.c \
1200 1287 $src_dir/src/util/rand_xor.c \ $src_dir/src/util/rand_xor.c \
1288 $src_dir/src/util/rb_tree.c \
1201 1289 $src_dir/src/util/register_allocate.c \ $src_dir/src/util/register_allocate.c \
1202 1290 $src_dir/src/util/rgtc.c \ $src_dir/src/util/rgtc.c \
1203 1291 $src_dir/src/util/set.c \ $src_dir/src/util/set.c \
1204 1292 $src_dir/src/util/slab.c \ $src_dir/src/util/slab.c \
1205 1293 $src_dir/src/util/softfloat.c \ $src_dir/src/util/softfloat.c \
1294 $src_dir/src/util/sparse_array.c \
1206 1295 $src_dir/src/util/string_buffer.c \ $src_dir/src/util/string_buffer.c \
1207 1296 $src_dir/src/util/strtod.c \ $src_dir/src/util/strtod.c \
1208 1297 $src_dir/src/util/u_atomic.c \ $src_dir/src/util/u_atomic.c \
1298 $src_dir/src/util/u_cpu_detect.c \
1299 $src_dir/src/util/u_debug.c \
1300 $src_dir/src/util/u_math.c \
1209 1301 $src_dir/src/util/u_process.c \ $src_dir/src/util/u_process.c \
1210 1302 $src_dir/src/util/u_queue.c \ $src_dir/src/util/u_queue.c \
1211 1303 $src_dir/src/util/u_vector.c \ $src_dir/src/util/u_vector.c \
1212 1304 $src_dir/src/util/vma.c \ $src_dir/src/util/vma.c \
1213 1305 " "
1306
1214 1307 #------------------------------------------------------------------------------ #------------------------------------------------------------------------------
1215 1308 for f in $libmesautil_files for f in $libmesautil_files
1216 1309 do do
 
... ... $libdrm_cppflags \
1280 1373 $libdrm_amdgpu_cppflags \ $libdrm_amdgpu_cppflags \
1281 1374 $llvm_cppflags \ $llvm_cppflags \
1282 1375 $libx11_cppflags \ $libx11_cppflags \
1376 $libxrandr_cppflags \
1377 $libxrender_cppflags \
1283 1378 $libxcb_cppflags \ $libxcb_cppflags \
1284 1379 $xorgproto_cppflags \ $xorgproto_cppflags \
1285 1380 $libxshmfence_cppflags \ $libxshmfence_cppflags \
 
... ... $src_dir/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c \
1328 1423 $src_dir/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c \ $src_dir/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c \
1329 1424 \ \
1330 1425 $src_dir/src/amd/vulkan//radv_wsi_x11.c \ $src_dir/src/amd/vulkan//radv_wsi_x11.c \
1426 $src_dir/src/amd/vulkan//radv_wsi_display.c \
1331 1427 " "
1332 1428 #------------------------------------------------------------------------------ #------------------------------------------------------------------------------
1333 1429 wait wait
 
... ... driver_link_cmd="g++ -o $soname -Wl,-soname=$soname \
1384 1480 $libdrm_ldflags \ $libdrm_ldflags \
1385 1481 $libdrm_amdgpu_ldflags \ $libdrm_amdgpu_ldflags \
1386 1482 $libx11_ldflags \ $libx11_ldflags \
1483 $libxrandr_ldflags \
1484 $libxrender_ldflags \
1387 1485 $libxcb_ldflags \ $libxcb_ldflags \
1388 1486 $libxshmfence_ldflags \ $libxshmfence_ldflags \
1389 1487 -lpthread \ -lpthread \
File builders/mesa-vulkan-1/builder.sh changed (mode: 100644) (index 7e340e2..6296846)
1 1 src_name=mesa src_name=mesa
2 git_commit=4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc
2 git_commit=538d2c33b86dd9e66a6e900ac8e1cda10a5bfc4d
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 slot=1 slot=1
 
... ... s:LIB_INSTALL_DIR:/nyan/mesa-vulkan/$slot/lib:" \
42 42 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
43 43
44 44 # cleanup and tidying # cleanup and tidying
45 strip -s /nyan/mesa-vulkan/$slot/lib/libvulkan_radeon.so
45 ##strip -s /nyan/mesa-vulkan/$slot/lib/libvulkan_radeon.so
46 46
47 47 rm -Rf $build_dir $pkg_dir rm -Rf $build_dir $pkg_dir
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index fca205d..ffb671d)
1 1 #define NIR_INTRINSIC_SRCS_N_MAX 5 #define NIR_INTRINSIC_SRCS_N_MAX 5
2 2
3 /* A constant 'base' value that is added to an offset src */
3 4 #define NIR_INTRINSIC_IDX_BASE 1 #define NIR_INTRINSIC_IDX_BASE 1
5 /* For store instructions, a writemask */
4 6 #define NIR_INTRINSIC_IDX_WRMASK 2 #define NIR_INTRINSIC_IDX_WRMASK 2
7 /* The stream-id for GS emit_vertex/end_primitive intrinsics */
5 8 #define NIR_INTRINSIC_IDX_STREAM_ID 3 #define NIR_INTRINSIC_IDX_STREAM_ID 3
9 /* The clip-plane id for load_user_clip_plane intrinsics */
6 10 #define NIR_INTRINSIC_IDX_UCP_ID 4 #define NIR_INTRINSIC_IDX_UCP_ID 4
11 /*
12 * The amount of data, starting from BASE, that this instruction
13 * may access. This is used to provide bounds if the offset is
14 * not constant.
15 */
7 16 #define NIR_INTRINSIC_IDX_RANGE 5 #define NIR_INTRINSIC_IDX_RANGE 5
17 /*
18 * The vulkan descriptor set binding for vulkan_resource_index
19 * intrinsic
20 */
8 21 #define NIR_INTRINSIC_IDX_DESC_SET 6 #define NIR_INTRINSIC_IDX_DESC_SET 6
22 /*
23 * The vulkan descriptor set binding for vulkan_resource_index
24 * intrinsic
25 */
9 26 #define NIR_INTRINSIC_IDX_BINDING 7 #define NIR_INTRINSIC_IDX_BINDING 7
27 /* Component offset */
10 28 #define NIR_INTRINSIC_IDX_COMPONENT 8 #define NIR_INTRINSIC_IDX_COMPONENT 8
29 /* Interpolation mode (only meaningful for FS inputs) */
11 30 #define NIR_INTRINSIC_IDX_INTERP_MODE 9 #define NIR_INTRINSIC_IDX_INTERP_MODE 9
31 /* A binary nir_op to use when performing a reduction or scan operation */
12 32 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10
33 /* Cluster size for reduction operations */
13 34 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11
35 /* Parameter index for a load_param intrinsic */
14 36 #define NIR_INTRINSIC_IDX_PARAM_IDX 12 #define NIR_INTRINSIC_IDX_PARAM_IDX 12
37 /* Image dimensionality for image intrinsics */
15 38 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13
39 /* Non-zero if we are accessing an array image */
16 40 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14
41 /* Image format for image intrinsics */
17 42 #define NIR_INTRINSIC_IDX_FORMAT 15 #define NIR_INTRINSIC_IDX_FORMAT 15
43 /* Access qualifiers for image and memory access intrinsics */
18 44 #define NIR_INTRINSIC_IDX_ACCESS 16 #define NIR_INTRINSIC_IDX_ACCESS 16
19 45 #define NIR_INTRINSIC_IDX_DST_ACCESS 17 #define NIR_INTRINSIC_IDX_DST_ACCESS 17
20 46 #define NIR_INTRINSIC_IDX_SRC_ACCESS 18 #define NIR_INTRINSIC_IDX_SRC_ACCESS 18
47 /* Offset or address alignment */
21 48 #define NIR_INTRINSIC_IDX_ALIGN_MUL 19 #define NIR_INTRINSIC_IDX_ALIGN_MUL 19
22 49 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 20 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 20
50 /* The vulkan descriptor type for vulkan_resource_index */
23 51 #define NIR_INTRINSIC_IDX_DESC_TYPE 21 #define NIR_INTRINSIC_IDX_DESC_TYPE 21
52 /* The nir_alu_type of a uniform/input/output */
24 53 #define NIR_INTRINSIC_IDX_TYPE 22 #define NIR_INTRINSIC_IDX_TYPE 22
54 /* The swizzle mask for quad_swizzle_amd & masked_swizzle_amd */
25 55 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 23 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 23
56 /* Driver location of attribute */
26 57 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 24 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 24
27 #define NIR_INTRINSIC_IDXS_N_MAX 25
58 /* ordering and visibility of a memory operation */
59 #define NIR_INTRINSIC_IDX_MEMORY_SEMANTICS 25
60 /* Modes affected by a memory operation */
61 #define NIR_INTRINSIC_IDX_MEMORY_MODES 26
62 /* Scope of a memory operation */
63 #define NIR_INTRINSIC_IDX_MEMORY_SCOPE 27
64 #define NIR_INTRINSIC_IDXS_N_MAX 28
28 65
29 66 #define NIR_INTRINSIC_FLAGS_CAN_ELIMINATE 0x01 #define NIR_INTRINSIC_FLAGS_CAN_ELIMINATE 0x01
30 67 #define NIR_INTRINSIC_FLAGS_CAN_REORDER 0x02 #define NIR_INTRINSIC_FLAGS_CAN_REORDER 0x02
 
... ... struct nir_intrinsic nir_load_vulkan_descriptor = {
1075 1112 }, },
1076 1113 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1077 1114 }; };
1115 /*
1116 * Memory barrier with semantics analogous to the memoryBarrier() GLSL
1117 * intrinsic.
1118 */
1078 1119 struct nir_intrinsic nir_memory_barrier = { struct nir_intrinsic nir_memory_barrier = {
1079 1120 .name = "memory_barrier" .name = "memory_barrier"
1080 1121 }; };
1122 /*
1123 * Memory barrier with explicit scope. Follows the semantics of SPIR-V
1124 * OpMemoryBarrier, used to implement Vulkan Memory Model. Storage that the
1125 * barrierr applies is represented using NIR variable modes.
1126 */
1127 struct nir_intrinsic nir_scoped_memory_barrier = {
1128 .name = "scoped_memory_barrier",
1129 .idxs_n = 3,
1130 .idxs_map = {
1131 [NIR_INTRINSIC_IDX_MEMORY_SEMANTICS] = 1,
1132 [NIR_INTRINSIC_IDX_MEMORY_MODES] = 2,
1133 [NIR_INTRINSIC_IDX_MEMORY_SCOPE] = 3
1134 }
1135 };
1081 1136 struct nir_intrinsic nir_memory_barrier_atomic_counter = { struct nir_intrinsic nir_memory_barrier_atomic_counter = {
1082 1137 .name = "memory_barrier_atomic_counter" .name = "memory_barrier_atomic_counter"
1083 1138 }; };
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
2277 2332 &nir_load_gs_header_ir3, &nir_load_gs_header_ir3,
2278 2333 &nir_load_primitive_location_ir3, &nir_load_primitive_location_ir3,
2279 2334 &nir_store_shared_ir3, &nir_store_shared_ir3,
2280 &nir_load_shared_ir3
2335 &nir_load_shared_ir3,
2336 /* git 4c9b9ed5f9c83d97ce6ec37c0dd5bfed53f913dc..a0c003007515e31c63e18f4a3c8abc86814143bf */
2337 &nir_load_alpha_ref_float,
2338 &nir_scoped_memory_barrier
2281 2339 }; };
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_system_values.c changed (mode: 100644) (index b611084..0376800)
... ... static struct nir_intrinsic nir_load_helper_invocation = {
238 238 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER, .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
239 239 .system_value = true .system_value = true
240 240 }; };
241 static struct nir_intrinsic nir_load_alpha_ref_float = {
242 .name = "load_alpha_ref_float",
243 .has_dest = true,
244 .dest_components_n = 1,
245 .bit_szs = 0x20,
246 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
247 .system_value = true
248 };
241 249 static struct nir_intrinsic nir_load_layer_id = { static struct nir_intrinsic nir_load_layer_id = {
242 250 .name = "load_layer_id", .name = "load_layer_id",
243 251 .has_dest = true, .has_dest = true,
File builders/mesa-vulkan-1/contrib/generators/nir/nir_intrinsics_c.c changed (mode: 100644) (index a7067d7..ccec516)
... ... static char *idx_str(u8 idx)
120 120 case NIR_INTRINSIC_IDX_TYPE: return "NIR_INTRINSIC_TYPE"; case NIR_INTRINSIC_IDX_TYPE: return "NIR_INTRINSIC_TYPE";
121 121 case NIR_INTRINSIC_IDX_SWIZZLE_MASK: return "NIR_INTRINSIC_SWIZZLE_MASK"; case NIR_INTRINSIC_IDX_SWIZZLE_MASK: return "NIR_INTRINSIC_SWIZZLE_MASK";
122 122 case NIR_INTRINSIC_IDX_DRIVER_LOCATION: return "NIR_INTRINSIC_DRIVER_LOCATION"; case NIR_INTRINSIC_IDX_DRIVER_LOCATION: return "NIR_INTRINSIC_DRIVER_LOCATION";
123 case NIR_INTRINSIC_IDX_MEMORY_SEMANTICS:return "NIR_INTRINSIC_MEMORY_SEMANTICS";
124 case NIR_INTRINSIC_IDX_MEMORY_MODES: return "NIR_INTRINSIC_MEMORY_MODES";
125 case NIR_INTRINSIC_IDX_MEMORY_SCOPE: return "NIR_INTRINSIC_MEMORY_SCOPE";
123 126 } }
124 127 } }
125 128
File builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index b56c2bb..e65b950)
... ... fi
81 81 # all symbols are tagged hidden by default, then only the public symbol # all symbols are tagged hidden by default, then only the public symbol
82 82 # will be tagged public explicitely in the code (with extensions to C) # will be tagged public explicitely in the code (with extensions to C)
83 83 # (for the gl gallium dri driver, it's a gnu ld version script) # (for the gl gallium dri driver, it's a gnu ld version script)
84 #TODO: SWITCH BACK TO O2
84 85 if test "${cc-unset}" = unset; then if test "${cc-unset}" = unset; then
85 cc="gcc -pipe -fPIC -O2 -c -static-libgcc -fvisibility=hidden \
86 cc="gcc -pipe -fPIC -g -c -static-libgcc -fvisibility=hidden \
86 87 -I/nyan/glibc/current/include-linux" -I/nyan/glibc/current/include-linux"
87 88 fi fi
88 89
89 90 if test "${cxx-unset}" = unset; then if test "${cxx-unset}" = unset; then
90 cxx="g++ -pipe -fPIC -O2 -c -static-libgcc -static-libstdc++ \
91 cxx="g++ -pipe -fPIC -g -c -static-libgcc -static-libstdc++ \
91 92 -fno-rtti -fvisibility=hidden -I/nyan/glibc/current/include-linux" -fno-rtti -fvisibility=hidden -I/nyan/glibc/current/include-linux"
92 93 fi fi
93 94
 
... ... $cc -o $build_dir/xmlconfig.o $src_dir/src/util/xmlconfig.c \
588 589 #=============================================================================== #===============================================================================
589 590 # vulkan util # vulkan util
590 591 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
591 # vk_enum_to_str.h and vk_enum_to_str.c
592 $build_cc -I$src_dir/contrib/ezxml \
593 $src_dir/contrib/generators/gen_enum_to_str/gen_enum_to_str.c \
594 -o $build_dir/gen_enum_to_str.o
595
596 $build_ccld $build_dir/ezxml.o $build_dir/gen_enum_to_str.o \
597 -o $build_dir/gen_enum_to_str
598
599 $build_dir/gen_enum_to_str $vulkan_api_xml $build_dir
592 #-------------------------------------------------------------------------------
593 # keep that here since some upstream updates don't get properly traced by git
594 # and going out of sync will break vulkan
595 export PYTHONPATH=$mako
596 $python3 $src_dir/src/vulkan/util/gen_enum_to_str.py \
597 --xml $vulkan_api_xml \
598 --outdir $build_dir
599 unset PYTHONPATH
600 #-------------------------------------------------------------------------------
601 #-------------------------------------------------------------------------------
602 #### vk_enum_to_str.h and vk_enum_to_str.c
603 ###$build_cc -I$src_dir/contrib/ezxml \
604 ###$src_dir/contrib/generators/gen_enum_to_str/gen_enum_to_str.c \
605 ###-o $build_dir/gen_enum_to_str.o
606 ###
607 ###$build_ccld $build_dir/ezxml.o $build_dir/gen_enum_to_str.o \
608 ###-o $build_dir/gen_enum_to_str
609 ###
610 ###$build_dir/gen_enum_to_str $vulkan_api_xml $build_dir
600 611 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
601 612 cppflags="\ cppflags="\
602 613 $cppflags_common \ $cppflags_common \
 
... ... $python3 $src_dir/src/amd/registers/makeregheader.py \
674 685 --guard AMDGFXREGS_H \ --guard AMDGFXREGS_H \
675 686 >$build_dir/amdgfxregs.h & >$build_dir/amdgfxregs.h &
676 687 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
677 $build_cc -I$src/contrib/generators/nir \
678 $src_dir/contrib/generators/nir/nir_builder_opcodes_h.c \
679 -o $build_dir/nir_builder_opcodes_h.o
680
681 $build_ccld $build_dir/nir_builder_opcodes_h.o \
682 -o $build_dir/nir_builder_opcodes_h
683
684 $build_dir/nir_builder_opcodes_h >$build_dir/nir_builder_opcodes.h &
685 688 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
686 $build_cc -I$src/contrib/generators/nir \
687 $src_dir/contrib/generators/nir/nir_opcodes_h.c \
688 -o $build_dir/nir_opcodes_h.o
689 # keep that here since some upstream updates don't get properly traced by git
690 # and going out of sync will break nir
691 export PYTHONPATH=$mako
692 $python3 $src_dir/src/compiler/nir/nir_builder_opcodes_h.py \
693 >$build_dir/nir_builder_opcodes.h &
689 694
690 $build_ccld $build_dir/nir_opcodes_h.o \
691 -o $build_dir/nir_opcodes_h
695 $python3 $src_dir/src/compiler/nir/nir_opcodes_h.py \
696 >$build_dir/nir_opcodes.h &
692 697
693 $build_dir/nir_opcodes_h >$build_dir/nir_opcodes.h &
698 $python3 $src_dir/src/compiler/nir/nir_intrinsics_h.py \
699 --outdir $build_dir &
700 unset PYTHONPATH
694 701 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
695 # nir_intrinsics.h
696 $build_cc -I$src/contrib/generators/nir \
697 $src_dir/contrib/generators/nir/nir_intrinsics_h.c \
698 -o $build_dir/nir_intrinsics_h.o
699
700 $build_ccld $build_dir/nir_intrinsics_h.o \
701 -o $build_dir/nir_intrinsics_h
702
703 $build_dir/nir_intrinsics_h >$build_dir/nir_intrinsics.h &
702 #-------------------------------------------------------------------------------
703 ###$build_cc -I$src/contrib/generators/nir \
704 ###$src_dir/contrib/generators/nir/nir_builder_opcodes_h.c \
705 ###-o $build_dir/nir_builder_opcodes_h.o
706 ###
707 ###$build_ccld $build_dir/nir_builder_opcodes_h.o \
708 ###-o $build_dir/nir_builder_opcodes_h
709 ###
710 ###$build_dir/nir_builder_opcodes_h >$build_dir/nir_builder_opcodes.h &
711 ####-------------------------------------------------------------------------------
712 ###$build_cc -I$src/contrib/generators/nir \
713 ###$src_dir/contrib/generators/nir/nir_opcodes_h.c \
714 ###-o $build_dir/nir_opcodes_h.o
715 ###
716 ###$build_ccld $build_dir/nir_opcodes_h.o \
717 ###-o $build_dir/nir_opcodes_h
718 ###
719 ###$build_dir/nir_opcodes_h >$build_dir/nir_opcodes.h &
720 ####-------------------------------------------------------------------------------
721 #### nir_intrinsics.h
722 ###$build_cc -I$src/contrib/generators/nir \
723 ###$src_dir/contrib/generators/nir/nir_intrinsics_h.c \
724 ###-o $build_dir/nir_intrinsics_h.o
725 ###
726 ###$build_ccld $build_dir/nir_intrinsics_h.o \
727 ###-o $build_dir/nir_intrinsics_h
728 ###
729 ###$build_dir/nir_intrinsics_h >$build_dir/nir_intrinsics.h &
704 730 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
705 731 cppflags="\ cppflags="\
706 732 $cppflags_common \ $cppflags_common \
 
... ... $python3 $src_dir/src/compiler/nir/nir_constant_expressions.py \
898 924 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
899 925 $python3 $src_dir/src/compiler/nir/nir_opt_algebraic.py \ $python3 $src_dir/src/compiler/nir/nir_opt_algebraic.py \
900 926 >$build_dir/nir_opt_algebraic.c & >$build_dir/nir_opt_algebraic.c &
901 unset PYTHONPATH
902 927 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
903 # nir_intrinsics.c
904 $build_cc -I$src/contrib/generators/nir \
905 $src_dir/contrib/generators/nir/nir_intrinsics_c.c \
906 -o $build_dir/nir_intrinsics_c.o
907
908 $build_ccld $build_dir/nir_intrinsics_c.o \
909 -o $build_dir/nir_intrinsics_c
910
911 $build_dir/nir_intrinsics_c >$build_dir/nir_intrinsics.c &
912 928 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
913 $build_cc -I$src/contrib/generators/nir \
914 $src_dir/contrib/generators/nir/nir_opcodes_c.c \
915 -o $build_dir/nir_opcodes_c.o
929 # keep that here since some upstream updates don't get properly traced by git
930 # and going out of sync will break nir
931 $python3 $src_dir/src/compiler/nir/nir_opcodes_c.py \
932 >$build_dir/nir_opcodes.c &
916 933
917 $build_ccld $build_dir/nir_opcodes_c.o \
918 -o $build_dir/nir_opcodes_c
919
920 $build_dir/nir_opcodes_c >$build_dir/nir_opcodes.c &
934 $python3 $src_dir/src/compiler/nir/nir_intrinsics_c.py \
935 --outdir $build_dir &
936 #-------------------------------------------------------------------------------
937 #-------------------------------------------------------------------------------
938 unset PYTHONPATH
939 #-------------------------------------------------------------------------------
940 #### nir_intrinsics.c
941 ###$build_cc -I$src/contrib/generators/nir \
942 ###$src_dir/contrib/generators/nir/nir_intrinsics_c.c \
943 ###-o $build_dir/nir_intrinsics_c.o
944 ###
945 ###$build_ccld $build_dir/nir_intrinsics_c.o \
946 ###-o $build_dir/nir_intrinsics_c
947 ###
948 ###$build_dir/nir_intrinsics_c >$build_dir/nir_intrinsics.c &
949 ####-------------------------------------------------------------------------------
950 ###$build_cc -I$src/contrib/generators/nir \
951 ###$src_dir/contrib/generators/nir/nir_opcodes_c.c \
952 ###-o $build_dir/nir_opcodes_c.o
953 ###
954 ###$build_ccld $build_dir/nir_opcodes_c.o \
955 ###-o $build_dir/nir_opcodes_c
956 ###
957 ###$build_dir/nir_opcodes_c >$build_dir/nir_opcodes.c &
921 958 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
922 959 cppflags="\ cppflags="\
923 960 $cppflags_common \ $cppflags_common \
 
... ... $src_dir/src/compiler/nir/nir_serialize.c \
1062 1099 $src_dir/src/compiler/nir/nir_split_per_member_structs.c \ $src_dir/src/compiler/nir/nir_split_per_member_structs.c \
1063 1100 $src_dir/src/compiler/nir/nir_split_var_copies.c \ $src_dir/src/compiler/nir/nir_split_var_copies.c \
1064 1101 $src_dir/src/compiler/nir/nir_split_vars.c \ $src_dir/src/compiler/nir/nir_split_vars.c \
1102 $src_dir/src/compiler/nir/nir_strip.c \
1065 1103 $src_dir/src/compiler/nir/nir_sweep.c \ $src_dir/src/compiler/nir/nir_sweep.c \
1066 1104 $src_dir/src/compiler/nir/nir_to_lcssa.c \ $src_dir/src/compiler/nir/nir_to_lcssa.c \
1067 1105 $src_dir/src/compiler/nir/nir_validate.c \ $src_dir/src/compiler/nir/nir_validate.c \
 
... ... $src_dir/src/amd/compiler/aco_reduce_assign.cpp \
1134 1172 $src_dir/src/amd/compiler/aco_register_allocation.cpp \ $src_dir/src/amd/compiler/aco_register_allocation.cpp \
1135 1173 $src_dir/src/amd/compiler/aco_live_var_analysis.cpp \ $src_dir/src/amd/compiler/aco_live_var_analysis.cpp \
1136 1174 $src_dir/src/amd/compiler/aco_lower_bool_phis.cpp \ $src_dir/src/amd/compiler/aco_lower_bool_phis.cpp \
1175 $src_dir/src/amd/compiler/aco_lower_to_cssa.cpp \
1137 1176 $src_dir/src/amd/compiler/aco_lower_to_hw_instr.cpp \ $src_dir/src/amd/compiler/aco_lower_to_hw_instr.cpp \
1138 1177 $build_dir/aco_opcodes.cpp \ $build_dir/aco_opcodes.cpp \
1139 1178 $src_dir/src/amd/compiler/aco_optimizer.cpp \ $src_dir/src/amd/compiler/aco_optimizer.cpp \
 
... ... $src_dir/src/util/rgtc.c \
1203 1242 $src_dir/src/util/set.c \ $src_dir/src/util/set.c \
1204 1243 $src_dir/src/util/slab.c \ $src_dir/src/util/slab.c \
1205 1244 $src_dir/src/util/softfloat.c \ $src_dir/src/util/softfloat.c \
1245 $src_dir/src/util/sparse_array.c \
1206 1246 $src_dir/src/util/string_buffer.c \ $src_dir/src/util/string_buffer.c \
1207 1247 $src_dir/src/util/strtod.c \ $src_dir/src/util/strtod.c \
1208 1248 $src_dir/src/util/u_atomic.c \ $src_dir/src/util/u_atomic.c \
File builders/mplayer-0/builder.sh changed (mode: 100644) (index ca08736..9056f33)
1 1 src_name=mplayer src_name=mplayer
2 date=2019-10-24
2 date=2019-11-04
3 3 archive_name=$src_name-export-snapshot.tar.bz2 archive_name=$src_name-export-snapshot.tar.bz2
4 4 url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name
5 ffmpeg_git_commit=37d8ae9da8ac9f3dd01d30996b538c82ba4d8085
5 ffmpeg_git_commit=ec3d3fc65d06a9f7bc4d32b12b14a7c75e00484d
6 6
7 7 src_dir=$src_dir_root/$src_name-export-$date src_dir=$src_dir_root/$src_name-export-$date
8 8 cd $src_dir_root cd $src_dir_root
File builders/mplayer-1/builder.sh changed (mode: 100644) (index f22e73b..2be9fc8)
1 1 src_name=mplayer src_name=mplayer
2 date=2019-10-28
2 date=2019-11-11
3 3 archive_name=$src_name-export-snapshot.tar.bz2 archive_name=$src_name-export-snapshot.tar.bz2
4 4 url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name
5 ffmpeg_git_commit=68f623d64451a6ee8c81b6071ec68d6097c0f213
5 ffmpeg_git_commit=b25b6432a7345791c488fadba3bd1ac75ebb2cbb
6 6
7 7 src_dir=$src_dir_root/$src_name-export-$date src_dir=$src_dir_root/$src_name-export-$date
8 8 cd $src_dir_root cd $src_dir_root
File builders/vulkan-headers-0/builder.sh added (mode: 100644) (index 0000000..a362cc9)
1 src_name=vulkan-headers
2 git_commit=f3128cf6eaffeef6493b36dbfff732a249528bf7
3 git_url0=git://github.com/khronosgroup/$pkg_name
4
5 slot=0
6
7 pkg_dir=$pkgs_dir_root/$pkg_name
8 src_dir=$src_dir_root/$src_name
9 rm -Rf $pkg_dir
10 mkdir -p $pkgs_dir_root
11 cp -r $src_dir $pkg_dir
12
13 #-------------------------------------------------------------------------------
14
15 cd $pkg_dir
16
17 git checkout --force $git_commit
18 git reset --hard
19
20 #-------------------------------------------------------------------------------
21
22 install_dir=/nyan/vulkan-headers/$slot/include/vulkan
23 mkdir -p $install_dir
24 cp -r $pkg_dir/include/vulkan/* $install_dir
25
26 #-------------------------------------------------------------------------------
27
28 rm -Rf $pkg_dir
File builders/vulkan-loader-0/builder.sh added (mode: 100644) (index 0000000..9932929)
1 src_name=vulkan-loader
2 git_commit=81e965357555eee1a07af512824cfc1e5dd42173
3 git_url0=git://github.com/khronosgroup/vulkan-loadr
4
5 slot=0
6
7 src_dir=$src_dir_root/$src_name
8 pkg_dir=$pkgs_dir_root/$pkg_name
9 rm -Rf $pkg_dir
10 mkdir -p $pkgs_dir_root
11 cp -r $src_dir $pkg_dir
12
13 cd $pkg_dir
14
15 git checkout --force $git_commit
16 git reset --hard
17
18 # install our canonical build system from the contrib dir
19 cp -rf $nyan_root/builders/$pkg_name/contrib $pkg_dir
20
21 build_dir=$builds_dir_root/$pkg_name
22 rm -Rf $build_dir
23 mkdir -p $build_dir
24 cd $build_dir
25
26 $pkg_dir/contrib/x86_64_linux_gnu_xlib_xcb.sh
27
28 #-------------------------------------------------------------------------------
29 # the pkgconfig is incomplete
30 sed -e "s:@CMAKE_INSTALL_PREFIX@:/nyan/vulkan-loader/$slot:" -i $build_dir/vulkan.pc
31 #-------------------------------------------------------------------------------
32
33 mkdir -p /nyan/vulkan-loader/$slot/lib/pkgconfig
34 cp -f $build_dir/libvulkan.so.1.*.* /nyan/vulkan-loader/$slot/lib
35 strip -s /nyan/vulkan-loader/$slot/lib/libvulkan.so.1.*.*
36
37 ln -sTf $(basename /nyan/vulkan-loader/$slot/lib/libvulkan.so.1.*.*) /nyan/vulkan-loader/$slot/lib/libvulkan.so.1
38 ln -sTf libvulkan.so.1 /nyan/vulkan-loader/$slot/lib/libvulkan.so
39
40 cp -f $build_dir/vulkan.pc /nyan/vulkan-loader/$slot/lib/pkgconfig
41
42 rm -Rf $build_dir $pkg_dir
File builders/vulkan-loader-0/contrib/loader_cmake_config.h added (mode: 100644) (index 0000000..8878ee1)
1 #define HAVE_SECURE_GETENV
2 #undef HAVE___SECURE_GETENV
File builders/vulkan-loader-0/contrib/x86_64_linux_gnu_xlib_xcb.sh added (mode: 100755) (index 0000000..f45fb46)
1 #!/bin/sh
2
3 # Canonical specialized build scripts on gnu/linux distros.
4 # Look for "unset", you'll find the values you can override in $1 or
5 # $build_dir/local_conf.sh file, that in order to tune the script for your
6 # specific distro/needs.
7
8 # Usage, drop the script at the top of mesa source tree, create somewhere else
9 # a build directory, cd into it, and call from there this script.
10 #===============================================================================
11
12 set -e
13
14 #===============================================================================
15 # build dir and src dir
16 build_dir=$(readlink -e .)
17 echo "build_dir=$build_dir"
18 # we are in contrib
19 src_dir=$(readlink -e $(dirname $0)/..)
20 echo "src_dir=$src_dir"
21 #===============================================================================
22
23
24 #===============================================================================
25 # the current configur-able variables may be individually overridden with the
26 # content of the file in $1 or $build_dir/local_conf.sh. Look for "unset"
27 # in those scripts to find what you can override to tune the build.
28 if test -f "$1"; then
29 . "$1"
30 else
31 if test -f $build_dir/local_conf.sh; then
32 . $build_dir/local_conf.sh
33 fi
34 fi
35 #===============================================================================
36
37
38 #===============================================================================
39 if test "${sysconfdir-unset}" = unset; then
40 sysconfdir='/nyan/vulkan-loader/current/etc'
41 fi
42 #===============================================================================
43
44
45 #===============================================================================
46 if test "${libxcb_cppflags-unset}" = unset; then
47 libxcb_cppflags='-I/nyan/libxcb/current/include'
48 fi
49 #===============================================================================
50
51
52 #===============================================================================
53 if test "${xorgproto_cppflags-unset}" = unset; then
54 xorgproto_cppflags='-I/nyan/xorgproto/current/include'
55 fi
56 #===============================================================================
57
58
59 #===============================================================================
60 if test "${libx11_cppflags-unset}" = unset; then
61 libx11_cppflags='-I/nyan/libX11/current/include'
62 fi
63 #===============================================================================
64
65
66 #===============================================================================
67 if test "${libxrandr_cppflags-unset}" = unset; then
68 libxrandr_cppflags='-I/nyan/libXrandr/current/include'
69 fi
70 #===============================================================================
71
72
73 #===============================================================================
74 if test "${libxrender_cppflags-unset}" = unset; then
75 libxrender_cppflags='-I/nyan/libXrender/current/include'
76 fi
77 #===============================================================================
78
79
80 #===============================================================================
81 if test "${vulkan_headers-unset}" = unset; then
82 vulkan_headers=/nyan/vulkan-headers/current/include
83 fi
84
85 vk_major=0
86 vk_minor=0
87
88 egrep '^#define[[:space:]]+VK_API_VERSION.*VK_MAKE_VERSION' \
89 <$vulkan_headers/vulkan/vulkan_core.h \
90 >/tmp/hdr_lines
91
92 while IFS='' read -r l
93 do
94 major=$(echo "$l" | sed -E -e 's/^.+VK_MAKE_VERSION\(([[:digit:]]+),.+$/\1/')
95 minor=$(echo "$l" | sed -E -e 's/^.+VK_MAKE_VERSION\([[:digit:]]+,[[:space:]]*([[:digit:]]+).+$/\1/')
96 if test $major -gt $vk_major; then
97 vk_major=$major;
98 vk_minor=$minor;
99 else
100 if test $major -eq $vk_major; then
101 if test $minor -gt $vk_minor; then
102 vk_minor=$minor;
103 fi
104 fi
105 fi
106
107 done </tmp/hdr_lines
108
109 vk_patch=$(egrep '^#define[[:space:]]+VK_HEADER_VERSION' <$vulkan_headers/vulkan/vulkan_core.h \
110 | sed -E -e 's/^.+VK_HEADER_VERSION[[:space:]]+([[:digit:]]+).*$/\1/')
111
112 echo "vulkan headers version=$vk_major.$vk_minor.$vk_patch"
113 #===============================================================================
114
115
116 #===============================================================================
117 # build system compiler, _not_ the target compiler if you cross compile
118 if test "${build_cc-unset}" = unset; then
119 build_cc="gcc -pipe -O2 -c -I/nyan/glibc/current/include-linux"
120 fi
121 if test "${build_ccld-unset}" = unset; then
122 build_ccld="gcc -pipe -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib"
123 fi
124 #===============================================================================
125
126
127 #===============================================================================
128 # all symbols are tagged hidden by default, then only the public symbol
129 # will be tagged public explicitely in the code (with extensions to C)
130 if test "${cc-unset}" = unset; then
131 cc="gcc -pipe -fPIC -O2 -c -static-libgcc -fvisibility=hidden \
132 -fno-strict-aliasing -fno-builtin-memcmp \
133 -I/nyan/glibc/current/include-linux"
134 fi
135
136 if test "${ccas-unset}" = unset; then
137 ccas="gcc -pipe -c -fvisibility=hidden"
138 fi
139 #===============================================================================
140
141
142 #===============================================================================
143 cp $src_dir/contrib/loader_cmake_config.h $build_dir
144 #===============================================================================
145
146
147 #===============================================================================
148 # generate and do assemble some assembler for fast procedure call dispatch
149 $build_cc $src_dir/loader/asm_offset.c -o $build_dir/asm_offset.o \
150 -I$build_dir \
151 -I$src_dir/loader/generated \
152 -I$src_dir/loader \
153 -I$vulkan_headers
154 $build_ccld $build_dir/asm_offset.o -o $build_dir/asm_offset
155
156 # will generate $build_dir/gen_defines.asm
157 old_pwd=$PWD
158 cd $build_dir
159 $build_dir/asm_offset GAS
160 cd $old_pwd
161
162 $ccas $src_dir/loader/unknown_ext_chain_gas.S \
163 -o $build_dir/unknown_ext_chain_gas.o \
164 -I$build_dir &
165 loader_objs="$loader_objs $build_dir/unknown_ext_chain_gas.o"
166 #===============================================================================
167
168
169 #===============================================================================
170 cppflags="\
171 -I$build_dir \
172 -I$src_dir/loader/generated \
173 -I$src_dir/loader \
174 -I$vulkan_headers \
175 $libxcb_cppflags \
176 $libx11_cppflags \
177 $xorgproto_cppflags \
178 $libxrandr_cppflags \
179 $libxrender_cppflags \
180 -DVK_USE_PLATFORM_XCB_KHR \
181 -DVK_USE_PLATFORM_XLIB_KHR \
182 -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
183 -DSYSCONFDIR=\"$sysconfdir\" \
184 -DFALLBACK_DATA_DIRS=\"/usr/local/share:/usr/share\" \
185 -DFALLBACK_CONFIG_DIRS=\"/etc/xdg\" \
186 "
187
188 normal_loader_c_files="\
189 $src_dir/loader/extension_manual.c \
190 $src_dir/loader/loader.c \
191 $src_dir/loader/trampoline.c \
192 $src_dir/loader/wsi.c \
193 $src_dir/loader/debug_utils.c \
194 $src_dir/loader/cJSON.c \
195 $src_dir/loader/murmurhash.c \
196 "
197
198 opt_loader_base_c_files="\
199 $src_dir/loader/dev_ext_trampoline.c \
200 $src_dir/loader/phys_dev_ext.c \
201 "
202
203 for f in $normal_loader_c_files $opt_loader_base_c_files
204 do
205 loader_obj=$build_dir/$(basename $f .c).o
206 loader_objs="$loader_objs $loader_obj"
207
208 $cc $cppflags $f -o $loader_obj &
209 done
210 #===============================================================================
211
212
213 #===============================================================================
214 wait
215
216 # XXX:the attempt to generalize without kludge the link stage of real program
217 # build is near a total and complete failure and allows sdk nasty kludges to
218 # sneak in
219 if test "${loader_link_cmd-unset}" = unset ; then
220 loader_link_cmd="gcc -o $build_dir/libvulkan.so.$vk_major.$vk_minor.$vk_patch -Wl,-soname=libvulkan.so.$vk_major \
221 -shared -static-libgcc \
222 -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib \
223 -Wl,--no-undefined,--gc-sections,-Bsymbolic \
224 $loader_objs \
225 -Wl,--as-needed \
226 -lpthread \
227 -ldl \
228 -lm \
229 -Wl,--no-as-needed"
230 fi
231 eval $loader_link_cmd
232 #===============================================================================
233
234
235 #===============================================================================
236 cp -f $src_dir/loader/vulkan.pc.in $build_dir/vulkan.pc
237 # from the last "project" command in cmake
238 sed -e "s:@CMAKE_PROJECT_NAME@:vulkan-loader:" -i $build_dir/vulkan.pc
239 sed -e "s:@CMAKE_INSTALL_LIBDIR@:lib:" -i $build_dir/vulkan.pc
240 sed -e "s:@VK_API_VERSION@:$vk_major.$vk_minor.$vk_patch:" -i $build_dir/vulkan.pc
241 sed -e "s:@PRIVATE_LIBS@::" -i $build_dir/vulkan.pc
242 #===============================================================================
File builders/xserver-0/builder.sh changed (mode: 100644) (index 9e53348..94b8325)
1 1 src_name=xserver src_name=xserver
2 git_commit=a1e3dfa50a9a9a41c93c12f19f40d97c56ddf850
2 git_commit=eddad048e35cbf0968d0f892009a248359a15ecd
3 3 git_url0=git://anongit.freedesktop.org/xorg/$src_name git_url0=git://anongit.freedesktop.org/xorg/$src_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/xserver-1/builder.sh changed (mode: 100644) (index 7f17b2e..d167607)
1 1 src_name=xserver src_name=xserver
2 git_commit=427f8bc00981703abe3153b6da575faa69fe2748
2 git_commit=622eea366aaf162479eaabd93c88fa04efe98bcc
3 3 git_url0=git://anongit.freedesktop.org/xorg/$src_name git_url0=git://anongit.freedesktop.org/xorg/$src_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
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