sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
gfx stack update ad4649440de4767f6c8e19d3fef195f83f5692df Sylvain BERTRAND 2019-09-02 18:44:20
cleanup the vim rc file for st 8e79fbae8dc9012e7375ab4f36cdbc257499ed0f Sylvain BERTRAND 2019-08-28 18:58:46
gfx stack update 88adf3214b48956bfb80123a488d63e5dbb894a2 Sylvain BERTRAND 2019-08-26 22:28:57
gfx stack update b1523ccd3b839a3283b81caac5b31f5925b1a53e Sylvain BERTRAND 2019-08-19 18:33:40
gfx stack update (llvm is broken) a7abbdfa6aa3f5590c495604532d643ad265c62f Sylvain BERTRAND 2019-08-12 23:30:59
gfx stack update 539eca82bea2aa97ecec53e0e3a0b3b542df954b Sylvain BERTRAND 2019-08-05 14:41:05
gfx stack update a45590fd2cf98c310a418e85767543228c12475f Sylvain BERTRAND 2019-07-30 03:14:12
gfx stack update a86caca36bb79689296c0faffe3ac321911ac66e Sylvain BERTRAND 2019-07-23 19:07:32
gfx stack update fae46b3c08698cfe4394ee04bbec3ab1339f67e4 Sylvain BERTRAND 2019-07-16 22:09:24
map generator script tidying a6d94608df12c1c7f96e5e3290f80b537cc2104f Sylvain BERTRAND 2019-07-12 18:14:16
gfx stack update 5570ddb901ca177ddaa00a302fd66c3f1a73275b Sylvain BERTRAND 2019-07-08 19:03:09
gfx stack update 2720626971b434e7ba2126e9aee38ded4739aaa4 Sylvain BERTRAND 2019-07-02 02:34:17
gfx stack update 98f523c2a571a4c5a9fd7a71b661fc32eec9851b Sylvain BERTRAND 2019-06-24 20:17:18
gfx stack update 7381ebddee043978f83504ddd36bc2e993ed147c Sylvain BERTRAND 2019-06-18 11:29:00
improve the tw heuristic hls downloader e6d7d5ab9d2d6de264091b7350e237bbc8c59e10 Sylvain BERTRAND 2019-06-18 11:27:52
gfx stack update 04d2687fb069b1cf7445c0fc6a80add4fae19657 Sylvain BERTRAND 2019-06-10 20:55:47
gfx stack update 0d480323653125a21612ddd4564ede9da79135b2 Sylvain BERTRAND 2019-06-03 21:00:33
curl/libcurl update c92ed686e0d395e4d799cb358e1a236dbe92e736 Sylvain BERTRAND 2019-05-31 12:36:28
google silent crap 4a7de70aa27cae0e92fcd899f71a1b929b4c4c3b Sylvain BERTRAND 2019-05-31 00:42:29
gfx stack update 4638d4a34e07b9559a568a8445ddcded092572e8 Sylvain BERTRAND 2019-05-27 12:06:23
Commit ad4649440de4767f6c8e19d3fef195f83f5692df - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2019-09-02 18:44
Committer name: Sylvain BERTRAND
Committer date (UTC): 2019-09-02 18:44
Parent(s): 8e79fbae8dc9012e7375ab4f36cdbc257499ed0f
Signer:
Signing key:
Signing status: N
Tree: a3720ee3c811ea1bd8d757dedeb89a3a9f150027
File Lines added Lines deleted
builders/ffmpeg-0/builder.sh 1 1
builders/llvm-0/builder.sh 1 1
builders/llvm-0/llvm-config 1 1
builders/mesa-gl-0/builder.sh 1 1
builders/mesa-gl-0/contrib/compiler_nir.sh 1 0
builders/mesa-gl-0/contrib/external_deps.sh 5 3
builders/mesa-vulkan-0/builder.sh 1 1
builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c 15 811
builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_image.c 0 0
builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 4 1
builders/mplayer-1/builder.sh 2 2
builders/xserver-1/builder.sh 1 1
File builders/ffmpeg-0/builder.sh changed (mode: 100644) (index 222c30e..6204a2d)
1 1 src_name=ffmpeg src_name=ffmpeg
2 git_commit=d0fa1a58da71492f665759e73c47daf04a9b658c
2 git_commit=6b57a294a32874c9cdc1de0310cbf1d693b4776f
3 3 git_url0=https://git.ffmpeg.org/$src_name.git git_url0=https://git.ffmpeg.org/$src_name.git
4 4
5 5 pkg_dir=$pkgs_dir_root/$pkg_name pkg_dir=$pkgs_dir_root/$pkg_name
File builders/llvm-0/builder.sh changed (mode: 100644) (index c8421bc..6e73e7c)
1 1 src_name=llvm src_name=llvm
2 git_commit=c81cf445a3132cf48fbe8f75f0314cbd346d87ab
2 git_commit=fe8bd23157bb34bc5f5d99ae6a905a9b9b746639
3 3 git_url0=http://llvm.org/git/llvm.git git_url0=http://llvm.org/git/llvm.git
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/llvm-0/llvm-config changed (mode: 100755) (index aff072d..2864c32)
... ... do
22 22 echo "AMDGPU" echo "AMDGPU"
23 23 ;; ;;
24 24 --version) --version)
25 echo "9.0.0svn"
25 echo "10.0.0svn"
26 26 ;; ;;
27 27 --cppflags) --cppflags)
28 28 echo "-I$LLVM_CONFIG_TARGET_SYSROOT/nyan/llvm/0/include -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS" echo "-I$LLVM_CONFIG_TARGET_SYSROOT/nyan/llvm/0/include -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS"
File builders/mesa-gl-0/builder.sh changed (mode: 100644) (index 0fefa78..3d5cb59)
1 1 src_name=mesa src_name=mesa
2 git_commit=c550d367a747472ee71ed4c99e210174730aa82b
2 git_commit=87fa8d9ebc0dcd8c0ba1405d590ee6337fce69ba
3 3 git_url0=git://anongit.freedesktop.org/mesa/$pkg_name git_url0=git://anongit.freedesktop.org/mesa/$pkg_name
4 4
5 5 slot=0 slot=0
File builders/mesa-gl-0/contrib/compiler_nir.sh changed (mode: 100644) (index 80b49be..20d31c8)
... ... $src_dir/src/compiler/nir/nir_builtin_builder.c \
42 42 $src_dir/src/compiler/nir/nir_clone.c \ $src_dir/src/compiler/nir/nir_clone.c \
43 43 $src_dir/src/compiler/nir/nir_control_flow.c \ $src_dir/src/compiler/nir/nir_control_flow.c \
44 44 $src_dir/src/compiler/nir/nir_deref.c \ $src_dir/src/compiler/nir/nir_deref.c \
45 $src_dir/src/compiler/nir/nir_divergence_analysis.c \
45 46 $src_dir/src/compiler/nir/nir_dominance.c \ $src_dir/src/compiler/nir/nir_dominance.c \
46 47 $src_dir/src/compiler/nir/nir_from_ssa.c \ $src_dir/src/compiler/nir/nir_from_ssa.c \
47 48 $src_dir/src/compiler/nir/nir_gather_info.c \ $src_dir/src/compiler/nir/nir_gather_info.c \
File builders/mesa-gl-0/contrib/external_deps.sh changed (mode: 100644) (index 07e4462..0c98063)
... ... fi
214 214 #=============================================================================== #===============================================================================
215 215 # llvm related configuration # llvm related configuration
216 216 # the following are values from the llvm-config script # the following are values from the llvm-config script
217 llvm_version=0x0900
218 llvm_version_str='9.0.0svn'
217 llvm_version=0x0a00
218 llvm_version_str='10.0.0svn'
219 219
220 220 if test "${llvm_cppflags-unset}" = unset; then if test "${llvm_cppflags-unset}" = unset; then
221 221 llvm_cppflags="-I/nyan/llvm/current/include -DHAVE_LLVM=$llvm_version \ llvm_cppflags="-I/nyan/llvm/current/include -DHAVE_LLVM=$llvm_version \
 
... ... libLLVMSupport.a:\
284 284 libLLVMXRay.a:\ libLLVMXRay.a:\
285 285 libLLVMTarget.a:\ libLLVMTarget.a:\
286 286 libLLVMAMDGPUDisassembler.a:\ libLLVMAMDGPUDisassembler.a:\
287 libLLVMRuntimeDyld.a"
287 libLLVMRuntimeDyld.a:\
288 libLLVMTextAPI.a"
288 289 fi fi
289 290 if test "${llvm_ldflags-unset}" = unset; then if test "${llvm_ldflags-unset}" = unset; then
290 291 llvm_ldflags="\ llvm_ldflags="\
 
... ... llvm_ldflags="\
349 350 /nyan/llvm/current/lib/libLLVMTarget.a \ /nyan/llvm/current/lib/libLLVMTarget.a \
350 351 /nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \ /nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \
351 352 /nyan/llvm/current/lib/libLLVMRuntimeDyld.a \ /nyan/llvm/current/lib/libLLVMRuntimeDyld.a \
353 /nyan/llvm/current/lib/libLLVMTextAPI.a \
352 354 -Wl,--end-group \ -Wl,--end-group \
353 355 " "
354 356 external_deps_static_ldflags="$external_deps_static_ldflags $llvm_ldflags" external_deps_static_ldflags="$external_deps_static_ldflags $llvm_ldflags"
File builders/mesa-vulkan-0/builder.sh changed (mode: 100644) (index a58b38e..89b2cae)
1 1 src_name=mesa src_name=mesa
2 git_commit=c550d367a747472ee71ed4c99e210174730aa82b
2 git_commit=87fa8d9ebc0dcd8c0ba1405d590ee6337fce69ba
3 3 git_url0=git://anongit.freedesktop.org/mesa/$src_name git_url0=git://anongit.freedesktop.org/mesa/$src_name
4 4
5 5 slot=0 slot=0
File builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index 317d0b3..55e2d65)
... ... struct nir_intrinsic nir_global_atomic_xor = {
861 861 struct nir_intrinsic nir_group_memory_barrier = { struct nir_intrinsic nir_group_memory_barrier = {
862 862 .name = "group_memory_barrier" .name = "group_memory_barrier"
863 863 }; };
864 /******************************************************************************/
865 /*
866 * Image load, store and atomic intrinsics.
867 *
868 * All image intrinsics come in three versions. One which take an image target
869 * passed as a deref chain as the first source, one which takes an index as the
870 * first source, and one which takes a bindless handle as the first source.
871 * In the first version, the image variable contains the memory and layout
872 * qualifiers that influence the semantics of the intrinsic. In the second and
873 * third, the image format and access qualifiers are provided as constant
874 * indices.
875 *
876 * All image intrinsics take a four-coordinate vector and a sample index as
877 * 2nd and 3rd sources, determining the location within the image that will be
878 * accessed by the intrinsic. Components not applicable to the image target
879 * in use are undefined. Image store takes an additional four-component
880 * argument with the value to be written, and image atomic operations take
881 * either one or two additional scalar arguments with the same meaning as in
882 * the ARB_shader_image_load_store specification.
883 */
884 /*----------------------------------------------------------------------------*/
885 /* deref version */
886 struct nir_intrinsic nir_image_deref_load = {
887 .name = "image_deref_load",
888 .srcs_n = 3,
889 .src_components_n = {
890 1,4,1
891 },
892 .has_dest = true,
893 .dest_components_n = 0,
894 .idxs_n = 1,
895 .idxs_map = {
896 [NIR_INTRINSIC_IDX_ACCESS] = 1
897 },
898 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
899 };
900 struct nir_intrinsic nir_image_deref_store = {
901 .name = "image_deref_store",
902 .srcs_n = 4,
903 .src_components_n = {
904 1,4,1,0
905 },
906 .idxs_n = 1,
907 .idxs_map = {
908 [NIR_INTRINSIC_IDX_ACCESS] = 1
909 }
910 };
911 struct nir_intrinsic nir_image_deref_atomic_add = {
912 .name = "image_deref_atomic_add",
913 .srcs_n = 4,
914 .src_components_n = {
915 1,4,1,1
916 },
917 .has_dest = true,
918 .dest_components_n = 1,
919 .idxs_n = 1,
920 .idxs_map = {
921 [NIR_INTRINSIC_IDX_ACCESS] = 1
922 }
923 };
924 struct nir_intrinsic nir_image_deref_atomic_min = {
925 .name = "image_deref_atomic_min",
926 .srcs_n = 4,
927 .src_components_n = {
928 1,4,1,1
929 },
930 .has_dest = true,
931 .dest_components_n = 1,
932 .idxs_n = 1,
933 .idxs_map = {
934 [NIR_INTRINSIC_IDX_ACCESS] = 1
935 }
936 };
937 struct nir_intrinsic nir_image_deref_atomic_max = {
938 .name = "image_deref_atomic_max",
939 .srcs_n = 4,
940 .src_components_n = {
941 1,4,1,1
942 },
943 .has_dest = true,
944 .dest_components_n = 1,
945 .idxs_n = 1,
946 .idxs_map = {
947 [NIR_INTRINSIC_IDX_ACCESS] = 1
948 }
949 };
950 struct nir_intrinsic nir_image_deref_atomic_and = {
951 .name = "image_deref_atomic_and",
952 .srcs_n = 4,
953 .src_components_n = {
954 1,4,1,1
955 },
956 .has_dest = true,
957 .dest_components_n = 1,
958 .idxs_n = 1,
959 .idxs_map = {
960 [NIR_INTRINSIC_IDX_ACCESS] = 1
961 }
962 };
963 struct nir_intrinsic nir_image_deref_atomic_or = {
964 .name = "image_deref_atomic_or",
965 .srcs_n = 4,
966 .src_components_n = {
967 1,4,1,1
968 },
969 .has_dest = true,
970 .dest_components_n = 1,
971 .idxs_n = 1,
972 .idxs_map = {
973 [NIR_INTRINSIC_IDX_ACCESS] = 1
974 }
975 };
976 struct nir_intrinsic nir_image_deref_atomic_xor = {
977 .name = "image_deref_atomic_xor",
978 .srcs_n = 4,
979 .src_components_n = {
980 1,4,1,1
981 },
982 .has_dest = true,
983 .dest_components_n = 1,
984 .idxs_n = 1,
985 .idxs_map = {
986 [NIR_INTRINSIC_IDX_ACCESS] = 1
987 }
988 };
989 struct nir_intrinsic nir_image_deref_atomic_exchange = {
990 .name = "image_deref_atomic_exchange",
991 .srcs_n = 4,
992 .src_components_n = {
993 1,4,1,1
994 },
995 .has_dest = true,
996 .dest_components_n = 1,
997 .idxs_n = 1,
998 .idxs_map = {
999 [NIR_INTRINSIC_IDX_ACCESS] = 1
1000 }
1001 };
1002 struct nir_intrinsic nir_image_deref_atomic_comp_swap = {
1003 .name = "image_deref_atomic_comp_swap",
1004 .srcs_n = 5,
1005 .src_components_n = {
1006 1,4,1,1,1
1007 },
1008 .has_dest = true,
1009 .dest_components_n = 1,
1010 .idxs_n = 1,
1011 .idxs_map = {
1012 [NIR_INTRINSIC_IDX_ACCESS] = 1
1013 }
1014 };
1015 struct nir_intrinsic nir_image_deref_atomic_fadd = {
1016 .name = "image_deref_atomic_fadd",
1017 .srcs_n = 5,
1018 .src_components_n = {
1019 1,1,4,1,1
1020 },
1021 .has_dest = true,
1022 .dest_components_n = 1,
1023 .idxs_n = 1,
1024 .idxs_map = {
1025 [NIR_INTRINSIC_IDX_ACCESS] = 1
1026 }
1027 };
1028 struct nir_intrinsic nir_image_deref_size = {
1029 .name = "image_deref_size",
1030 .srcs_n = 1,
1031 .src_components_n = {
1032 1
1033 },
1034 .has_dest = true,
1035 .idxs_n = 1,
1036 .idxs_map = {
1037 [NIR_INTRINSIC_IDX_ACCESS] = 1
1038 },
1039 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1040 };
1041 struct nir_intrinsic nir_image_deref_samples = {
1042 .name = "image_deref_samples",
1043 .srcs_n = 1,
1044 .src_components_n = {
1045 1
1046 },
1047 .has_dest = true,
1048 .dest_components_n = 1,
1049 .idxs_n = 1,
1050 .idxs_map = {
1051 [NIR_INTRINSIC_IDX_ACCESS] = 1
1052 },
1053 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1054 };
1055 struct nir_intrinsic nir_image_deref_load_raw_intel = {
1056 .name = "image_deref_load_raw_intel",
1057 .srcs_n = 2,
1058 .src_components_n = {
1059 1,1
1060 },
1061 .has_dest = true,
1062 .idxs_n = 1,
1063 .idxs_map = {
1064 [NIR_INTRINSIC_IDX_ACCESS] = 1
1065 },
1066 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1067 };
1068 struct nir_intrinsic nir_image_deref_store_raw_intel = {
1069 .name = "image_deref_store_raw_intel",
1070 .srcs_n = 3,
1071 .src_components_n = {
1072 1,1,0
1073 },
1074 .idxs_n = 1,
1075 .idxs_map = {
1076 [NIR_INTRINSIC_IDX_ACCESS] = 1
1077 }
1078 };
1079 struct nir_intrinsic nir_image_deref_atomic_inc_wrap = {
1080 .name = "image_deref_atomic_inc_wrap",
1081 .srcs_n = 4,
1082 .src_components_n = {
1083 1,4,1,1
1084 },
1085 .has_dest = true,
1086 .dest_components_n = 1,
1087 .idxs_n = 1,
1088 .idxs_map = {
1089 [NIR_INTRINSIC_IDX_ACCESS] = 1
1090 }
1091 };
1092 struct nir_intrinsic nir_image_deref_atomic_dec_wrap = {
1093 .name = "image_deref_atomic_dec_wrap",
1094 .srcs_n = 4,
1095 .src_components_n = {
1096 1,4,1,1
1097 },
1098 .has_dest = true,
1099 .dest_components_n = 1,
1100 .idxs_n = 1,
1101 .idxs_map = {
1102 [NIR_INTRINSIC_IDX_ACCESS] = 1
1103 }
1104 };
1105 /* deref version */
1106 /*----------------------------------------------------------------------------*/
1107 /* plain version */
1108 struct nir_intrinsic nir_image_load = {
1109 .name = "image_load",
1110 .srcs_n = 3,
1111 .src_components_n = {
1112 1,4,1
1113 },
1114 .has_dest = true,
1115 .idxs_n = 4,
1116 .idxs_map = {
1117 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1118 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1119 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1120 [NIR_INTRINSIC_IDX_ACCESS] = 4
1121 },
1122 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1123 };
1124 struct nir_intrinsic nir_image_store = {
1125 .name = "image_store",
1126 .srcs_n = 4,
1127 .src_components_n = {
1128 1,4,1,0
1129 },
1130 .idxs_n = 4,
1131 .idxs_map = {
1132 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1133 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1134 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1135 [NIR_INTRINSIC_IDX_ACCESS] = 4
1136 }
1137 };
1138 struct nir_intrinsic nir_image_atomic_add = {
1139 .name = "image_atomic_add",
1140 .srcs_n = 4,
1141 .src_components_n = {
1142 1,4,1,1
1143 },
1144 .has_dest = true,
1145 .dest_components_n = 1,
1146 .idxs_n = 4,
1147 .idxs_map = {
1148 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1149 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1150 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1151 [NIR_INTRINSIC_IDX_ACCESS] = 4
1152 }
1153 };
1154 struct nir_intrinsic nir_image_atomic_min = {
1155 .name = "image_atomic_min",
1156 .srcs_n = 4,
1157 .src_components_n = {
1158 1,4,1,1
1159 },
1160 .has_dest = true,
1161 .dest_components_n = 1,
1162 .idxs_n = 4,
1163 .idxs_map = {
1164 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1165 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1166 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1167 [NIR_INTRINSIC_IDX_ACCESS] = 4
1168 }
1169 };
1170 struct nir_intrinsic nir_image_atomic_max = {
1171 .name = "image_atomic_max",
1172 .srcs_n = 4,
1173 .src_components_n = {
1174 1,4,1,1
1175 },
1176 .has_dest = true,
1177 .dest_components_n = 1,
1178 .idxs_n = 4,
1179 .idxs_map = {
1180 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1181 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1182 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1183 [NIR_INTRINSIC_IDX_ACCESS] = 4
1184 }
1185 };
1186 struct nir_intrinsic nir_image_atomic_and = {
1187 .name = "image_atomic_and",
1188 .srcs_n = 4,
1189 .src_components_n = {
1190 1,4,1,1
1191 },
1192 .has_dest = true,
1193 .dest_components_n = 1,
1194 .idxs_n = 4,
1195 .idxs_map = {
1196 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1197 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1198 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1199 [NIR_INTRINSIC_IDX_ACCESS] = 4
1200 }
1201 };
1202 struct nir_intrinsic nir_image_atomic_or = {
1203 .name = "image_atomic_or",
1204 .srcs_n = 4,
1205 .src_components_n = {
1206 1,4,1,1
1207 },
1208 .has_dest = true,
1209 .dest_components_n = 1,
1210 .idxs_n = 4,
1211 .idxs_map = {
1212 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1213 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1214 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1215 [NIR_INTRINSIC_IDX_ACCESS] = 4
1216 }
1217 };
1218 struct nir_intrinsic nir_image_atomic_xor = {
1219 .name = "image_atomic_xor",
1220 .srcs_n = 4,
1221 .src_components_n = {
1222 1,4,1,1
1223 },
1224 .has_dest = true,
1225 .dest_components_n = 1,
1226 .idxs_n = 4,
1227 .idxs_map = {
1228 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1229 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1230 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1231 [NIR_INTRINSIC_IDX_ACCESS] = 4
1232 }
1233 };
1234 struct nir_intrinsic nir_image_atomic_exchange = {
1235 .name = "image_atomic_exchange",
1236 .srcs_n = 4,
1237 .src_components_n = {
1238 1,4,1,1
1239 },
1240 .has_dest = true,
1241 .dest_components_n = 1,
1242 .idxs_n = 4,
1243 .idxs_map = {
1244 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1245 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1246 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1247 [NIR_INTRINSIC_IDX_ACCESS] = 4
1248 }
1249 };
1250 struct nir_intrinsic nir_image_atomic_comp_swap = {
1251 .name = "image_atomic_comp_swap",
1252 .srcs_n = 5,
1253 .src_components_n = {
1254 1,4,1,1,1
1255 },
1256 .has_dest = true,
1257 .dest_components_n = 1,
1258 .idxs_n = 4,
1259 .idxs_map = {
1260 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1261 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1262 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1263 [NIR_INTRINSIC_IDX_ACCESS] = 4
1264 }
1265 };
1266 struct nir_intrinsic nir_image_atomic_fadd = {
1267 .name = "image_atomic_fadd",
1268 .srcs_n = 5,
1269 .src_components_n = {
1270 1,1,4,1,1
1271 },
1272 .has_dest = true,
1273 .dest_components_n = 1,
1274 .idxs_n = 4,
1275 .idxs_map = {
1276 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1277 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1278 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1279 [NIR_INTRINSIC_IDX_ACCESS] = 4
1280 }
1281 };
1282 struct nir_intrinsic nir_image_size = {
1283 .name = "image_size",
1284 .srcs_n = 1,
1285 .src_components_n = {
1286 1
1287 },
1288 .has_dest = true,
1289 .idxs_n = 4,
1290 .idxs_map = {
1291 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1292 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1293 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1294 [NIR_INTRINSIC_IDX_ACCESS] = 4
1295 },
1296 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1297 };
1298 struct nir_intrinsic nir_image_samples = {
1299 .name = "image_samples",
1300 .srcs_n = 1,
1301 .src_components_n = {
1302 1
1303 },
1304 .has_dest = true,
1305 .dest_components_n = 1,
1306 .idxs_n = 4,
1307 .idxs_map = {
1308 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1309 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1310 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1311 [NIR_INTRINSIC_IDX_ACCESS] = 4
1312 },
1313 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1314 };
1315 struct nir_intrinsic nir_image_load_raw_intel = {
1316 .name = "image_load_raw_intel",
1317 .srcs_n = 2,
1318 .src_components_n = {
1319 1,1
1320 },
1321 .has_dest = true,
1322 .idxs_n = 4,
1323 .idxs_map = {
1324 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1325 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1326 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1327 [NIR_INTRINSIC_IDX_ACCESS] = 4
1328 },
1329 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1330 };
1331 struct nir_intrinsic nir_image_store_raw_intel = {
1332 .name = "image_store_raw_intel",
1333 .srcs_n = 3,
1334 .src_components_n = {
1335 1,1,0
1336 },
1337 .idxs_n = 4,
1338 .idxs_map = {
1339 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1340 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1341 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1342 [NIR_INTRINSIC_IDX_ACCESS] = 4
1343 }
1344 };
1345 struct nir_intrinsic nir_image_atomic_inc_wrap = {
1346 .name = "image_atomic_inc_wrap",
1347 .srcs_n = 4,
1348 .src_components_n = {
1349 1,4,1,1
1350 },
1351 .has_dest = true,
1352 .dest_components_n = 1,
1353 .idxs_n = 4,
1354 .idxs_map = {
1355 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1356 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1357 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1358 [NIR_INTRINSIC_IDX_ACCESS] = 4
1359 }
1360 };
1361 struct nir_intrinsic nir_image_atomic_dec_wrap = {
1362 .name = "image_atomic_dec_wrap",
1363 .srcs_n = 4,
1364 .src_components_n = {
1365 1,4,1,1
1366 },
1367 .has_dest = true,
1368 .dest_components_n = 1,
1369 .idxs_n = 4,
1370 .idxs_map = {
1371 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1372 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1373 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1374 [NIR_INTRINSIC_IDX_ACCESS] = 4
1375 }
1376 };
1377 /* plain version */
1378 /*----------------------------------------------------------------------------*/
1379 /* bindless version */
1380 struct nir_intrinsic nir_bindless_image_load = {
1381 .name = "bindless_image_load",
1382 .srcs_n = 3,
1383 .src_components_n = {
1384 1,4,1
1385 },
1386 .has_dest = true,
1387 .idxs_n = 4,
1388 .idxs_map = {
1389 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1390 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1391 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1392 [NIR_INTRINSIC_IDX_ACCESS] = 4
1393 },
1394 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1395 };
1396 struct nir_intrinsic nir_bindless_image_store = {
1397 .name = "bindless_image_store",
1398 .srcs_n = 4,
1399 .src_components_n = {
1400 1,4,1,0
1401 },
1402 .idxs_n = 4,
1403 .idxs_map = {
1404 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1405 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1406 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1407 [NIR_INTRINSIC_IDX_ACCESS] = 4
1408 }
1409 };
1410 struct nir_intrinsic nir_bindless_image_atomic_add = {
1411 .name = "bindless_image_atomic_add",
1412 .srcs_n = 4,
1413 .src_components_n = {
1414 1,4,1,1
1415 },
1416 .has_dest = true,
1417 .dest_components_n = 1,
1418 .idxs_n = 4,
1419 .idxs_map = {
1420 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1421 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1422 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1423 [NIR_INTRINSIC_IDX_ACCESS] = 4
1424 }
1425 };
1426 struct nir_intrinsic nir_bindless_image_atomic_min = {
1427 .name = "bindless_image_atomic_min",
1428 .srcs_n = 4,
1429 .src_components_n = {
1430 1,4,1,1
1431 },
1432 .has_dest = true,
1433 .dest_components_n = 1,
1434 .idxs_n = 4,
1435 .idxs_map = {
1436 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1437 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1438 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1439 [NIR_INTRINSIC_IDX_ACCESS] = 4
1440 }
1441 };
1442 struct nir_intrinsic nir_bindless_image_atomic_max = {
1443 .name = "bindless_image_atomic_max",
1444 .srcs_n = 4,
1445 .src_components_n = {
1446 1,4,1,1
1447 },
1448 .has_dest = true,
1449 .dest_components_n = 1,
1450 .idxs_n = 4,
1451 .idxs_map = {
1452 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1453 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1454 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1455 [NIR_INTRINSIC_IDX_ACCESS] = 4
1456 }
1457 };
1458 struct nir_intrinsic nir_bindless_image_atomic_and = {
1459 .name = "bindless_image_atomic_and",
1460 .srcs_n = 4,
1461 .src_components_n = {
1462 1,4,1,1
1463 },
1464 .has_dest = true,
1465 .dest_components_n = 1,
1466 .idxs_n = 4,
1467 .idxs_map = {
1468 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1469 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1470 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1471 [NIR_INTRINSIC_IDX_ACCESS] = 4
1472 }
1473 };
1474 struct nir_intrinsic nir_bindless_image_atomic_or = {
1475 .name = "bindless_image_atomic_or",
1476 .srcs_n = 4,
1477 .src_components_n = {
1478 1,4,1,1
1479 },
1480 .has_dest = true,
1481 .dest_components_n = 1,
1482 .idxs_n = 4,
1483 .idxs_map = {
1484 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1485 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1486 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1487 [NIR_INTRINSIC_IDX_ACCESS] = 4
1488 }
1489 };
1490 struct nir_intrinsic nir_bindless_image_atomic_xor = {
1491 .name = "bindless_image_atomic_xor",
1492 .srcs_n = 4,
1493 .src_components_n = {
1494 1,4,1,1
1495 },
1496 .has_dest = true,
1497 .dest_components_n = 1,
1498 .idxs_n = 4,
1499 .idxs_map = {
1500 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1501 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1502 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1503 [NIR_INTRINSIC_IDX_ACCESS] = 4
1504 }
1505 };
1506 struct nir_intrinsic nir_bindless_image_atomic_exchange = {
1507 .name = "bindless_image_atomic_exchange",
1508 .srcs_n = 4,
1509 .src_components_n = {
1510 1,4,1,1
1511 },
1512 .has_dest = true,
1513 .dest_components_n = 1,
1514 .idxs_n = 4,
1515 .idxs_map = {
1516 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1517 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1518 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1519 [NIR_INTRINSIC_IDX_ACCESS] = 4
1520 }
1521 };
1522 struct nir_intrinsic nir_bindless_image_atomic_comp_swap = {
1523 .name = "bindless_image_atomic_comp_swap",
1524 .srcs_n = 5,
1525 .src_components_n = {
1526 1,4,1,1,1
1527 },
1528 .has_dest = true,
1529 .dest_components_n = 1,
1530 .idxs_n = 4,
1531 .idxs_map = {
1532 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1533 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1534 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1535 [NIR_INTRINSIC_IDX_ACCESS] = 4
1536 }
1537 };
1538 struct nir_intrinsic nir_bindless_image_atomic_fadd = {
1539 .name = "bindless_image_atomic_fadd",
1540 .srcs_n = 5,
1541 .src_components_n = {
1542 1,1,4,1,1
1543 },
1544 .has_dest = true,
1545 .dest_components_n = 1,
1546 .idxs_n = 4,
1547 .idxs_map = {
1548 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1549 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1550 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1551 [NIR_INTRINSIC_IDX_ACCESS] = 4
1552 }
1553 };
1554 struct nir_intrinsic nir_bindless_image_size = {
1555 .name = "bindless_image_size",
1556 .srcs_n = 1,
1557 .src_components_n = {
1558 1
1559 },
1560 .has_dest = true,
1561 .idxs_n = 4,
1562 .idxs_map = {
1563 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1564 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1565 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1566 [NIR_INTRINSIC_IDX_ACCESS] = 4
1567 },
1568 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1569 };
1570 struct nir_intrinsic nir_bindless_image_samples = {
1571 .name = "bindless_image_samples",
1572 .srcs_n = 1,
1573 .src_components_n = {
1574 1
1575 },
1576 .has_dest = true,
1577 .dest_components_n = 1,
1578 .idxs_n = 4,
1579 .idxs_map = {
1580 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1581 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1582 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1583 [NIR_INTRINSIC_IDX_ACCESS] = 4
1584 },
1585 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1586 };
1587 struct nir_intrinsic nir_bindless_image_load_raw_intel = {
1588 .name = "bindless_image_load_raw_intel",
1589 .srcs_n = 2,
1590 .src_components_n = {
1591 1,1
1592 },
1593 .has_dest = true,
1594 .idxs_n = 4,
1595 .idxs_map = {
1596 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1597 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1598 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1599 [NIR_INTRINSIC_IDX_ACCESS] = 4
1600 },
1601 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1602 };
1603 struct nir_intrinsic nir_bindless_image_store_raw_intel = {
1604 .name = "bindless_image_store_raw_intel",
1605 .srcs_n = 3,
1606 .src_components_n = {
1607 1,1,0
1608 },
1609 .idxs_n = 4,
1610 .idxs_map = {
1611 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1612 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1613 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1614 [NIR_INTRINSIC_IDX_ACCESS] = 4
1615 }
1616 };
1617 struct nir_intrinsic nir_bindless_image_atomic_inc_wrap = {
1618 .name = "bindless_image_atomic_inc_wrap",
1619 .srcs_n = 4,
1620 .src_components_n = {
1621 1,4,1,1
1622 },
1623 .has_dest = true,
1624 .dest_components_n = 1,
1625 .idxs_n = 4,
1626 .idxs_map = {
1627 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1628 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1629 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1630 [NIR_INTRINSIC_IDX_ACCESS] = 4
1631 }
1632 };
1633 struct nir_intrinsic nir_bindless_image_atomic_dec_wrap = {
1634 .name = "bindless_image_atomic_dec_wrap",
1635 .srcs_n = 4,
1636 .src_components_n = {
1637 1,4,1,1
1638 },
1639 .has_dest = true,
1640 .dest_components_n = 1,
1641 .idxs_n = 4,
1642 .idxs_map = {
1643 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1644 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1645 [NIR_INTRINSIC_IDX_FORMAT] = 3,
1646 [NIR_INTRINSIC_IDX_ACCESS] = 4
1647 }
1648 };
1649 /* bindless version */
1650 /*----------------------------------------------------------------------------*/
1651 /* the following is solo */
1652 struct nir_intrinsic nir_image_deref_load_param_intel = {
1653 .name = "image_deref_load_param_intel",
1654 .srcs_n = 1,
1655 .src_components_n = {
1656 1
1657 },
1658 .has_dest = true,
1659 .dest_components_n = 0,
1660 .idxs_n = 1,
1661 .idxs_map = {
1662 [NIR_INTRINSIC_IDX_BASE] = 1
1663 },
1664 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
1665 };
1666 /* Image load, store and atomic intrinsics */
1667 /******************************************************************************/
1668 864 struct nir_intrinsic nir_inclusive_scan = { struct nir_intrinsic nir_inclusive_scan = {
1669 865 .name = "inclusive_scan", .name = "inclusive_scan",
1670 866 .srcs_n = 1, .srcs_n = 1,
 
... ... struct nir_intrinsic nir_store_tlb_sample_color_v3d = {
3088 2284 /******************************************************************************/ /******************************************************************************/
3089 2285
3090 2286 #include "nir_database_intrinsic_system_values.c" #include "nir_database_intrinsic_system_values.c"
2287 #include "nir_database_intrinsic_image.c"
3091 2288
3092 2289 struct nir_intrinsic *nir_intrinsics[] = { struct nir_intrinsic *nir_intrinsics[] = {
3093 2290 &nir_atomic_counter_add, &nir_atomic_counter_add,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
3169 2366 &nir_image_atomic_comp_swap, &nir_image_atomic_comp_swap,
3170 2367 &nir_image_atomic_exchange, &nir_image_atomic_exchange,
3171 2368 &nir_image_atomic_fadd, &nir_image_atomic_fadd,
3172 &nir_image_atomic_max,
3173 &nir_image_atomic_min,
3174 2369 &nir_image_atomic_or, &nir_image_atomic_or,
3175 2370 &nir_image_atomic_xor, &nir_image_atomic_xor,
3176 2371 &nir_image_deref_atomic_add, &nir_image_deref_atomic_add,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
3178 2373 &nir_image_deref_atomic_comp_swap, &nir_image_deref_atomic_comp_swap,
3179 2374 &nir_image_deref_atomic_exchange, &nir_image_deref_atomic_exchange,
3180 2375 &nir_image_deref_atomic_fadd, &nir_image_deref_atomic_fadd,
3181 &nir_image_deref_atomic_max,
3182 &nir_image_deref_atomic_min,
3183 2376 &nir_image_deref_atomic_or, &nir_image_deref_atomic_or,
3184 2377 &nir_image_deref_atomic_xor, &nir_image_deref_atomic_xor,
3185 2378 &nir_image_deref_load, &nir_image_deref_load,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
3346 2539 &nir_bindless_image_load, &nir_bindless_image_load,
3347 2540 &nir_bindless_image_store, &nir_bindless_image_store,
3348 2541 &nir_bindless_image_atomic_add, &nir_bindless_image_atomic_add,
3349 &nir_bindless_image_atomic_min,
3350 &nir_bindless_image_atomic_max,
3351 2542 &nir_bindless_image_atomic_and, &nir_bindless_image_atomic_and,
3352 2543 &nir_bindless_image_atomic_or, &nir_bindless_image_atomic_or,
3353 2544 &nir_bindless_image_atomic_xor, &nir_bindless_image_atomic_xor,
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
3403 2594 /* git 5ed4e31c08dc079473dd2e459c973355d49cd529..c550d367a747472ee71ed4c99e210174730aa82b */ /* git 5ed4e31c08dc079473dd2e459c973355d49cd529..c550d367a747472ee71ed4c99e210174730aa82b */
3404 2595 &nir_load_user_data_amd, &nir_load_user_data_amd,
3405 2596 &nir_load_tess_level_outer_default, &nir_load_tess_level_outer_default,
3406 &nir_load_tess_level_inner_default
2597 &nir_load_tess_level_inner_default,
2598 /* git c550d367a747472ee71ed4c99e210174730aa82b..f58e0405b6ca15d9b82122d82311e8b82f4a0939 */
2599 &nir_image_deref_atomic_imin,
2600 &nir_image_deref_atomic_imax,
2601 &nir_image_deref_atomic_umin,
2602 &nir_image_deref_atomic_umax,
2603 &nir_image_atomic_imin,
2604 &nir_image_atomic_imax,
2605 &nir_image_atomic_umin,
2606 &nir_image_atomic_umax,
2607 &nir_bindless_image_atomic_imin,
2608 &nir_bindless_image_atomic_imax,
2609 &nir_bindless_image_atomic_umin,
2610 &nir_bindless_image_atomic_umax
3407 2611 }; };
File builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_image.c copied from file builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_image.c (similarity 100%)
File builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index 1f9d8c4..3f5948c)
... ... libLLVMSupport.a:\
470 470 libLLVMXRay.a:\ libLLVMXRay.a:\
471 471 libLLVMTarget.a:\ libLLVMTarget.a:\
472 472 libLLVMAMDGPUDisassembler.a:\ libLLVMAMDGPUDisassembler.a:\
473 libLLVMRuntimeDyld.a"
473 libLLVMRuntimeDyld.a:\
474 libLLVMTextAPI.a"
474 475 fi fi
475 476
476 477 if test "${llvm_ldflags-unset}" = unset; then if test "${llvm_ldflags-unset}" = unset; then
 
... ... llvm_ldflags="\
536 537 /nyan/llvm/current/lib/libLLVMTarget.a \ /nyan/llvm/current/lib/libLLVMTarget.a \
537 538 /nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \ /nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \
538 539 /nyan/llvm/current/lib/libLLVMRuntimeDyld.a \ /nyan/llvm/current/lib/libLLVMRuntimeDyld.a \
540 /nyan/llvm/current/lib/libLLVMTextAPI.a \
539 541 -Wl,--end-group \ -Wl,--end-group \
540 542 " "
541 543 fi fi
 
... ... $src_dir/src/compiler/nir/nir_builtin_builder.c \
910 912 $src_dir/src/compiler/nir/nir_clone.c \ $src_dir/src/compiler/nir/nir_clone.c \
911 913 $src_dir/src/compiler/nir/nir_control_flow.c \ $src_dir/src/compiler/nir/nir_control_flow.c \
912 914 $src_dir/src/compiler/nir/nir_deref.c \ $src_dir/src/compiler/nir/nir_deref.c \
915 $src_dir/src/compiler/nir/nir_divergence_analysis.c \
913 916 $src_dir/src/compiler/nir/nir_dominance.c \ $src_dir/src/compiler/nir/nir_dominance.c \
914 917 $src_dir/src/compiler/nir/nir_from_ssa.c \ $src_dir/src/compiler/nir/nir_from_ssa.c \
915 918 $src_dir/src/compiler/nir/nir_gather_info.c \ $src_dir/src/compiler/nir/nir_gather_info.c \
File builders/mplayer-1/builder.sh changed (mode: 100644) (index 9e17f5d..6ee9f07)
1 1 src_name=mplayer src_name=mplayer
2 date=2019-08-19
2 date=2019-09-02
3 3 archive_name=$src_name-export-snapshot.tar.bz2 archive_name=$src_name-export-snapshot.tar.bz2
4 4 url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name
5 ffmpeg_git_commit=d0fa1a58da71492f665759e73c47daf04a9b658c
5 ffmpeg_git_commit=6b57a294a32874c9cdc1de0310cbf1d693b4776f
6 6
7 7 src_dir=$src_dir_root/$src_name-export-$date src_dir=$src_dir_root/$src_name-export-$date
8 8 cd $src_dir_root cd $src_dir_root
File builders/xserver-1/builder.sh changed (mode: 100644) (index a587c4f..85f675b)
1 1 src_name=xserver src_name=xserver
2 git_commit=aed62f8fbea3f618f97ee0105b2d430c8cddf8f5
2 git_commit=7d0e660e0e2808e098ab9d4de843e9b31c64af21
3 3 git_url0=git://anongit.freedesktop.org/xorg/$src_name git_url0=git://anongit.freedesktop.org/xorg/$src_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/nyanlinux

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Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/nyanlinux

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main