RocketGit

sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)

scripts for a lean, from scratch, amd hardware, linux distro

Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux

master

List of commits:

Subject	Hash	Author	Date (UTC)
gfx stack update	88adf3214b48956bfb80123a488d63e5dbb894a2	Sylvain BERTRAND	2019-08-26 22:28:57
gfx stack update	b1523ccd3b839a3283b81caac5b31f5925b1a53e	Sylvain BERTRAND	2019-08-19 18:33:40
gfx stack update (llvm is broken)	a7abbdfa6aa3f5590c495604532d643ad265c62f	Sylvain BERTRAND	2019-08-12 23:30:59
gfx stack update	539eca82bea2aa97ecec53e0e3a0b3b542df954b	Sylvain BERTRAND	2019-08-05 14:41:05
gfx stack update	a45590fd2cf98c310a418e85767543228c12475f	Sylvain BERTRAND	2019-07-30 03:14:12
gfx stack update	a86caca36bb79689296c0faffe3ac321911ac66e	Sylvain BERTRAND	2019-07-23 19:07:32
gfx stack update	fae46b3c08698cfe4394ee04bbec3ab1339f67e4	Sylvain BERTRAND	2019-07-16 22:09:24
map generator script tidying	a6d94608df12c1c7f96e5e3290f80b537cc2104f	Sylvain BERTRAND	2019-07-12 18:14:16
gfx stack update	5570ddb901ca177ddaa00a302fd66c3f1a73275b	Sylvain BERTRAND	2019-07-08 19:03:09
gfx stack update	2720626971b434e7ba2126e9aee38ded4739aaa4	Sylvain BERTRAND	2019-07-02 02:34:17
gfx stack update	98f523c2a571a4c5a9fd7a71b661fc32eec9851b	Sylvain BERTRAND	2019-06-24 20:17:18
gfx stack update	7381ebddee043978f83504ddd36bc2e993ed147c	Sylvain BERTRAND	2019-06-18 11:29:00
improve the tw heuristic hls downloader	e6d7d5ab9d2d6de264091b7350e237bbc8c59e10	Sylvain BERTRAND	2019-06-18 11:27:52
gfx stack update	04d2687fb069b1cf7445c0fc6a80add4fae19657	Sylvain BERTRAND	2019-06-10 20:55:47
gfx stack update	0d480323653125a21612ddd4564ede9da79135b2	Sylvain BERTRAND	2019-06-03 21:00:33
curl/libcurl update	c92ed686e0d395e4d799cb358e1a236dbe92e736	Sylvain BERTRAND	2019-05-31 12:36:28
google silent crap	4a7de70aa27cae0e92fcd899f71a1b929b4c4c3b	Sylvain BERTRAND	2019-05-31 00:42:29
gfx stack update	4638d4a34e07b9559a568a8445ddcded092572e8	Sylvain BERTRAND	2019-05-27 12:06:23
online map generator only in case of emergency	c50d534010ed0e53e372aad868891ac025b39af7	Sylvain BERTRAND	2019-05-23 22:33:05
gfx stack update	cb1dae4538e780bc0b61bd0b4e9dba754ec1ea64	Sylvain BERTRAND	2019-05-21 21:03:37

Commit 88adf3214b48956bfb80123a488d63e5dbb894a2 - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2019-08-26 22:28
Committer name: Sylvain BERTRAND
Committer date (UTC): 2019-08-26 22:28
Parent(s): b1523ccd3b839a3283b81caac5b31f5925b1a53e
Signer:
Signing key:
Signing status: N
Tree: f825c1fa8cb56e6eb9012bac6e510fa5606b1e2e

File	Lines added	Lines deleted
builders/ffmpeg-1/builder.sh	1	1
builders/llvm-1/builder.sh	1	1
builders/mesa-gl-1/builder.sh	2	2
builders/mesa-gl-1/contrib/compiler_nir.sh	4	3
builders/mesa-gl-1/contrib/external_deps.sh	3	1
builders/mesa-gl-1/contrib/gcc_binutils.sh	2	1
builders/mesa-vulkan-1/builder.sh	1	1
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c	21	1302
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_image.c	891	0
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_system_values.c	0	0
builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh	7	4
builders/mplayer-0/builder.sh	2	2
builders/xserver-0/builder.sh	1	1

File builders/ffmpeg-1/builder.sh changed (mode: 100644) (index 510c171..07518b6)
1	1	src_name=ffmpeg	src_name=ffmpeg
2		git_commit=faa9cd312f02cec5f74658319d1119fcaa7f9088
	2		git_commit=59da9dcd7ef6277e4e04998ced71b05a6083c635
3	3	git_url0=https://git.ffmpeg.org/$src_name.git	git_url0=https://git.ffmpeg.org/$src_name.git
4	4
5	5	pkg_dir=$pkgs_dir_root/$pkg_name	pkg_dir=$pkgs_dir_root/$pkg_name

File builders/llvm-1/builder.sh changed (mode: 100644) (index 2d4e6bf..4cc69fd)
1	1	src_name=llvm	src_name=llvm
2		git_commit=c3977501b64b26ab6d04883d6272ce43f2e18b37
	2		git_commit=d55ea9f2a73e1e933934c2216d96d8423b1a0379
3	3	git_url0=http://llvm.org/git/llvm.git	git_url0=http://llvm.org/git/llvm.git
4	4
5	5	src_dir=$src_dir_root/$src_name	src_dir=$src_dir_root/$src_name

File builders/mesa-gl-1/builder.sh changed (mode: 100644) (index f1481af..9fe8fe5)
1	1	src_name=mesa	src_name=mesa
2		git_commit=5ed4e31c08dc079473dd2e459c973355d49cd529
	2		git_commit=f58e0405b6ca15d9b82122d82311e8b82f4a0939
3	3	git_url0=git://anongit.freedesktop.org/mesa/$pkg_name	git_url0=git://anongit.freedesktop.org/mesa/$pkg_name
4	4
5	5	slot=1	slot=1

...	...	git checkout --force $git_commit
18	18	git reset --hard	git reset --hard
19	19
20	20	# copy the canonical lean build scripts	# copy the canonical lean build scripts
21		cp -r $nyan_root/builders/$pkg_name/contrib ./
	21		cp -r $nyan_root/builders/$pkg_name/contrib .
22	22
23	23	#-------------------------------------------------------------------------------	#-------------------------------------------------------------------------------
24	24

File builders/mesa-gl-1/contrib/external_deps.sh changed (mode: 100644) (index 07e4462..ac72252)
...	...	libLLVMSupport.a:\
284	284	libLLVMXRay.a:\	libLLVMXRay.a:\
285	285	libLLVMTarget.a:\	libLLVMTarget.a:\
286	286	libLLVMAMDGPUDisassembler.a:\	libLLVMAMDGPUDisassembler.a:\
287		libLLVMRuntimeDyld.a"
	287		libLLVMRuntimeDyld.a:\
	288		libLLVMTextAPI.a"
288	289	fi	fi
289	290	if test "${llvm_ldflags-unset}" = unset; then	if test "${llvm_ldflags-unset}" = unset; then
290	291	llvm_ldflags="\	llvm_ldflags="\

...	...	llvm_ldflags="\
349	350	/nyan/llvm/current/lib/libLLVMTarget.a \	/nyan/llvm/current/lib/libLLVMTarget.a \
350	351	/nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \	/nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \
351	352	/nyan/llvm/current/lib/libLLVMRuntimeDyld.a \	/nyan/llvm/current/lib/libLLVMRuntimeDyld.a \
	353		/nyan/llvm/current/lib/libLLVMTextAPI.a \
352	354	-Wl,--end-group \	-Wl,--end-group \
353	355	"	"
354	356	external_deps_static_ldflags="$external_deps_static_ldflags $llvm_ldflags"	external_deps_static_ldflags="$external_deps_static_ldflags $llvm_ldflags"

File builders/mesa-gl-1/contrib/gcc_binutils.sh changed (mode: 100644) (index dc05ffa..9063171)
...	...	if test "${cco_slib-unset}" = unset; then
4	4	cco_slib='gcc -fvisibility=hidden -static-libgcc -pipe -fPIC -std=c99 -c'	cco_slib='gcc -fvisibility=hidden -static-libgcc -pipe -fPIC -std=c99 -c'
5	5	fi	fi
6	6
	7		# llvm is now c++ crap from 2014
7	8	if test "${cxxo_slib-unset}" = unset; then	if test "${cxxo_slib-unset}" = unset; then
8		cxxo_slib='g++ -fvisibility=hidden -static-libgcc -static-libstdc++ -std=c++11 -fno-rtti -pipe -fPIC -c'
	9		cxxo_slib='g++ -fvisibility=hidden -static-libgcc -static-libstdc++ -std=c++14 -fno-rtti -pipe -fPIC -c'
9	10	fi	fi
10	11
11	12	if test "${cflags_opt-unset}" = unset; then	if test "${cflags_opt-unset}" = unset; then

File builders/mesa-vulkan-1/builder.sh changed (mode: 100644) (index d532ab8..db34530)
1	1	src_name=mesa	src_name=mesa
2		git_commit=5ed4e31c08dc079473dd2e459c973355d49cd529
	2		git_commit=f58e0405b6ca15d9b82122d82311e8b82f4a0939
3	3	git_url0=git://anongit.freedesktop.org/mesa/$src_name	git_url0=git://anongit.freedesktop.org/mesa/$src_name
4	4
5	5	slot=1	slot=1

File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index c03a4dc..55e2d65)
...	...	struct nir_intrinsic nir_global_atomic_xor = {
861	861	struct nir_intrinsic nir_group_memory_barrier = {	struct nir_intrinsic nir_group_memory_barrier = {
862	862	.name = "group_memory_barrier"	.name = "group_memory_barrier"
863	863	};	};
864		/******************************************************************************/
865		/*
866		* Image load, store and atomic intrinsics.
867		*
868		* All image intrinsics come in three versions. One which take an image target
869		* passed as a deref chain as the first source, one which takes an index as the
870		* first source, and one which takes a bindless handle as the first source.
871		* In the first version, the image variable contains the memory and layout
872		* qualifiers that influence the semantics of the intrinsic. In the second and
873		* third, the image format and access qualifiers are provided as constant
874		* indices.
875		*
876		* All image intrinsics take a four-coordinate vector and a sample index as
877		* 2nd and 3rd sources, determining the location within the image that will be
878		* accessed by the intrinsic. Components not applicable to the image target
879		* in use are undefined. Image store takes an additional four-component
880		* argument with the value to be written, and image atomic operations take
881		* either one or two additional scalar arguments with the same meaning as in
882		* the ARB_shader_image_load_store specification.
883		*/
884		/----------------------------------------------------------------------------/
885		/* deref version */
886		struct nir_intrinsic nir_image_deref_load = {
887		.name = "image_deref_load",
888		.srcs_n = 3,
889		.src_components_n = {
890		1,4,1
891		},
892		.has_dest = true,
893		.dest_components_n = 0,
894		.idxs_n = 1,
895		.idxs_map = {
896		[NIR_INTRINSIC_IDX_ACCESS] = 1
897		},
898		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
899		};
900		struct nir_intrinsic nir_image_deref_store = {
901		.name = "image_deref_store",
902		.srcs_n = 4,
903		.src_components_n = {
904		1,4,1,0
905		},
906		.idxs_n = 1,
907		.idxs_map = {
908		[NIR_INTRINSIC_IDX_ACCESS] = 1
909		}
910		};
911		struct nir_intrinsic nir_image_deref_atomic_add = {
912		.name = "image_deref_atomic_add",
913		.srcs_n = 4,
914		.src_components_n = {
915		1,4,1,1
916		},
917		.has_dest = true,
918		.dest_components_n = 1,
919		.idxs_n = 1,
920		.idxs_map = {
921		[NIR_INTRINSIC_IDX_ACCESS] = 1
922		}
923		};
924		struct nir_intrinsic nir_image_deref_atomic_min = {
925		.name = "image_deref_atomic_min",
926		.srcs_n = 4,
927		.src_components_n = {
928		1,4,1,1
929		},
930		.has_dest = true,
931		.dest_components_n = 1,
932		.idxs_n = 1,
933		.idxs_map = {
934		[NIR_INTRINSIC_IDX_ACCESS] = 1
935		}
936		};
937		struct nir_intrinsic nir_image_deref_atomic_max = {
938		.name = "image_deref_atomic_max",
939		.srcs_n = 4,
940		.src_components_n = {
941		1,4,1,1
942		},
943		.has_dest = true,
944		.dest_components_n = 1,
945		.idxs_n = 1,
946		.idxs_map = {
947		[NIR_INTRINSIC_IDX_ACCESS] = 1
948		}
949		};
950		struct nir_intrinsic nir_image_deref_atomic_and = {
951		.name = "image_deref_atomic_and",
952		.srcs_n = 4,
953		.src_components_n = {
954		1,4,1,1
955		},
956		.has_dest = true,
957		.dest_components_n = 1,
958		.idxs_n = 1,
959		.idxs_map = {
960		[NIR_INTRINSIC_IDX_ACCESS] = 1
961		}
962		};
963		struct nir_intrinsic nir_image_deref_atomic_or = {
964		.name = "image_deref_atomic_or",
965		.srcs_n = 4,
966		.src_components_n = {
967		1,4,1,1
968		},
969		.has_dest = true,
970		.dest_components_n = 1,
971		.idxs_n = 1,
972		.idxs_map = {
973		[NIR_INTRINSIC_IDX_ACCESS] = 1
974		}
975		};
976		struct nir_intrinsic nir_image_deref_atomic_xor = {
977		.name = "image_deref_atomic_xor",
978		.srcs_n = 4,
979		.src_components_n = {
980		1,4,1,1
981		},
982		.has_dest = true,
983		.dest_components_n = 1,
984		.idxs_n = 1,
985		.idxs_map = {
986		[NIR_INTRINSIC_IDX_ACCESS] = 1
987		}
988		};
989		struct nir_intrinsic nir_image_deref_atomic_exchange = {
990		.name = "image_deref_atomic_exchange",
991		.srcs_n = 4,
992		.src_components_n = {
993		1,4,1,1
994		},
995		.has_dest = true,
996		.dest_components_n = 1,
997		.idxs_n = 1,
998		.idxs_map = {
999		[NIR_INTRINSIC_IDX_ACCESS] = 1
1000		}
1001		};
1002		struct nir_intrinsic nir_image_deref_atomic_comp_swap = {
1003		.name = "image_deref_atomic_comp_swap",
1004		.srcs_n = 5,
1005		.src_components_n = {
1006		1,4,1,1,1
1007		},
1008		.has_dest = true,
1009		.dest_components_n = 1,
1010		.idxs_n = 1,
1011		.idxs_map = {
1012		[NIR_INTRINSIC_IDX_ACCESS] = 1
1013		}
1014		};
1015		struct nir_intrinsic nir_image_deref_atomic_fadd = {
1016		.name = "image_deref_atomic_fadd",
1017		.srcs_n = 5,
1018		.src_components_n = {
1019		1,1,4,1,1
1020		},
1021		.has_dest = true,
1022		.dest_components_n = 1,
1023		.idxs_n = 1,
1024		.idxs_map = {
1025		[NIR_INTRINSIC_IDX_ACCESS] = 1
1026		}
1027		};
1028		struct nir_intrinsic nir_image_deref_size = {
1029		.name = "image_deref_size",
1030		.srcs_n = 1,
1031		.src_components_n = {
1032		1
1033		},
1034		.has_dest = true,
1035		.idxs_n = 1,
1036		.idxs_map = {
1037		[NIR_INTRINSIC_IDX_ACCESS] = 1
1038		},
1039		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1040		};
1041		struct nir_intrinsic nir_image_deref_samples = {
1042		.name = "image_deref_samples",
1043		.srcs_n = 1,
1044		.src_components_n = {
1045		1
1046		},
1047		.has_dest = true,
1048		.dest_components_n = 1,
1049		.idxs_n = 1,
1050		.idxs_map = {
1051		[NIR_INTRINSIC_IDX_ACCESS] = 1
1052		},
1053		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1054		};
1055		struct nir_intrinsic nir_image_deref_load_raw_intel = {
1056		.name = "image_deref_load_raw_intel",
1057		.srcs_n = 2,
1058		.src_components_n = {
1059		1,1
1060		},
1061		.has_dest = true,
1062		.idxs_n = 1,
1063		.idxs_map = {
1064		[NIR_INTRINSIC_IDX_ACCESS] = 1
1065		},
1066		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1067		};
1068		struct nir_intrinsic nir_image_deref_store_raw_intel = {
1069		.name = "image_deref_store_raw_intel",
1070		.srcs_n = 3,
1071		.src_components_n = {
1072		1,1,0
1073		},
1074		.idxs_n = 1,
1075		.idxs_map = {
1076		[NIR_INTRINSIC_IDX_ACCESS] = 1
1077		}
1078		};
1079		struct nir_intrinsic nir_image_deref_atomic_inc_wrap = {
1080		.name = "image_deref_atomic_inc_wrap",
1081		.srcs_n = 4,
1082		.src_components_n = {
1083		1,4,1,1
1084		},
1085		.has_dest = true,
1086		.dest_components_n = 1,
1087		.idxs_n = 1,
1088		.idxs_map = {
1089		[NIR_INTRINSIC_IDX_ACCESS] = 1
1090		}
1091		};
1092		struct nir_intrinsic nir_image_deref_atomic_dec_wrap = {
1093		.name = "image_deref_atomic_dec_wrap",
1094		.srcs_n = 4,
1095		.src_components_n = {
1096		1,4,1,1
1097		},
1098		.has_dest = true,
1099		.dest_components_n = 1,
1100		.idxs_n = 1,
1101		.idxs_map = {
1102		[NIR_INTRINSIC_IDX_ACCESS] = 1
1103		}
1104		};
1105		/* deref version */
1106		/----------------------------------------------------------------------------/
1107		/* plain version */
1108		struct nir_intrinsic nir_image_load = {
1109		.name = "image_load",
1110		.srcs_n = 3,
1111		.src_components_n = {
1112		1,4,1
1113		},
1114		.has_dest = true,
1115		.idxs_n = 4,
1116		.idxs_map = {
1117		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1118		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1119		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1120		[NIR_INTRINSIC_IDX_ACCESS] = 4
1121		},
1122		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1123		};
1124		struct nir_intrinsic nir_image_store = {
1125		.name = "image_store",
1126		.srcs_n = 4,
1127		.src_components_n = {
1128		1,4,1,0
1129		},
1130		.idxs_n = 4,
1131		.idxs_map = {
1132		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1133		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1134		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1135		[NIR_INTRINSIC_IDX_ACCESS] = 4
1136		}
1137		};
1138		struct nir_intrinsic nir_image_atomic_add = {
1139		.name = "image_atomic_add",
1140		.srcs_n = 4,
1141		.src_components_n = {
1142		1,4,1,1
1143		},
1144		.has_dest = true,
1145		.dest_components_n = 1,
1146		.idxs_n = 4,
1147		.idxs_map = {
1148		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1149		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1150		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1151		[NIR_INTRINSIC_IDX_ACCESS] = 4
1152		}
1153		};
1154		struct nir_intrinsic nir_image_atomic_min = {
1155		.name = "image_atomic_min",
1156		.srcs_n = 4,
1157		.src_components_n = {
1158		1,4,1,1
1159		},
1160		.has_dest = true,
1161		.dest_components_n = 1,
1162		.idxs_n = 4,
1163		.idxs_map = {
1164		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1165		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1166		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1167		[NIR_INTRINSIC_IDX_ACCESS] = 4
1168		}
1169		};
1170		struct nir_intrinsic nir_image_atomic_max = {
1171		.name = "image_atomic_max",
1172		.srcs_n = 4,
1173		.src_components_n = {
1174		1,4,1,1
1175		},
1176		.has_dest = true,
1177		.dest_components_n = 1,
1178		.idxs_n = 4,
1179		.idxs_map = {
1180		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1181		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1182		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1183		[NIR_INTRINSIC_IDX_ACCESS] = 4
1184		}
1185		};
1186		struct nir_intrinsic nir_image_atomic_and = {
1187		.name = "image_atomic_and",
1188		.srcs_n = 4,
1189		.src_components_n = {
1190		1,4,1,1
1191		},
1192		.has_dest = true,
1193		.dest_components_n = 1,
1194		.idxs_n = 4,
1195		.idxs_map = {
1196		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1197		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1198		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1199		[NIR_INTRINSIC_IDX_ACCESS] = 4
1200		}
1201		};
1202		struct nir_intrinsic nir_image_atomic_or = {
1203		.name = "image_atomic_or",
1204		.srcs_n = 4,
1205		.src_components_n = {
1206		1,4,1,1
1207		},
1208		.has_dest = true,
1209		.dest_components_n = 1,
1210		.idxs_n = 4,
1211		.idxs_map = {
1212		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1213		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1214		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1215		[NIR_INTRINSIC_IDX_ACCESS] = 4
1216		}
1217		};
1218		struct nir_intrinsic nir_image_atomic_xor = {
1219		.name = "image_atomic_xor",
1220		.srcs_n = 4,
1221		.src_components_n = {
1222		1,4,1,1
1223		},
1224		.has_dest = true,
1225		.dest_components_n = 1,
1226		.idxs_n = 4,
1227		.idxs_map = {
1228		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1229		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1230		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1231		[NIR_INTRINSIC_IDX_ACCESS] = 4
1232		}
1233		};
1234		struct nir_intrinsic nir_image_atomic_exchange = {
1235		.name = "image_atomic_exchange",
1236		.srcs_n = 4,
1237		.src_components_n = {
1238		1,4,1,1
1239		},
1240		.has_dest = true,
1241		.dest_components_n = 1,
1242		.idxs_n = 4,
1243		.idxs_map = {
1244		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1245		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1246		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1247		[NIR_INTRINSIC_IDX_ACCESS] = 4
1248		}
1249		};
1250		struct nir_intrinsic nir_image_atomic_comp_swap = {
1251		.name = "image_atomic_comp_swap",
1252		.srcs_n = 5,
1253		.src_components_n = {
1254		1,4,1,1,1
1255		},
1256		.has_dest = true,
1257		.dest_components_n = 1,
1258		.idxs_n = 4,
1259		.idxs_map = {
1260		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1261		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1262		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1263		[NIR_INTRINSIC_IDX_ACCESS] = 4
1264		}
1265		};
1266		struct nir_intrinsic nir_image_atomic_fadd = {
1267		.name = "image_atomic_fadd",
1268		.srcs_n = 5,
1269		.src_components_n = {
1270		1,1,4,1,1
1271		},
1272		.has_dest = true,
1273		.dest_components_n = 1,
1274		.idxs_n = 4,
1275		.idxs_map = {
1276		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1277		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1278		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1279		[NIR_INTRINSIC_IDX_ACCESS] = 4
1280		}
1281		};
1282		struct nir_intrinsic nir_image_size = {
1283		.name = "image_size",
1284		.srcs_n = 1,
1285		.src_components_n = {
1286		1
1287		},
1288		.has_dest = true,
1289		.idxs_n = 4,
1290		.idxs_map = {
1291		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1292		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1293		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1294		[NIR_INTRINSIC_IDX_ACCESS] = 4
1295		},
1296		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1297		};
1298		struct nir_intrinsic nir_image_samples = {
1299		.name = "image_samples",
1300		.srcs_n = 1,
1301		.src_components_n = {
1302		1
1303		},
1304		.has_dest = true,
1305		.dest_components_n = 1,
1306		.idxs_n = 4,
1307		.idxs_map = {
1308		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1309		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1310		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1311		[NIR_INTRINSIC_IDX_ACCESS] = 4
1312		},
1313		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1314		};
1315		struct nir_intrinsic nir_image_load_raw_intel = {
1316		.name = "image_load_raw_intel",
1317		.srcs_n = 2,
1318		.src_components_n = {
1319		1,1
1320		},
1321		.has_dest = true,
1322		.idxs_n = 4,
1323		.idxs_map = {
1324		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1325		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1326		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1327		[NIR_INTRINSIC_IDX_ACCESS] = 4
1328		},
1329		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1330		};
1331		struct nir_intrinsic nir_image_store_raw_intel = {
1332		.name = "image_store_raw_intel",
1333		.srcs_n = 3,
1334		.src_components_n = {
1335		1,1,0
1336		},
1337		.idxs_n = 4,
1338		.idxs_map = {
1339		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1340		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1341		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1342		[NIR_INTRINSIC_IDX_ACCESS] = 4
1343		}
1344		};
1345		struct nir_intrinsic nir_image_atomic_inc_wrap = {
1346		.name = "image_atomic_inc_wrap",
1347		.srcs_n = 4,
1348		.src_components_n = {
1349		1,4,1,1
1350		},
1351		.has_dest = true,
1352		.dest_components_n = 1,
1353		.idxs_n = 4,
1354		.idxs_map = {
1355		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1356		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1357		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1358		[NIR_INTRINSIC_IDX_ACCESS] = 4
1359		}
1360		};
1361		struct nir_intrinsic nir_image_atomic_dec_wrap = {
1362		.name = "image_atomic_dec_wrap",
1363		.srcs_n = 4,
1364		.src_components_n = {
1365		1,4,1,1
1366		},
1367		.has_dest = true,
1368		.dest_components_n = 1,
1369		.idxs_n = 4,
1370		.idxs_map = {
1371		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1372		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1373		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1374		[NIR_INTRINSIC_IDX_ACCESS] = 4
1375		}
1376		};
1377		/* plain version */
1378		/----------------------------------------------------------------------------/
1379		/* bindless version */
1380		struct nir_intrinsic nir_bindless_image_load = {
1381		.name = "bindless_image_load",
1382		.srcs_n = 3,
1383		.src_components_n = {
1384		1,4,1
1385		},
1386		.has_dest = true,
1387		.idxs_n = 4,
1388		.idxs_map = {
1389		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1390		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1391		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1392		[NIR_INTRINSIC_IDX_ACCESS] = 4
1393		},
1394		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1395		};
1396		struct nir_intrinsic nir_bindless_image_store = {
1397		.name = "bindless_image_store",
1398		.srcs_n = 4,
1399		.src_components_n = {
1400		1,4,1,0
1401		},
1402		.idxs_n = 4,
1403		.idxs_map = {
1404		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1405		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1406		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1407		[NIR_INTRINSIC_IDX_ACCESS] = 4
1408		}
1409		};
1410		struct nir_intrinsic nir_bindless_image_atomic_add = {
1411		.name = "bindless_image_atomic_add",
1412		.srcs_n = 4,
1413		.src_components_n = {
1414		1,4,1,1
1415		},
1416		.has_dest = true,
1417		.dest_components_n = 1,
1418		.idxs_n = 4,
1419		.idxs_map = {
1420		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1421		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1422		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1423		[NIR_INTRINSIC_IDX_ACCESS] = 4
1424		}
1425		};
1426		struct nir_intrinsic nir_bindless_image_atomic_min = {
1427		.name = "bindless_image_atomic_min",
1428		.srcs_n = 4,
1429		.src_components_n = {
1430		1,4,1,1
1431		},
1432		.has_dest = true,
1433		.dest_components_n = 1,
1434		.idxs_n = 4,
1435		.idxs_map = {
1436		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1437		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1438		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1439		[NIR_INTRINSIC_IDX_ACCESS] = 4
1440		}
1441		};
1442		struct nir_intrinsic nir_bindless_image_atomic_max = {
1443		.name = "bindless_image_atomic_max",
1444		.srcs_n = 4,
1445		.src_components_n = {
1446		1,4,1,1
1447		},
1448		.has_dest = true,
1449		.dest_components_n = 1,
1450		.idxs_n = 4,
1451		.idxs_map = {
1452		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1453		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1454		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1455		[NIR_INTRINSIC_IDX_ACCESS] = 4
1456		}
1457		};
1458		struct nir_intrinsic nir_bindless_image_atomic_and = {
1459		.name = "bindless_image_atomic_and",
1460		.srcs_n = 4,
1461		.src_components_n = {
1462		1,4,1,1
1463		},
1464		.has_dest = true,
1465		.dest_components_n = 1,
1466		.idxs_n = 4,
1467		.idxs_map = {
1468		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1469		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1470		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1471		[NIR_INTRINSIC_IDX_ACCESS] = 4
1472		}
1473		};
1474		struct nir_intrinsic nir_bindless_image_atomic_or = {
1475		.name = "bindless_image_atomic_or",
1476		.srcs_n = 4,
1477		.src_components_n = {
1478		1,4,1,1
1479		},
1480		.has_dest = true,
1481		.dest_components_n = 1,
1482		.idxs_n = 4,
1483		.idxs_map = {
1484		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1485		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1486		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1487		[NIR_INTRINSIC_IDX_ACCESS] = 4
1488		}
1489		};
1490		struct nir_intrinsic nir_bindless_image_atomic_xor = {
1491		.name = "bindless_image_atomic_xor",
1492		.srcs_n = 4,
1493		.src_components_n = {
1494		1,4,1,1
1495		},
1496		.has_dest = true,
1497		.dest_components_n = 1,
1498		.idxs_n = 4,
1499		.idxs_map = {
1500		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1501		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1502		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1503		[NIR_INTRINSIC_IDX_ACCESS] = 4
1504		}
1505		};
1506		struct nir_intrinsic nir_bindless_image_atomic_exchange = {
1507		.name = "bindless_image_atomic_exchange",
1508		.srcs_n = 4,
1509		.src_components_n = {
1510		1,4,1,1
1511		},
1512		.has_dest = true,
1513		.dest_components_n = 1,
1514		.idxs_n = 4,
1515		.idxs_map = {
1516		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1517		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1518		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1519		[NIR_INTRINSIC_IDX_ACCESS] = 4
1520		}
1521		};
1522		struct nir_intrinsic nir_bindless_image_atomic_comp_swap = {
1523		.name = "bindless_image_atomic_comp_swap",
1524		.srcs_n = 5,
1525		.src_components_n = {
1526		1,4,1,1,1
1527		},
1528		.has_dest = true,
1529		.dest_components_n = 1,
1530		.idxs_n = 4,
1531		.idxs_map = {
1532		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1533		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1534		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1535		[NIR_INTRINSIC_IDX_ACCESS] = 4
1536		}
1537		};
1538		struct nir_intrinsic nir_bindless_image_atomic_fadd = {
1539		.name = "bindless_image_atomic_fadd",
1540		.srcs_n = 5,
1541		.src_components_n = {
1542		1,1,4,1,1
1543		},
1544		.has_dest = true,
1545		.dest_components_n = 1,
1546		.idxs_n = 4,
1547		.idxs_map = {
1548		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1549		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1550		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1551		[NIR_INTRINSIC_IDX_ACCESS] = 4
1552		}
1553		};
1554		struct nir_intrinsic nir_bindless_image_size = {
1555		.name = "bindless_image_size",
1556		.srcs_n = 1,
1557		.src_components_n = {
1558		1
1559		},
1560		.has_dest = true,
1561		.idxs_n = 4,
1562		.idxs_map = {
1563		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1564		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1565		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1566		[NIR_INTRINSIC_IDX_ACCESS] = 4
1567		},
1568		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1569		};
1570		struct nir_intrinsic nir_bindless_image_samples = {
1571		.name = "bindless_image_samples",
1572		.srcs_n = 1,
1573		.src_components_n = {
1574		1
1575		},
1576		.has_dest = true,
1577		.dest_components_n = 1,
1578		.idxs_n = 4,
1579		.idxs_map = {
1580		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1581		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1582		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1583		[NIR_INTRINSIC_IDX_ACCESS] = 4
1584		},
1585		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1586		};
1587		struct nir_intrinsic nir_bindless_image_load_raw_intel = {
1588		.name = "bindless_image_load_raw_intel",
1589		.srcs_n = 2,
1590		.src_components_n = {
1591		1,1
1592		},
1593		.has_dest = true,
1594		.idxs_n = 4,
1595		.idxs_map = {
1596		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1597		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1598		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1599		[NIR_INTRINSIC_IDX_ACCESS] = 4
1600		},
1601		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1602		};
1603		struct nir_intrinsic nir_bindless_image_store_raw_intel = {
1604		.name = "bindless_image_store_raw_intel",
1605		.srcs_n = 3,
1606		.src_components_n = {
1607		1,1,0
1608		},
1609		.idxs_n = 4,
1610		.idxs_map = {
1611		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1612		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1613		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1614		[NIR_INTRINSIC_IDX_ACCESS] = 4
1615		}
1616		};
1617		struct nir_intrinsic nir_bindless_image_atomic_inc_wrap = {
1618		.name = "bindless_image_atomic_inc_wrap",
1619		.srcs_n = 4,
1620		.src_components_n = {
1621		1,4,1,1
1622		},
1623		.has_dest = true,
1624		.dest_components_n = 1,
1625		.idxs_n = 4,
1626		.idxs_map = {
1627		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1628		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1629		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1630		[NIR_INTRINSIC_IDX_ACCESS] = 4
1631		}
1632		};
1633		struct nir_intrinsic nir_bindless_image_atomic_dec_wrap = {
1634		.name = "bindless_image_atomic_dec_wrap",
1635		.srcs_n = 4,
1636		.src_components_n = {
1637		1,4,1,1
1638		},
1639		.has_dest = true,
1640		.dest_components_n = 1,
1641		.idxs_n = 4,
1642		.idxs_map = {
1643		[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
1644		[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
1645		[NIR_INTRINSIC_IDX_FORMAT] = 3,
1646		[NIR_INTRINSIC_IDX_ACCESS] = 4
1647		}
1648		};
1649		/* bindless version */
1650		/----------------------------------------------------------------------------/
1651		/* the following is solo */
1652		struct nir_intrinsic nir_image_deref_load_param_intel = {
1653		.name = "image_deref_load_param_intel",
1654		.srcs_n = 1,
1655		.src_components_n = {
1656		1
1657		},
1658		.has_dest = true,
1659		.dest_components_n = 0,
1660		.idxs_n = 1,
1661		.idxs_map = {
1662		[NIR_INTRINSIC_IDX_BASE] = 1
1663		},
1664		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1665		};
1666		/* Image load, store and atomic intrinsics */
1667		/******************************************************************************/
1668	864	struct nir_intrinsic nir_inclusive_scan = {	struct nir_intrinsic nir_inclusive_scan = {
1669	865	.name = "inclusive_scan",	.name = "inclusive_scan",
1670	866	.srcs_n = 1,	.srcs_n = 1,

...	...	struct nir_intrinsic nir_interp_deref_at_sample = {
1705	901	.has_dest = true,	.has_dest = true,
1706	902	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
1707	903	};	};
1708		static struct nir_intrinsic nir_load_alpha_ref_float = {
1709		.name = "load_alpha_ref_float",
1710		.has_dest = true,
1711		.dest_components_n = 1,
1712		.bit_szs = 0x20,
1713		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1714		.system_value = true
1715		};
1716	904	/******************************************************************************/	/******************************************************************************/
1717	905	/*	/*
1718	906	* Barycentric coordinate intrinsics.	* Barycentric coordinate intrinsics.

...	...	struct nir_intrinsic nir_load_barycentric_at_sample = {
1797	985	};	};
1798	986	/* Barycentric coordinate intrinsics. */	/* Barycentric coordinate intrinsics. */
1799	987	/******************************************************************************/	/******************************************************************************/
1800		static struct nir_intrinsic nir_load_base_instance = {
1801		.name = "load_base_instance",
1802		.has_dest = true,
1803		.dest_components_n = 1,
1804		.bit_szs = 0x20,
1805		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1806		.system_value = true
1807		};
1808		static struct nir_intrinsic nir_load_base_vertex = {
1809		.name = "load_base_vertex",
1810		.has_dest = true,
1811		.dest_components_n = 1,
1812		.bit_szs = 0x20,
1813		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1814		.system_value = true
1815		};
1816		static struct nir_intrinsic nir_load_blend_const_color_a_float = {
1817		.name = "load_blend_const_color_a_float",
1818		.has_dest = true,
1819		.dest_components_n = 1,
1820		.bit_szs = 0x20,
1821		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1822		.system_value = true
1823		};
1824		static struct nir_intrinsic nir_load_blend_const_color_aaaa8888_unorm = {
1825		.name = "load_blend_const_color_aaaa8888_unorm",
1826		.has_dest = true,
1827		.dest_components_n = 1,
1828		.bit_szs = 0x20,
1829		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1830		.system_value = true
1831		};
1832		static struct nir_intrinsic nir_load_blend_const_color_b_float = {
1833		.name = "load_blend_const_color_b_float",
1834		.has_dest = true,
1835		.dest_components_n = 1,
1836		.bit_szs = 0x20,
1837		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1838		.system_value = true
1839		};
1840		static struct nir_intrinsic nir_load_blend_const_color_g_float = {
1841		.name = "load_blend_const_color_g_float",
1842		.has_dest = true,
1843		.dest_components_n = 1,
1844		.bit_szs = 0x20,
1845		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1846		.system_value = true
1847		};
1848		static struct nir_intrinsic nir_load_blend_const_color_r_float = {
1849		.name = "load_blend_const_color_r_float",
1850		.has_dest = true,
1851		.dest_components_n = 1,
1852		.bit_szs = 0x20,
1853		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1854		.system_value = true
1855		};
1856		static struct nir_intrinsic nir_load_blend_const_color_rgb = {
1857		.name = "load_blend_const_color_rgba",
1858		.has_dest = true,
1859		.dest_components_n = 4,
1860		.bit_szs = 0x20,
1861		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1862		.system_value = true
1863		};
1864		static struct nir_intrinsic nir_load_blend_const_color_rgba8888_unorm = {
1865		.name = "load_blend_const_color_rgba8888_unorm",
1866		.has_dest = true,
1867		.dest_components_n = 1,
1868		.bit_szs = 0x20,
1869		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1870		.system_value = true
1871		};
1872	988
1873		/******************************************************************************/
1874		/*
1875		* System values for gl_Color, for radeonsi which interpolates these in the
1876		* shader prolog to handle two-sided color without recompiles and therefore
1877		* doesn't handle these in the main shader part like normal varyings.
1878		*/
1879		static struct nir_intrinsic nir_load_color0 = {
1880		.name = "load_color0",
1881		.has_dest = true,
1882		.dest_components_n = 4,
1883		.bit_szs = 0x20,
1884		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1885		.system_value = true
1886		};
1887		static struct nir_intrinsic nir_load_color1 = {
1888		.name = "load_color1",
1889		.has_dest = true,
1890		.dest_components_n = 4,
1891		.bit_szs = 0x20,
1892		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1893		.system_value = true
1894		};
1895		/* system color0 and system color1 */
1896		/******************************************************************************/
1897	989	struct nir_intrinsic nir_load_deref = {	struct nir_intrinsic nir_load_deref = {
1898	990	.name = "load_deref",	.name = "load_deref",
1899	991	.srcs_n = 1,	.srcs_n = 1,

...	...	struct nir_intrinsic nir_load_deref = {
1907	999	},	},
1908	1000	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
1909	1001	};	};
1910		static struct nir_intrinsic nir_load_draw_id = {
1911		.name = "load_draw_id",
1912		.has_dest = true,
1913		.dest_components_n = 1,
1914		.bit_szs = 0x20,
1915		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1916		.system_value = true
1917		};
1918		static struct nir_intrinsic nir_load_first_vertex = {
1919		.name = "load_first_vertex",
1920		.has_dest = true,
1921		.dest_components_n = 1,
1922		.bit_szs = 0x20,
1923		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1924		.system_value = true
1925		};
1926		static struct nir_intrinsic nir_load_frag_coord = {
1927		.name = "load_frag_coord",
1928		.has_dest = true,
1929		.dest_components_n = 4,
1930		.bit_szs = 0x20,
1931		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1932		.system_value = true
1933		};
1934		static struct nir_intrinsic nir_load_point_coord = {
1935		.name = "load_point_coord",
1936		.has_dest = true,
1937		.dest_components_n = 2,
1938		.bit_szs = 0x20,
1939		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1940		.system_value = true
1941		};
1942		static struct nir_intrinsic nir_load_front_face = {
1943		.name = "load_front_face",
1944		.has_dest = true,
1945		.dest_components_n = 1,
1946		.bit_szs = 0x21,
1947		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
1948		.system_value = true
1949		};
1950	1002
1951	1003	/*	/*
1952	1004	* Load sample position:	* Load sample position:

...	...	struct nir_intrinsic nir_store_scratch = {
2338	1390	};	};
2339	1391	/* Stores */	/* Stores */
2340	1392	/******************************************************************************/	/******************************************************************************/
2341		static struct nir_intrinsic nir_load_global_invocation_id = {
2342		.name = "load_global_invocation_id",
2343		.has_dest = true,
2344		.dest_components_n = 3,
2345		.bit_szs = 0x60,
2346		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2347		.system_value = true
2348		};
2349		static struct nir_intrinsic nir_load_global_invocation_index = {
2350		.name = "load_global_invocation_index",
2351		.has_dest = true,
2352		.dest_components_n = 1,
2353		.bit_szs = 0x60,
2354		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2355		.system_value = true
2356		};
2357		static struct nir_intrinsic nir_load_helper_invocation = {
2358		.name = "load_helper_invocation",
2359		.has_dest = true,
2360		.dest_components_n = 1,
2361		.bit_szs = 0x21,
2362		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2363		.system_value = true
2364		};
2365		static struct nir_intrinsic nir_load_instance_id = {
2366		.name = "load_instance_id",
2367		.has_dest = true,
2368		.dest_components_n = 1,
2369		.bit_szs = 0x20,
2370		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2371		.system_value = true
2372		};
2373		static struct nir_intrinsic nir_load_invocation_id = {
2374		.name = "load_invocation_id",
2375		.has_dest = true,
2376		.dest_components_n = 1,
2377		.bit_szs = 0x20,
2378		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2379		.system_value = true
2380		};
2381		static struct nir_intrinsic nir_load_is_indexed_draw = {
2382		.name = "load_is_indexed_draw",
2383		.has_dest = true,
2384		.dest_components_n = 1,
2385		.bit_szs = 0x20,
2386		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2387		.system_value = true
2388		};
2389		static struct nir_intrinsic nir_load_layer_id = {
2390		.name = "load_layer_id",
2391		.has_dest = true,
2392		.dest_components_n = 1,
2393		.bit_szs = 0x20,
2394		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2395		.system_value = true
2396		};
2397		static struct nir_intrinsic nir_load_local_group_size = {
2398		.name = "load_local_group_size",
2399		.has_dest = true,
2400		.dest_components_n = 3,
2401		.bit_szs = 0x20,
2402		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2403		.system_value = true
2404		};
2405		static struct nir_intrinsic nir_load_local_invocation_id = {
2406		.name = "load_local_invocation_id",
2407		.has_dest = true,
2408		.dest_components_n = 3,
2409		.bit_szs = 0x20,
2410		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2411		.system_value = true
2412		};
2413		static struct nir_intrinsic nir_load_local_invocation_index = {
2414		.name = "load_local_invocation_index",
2415		.has_dest = true,
2416		.dest_components_n = 1,
2417		.bit_szs = 0x20,
2418		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2419		.system_value = true
2420		};
2421		static struct nir_intrinsic nir_load_num_subgroups = {
2422		.name = "load_num_subgroups",
2423		.has_dest = true,
2424		.dest_components_n = 1,
2425		.bit_szs = 0x20,
2426		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2427		.system_value = true
2428		};
2429		static struct nir_intrinsic nir_load_num_work_groups = {
2430		.name = "load_num_work_groups",
2431		.has_dest = true,
2432		.dest_components_n = 3,
2433		.bit_szs = 0x20,
2434		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2435		.system_value = true
2436		};
2437	1393	struct nir_intrinsic nir_load_param = {	struct nir_intrinsic nir_load_param = {
2438	1394	.name = "load_param",	.name = "load_param",
2439	1395	.srcs_n = 0,	.srcs_n = 0,

...	...	struct nir_intrinsic nir_load_param = {
2444	1400	},	},
2445	1401	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
2446	1402	};	};
2447		static struct nir_intrinsic nir_load_patch_vertices_in = {
2448		.name = "load_patch_vertices_in",
2449		.has_dest = true,
2450		.dest_components_n = 1,
2451		.bit_szs = 0x20,
2452		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2453		.system_value = true
2454		};
2455		static struct nir_intrinsic nir_load_primitive_id = {
2456		.name = "load_primitive_id",
2457		.has_dest = true,
2458		.dest_components_n = 1,
2459		.bit_szs = 0x20,
2460		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2461		.system_value = true
2462		};
2463		static struct nir_intrinsic nir_load_sample_id = {
2464		.name = "load_sample_id",
2465		.has_dest = true,
2466		.dest_components_n = 1,
2467		.bit_szs = 0x20,
2468		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2469		.system_value = true
2470		};
2471		static struct nir_intrinsic nir_load_sample_id_no_per_sample = {
2472		.name = "load_sample_id_no_per_sample",
2473		.has_dest = true,
2474		.dest_components_n = 1,
2475		.bit_szs = 0x20,
2476		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2477		.system_value = true
2478		};
2479		static struct nir_intrinsic nir_load_sample_mask_in = {
2480		.name = "load_sample_mask_in",
2481		.has_dest = true,
2482		.dest_components_n = 1,
2483		.bit_szs = 0x20,
2484		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2485		.system_value = true
2486		};
2487		static struct nir_intrinsic nir_load_sample_pos = {
2488		.name = "load_sample_pos",
2489		.has_dest = true,
2490		.dest_components_n = 2,
2491		.bit_szs = 0x20,
2492		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2493		.system_value = true
2494		};
2495		static struct nir_intrinsic nir_load_subgroup_eq_mask = {
2496		.name = "load_subgroup_eq_mask",
2497		.has_dest = true,
2498		.dest_components_n = 0,
2499		.bit_szs = 0x60,
2500		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2501		.system_value = true
2502		};
2503		static struct nir_intrinsic nir_load_subgroup_ge_mask = {
2504		.name = "load_subgroup_ge_mask",
2505		.has_dest = true,
2506		.dest_components_n = 0,
2507		.bit_szs = 0x60,
2508		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2509		.system_value = true
2510		};
2511		static struct nir_intrinsic nir_load_subgroup_gt_mask = {
2512		.name = "load_subgroup_gt_mask",
2513		.has_dest = true,
2514		.dest_components_n = 0,
2515		.bit_szs = 0x60,
2516		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2517		.system_value = true
2518		};
2519		static struct nir_intrinsic nir_load_subgroup_id = {
2520		.name = "load_subgroup_id",
2521		.has_dest = true,
2522		.dest_components_n = 1,
2523		.bit_szs = 0x20,
2524		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2525		.system_value = true
2526		};
2527		static struct nir_intrinsic nir_load_subgroup_invocation = {
2528		.name = "load_subgroup_invocation",
2529		.has_dest = true,
2530		.dest_components_n = 1,
2531		.bit_szs = 0x20,
2532		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2533		.system_value = true
2534		};
2535		static struct nir_intrinsic nir_load_subgroup_le_mask = {
2536		.name = "load_subgroup_le_mask",
2537		.has_dest = true,
2538		.dest_components_n = 0,
2539		.bit_szs = 0x60,
2540		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2541		.system_value = true
2542		};
2543		static struct nir_intrinsic nir_load_subgroup_lt_mask = {
2544		.name = "load_subgroup_lt_mask",
2545		.has_dest = true,
2546		.dest_components_n = 0,
2547		.bit_szs = 0x60,
2548		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2549		.system_value = true
2550		};
2551		static struct nir_intrinsic nir_load_subgroup_size = {
2552		.name = "load_subgroup_size",
2553		.has_dest = true,
2554		.dest_components_n = 1,
2555		.bit_szs = 0x20,
2556		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2557		.system_value = true
2558		};
2559		static struct nir_intrinsic nir_load_tess_coord = {
2560		.name = "load_tess_coord",
2561		.has_dest = true,
2562		.dest_components_n = 3,
2563		.bit_szs = 0x20,
2564		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2565		.system_value = true
2566		};
2567		static struct nir_intrinsic nir_load_tess_level_inner = {
2568		.name = "load_tess_level_inner",
2569		.has_dest = true,
2570		.dest_components_n = 2,
2571		.bit_szs = 0x20,
2572		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2573		.system_value = true
2574		};
2575		static struct nir_intrinsic nir_load_tess_level_outer = {
2576		.name = "load_tess_level_outer",
2577		.has_dest = true,
2578		.dest_components_n = 4,
2579		.bit_szs = 0x20,
2580		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2581		.system_value = true
2582		};
2583		static struct nir_intrinsic nir_load_user_clip_plane = {
2584		.name = "load_user_clip_plane",
2585		.has_dest = true,
2586		.dest_components_n = 4,
2587		.idxs_n = 1,
2588		.idxs_map = {
2589		[NIR_INTRINSIC_IDX_UCP_ID] = 1,
2590		},
2591		.bit_szs = 0x20,
2592		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2593		.system_value = true
2594		};
2595		static struct nir_intrinsic nir_load_vertex_id = {
2596		.name = "load_vertex_id",
2597		.has_dest = true,
2598		.dest_components_n = 1,
2599		.bit_szs = 0x20,
2600		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2601		.system_value = true
2602		};
2603		static struct nir_intrinsic nir_load_vertex_id_zero_base = {
2604		.name = "load_vertex_id_zero_base",
2605		.has_dest = true,
2606		.dest_components_n = 1,
2607		.bit_szs = 0x20,
2608		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2609		.system_value = true
2610		};
2611		static struct nir_intrinsic nir_load_view_index = {
2612		.name = "load_view_index",
2613		.has_dest = true,
2614		.dest_components_n = 1,
2615		.bit_szs = 0x20,
2616		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2617		.system_value = true
2618		};
2619	1403	struct nir_intrinsic nir_load_vulkan_descriptor = {	struct nir_intrinsic nir_load_vulkan_descriptor = {
2620	1404	.name = "load_vulkan_descriptor",	.name = "load_vulkan_descriptor",
2621	1405	.srcs_n = 1,	.srcs_n = 1,

...	...	struct nir_intrinsic nir_load_vulkan_descriptor = {
2629	1413	},	},
2630	1414	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
2631	1415	};	};
2632		static struct nir_intrinsic nir_load_work_dim = {
2633		.name = "load_work_dim",
2634		.has_dest = true,
2635		.dest_components_n = 1,
2636		.bit_szs = 0x20,
2637		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2638		.system_value = true
2639		};
2640		static struct nir_intrinsic nir_load_work_group_id = {
2641		.name = "load_work_group_id",
2642		.has_dest = true,
2643		.dest_components_n = 3,
2644		.bit_szs = 0x20,
2645		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
2646		.system_value = true
2647		};
2648	1416	struct nir_intrinsic nir_memory_barrier = {	struct nir_intrinsic nir_memory_barrier = {
2649	1417	.name = "memory_barrier"	.name = "memory_barrier"
2650	1418	};	};

...	...	struct nir_intrinsic nir_ssbo_atomic_swap_ir3 = {
3374	2142	.dest_components_n = 1	.dest_components_n = 1
3375	2143	};	};
3376	2144
3377		/******************************************************************************/
3378		/*
3379		* Driver-specific viewport scale/offset parameters.
3380		*
3381		* VC4 and V3D need to emit a scaled version of the position in the vertex
3382		* shaders for binning, and having system values lets us move the math for that
3383		* into NIR.
3384		*
3385		* Panfrost needs to implement all coordinate transformation in the
3386		* vertex shader; system values allow us to share this routine in NIR.
3387		*/
3388		static struct nir_intrinsic nir_load_viewport_x_scale = {
3389		.name = "load_viewport_x_scale",
3390		.has_dest = true,
3391		.dest_components_n = 1,
3392		.bit_szs = 0x20,
3393		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3394		.system_value = true
3395		};
3396		static struct nir_intrinsic nir_load_viewport_y_scale = {
3397		.name = "load_viewport_y_scale",
3398		.has_dest = true,
3399		.dest_components_n = 1,
3400		.bit_szs = 0x20,
3401		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3402		.system_value = true
3403		};
3404		static struct nir_intrinsic nir_load_viewport_z_scale = {
3405		.name = "load_viewport_z_scale",
3406		.has_dest = true,
3407		.dest_components_n = 1,
3408		.bit_szs = 0x20,
3409		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3410		.system_value = true
3411		};
3412		static struct nir_intrinsic nir_load_viewport_z_offset = {
3413		.name = "load_viewport_z_offset",
3414		.has_dest = true,
3415		.dest_components_n = 1,
3416		.bit_szs = 0x20,
3417		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3418		.system_value = true
3419		};
3420		static struct nir_intrinsic nir_load_viewport_scale = {
3421		.name = "load_viewport_scale",
3422		.has_dest = true,
3423		.dest_components_n = 3,
3424		.bit_szs = 0x20,
3425		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3426		.system_value = true
3427		};
3428		static struct nir_intrinsic nir_load_viewport_offset = {
3429		.name = "load_viewport_offset",
3430		.has_dest = true,
3431		.dest_components_n = 3,
3432		.bit_szs = 0x20,
3433		.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER,
3434		.system_value = true
3435		};
3436		/* viewport */
3437		/******************************************************************************/
3438
3439	2145	/******************************************************************************/	/******************************************************************************/
3440	2146	/* AMD Shader ballot operations */	/* AMD Shader ballot operations */
3441	2147	struct nir_intrinsic nir_quad_swizzle_amd = {	struct nir_intrinsic nir_quad_swizzle_amd = {

...	...	struct nir_intrinsic nir_store_tlb_sample_color_v3d = {
3576	2282	};	};
3577	2283	/* v3d */	/* v3d */
3578	2284	/******************************************************************************/	/******************************************************************************/
3579		/----------------------------------------------------------------------------/
	2285
	2286		#include "nir_database_intrinsic_system_values.c"
	2287		#include "nir_database_intrinsic_image.c"
3580	2288
3581	2289	struct nir_intrinsic *nir_intrinsics[] = {	struct nir_intrinsic *nir_intrinsics[] = {
3582	2290	&nir_atomic_counter_add,	&nir_atomic_counter_add,

...	...	struct nir_intrinsic nir_intrinsics[] = {*
3658	2366	&nir_image_atomic_comp_swap,	&nir_image_atomic_comp_swap,
3659	2367	&nir_image_atomic_exchange,	&nir_image_atomic_exchange,
3660	2368	&nir_image_atomic_fadd,	&nir_image_atomic_fadd,
3661		&nir_image_atomic_max,
3662		&nir_image_atomic_min,
3663	2369	&nir_image_atomic_or,	&nir_image_atomic_or,
3664	2370	&nir_image_atomic_xor,	&nir_image_atomic_xor,
3665	2371	&nir_image_deref_atomic_add,	&nir_image_deref_atomic_add,

...	...	struct nir_intrinsic nir_intrinsics[] = {*
3667	2373	&nir_image_deref_atomic_comp_swap,	&nir_image_deref_atomic_comp_swap,
3668	2374	&nir_image_deref_atomic_exchange,	&nir_image_deref_atomic_exchange,
3669	2375	&nir_image_deref_atomic_fadd,	&nir_image_deref_atomic_fadd,
3670		&nir_image_deref_atomic_max,
3671		&nir_image_deref_atomic_min,
3672	2376	&nir_image_deref_atomic_or,	&nir_image_deref_atomic_or,
3673	2377	&nir_image_deref_atomic_xor,	&nir_image_deref_atomic_xor,
3674	2378	&nir_image_deref_load,	&nir_image_deref_load,

...	...	struct nir_intrinsic nir_intrinsics[] = {*
3835	2539	&nir_bindless_image_load,	&nir_bindless_image_load,
3836	2540	&nir_bindless_image_store,	&nir_bindless_image_store,
3837	2541	&nir_bindless_image_atomic_add,	&nir_bindless_image_atomic_add,
3838		&nir_bindless_image_atomic_min,
3839		&nir_bindless_image_atomic_max,
3840	2542	&nir_bindless_image_atomic_and,	&nir_bindless_image_atomic_and,
3841	2543	&nir_bindless_image_atomic_or,	&nir_bindless_image_atomic_or,
3842	2544	&nir_bindless_image_atomic_xor,	&nir_bindless_image_atomic_xor,

...	...	struct nir_intrinsic nir_intrinsics[] = {*
3888	2590	&nir_bindless_image_atomic_inc_wrap,	&nir_bindless_image_atomic_inc_wrap,
3889	2591	&nir_image_deref_atomic_dec_wrap,	&nir_image_deref_atomic_dec_wrap,
3890	2592	&nir_image_atomic_dec_wrap,	&nir_image_atomic_dec_wrap,
3891		&nir_bindless_image_atomic_dec_wrap
	2593		&nir_bindless_image_atomic_dec_wrap,
	2594		/* git 5ed4e31c08dc079473dd2e459c973355d49cd529..c550d367a747472ee71ed4c99e210174730aa82b */
	2595		&nir_load_user_data_amd,
	2596		&nir_load_tess_level_outer_default,
	2597		&nir_load_tess_level_inner_default,
	2598		/* git c550d367a747472ee71ed4c99e210174730aa82b..f58e0405b6ca15d9b82122d82311e8b82f4a0939 */
	2599		&nir_image_deref_atomic_imin,
	2600		&nir_image_deref_atomic_imax,
	2601		&nir_image_deref_atomic_umin,
	2602		&nir_image_deref_atomic_umax,
	2603		&nir_image_atomic_imin,
	2604		&nir_image_atomic_imax,
	2605		&nir_image_atomic_umin,
	2606		&nir_image_atomic_umax,
	2607		&nir_bindless_image_atomic_imin,
	2608		&nir_bindless_image_atomic_imax,
	2609		&nir_bindless_image_atomic_umin,
	2610		&nir_bindless_image_atomic_umax
3892	2611	};	};

File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_image.c added (mode: 100644) (index 0000000..8981bb2)
	1	/*
	2	* Image load, store and atomic intrinsics.
	3	*
	4	* All image intrinsics come in three versions. One which take an image target
	5	* passed as a deref chain as the first source, one which takes an index as the
	6	* first source, and one which takes a bindless handle as the first source.
	7	* In the first version, the image variable contains the memory and layout
	8	* qualifiers that influence the semantics of the intrinsic. In the second and
	9	* third, the image format and access qualifiers are provided as constant
	10	* indices.
	11	*
	12	* All image intrinsics take a four-coordinate vector and a sample index as
	13	* 2nd and 3rd sources, determining the location within the image that will be
	14	* accessed by the intrinsic. Components not applicable to the image target
	15	* in use are undefined. Image store takes an additional four-component
	16	* argument with the value to be written, and image atomic operations take
	17	* either one or two additional scalar arguments with the same meaning as in
	18	* the ARB_shader_image_load_store specification.
	19	*/
	20	/----------------------------------------------------------------------------/
	21	/* deref version */
	22	struct nir_intrinsic nir_image_deref_load = {
	23	.name = "image_deref_load",
	24	.srcs_n = 3,
	25	.src_components_n = {
	26	1,4,1
	27	},
	28	.has_dest = true,
	29	.dest_components_n = 0,
	30	.idxs_n = 1,
	31	.idxs_map = {
	32	[NIR_INTRINSIC_IDX_ACCESS] = 1
	33	},
	34	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	35	};
	36	struct nir_intrinsic nir_image_deref_store = {
	37	.name = "image_deref_store",
	38	.srcs_n = 4,
	39	.src_components_n = {
	40	1,4,1,0
	41	},
	42	.idxs_n = 1,
	43	.idxs_map = {
	44	[NIR_INTRINSIC_IDX_ACCESS] = 1
	45	}
	46	};
	47	struct nir_intrinsic nir_image_deref_atomic_add = {
	48	.name = "image_deref_atomic_add",
	49	.srcs_n = 4,
	50	.src_components_n = {
	51	1,4,1,1
	52	},
	53	.has_dest = true,
	54	.dest_components_n = 1,
	55	.idxs_n = 1,
	56	.idxs_map = {
	57	[NIR_INTRINSIC_IDX_ACCESS] = 1
	58	}
	59	};
	60	struct nir_intrinsic nir_image_deref_atomic_imin = {
	61	.name = "image_deref_atomic_imin",
	62	.srcs_n = 4,
	63	.src_components_n = {
	64	1,4,1,1
	65	},
	66	.has_dest = true,
	67	.dest_components_n = 1,
	68	.idxs_n = 1,
	69	.idxs_map = {
	70	[NIR_INTRINSIC_IDX_ACCESS] = 1
	71	}
	72	};
	73	struct nir_intrinsic nir_image_deref_atomic_imax = {
	74	.name = "image_deref_atomic_imax",
	75	.srcs_n = 4,
	76	.src_components_n = {
	77	1,4,1,1
	78	},
	79	.has_dest = true,
	80	.dest_components_n = 1,
	81	.idxs_n = 1,
	82	.idxs_map = {
	83	[NIR_INTRINSIC_IDX_ACCESS] = 1
	84	}
	85	};
	86	struct nir_intrinsic nir_image_deref_atomic_umin = {
	87	.name = "image_deref_atomic_umin",
	88	.srcs_n = 4,
	89	.src_components_n = {
	90	1,4,1,1
	91	},
	92	.has_dest = true,
	93	.dest_components_n = 1,
	94	.idxs_n = 1,
	95	.idxs_map = {
	96	[NIR_INTRINSIC_IDX_ACCESS] = 1
	97	}
	98	};
	99	struct nir_intrinsic nir_image_deref_atomic_umax = {
	100	.name = "image_deref_atomic_umax",
	101	.srcs_n = 4,
	102	.src_components_n = {
	103	1,4,1,1
	104	},
	105	.has_dest = true,
	106	.dest_components_n = 1,
	107	.idxs_n = 1,
	108	.idxs_map = {
	109	[NIR_INTRINSIC_IDX_ACCESS] = 1
	110	}
	111	};
	112	struct nir_intrinsic nir_image_deref_atomic_and = {
	113	.name = "image_deref_atomic_and",
	114	.srcs_n = 4,
	115	.src_components_n = {
	116	1,4,1,1
	117	},
	118	.has_dest = true,
	119	.dest_components_n = 1,
	120	.idxs_n = 1,
	121	.idxs_map = {
	122	[NIR_INTRINSIC_IDX_ACCESS] = 1
	123	}
	124	};
	125	struct nir_intrinsic nir_image_deref_atomic_or = {
	126	.name = "image_deref_atomic_or",
	127	.srcs_n = 4,
	128	.src_components_n = {
	129	1,4,1,1
	130	},
	131	.has_dest = true,
	132	.dest_components_n = 1,
	133	.idxs_n = 1,
	134	.idxs_map = {
	135	[NIR_INTRINSIC_IDX_ACCESS] = 1
	136	}
	137	};
	138	struct nir_intrinsic nir_image_deref_atomic_xor = {
	139	.name = "image_deref_atomic_xor",
	140	.srcs_n = 4,
	141	.src_components_n = {
	142	1,4,1,1
	143	},
	144	.has_dest = true,
	145	.dest_components_n = 1,
	146	.idxs_n = 1,
	147	.idxs_map = {
	148	[NIR_INTRINSIC_IDX_ACCESS] = 1
	149	}
	150	};
	151	struct nir_intrinsic nir_image_deref_atomic_exchange = {
	152	.name = "image_deref_atomic_exchange",
	153	.srcs_n = 4,
	154	.src_components_n = {
	155	1,4,1,1
	156	},
	157	.has_dest = true,
	158	.dest_components_n = 1,
	159	.idxs_n = 1,
	160	.idxs_map = {
	161	[NIR_INTRINSIC_IDX_ACCESS] = 1
	162	}
	163	};
	164	struct nir_intrinsic nir_image_deref_atomic_comp_swap = {
	165	.name = "image_deref_atomic_comp_swap",
	166	.srcs_n = 5,
	167	.src_components_n = {
	168	1,4,1,1,1
	169	},
	170	.has_dest = true,
	171	.dest_components_n = 1,
	172	.idxs_n = 1,
	173	.idxs_map = {
	174	[NIR_INTRINSIC_IDX_ACCESS] = 1
	175	}
	176	};
	177	struct nir_intrinsic nir_image_deref_atomic_fadd = {
	178	.name = "image_deref_atomic_fadd",
	179	.srcs_n = 5,
	180	.src_components_n = {
	181	1,1,4,1,1
	182	},
	183	.has_dest = true,
	184	.dest_components_n = 1,
	185	.idxs_n = 1,
	186	.idxs_map = {
	187	[NIR_INTRINSIC_IDX_ACCESS] = 1
	188	}
	189	};
	190	struct nir_intrinsic nir_image_deref_size = {
	191	.name = "image_deref_size",
	192	.srcs_n = 1,
	193	.src_components_n = {
	194	1
	195	},
	196	.has_dest = true,
	197	.idxs_n = 1,
	198	.idxs_map = {
	199	[NIR_INTRINSIC_IDX_ACCESS] = 1
	200	},
	201	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	202	};
	203	struct nir_intrinsic nir_image_deref_samples = {
	204	.name = "image_deref_samples",
	205	.srcs_n = 1,
	206	.src_components_n = {
	207	1
	208	},
	209	.has_dest = true,
	210	.dest_components_n = 1,
	211	.idxs_n = 1,
	212	.idxs_map = {
	213	[NIR_INTRINSIC_IDX_ACCESS] = 1
	214	},
	215	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	216	};
	217	struct nir_intrinsic nir_image_deref_load_raw_intel = {
	218	.name = "image_deref_load_raw_intel",
	219	.srcs_n = 2,
	220	.src_components_n = {
	221	1,1
	222	},
	223	.has_dest = true,
	224	.idxs_n = 1,
	225	.idxs_map = {
	226	[NIR_INTRINSIC_IDX_ACCESS] = 1
	227	},
	228	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	229	};
	230	struct nir_intrinsic nir_image_deref_store_raw_intel = {
	231	.name = "image_deref_store_raw_intel",
	232	.srcs_n = 3,
	233	.src_components_n = {
	234	1,1,0
	235	},
	236	.idxs_n = 1,
	237	.idxs_map = {
	238	[NIR_INTRINSIC_IDX_ACCESS] = 1
	239	}
	240	};
	241	struct nir_intrinsic nir_image_deref_atomic_inc_wrap = {
	242	.name = "image_deref_atomic_inc_wrap",
	243	.srcs_n = 4,
	244	.src_components_n = {
	245	1,4,1,1
	246	},
	247	.has_dest = true,
	248	.dest_components_n = 1,
	249	.idxs_n = 1,
	250	.idxs_map = {
	251	[NIR_INTRINSIC_IDX_ACCESS] = 1
	252	}
	253	};
	254	struct nir_intrinsic nir_image_deref_atomic_dec_wrap = {
	255	.name = "image_deref_atomic_dec_wrap",
	256	.srcs_n = 4,
	257	.src_components_n = {
	258	1,4,1,1
	259	},
	260	.has_dest = true,
	261	.dest_components_n = 1,
	262	.idxs_n = 1,
	263	.idxs_map = {
	264	[NIR_INTRINSIC_IDX_ACCESS] = 1
	265	}
	266	};
	267	/* deref version */
	268	/----------------------------------------------------------------------------/
	269	/* plain version */
	270	struct nir_intrinsic nir_image_load = {
	271	.name = "image_load",
	272	.srcs_n = 3,
	273	.src_components_n = {
	274	1,4,1
	275	},
	276	.has_dest = true,
	277	.idxs_n = 4,
	278	.idxs_map = {
	279	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	280	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	281	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	282	[NIR_INTRINSIC_IDX_ACCESS] = 4
	283	},
	284	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	285	};
	286	struct nir_intrinsic nir_image_store = {
	287	.name = "image_store",
	288	.srcs_n = 4,
	289	.src_components_n = {
	290	1,4,1,0
	291	},
	292	.idxs_n = 4,
	293	.idxs_map = {
	294	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	295	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	296	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	297	[NIR_INTRINSIC_IDX_ACCESS] = 4
	298	}
	299	};
	300	struct nir_intrinsic nir_image_atomic_add = {
	301	.name = "image_atomic_add",
	302	.srcs_n = 4,
	303	.src_components_n = {
	304	1,4,1,1
	305	},
	306	.has_dest = true,
	307	.dest_components_n = 1,
	308	.idxs_n = 4,
	309	.idxs_map = {
	310	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	311	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	312	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	313	[NIR_INTRINSIC_IDX_ACCESS] = 4
	314	}
	315	};
	316	struct nir_intrinsic nir_image_atomic_umin = {
	317	.name = "image_atomic_umin",
	318	.srcs_n = 4,
	319	.src_components_n = {
	320	1,4,1,1
	321	},
	322	.has_dest = true,
	323	.dest_components_n = 1,
	324	.idxs_n = 4,
	325	.idxs_map = {
	326	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	327	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	328	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	329	[NIR_INTRINSIC_IDX_ACCESS] = 4
	330	}
	331	};
	332	struct nir_intrinsic nir_image_atomic_umax = {
	333	.name = "image_atomic_umax",
	334	.srcs_n = 4,
	335	.src_components_n = {
	336	1,4,1,1
	337	},
	338	.has_dest = true,
	339	.dest_components_n = 1,
	340	.idxs_n = 4,
	341	.idxs_map = {
	342	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	343	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	344	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	345	[NIR_INTRINSIC_IDX_ACCESS] = 4
	346	}
	347	};
	348	struct nir_intrinsic nir_image_atomic_imin = {
	349	.name = "image_atomic_imin",
	350	.srcs_n = 4,
	351	.src_components_n = {
	352	1,4,1,1
	353	},
	354	.has_dest = true,
	355	.dest_components_n = 1,
	356	.idxs_n = 4,
	357	.idxs_map = {
	358	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	359	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	360	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	361	[NIR_INTRINSIC_IDX_ACCESS] = 4
	362	}
	363	};
	364	struct nir_intrinsic nir_image_atomic_imax = {
	365	.name = "image_atomic_imax",
	366	.srcs_n = 4,
	367	.src_components_n = {
	368	1,4,1,1
	369	},
	370	.has_dest = true,
	371	.dest_components_n = 1,
	372	.idxs_n = 4,
	373	.idxs_map = {
	374	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	375	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	376	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	377	[NIR_INTRINSIC_IDX_ACCESS] = 4
	378	}
	379	};
	380	struct nir_intrinsic nir_image_atomic_and = {
	381	.name = "image_atomic_and",
	382	.srcs_n = 4,
	383	.src_components_n = {
	384	1,4,1,1
	385	},
	386	.has_dest = true,
	387	.dest_components_n = 1,
	388	.idxs_n = 4,
	389	.idxs_map = {
	390	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	391	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	392	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	393	[NIR_INTRINSIC_IDX_ACCESS] = 4
	394	}
	395	};
	396	struct nir_intrinsic nir_image_atomic_or = {
	397	.name = "image_atomic_or",
	398	.srcs_n = 4,
	399	.src_components_n = {
	400	1,4,1,1
	401	},
	402	.has_dest = true,
	403	.dest_components_n = 1,
	404	.idxs_n = 4,
	405	.idxs_map = {
	406	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	407	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	408	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	409	[NIR_INTRINSIC_IDX_ACCESS] = 4
	410	}
	411	};
	412	struct nir_intrinsic nir_image_atomic_xor = {
	413	.name = "image_atomic_xor",
	414	.srcs_n = 4,
	415	.src_components_n = {
	416	1,4,1,1
	417	},
	418	.has_dest = true,
	419	.dest_components_n = 1,
	420	.idxs_n = 4,
	421	.idxs_map = {
	422	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	423	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	424	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	425	[NIR_INTRINSIC_IDX_ACCESS] = 4
	426	}
	427	};
	428	struct nir_intrinsic nir_image_atomic_exchange = {
	429	.name = "image_atomic_exchange",
	430	.srcs_n = 4,
	431	.src_components_n = {
	432	1,4,1,1
	433	},
	434	.has_dest = true,
	435	.dest_components_n = 1,
	436	.idxs_n = 4,
	437	.idxs_map = {
	438	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	439	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	440	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	441	[NIR_INTRINSIC_IDX_ACCESS] = 4
	442	}
	443	};
	444	struct nir_intrinsic nir_image_atomic_comp_swap = {
	445	.name = "image_atomic_comp_swap",
	446	.srcs_n = 5,
	447	.src_components_n = {
	448	1,4,1,1,1
	449	},
	450	.has_dest = true,
	451	.dest_components_n = 1,
	452	.idxs_n = 4,
	453	.idxs_map = {
	454	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	455	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	456	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	457	[NIR_INTRINSIC_IDX_ACCESS] = 4
	458	}
	459	};
	460	struct nir_intrinsic nir_image_atomic_fadd = {
	461	.name = "image_atomic_fadd",
	462	.srcs_n = 5,
	463	.src_components_n = {
	464	1,1,4,1,1
	465	},
	466	.has_dest = true,
	467	.dest_components_n = 1,
	468	.idxs_n = 4,
	469	.idxs_map = {
	470	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	471	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	472	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	473	[NIR_INTRINSIC_IDX_ACCESS] = 4
	474	}
	475	};
	476	struct nir_intrinsic nir_image_size = {
	477	.name = "image_size",
	478	.srcs_n = 1,
	479	.src_components_n = {
	480	1
	481	},
	482	.has_dest = true,
	483	.idxs_n = 4,
	484	.idxs_map = {
	485	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	486	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	487	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	488	[NIR_INTRINSIC_IDX_ACCESS] = 4
	489	},
	490	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	491	};
	492	struct nir_intrinsic nir_image_samples = {
	493	.name = "image_samples",
	494	.srcs_n = 1,
	495	.src_components_n = {
	496	1
	497	},
	498	.has_dest = true,
	499	.dest_components_n = 1,
	500	.idxs_n = 4,
	501	.idxs_map = {
	502	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	503	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	504	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	505	[NIR_INTRINSIC_IDX_ACCESS] = 4
	506	},
	507	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	508	};
	509	struct nir_intrinsic nir_image_load_raw_intel = {
	510	.name = "image_load_raw_intel",
	511	.srcs_n = 2,
	512	.src_components_n = {
	513	1,1
	514	},
	515	.has_dest = true,
	516	.idxs_n = 4,
	517	.idxs_map = {
	518	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	519	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	520	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	521	[NIR_INTRINSIC_IDX_ACCESS] = 4
	522	},
	523	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	524	};
	525	struct nir_intrinsic nir_image_store_raw_intel = {
	526	.name = "image_store_raw_intel",
	527	.srcs_n = 3,
	528	.src_components_n = {
	529	1,1,0
	530	},
	531	.idxs_n = 4,
	532	.idxs_map = {
	533	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	534	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	535	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	536	[NIR_INTRINSIC_IDX_ACCESS] = 4
	537	}
	538	};
	539	struct nir_intrinsic nir_image_atomic_inc_wrap = {
	540	.name = "image_atomic_inc_wrap",
	541	.srcs_n = 4,
	542	.src_components_n = {
	543	1,4,1,1
	544	},
	545	.has_dest = true,
	546	.dest_components_n = 1,
	547	.idxs_n = 4,
	548	.idxs_map = {
	549	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	550	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	551	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	552	[NIR_INTRINSIC_IDX_ACCESS] = 4
	553	}
	554	};
	555	struct nir_intrinsic nir_image_atomic_dec_wrap = {
	556	.name = "image_atomic_dec_wrap",
	557	.srcs_n = 4,
	558	.src_components_n = {
	559	1,4,1,1
	560	},
	561	.has_dest = true,
	562	.dest_components_n = 1,
	563	.idxs_n = 4,
	564	.idxs_map = {
	565	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	566	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	567	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	568	[NIR_INTRINSIC_IDX_ACCESS] = 4
	569	}
	570	};
	571	/* plain version */
	572	/----------------------------------------------------------------------------/
	573	/* bindless version */
	574	struct nir_intrinsic nir_bindless_image_load = {
	575	.name = "bindless_image_load",
	576	.srcs_n = 3,
	577	.src_components_n = {
	578	1,4,1
	579	},
	580	.has_dest = true,
	581	.idxs_n = 4,
	582	.idxs_map = {
	583	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	584	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	585	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	586	[NIR_INTRINSIC_IDX_ACCESS] = 4
	587	},
	588	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	589	};
	590	struct nir_intrinsic nir_bindless_image_store = {
	591	.name = "bindless_image_store",
	592	.srcs_n = 4,
	593	.src_components_n = {
	594	1,4,1,0
	595	},
	596	.idxs_n = 4,
	597	.idxs_map = {
	598	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	599	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	600	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	601	[NIR_INTRINSIC_IDX_ACCESS] = 4
	602	}
	603	};
	604	struct nir_intrinsic nir_bindless_image_atomic_add = {
	605	.name = "bindless_image_atomic_add",
	606	.srcs_n = 4,
	607	.src_components_n = {
	608	1,4,1,1
	609	},
	610	.has_dest = true,
	611	.dest_components_n = 1,
	612	.idxs_n = 4,
	613	.idxs_map = {
	614	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	615	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	616	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	617	[NIR_INTRINSIC_IDX_ACCESS] = 4
	618	}
	619	};
	620	struct nir_intrinsic nir_bindless_image_atomic_imin = {
	621	.name = "bindless_image_atomic_imin",
	622	.srcs_n = 4,
	623	.src_components_n = {
	624	1,4,1,1
	625	},
	626	.has_dest = true,
	627	.dest_components_n = 1,
	628	.idxs_n = 4,
	629	.idxs_map = {
	630	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	631	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	632	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	633	[NIR_INTRINSIC_IDX_ACCESS] = 4
	634	}
	635	};
	636	struct nir_intrinsic nir_bindless_image_atomic_imax = {
	637	.name = "bindless_image_atomic_imax",
	638	.srcs_n = 4,
	639	.src_components_n = {
	640	1,4,1,1
	641	},
	642	.has_dest = true,
	643	.dest_components_n = 1,
	644	.idxs_n = 4,
	645	.idxs_map = {
	646	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	647	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	648	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	649	[NIR_INTRINSIC_IDX_ACCESS] = 4
	650	}
	651	};
	652	struct nir_intrinsic nir_bindless_image_atomic_umin = {
	653	.name = "bindless_image_atomic_umin",
	654	.srcs_n = 4,
	655	.src_components_n = {
	656	1,4,1,1
	657	},
	658	.has_dest = true,
	659	.dest_components_n = 1,
	660	.idxs_n = 4,
	661	.idxs_map = {
	662	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	663	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	664	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	665	[NIR_INTRINSIC_IDX_ACCESS] = 4
	666	}
	667	};
	668	struct nir_intrinsic nir_bindless_image_atomic_umax = {
	669	.name = "bindless_image_atomic_umax",
	670	.srcs_n = 4,
	671	.src_components_n = {
	672	1,4,1,1
	673	},
	674	.has_dest = true,
	675	.dest_components_n = 1,
	676	.idxs_n = 4,
	677	.idxs_map = {
	678	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	679	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	680	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	681	[NIR_INTRINSIC_IDX_ACCESS] = 4
	682	}
	683	};
	684	struct nir_intrinsic nir_bindless_image_atomic_and = {
	685	.name = "bindless_image_atomic_and",
	686	.srcs_n = 4,
	687	.src_components_n = {
	688	1,4,1,1
	689	},
	690	.has_dest = true,
	691	.dest_components_n = 1,
	692	.idxs_n = 4,
	693	.idxs_map = {
	694	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	695	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	696	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	697	[NIR_INTRINSIC_IDX_ACCESS] = 4
	698	}
	699	};
	700	struct nir_intrinsic nir_bindless_image_atomic_or = {
	701	.name = "bindless_image_atomic_or",
	702	.srcs_n = 4,
	703	.src_components_n = {
	704	1,4,1,1
	705	},
	706	.has_dest = true,
	707	.dest_components_n = 1,
	708	.idxs_n = 4,
	709	.idxs_map = {
	710	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	711	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	712	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	713	[NIR_INTRINSIC_IDX_ACCESS] = 4
	714	}
	715	};
	716	struct nir_intrinsic nir_bindless_image_atomic_xor = {
	717	.name = "bindless_image_atomic_xor",
	718	.srcs_n = 4,
	719	.src_components_n = {
	720	1,4,1,1
	721	},
	722	.has_dest = true,
	723	.dest_components_n = 1,
	724	.idxs_n = 4,
	725	.idxs_map = {
	726	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	727	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	728	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	729	[NIR_INTRINSIC_IDX_ACCESS] = 4
	730	}
	731	};
	732	struct nir_intrinsic nir_bindless_image_atomic_exchange = {
	733	.name = "bindless_image_atomic_exchange",
	734	.srcs_n = 4,
	735	.src_components_n = {
	736	1,4,1,1
	737	},
	738	.has_dest = true,
	739	.dest_components_n = 1,
	740	.idxs_n = 4,
	741	.idxs_map = {
	742	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	743	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	744	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	745	[NIR_INTRINSIC_IDX_ACCESS] = 4
	746	}
	747	};
	748	struct nir_intrinsic nir_bindless_image_atomic_comp_swap = {
	749	.name = "bindless_image_atomic_comp_swap",
	750	.srcs_n = 5,
	751	.src_components_n = {
	752	1,4,1,1,1
	753	},
	754	.has_dest = true,
	755	.dest_components_n = 1,
	756	.idxs_n = 4,
	757	.idxs_map = {
	758	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	759	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	760	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	761	[NIR_INTRINSIC_IDX_ACCESS] = 4
	762	}
	763	};
	764	struct nir_intrinsic nir_bindless_image_atomic_fadd = {
	765	.name = "bindless_image_atomic_fadd",
	766	.srcs_n = 5,
	767	.src_components_n = {
	768	1,1,4,1,1
	769	},
	770	.has_dest = true,
	771	.dest_components_n = 1,
	772	.idxs_n = 4,
	773	.idxs_map = {
	774	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	775	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	776	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	777	[NIR_INTRINSIC_IDX_ACCESS] = 4
	778	}
	779	};
	780	struct nir_intrinsic nir_bindless_image_size = {
	781	.name = "bindless_image_size",
	782	.srcs_n = 1,
	783	.src_components_n = {
	784	1
	785	},
	786	.has_dest = true,
	787	.idxs_n = 4,
	788	.idxs_map = {
	789	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	790	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	791	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	792	[NIR_INTRINSIC_IDX_ACCESS] = 4
	793	},
	794	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	795	};
	796	struct nir_intrinsic nir_bindless_image_samples = {
	797	.name = "bindless_image_samples",
	798	.srcs_n = 1,
	799	.src_components_n = {
	800	1
	801	},
	802	.has_dest = true,
	803	.dest_components_n = 1,
	804	.idxs_n = 4,
	805	.idxs_map = {
	806	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	807	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	808	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	809	[NIR_INTRINSIC_IDX_ACCESS] = 4
	810	},
	811	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	812	};
	813	struct nir_intrinsic nir_bindless_image_load_raw_intel = {
	814	.name = "bindless_image_load_raw_intel",
	815	.srcs_n = 2,
	816	.src_components_n = {
	817	1,1
	818	},
	819	.has_dest = true,
	820	.idxs_n = 4,
	821	.idxs_map = {
	822	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	823	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	824	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	825	[NIR_INTRINSIC_IDX_ACCESS] = 4
	826	},
	827	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
	828	};
	829	struct nir_intrinsic nir_bindless_image_store_raw_intel = {
	830	.name = "bindless_image_store_raw_intel",
	831	.srcs_n = 3,
	832	.src_components_n = {
	833	1,1,0
	834	},
	835	.idxs_n = 4,
	836	.idxs_map = {
	837	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	838	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	839	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	840	[NIR_INTRINSIC_IDX_ACCESS] = 4
	841	}
	842	};
	843	struct nir_intrinsic nir_bindless_image_atomic_inc_wrap = {
	844	.name = "bindless_image_atomic_inc_wrap",
	845	.srcs_n = 4,
	846	.src_components_n = {
	847	1,4,1,1
	848	},
	849	.has_dest = true,
	850	.dest_components_n = 1,
	851	.idxs_n = 4,
	852	.idxs_map = {
	853	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	854	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	855	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	856	[NIR_INTRINSIC_IDX_ACCESS] = 4
	857	}
	858	};
	859	struct nir_intrinsic nir_bindless_image_atomic_dec_wrap = {
	860	.name = "bindless_image_atomic_dec_wrap",
	861	.srcs_n = 4,
	862	.src_components_n = {
	863	1,4,1,1
	864	},
	865	.has_dest = true,
	866	.dest_components_n = 1,
	867	.idxs_n = 4,
	868	.idxs_map = {
	869	[NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
	870	[NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
	871	[NIR_INTRINSIC_IDX_FORMAT] = 3,
	872	[NIR_INTRINSIC_IDX_ACCESS] = 4
	873	}
	874	};
	875	/* bindless version */
	876	/----------------------------------------------------------------------------/
	877	/* the following is solo */
	878	struct nir_intrinsic nir_image_deref_load_param_intel = {
	879	.name = "image_deref_load_param_intel",
	880	.srcs_n = 1,
	881	.src_components_n = {
	882	1
	883	},
	884	.has_dest = true,
	885	.dest_components_n = 0,
	886	.idxs_n = 1,
	887	.idxs_map = {
	888	[NIR_INTRINSIC_IDX_BASE] = 1
	889	},
	890	.flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE \| NIR_INTRINSIC_FLAGS_CAN_REORDER
	891	};

File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic_system_values.c copied from file builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic_system_values.c (similarity 100%)

File builders/mplayer-0/builder.sh changed (mode: 100644) (index 81edffa..81040e4)
1	1	src_name=mplayer	src_name=mplayer
2		date=2019-08-12
	2		date=2019-08-26
3	3	archive_name=$src_name-export-snapshot.tar.bz2	archive_name=$src_name-export-snapshot.tar.bz2
4	4	url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name	url0=http://www.mplayerhq.hu/MPlayer/releases/$archive_name
5		ffmpeg_git_commit=faa9cd312f02cec5f74658319d1119fcaa7f9088
	5		ffmpeg_git_commit=59da9dcd7ef6277e4e04998ced71b05a6083c635
6	6
7	7	src_dir=$src_dir_root/$src_name-export-$date	src_dir=$src_dir_root/$src_name-export-$date
8	8	cd $src_dir_root	cd $src_dir_root

File builders/xserver-0/builder.sh changed (mode: 100644) (index 6da8fff..2aa0a71)
1	1	src_name=xserver	src_name=xserver
2		git_commit=c69b37e8da87c9f76dbf4add7340a77ea443c760
	2		git_commit=4f27d1e05f67eb8953a9bbed7e6f34b03456c64f
3	3	git_url0=git://anongit.freedesktop.org/xorg/$src_name	git_url0=git://anongit.freedesktop.org/xorg/$src_name
4	4
5	5	src_dir=$src_dir_root/$src_name	src_dir=$src_dir_root/$src_name

Hints:
Before first commit, do not forget to setup your git environment:

git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):

git clone https://rocketgit.com/user/sylware/nyanlinux

Clone this repository using ssh (do not forget to upload a key first):

git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux

Clone this repository using git:

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You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:

... clone the repository ...
... make some changes and some commits ...
git push origin main

File builders/mesa-gl-1/contrib/compiler_nir.sh changed (mode: 100644) (index a133d98..20d31c8)
...	...	$src_dir/src/compiler/nir/nir_builtin_builder.c \
42	42	$src_dir/src/compiler/nir/nir_clone.c \	$src_dir/src/compiler/nir/nir_clone.c \
43	43	$src_dir/src/compiler/nir/nir_control_flow.c \	$src_dir/src/compiler/nir/nir_control_flow.c \
44	44	$src_dir/src/compiler/nir/nir_deref.c \	$src_dir/src/compiler/nir/nir_deref.c \
	45		$src_dir/src/compiler/nir/nir_divergence_analysis.c \
45	46	$src_dir/src/compiler/nir/nir_dominance.c \	$src_dir/src/compiler/nir/nir_dominance.c \
46	47	$src_dir/src/compiler/nir/nir_from_ssa.c \	$src_dir/src/compiler/nir/nir_from_ssa.c \
47	48	$src_dir/src/compiler/nir/nir_gather_info.c \	$src_dir/src/compiler/nir/nir_gather_info.c \

...	...	$src_dir/src/compiler/nir/nir_lower_packing.c \
90	91	$src_dir/src/compiler/nir/nir_lower_passthrough_edgeflags.c \	$src_dir/src/compiler/nir/nir_lower_passthrough_edgeflags.c \
91	92	$src_dir/src/compiler/nir/nir_lower_patch_vertices.c \	$src_dir/src/compiler/nir/nir_lower_patch_vertices.c \
92	93	$src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \	$src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \
	94		$src_dir/src/compiler/nir/nir_lower_point_size.c \
93	95	$src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \	$src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \
94	96	$src_dir/src/compiler/nir/nir_lower_returns.c \	$src_dir/src/compiler/nir/nir_lower_returns.c \
95	97	$src_dir/src/compiler/nir/nir_lower_scratch.c \	$src_dir/src/compiler/nir/nir_lower_scratch.c \

...	...	$src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \
107	109	$src_dir/src/compiler/nir/nir_lower_bit_size.c \	$src_dir/src/compiler/nir/nir_lower_bit_size.c \
108	110	$src_dir/src/compiler/nir/nir_lower_uniforms_to_ubo.c \	$src_dir/src/compiler/nir/nir_lower_uniforms_to_ubo.c \
109	111	$src_dir/src/compiler/nir/nir_metadata.c \	$src_dir/src/compiler/nir/nir_metadata.c \
110		$src_dir/src/compiler/nir/nir_move_load_const.c \
111	112	$src_dir/src/compiler/nir/nir_move_vec_src_uses_to_dest.c \	$src_dir/src/compiler/nir/nir_move_vec_src_uses_to_dest.c \
112	113	$src_dir/src/compiler/nir/nir_normalize_cubemap_coords.c \	$src_dir/src/compiler/nir/nir_normalize_cubemap_coords.c \
113	114	$src_dir/src/compiler/nir/nir_opt_combine_stores.c \	$src_dir/src/compiler/nir/nir_opt_combine_stores.c \

...	...	$src_dir/src/compiler/nir/nir_opt_if.c \
127	128	$src_dir/src/compiler/nir/nir_opt_intrinsics.c \	$src_dir/src/compiler/nir/nir_opt_intrinsics.c \
128	129	$src_dir/src/compiler/nir/nir_opt_large_constants.c \	$src_dir/src/compiler/nir/nir_opt_large_constants.c \
129	130	$src_dir/src/compiler/nir/nir_opt_loop_unroll.c \	$src_dir/src/compiler/nir/nir_opt_loop_unroll.c \
130		$src_dir/src/compiler/nir/nir_opt_move_comparisons.c \
131		$src_dir/src/compiler/nir/nir_opt_move_load_ubo.c \
	131		$src_dir/src/compiler/nir/nir_opt_move.c \
132	132	$src_dir/src/compiler/nir/nir_opt_peephole_select.c \	$src_dir/src/compiler/nir/nir_opt_peephole_select.c \
133	133	$src_dir/src/compiler/nir/nir_opt_rematerialize_compares.c \	$src_dir/src/compiler/nir/nir_opt_rematerialize_compares.c \
134	134	$src_dir/src/compiler/nir/nir_opt_remove_phis.c \	$src_dir/src/compiler/nir/nir_opt_remove_phis.c \
135	135	$src_dir/src/compiler/nir/nir_opt_shrink_load.c \	$src_dir/src/compiler/nir/nir_opt_shrink_load.c \
	136		$src_dir/src/compiler/nir/nir_opt_sink.c \
136	137	$src_dir/src/compiler/nir/nir_opt_trivial_continues.c \	$src_dir/src/compiler/nir/nir_opt_trivial_continues.c \
137	138	$src_dir/src/compiler/nir/nir_opt_undef.c \	$src_dir/src/compiler/nir/nir_opt_undef.c \
138	139	$src_dir/src/compiler/nir/nir_opt_vectorize.c \	$src_dir/src/compiler/nir/nir_opt_vectorize.c \

File builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index c1c1588..3f5948c)
...	...	libLLVMSupport.a:\
470	470	libLLVMXRay.a:\	libLLVMXRay.a:\
471	471	libLLVMTarget.a:\	libLLVMTarget.a:\
472	472	libLLVMAMDGPUDisassembler.a:\	libLLVMAMDGPUDisassembler.a:\
473		libLLVMRuntimeDyld.a"
	473		libLLVMRuntimeDyld.a:\
	474		libLLVMTextAPI.a"
474	475	fi	fi
475	476
476	477	if test "${llvm_ldflags-unset}" = unset; then	if test "${llvm_ldflags-unset}" = unset; then

...	...	llvm_ldflags="\
536	537	/nyan/llvm/current/lib/libLLVMTarget.a \	/nyan/llvm/current/lib/libLLVMTarget.a \
537	538	/nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \	/nyan/llvm/current/lib/libLLVMAMDGPUDisassembler.a \
538	539	/nyan/llvm/current/lib/libLLVMRuntimeDyld.a \	/nyan/llvm/current/lib/libLLVMRuntimeDyld.a \
	540		/nyan/llvm/current/lib/libLLVMTextAPI.a \
539	541	-Wl,--end-group \	-Wl,--end-group \
540	542	"	"
541	543	fi	fi

...	...	$src_dir/src/compiler/nir/nir_builtin_builder.c \
910	912	$src_dir/src/compiler/nir/nir_clone.c \	$src_dir/src/compiler/nir/nir_clone.c \
911	913	$src_dir/src/compiler/nir/nir_control_flow.c \	$src_dir/src/compiler/nir/nir_control_flow.c \
912	914	$src_dir/src/compiler/nir/nir_deref.c \	$src_dir/src/compiler/nir/nir_deref.c \
	915		$src_dir/src/compiler/nir/nir_divergence_analysis.c \
913	916	$src_dir/src/compiler/nir/nir_dominance.c \	$src_dir/src/compiler/nir/nir_dominance.c \
914	917	$src_dir/src/compiler/nir/nir_from_ssa.c \	$src_dir/src/compiler/nir/nir_from_ssa.c \
915	918	$src_dir/src/compiler/nir/nir_gather_info.c \	$src_dir/src/compiler/nir/nir_gather_info.c \

...	...	$src_dir/src/compiler/nir/nir_lower_packing.c \
958	961	$src_dir/src/compiler/nir/nir_lower_passthrough_edgeflags.c \	$src_dir/src/compiler/nir/nir_lower_passthrough_edgeflags.c \
959	962	$src_dir/src/compiler/nir/nir_lower_patch_vertices.c \	$src_dir/src/compiler/nir/nir_lower_patch_vertices.c \
960	963	$src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \	$src_dir/src/compiler/nir/nir_lower_phis_to_scalar.c \
	964		$src_dir/src/compiler/nir/nir_lower_point_size.c \
961	965	$src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \	$src_dir/src/compiler/nir/nir_lower_regs_to_ssa.c \
962	966	$src_dir/src/compiler/nir/nir_lower_returns.c \	$src_dir/src/compiler/nir/nir_lower_returns.c \
963	967	$src_dir/src/compiler/nir/nir_lower_scratch.c \	$src_dir/src/compiler/nir/nir_lower_scratch.c \

...	...	$src_dir/src/compiler/nir/nir_lower_viewport_transform.c \
973	977	$src_dir/src/compiler/nir/nir_lower_wpos_center.c \	$src_dir/src/compiler/nir/nir_lower_wpos_center.c \
974	978	$src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \	$src_dir/src/compiler/nir/nir_lower_wpos_ytransform.c \
975	979	$src_dir/src/compiler/nir/nir_metadata.c \	$src_dir/src/compiler/nir/nir_metadata.c \
976		$src_dir/src/compiler/nir/nir_move_load_const.c \
977	980	$src_dir/src/compiler/nir/nir_move_vec_src_uses_to_dest.c \	$src_dir/src/compiler/nir/nir_move_vec_src_uses_to_dest.c \
978	981	$src_dir/src/compiler/nir/nir_normalize_cubemap_coords.c \	$src_dir/src/compiler/nir/nir_normalize_cubemap_coords.c \
979	982	$src_dir/src/compiler/nir/nir_opt_combine_stores.c \	$src_dir/src/compiler/nir/nir_opt_combine_stores.c \

...	...	$src_dir/src/compiler/nir/nir_opt_gcm.c \
991	994	$src_dir/src/compiler/nir/nir_opt_if.c \	$src_dir/src/compiler/nir/nir_opt_if.c \
992	995	$src_dir/src/compiler/nir/nir_opt_intrinsics.c \	$src_dir/src/compiler/nir/nir_opt_intrinsics.c \
993	996	$src_dir/src/compiler/nir/nir_opt_loop_unroll.c \	$src_dir/src/compiler/nir/nir_opt_loop_unroll.c \
994		$src_dir/src/compiler/nir/nir_opt_move_comparisons.c \
995		$src_dir/src/compiler/nir/nir_opt_move_load_ubo.c \
	997		$src_dir/src/compiler/nir/nir_opt_move.c \
996	998	$src_dir/src/compiler/nir/nir_opt_peephole_select.c \	$src_dir/src/compiler/nir/nir_opt_peephole_select.c \
997	999	$src_dir/src/compiler/nir/nir_opt_remove_phis.c \	$src_dir/src/compiler/nir/nir_opt_remove_phis.c \
998	1000	$src_dir/src/compiler/nir/nir_opt_shrink_load.c \	$src_dir/src/compiler/nir/nir_opt_shrink_load.c \
	1001		$src_dir/src/compiler/nir/nir_opt_sink.c \
999	1002	$src_dir/src/compiler/nir/nir_opt_trivial_continues.c \	$src_dir/src/compiler/nir/nir_opt_trivial_continues.c \
1000	1003	$src_dir/src/compiler/nir/nir_opt_undef.c \	$src_dir/src/compiler/nir/nir_opt_undef.c \
1001	1004	$src_dir/src/compiler/nir/nir_opt_vectorize.c \	$src_dir/src/compiler/nir/nir_opt_vectorize.c \