sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
gfx stack update e77750988b70fd80025d2976b356610c29245112 Sylvain BERTRAND 2020-09-13 17:44:23
gfx stack update a3e78c179a9448d58de3c8570f8e481c1a3cb2a9 Sylvain BERTRAND 2020-09-06 19:11:59
x86:steam distributes the alsa-lib which breaks everything 49a7145777ae0033d8d203ab1afeec92e6ce64e1 Sylvain BERTRAND 2020-08-29 20:04:11
libxkbcommon with reasonable sdk 5a16c5350e09e0cc68fb4d842b9588994a04c944 Sylvain BERTRAND 2020-08-29 18:56:21
gfx stack update 76a10355fbb5a94dbe3f7b6fa2780cbe5ff9ec71 Sylvain BERTRAND 2020-08-24 21:43:41
gfx stack update caa9a0f9059e3c8140a10abe2b02d20faade28e7 Sylvain BERTRAND 2020-08-16 16:21:05
backup some wip 587cb6b5375b10533ebf92e4c151756f4541af7c Sylvain BERTRAND 2020-07-26 23:47:29
alsa-lib:wrong way to use a git snapshot here fb3c82ebddcd320bb7c435c80f88ac65b45401cf Sylvain BERTRAND 2020-07-26 23:35:30
gfx stack update 1a61af333cf6f4264679987cb53cb1258eca5b6f Sylvain BERTRAND 2020-07-26 22:15:23
update some c++ cr*p cf6270785e5ab1deaefdf3a09a5eb476f246bdda Sylvain BERTRAND 2020-07-19 21:43:11
gfx stack update 8a470044332a4ab0bb2f4247632d4ddc05591540 Sylvain BERTRAND 2020-07-19 21:42:01
gfx stack update 2c819ea9ca081c61a9e5f7961c188324e623b53d Sylvain BERTRAND 2020-07-12 17:50:40
gfx stack update bdc04d6f6e371752d5ff32737f1de0511cebe2b2 Sylvain BERTRAND 2020-07-05 18:03:47
gfx stack update 6bf84e0e956e8676945e47d8457f4b63857c912f Sylvain BERTRAND 2020-06-29 18:23:49
gfx stack update e5bc37ec0e4e5b33446eb377eb3c66f33ad79020 Sylvain BERTRAND 2020-06-15 02:43:05
add sample code for raw x11 cursor visibility 042be7d6259fd2ab4c759409fb0dceaf3043f4d9 Sylvain BERTRAND 2020-06-09 15:04:53
gfx stack update 7518a03d3592c7eefd8266d73545a803054fd807 Sylvain BERTRAND 2020-06-07 17:37:18
dwm: add npv to floating layout c270a17aeaee624528587328942ba20cd29a9e37 Sylvain BERTRAND 2020-06-05 22:19:55
st: update c4cdf6d812f06b0df6258fee5f798301c75744d7 Sylvain BERTRAND 2020-05-31 22:16:26
gfx stack update 53541f08719e9d5ea0757216d98790823fa34051 Sylvain BERTRAND 2020-05-31 14:37:45
Commit e77750988b70fd80025d2976b356610c29245112 - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2020-09-13 17:44
Committer name: Sylvain BERTRAND
Committer date (UTC): 2020-09-13 17:44
Parent(s): a3e78c179a9448d58de3c8570f8e481c1a3cb2a9
Signer:
Signing key:
Signing status: N
Tree: 311c0da58405eeab8b44fb109cea6123cd584cc4
File Lines added Lines deleted
builders/dwm-0/config.h 18 18
builders/ffmpeg-1/builder.sh 1 1
builders/llvm-1/builder.sh 1 1
builders/mesa-gl-0/builder.sh 1 1
builders/mesa-gl-0/contrib/amd.sh 16 4
builders/mesa-gl-0/contrib/gallium_auxiliary.sh 0 1
builders/mesa-gl-0/contrib/util.sh 7 5
builders/mesa-gl-0/contrib/x86_64_linux_glibc_amdgpu.sh 1 0
builders/mesa-vulkan-0/builder.sh 1 1
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/image.c 120 12
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/load.c 24 2
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/system_values.c 8 0
builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/intel/intel.c 12 0
builders/mesa-vulkan-0/contrib/generators/nir/nir_database_alu.c 41 6
builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c 43 26
builders/mesa-vulkan-0/contrib/generators/nir/nir_intrinsics_c.c 1 0
builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 22 4
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/intel/intel.c 12 0
builders/mesa-vulkan/builder.sh 4 2
builders/nyanmp-0/builder.sh 1 1
builders/xserver-1/builder.sh 1 1
File builders/dwm-0/config.h changed (mode: 100644) (index 6696aac..e8e4a1e)
... ... static const Layout layouts[] = {
57 57 { MODKEY|ControlMask|ShiftMask, KEY, toggletag, {.ui = 1 << TAG} }, { MODKEY|ControlMask|ShiftMask, KEY, toggletag, {.ui = 1 << TAG} },
58 58
59 59 #define TAGKEYS(KEY,TAG) \ #define TAGKEYS(KEY,TAG) \
60 { MODKEY|ControlMask, KEY, view, {.ui = 1 << TAG} }, \
61 { MODKEY|ControlMask|ShiftMask, KEY, tag, {.ui = 1 << TAG} },
60 { MODKEY|ShiftMask, KEY, view, {.ui = 1 << TAG} }, \
61 { MODKEY|ShiftMask|ControlMask, KEY, tag, {.ui = 1 << TAG} },
62 62
63 63 /* helper for spawning shell commands in the pre dwm-5.0 fashion */ /* helper for spawning shell commands in the pre dwm-5.0 fashion */
64 64 #define SHCMD(cmd) { .v = (const char*[]){ "/bin/sh", "-c", cmd, NULL } } #define SHCMD(cmd) { .v = (const char*[]){ "/bin/sh", "-c", cmd, NULL } }
 
... ... static Key keys[] = {
79 79 { 0, XF86XK_HomePage, spawn, {.v = linkscmd } }, { 0, XF86XK_HomePage, spawn, {.v = linkscmd } },
80 80 { ShiftMask, XF86XK_HomePage, spawn, {.v = norepcmd } }, { ShiftMask, XF86XK_HomePage, spawn, {.v = norepcmd } },
81 81 { 0, XF86XK_Mail, spawn, {.v = bgcmd } }, { 0, XF86XK_Mail, spawn, {.v = bgcmd } },
82 { MODKEY|ControlMask, XK_b, togglebar, {0} },
83 { MODKEY|ControlMask, XK_Page_Down, focusstack, {.i = +1 } },
84 { MODKEY|ControlMask, XK_Page_Up, focusstack, {.i = -1 } },
85 { MODKEY|ControlMask|ShiftMask, XK_n, incnmaster, {.i = +1 } },
86 { MODKEY|ControlMask|ShiftMask, XK_d, incnmaster, {.i = -1 } },
87 { MODKEY|ControlMask|ShiftMask, XK_h, setmfact, {.f = -0.05} },
88 { MODKEY|ControlMask, XK_h, togglefullscr, {0} },
89 { MODKEY|ControlMask|ShiftMask, XK_t, setmfact, {.f = +0.05} },
90 { MODKEY|ControlMask, XK_Return, zoom, {0} },
82 { MODKEY|ShiftMask, XK_b, togglebar, {0} },
83 { MODKEY|ShiftMask, XK_Page_Down, focusstack, {.i = +1 } },
84 { MODKEY|ShiftMask, XK_Page_Up, focusstack, {.i = -1 } },
85 { MODKEY|ShiftMask, XK_n, incnmaster, {.i = +1 } },
86 { MODKEY|ShiftMask, XK_d, incnmaster, {.i = -1 } },
87 { MODKEY|ShiftMask, XK_h, setmfact, {.f = -0.05} },
88 { MODKEY|ShiftMask, XK_z, togglefullscr, {0} },
89 { MODKEY|ShiftMask, XK_t, setmfact, {.f = +0.05} },
90 { MODKEY|ShiftMask, XK_Return, zoom, {0} },
91 91 // { MODKEY, XK_Tab, view, {0} }, // { MODKEY, XK_Tab, view, {0} },
92 { MODKEY|ControlMask|ShiftMask, XK_c, killclient, {0} },
93 { MODKEY|ControlMask, XK_t, setlayout, {.v = &layouts[0]} },
94 { MODKEY|ControlMask, XK_f, setlayout, {.v = &layouts[1]} },
95 { MODKEY|ControlMask, XK_m, setlayout, {.v = &layouts[2]} },
92 { MODKEY|ShiftMask, XK_c, killclient, {0} },
93 { MODKEY|ShiftMask, XK_t, setlayout, {.v = &layouts[0]} },
94 { MODKEY|ShiftMask, XK_f, setlayout, {.v = &layouts[1]} },
95 { MODKEY|ShiftMask, XK_m, setlayout, {.v = &layouts[2]} },
96 96 // { MODKEY, XK_space, setlayout, {0} }, // { MODKEY, XK_space, setlayout, {0} },
97 97 // { MODKEY|ShiftMask, XK_space, togglefloating, {0} }, // { MODKEY|ShiftMask, XK_space, togglefloating, {0} },
98 98 // { MODKEY, XK_0, view, {.ui = ~0 } }, // { MODKEY, XK_0, view, {.ui = ~0 } },
 
... ... static Button buttons[] = {
121 121 // { ClkLtSymbol, 0, Button3, setlayout, {.v = &layouts[2]} }, // { ClkLtSymbol, 0, Button3, setlayout, {.v = &layouts[2]} },
122 122 // { ClkWinTitle, 0, Button2, zoom, {0} }, // { ClkWinTitle, 0, Button2, zoom, {0} },
123 123 // { ClkStatusText, 0, Button2, spawn, {.v = termcmd } }, // { ClkStatusText, 0, Button2, spawn, {.v = termcmd } },
124 { ClkClientWin, MODKEY|ControlMask, Button1, movemouse, {0} },
125 { ClkClientWin, MODKEY|ControlMask, Button2, togglefloating, {0} },
126 { ClkClientWin, MODKEY|ControlMask, Button3, resizemouse, {0} },
124 { ClkClientWin, MODKEY|ShiftMask, Button1, movemouse, {0} },
125 { ClkClientWin, MODKEY|ShiftMask, Button2, togglefloating, {0} },
126 { ClkClientWin, MODKEY|ShiftMask, Button3, resizemouse, {0} },
127 127 // { ClkTagBar, 0, Button1, view, {0} }, // { ClkTagBar, 0, Button1, view, {0} },
128 128 // { ClkTagBar, 0, Button3, toggleview, {0} }, // { ClkTagBar, 0, Button3, toggleview, {0} },
129 129 // { ClkTagBar, MODKEY, Button1, tag, {0} }, // { ClkTagBar, MODKEY, Button1, tag, {0} },
File builders/ffmpeg-1/builder.sh changed (mode: 100644) (index 0168fe2..c9eb2e5)
1 git_commit=341064d68a134e2fb3dd35f8f5b50c6df8506c10
1 git_commit=ddc9cce3cd20fdf8d523e4bab3cab55de6b862b0
2 2 slot=1 slot=1
3 3 . $nyan_root/builders/ffmpeg/builder.sh . $nyan_root/builders/ffmpeg/builder.sh
File builders/llvm-1/builder.sh changed (mode: 100644) (index 08a7707..5711d20)
1 git_commit=bdb25b3ce5479a820a4c6539d22aeedad7e06875
1 git_commit=e2dee9af8db645fd3c0351da91d3cb09c1dcdd5d
2 2 version=12.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt version=12.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt
3 3 slot=1 slot=1
4 4 . $nyan_root/builders/llvm/builder.sh . $nyan_root/builders/llvm/builder.sh
File builders/mesa-gl-0/builder.sh changed (mode: 100644) (index 0e809f3..a60be53)
1 git_commit=ac6b8e42ce20e5003af0846602af3f5caec182fa
1 git_commit=4868ce1451ffceb65a03ef230da01da639286c2c
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/mesa-gl/builder.sh . $nyan_root/builders/mesa-gl/builder.sh
File builders/mesa-gl-0/contrib/amd.sh changed (mode: 100644) (index daadebd..72ab6a9)
... ... mkdir -p $build_dir/src/amd
54 54 $python3 \ $python3 \
55 55 $src_dir/src/amd/common/sid_tables.py \ $src_dir/src/amd/common/sid_tables.py \
56 56 $src_dir/src/amd/common/sid.h \ $src_dir/src/amd/common/sid.h \
57 $src_dir/src/amd/registers/amdgfxregs.json \
58 $src_dir/src/amd/registers/pkt3.json \
57 $src_dir/src/amd/registers/gfx6.json \
58 $src_dir/src/amd/registers/gfx7.json \
59 $src_dir/src/amd/registers/gfx8.json \
60 $src_dir/src/amd/registers/gfx81.json \
61 $src_dir/src/amd/registers/gfx9.json \
59 62 $src_dir/src/amd/registers/gfx10.json \ $src_dir/src/amd/registers/gfx10.json \
60 63 $src_dir/src/amd/registers/gfx10-rsrc.json \ $src_dir/src/amd/registers/gfx10-rsrc.json \
64 $src_dir/src/amd/registers/gfx103.json \
65 $src_dir/src/amd/registers/pkt3.json \
66 $src_dir/src/amd/registers/registers-manually-defined.json \
61 67 >$build_dir/src/amd/sid_tables.h >$build_dir/src/amd/sid_tables.h
62 68
63 69 $python3 \ $python3 \
64 70 $src_dir/src/amd/registers/makeregheader.py \ $src_dir/src/amd/registers/makeregheader.py \
65 $src_dir/src/amd/registers/amdgfxregs.json \
66 $src_dir/src/amd/registers/pkt3.json \
71 $src_dir/src/amd/registers/gfx6.json \
72 $src_dir/src/amd/registers/gfx7.json \
73 $src_dir/src/amd/registers/gfx8.json \
74 $src_dir/src/amd/registers/gfx81.json \
75 $src_dir/src/amd/registers/gfx9.json \
67 76 $src_dir/src/amd/registers/gfx10.json \ $src_dir/src/amd/registers/gfx10.json \
68 77 $src_dir/src/amd/registers/gfx10-rsrc.json \ $src_dir/src/amd/registers/gfx10-rsrc.json \
78 $src_dir/src/amd/registers/gfx103.json \
79 $src_dir/src/amd/registers/pkt3.json \
80 $src_dir/src/amd/registers/registers-manually-defined.json \
69 81 --sort address \ --sort address \
70 82 --guard AMDGFXREGS_H \ --guard AMDGFXREGS_H \
71 83 >$build_dir/src/amd/amdgfxregs.h >$build_dir/src/amd/amdgfxregs.h
File builders/mesa-gl-0/contrib/gallium_auxiliary.sh changed (mode: 100644) (index 73ada2a..f41322b)
... ... $src_dir/src/gallium/auxiliary/util/u_gen_mipmap.c \
151 151 $src_dir/src/gallium/auxiliary/util/u_handle_table.c \ $src_dir/src/gallium/auxiliary/util/u_handle_table.c \
152 152 $src_dir/src/gallium/auxiliary/util/u_hash_table.c \ $src_dir/src/gallium/auxiliary/util/u_hash_table.c \
153 153 $src_dir/src/gallium/auxiliary/util/u_helpers.c \ $src_dir/src/gallium/auxiliary/util/u_helpers.c \
154 $src_dir/src/gallium/auxiliary/util/u_idalloc.c \
155 154 $src_dir/src/gallium/auxiliary/util/u_index_modify.c \ $src_dir/src/gallium/auxiliary/util/u_index_modify.c \
156 155 $src_dir/src/gallium/auxiliary/util/u_linear.c \ $src_dir/src/gallium/auxiliary/util/u_linear.c \
157 156 $src_dir/src/gallium/auxiliary/util/u_live_shader_cache.c \ $src_dir/src/gallium/auxiliary/util/u_live_shader_cache.c \
File builders/mesa-gl-0/contrib/util.sh changed (mode: 100644) (index e26d5e7..219bc2d)
... ... $src_dir/src/util/build_id.c \
28 28 $src_dir/src/util/crc32.c \ $src_dir/src/util/crc32.c \
29 29 $src_dir/src/util/debug.c \ $src_dir/src/util/debug.c \
30 30 $src_dir/src/util/disk_cache.c \ $src_dir/src/util/disk_cache.c \
31 $src_dir/src/util/disk_cache_os.c \
31 32 $src_dir/src/util/double.c \ $src_dir/src/util/double.c \
32 33 $src_dir/src/util/fast_idiv_by_const.c \ $src_dir/src/util/fast_idiv_by_const.c \
33 34 $src_dir/src/util/half_float.c \ $src_dir/src/util/half_float.c \
 
... ... $src_dir/src/util/format/u_format_s3tc.c \
63 64 $src_dir/src/util/format/u_format_tests.c \ $src_dir/src/util/format/u_format_tests.c \
64 65 $src_dir/src/util/format/u_format_yuv.c \ $src_dir/src/util/format/u_format_yuv.c \
65 66 $src_dir/src/util/format/u_format_zs.c \ $src_dir/src/util/format/u_format_zs.c \
66 $src_dir/src/util/u_queue.c \
67 $src_dir/src/util/u_vector.c \
68 $src_dir/src/util/u_math.c \
69 $src_dir/src/util/u_mm.c \
67 $src_dir/src/util/u_cpu_detect.c \
70 68 $src_dir/src/util/u_debug.c \ $src_dir/src/util/u_debug.c \
71 69 $src_dir/src/util/u_debug_stack.c \ $src_dir/src/util/u_debug_stack.c \
72 70 $src_dir/src/util/u_debug_symbol.c \ $src_dir/src/util/u_debug_symbol.c \
73 $src_dir/src/util/u_cpu_detect.c \
71 $src_dir/src/util/u_idalloc.c \
72 $src_dir/src/util/u_math.c \
73 $src_dir/src/util/u_mm.c \
74 $src_dir/src/util/u_queue.c \
75 $src_dir/src/util/u_vector.c \
74 76 $src_dir/src/util/vma.c \ $src_dir/src/util/vma.c \
75 77 " "
76 78
File builders/mesa-gl-0/contrib/x86_64_linux_glibc_amdgpu.sh changed (mode: 100755) (index e472625..81d910e)
... ... glibc_cppflags="\
141 141 -DHAVE_PTHREAD_SETAFFINITY=1 \ -DHAVE_PTHREAD_SETAFFINITY=1 \
142 142 \ \
143 143 -DHAVE_PROGRAM_INVOCATION_NAME=1 \ -DHAVE_PROGRAM_INVOCATION_NAME=1 \
144 -DHAVE_FLOCK=1 \
144 145 " "
145 146 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
146 147 # glibc linux wrappers # glibc linux wrappers
File builders/mesa-vulkan-0/builder.sh changed (mode: 100644) (index cbb79f0..e488340)
1 git_commit=ac6b8e42ce20e5003af0846602af3f5caec182fa
1 git_commit=4868ce1451ffceb65a03ef230da01da639286c2c
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/mesa-vulkan/builder.sh . $nyan_root/builders/mesa-vulkan/builder.sh
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/image.c changed (mode: 100644) (index 3f2e8b9..8bef3d0)
... ... struct nir_intrinsic nir_image_deref_load = {
27 27 }, },
28 28 .has_dest = true, .has_dest = true,
29 29 .dest_components_n = 0, .dest_components_n = 0,
30 .idxs_n = 1,
30 .idxs_n = 2,
31 31 .idxs_map = { .idxs_map = {
32 [NIR_INTRINSIC_IDX_ACCESS] = 1
32 [NIR_INTRINSIC_IDX_ACCESS] = 1,
33 [NIR_INTRINSIC_IDX_TYPE] = 2
33 34 }, },
34 35 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
35 36 }; };
 
... ... struct nir_intrinsic nir_image_deref_store = {
39 40 .src_components_n = { .src_components_n = {
40 41 1,4,1,0,1 1,4,1,0,1
41 42 }, },
42 .idxs_n = 1,
43 .idxs_n = 2,
43 44 .idxs_map = { .idxs_map = {
44 [NIR_INTRINSIC_IDX_ACCESS] = 1
45 [NIR_INTRINSIC_IDX_ACCESS] = 1,
46 [NIR_INTRINSIC_IDX_TYPE] = 2
45 47 } }
46 48 }; };
47 49 struct nir_intrinsic nir_image_deref_atomic_add = { struct nir_intrinsic nir_image_deref_atomic_add = {
 
... ... struct nir_intrinsic nir_image_deref_atomic_dec_wrap = {
240 242 [NIR_INTRINSIC_IDX_ACCESS] = 1 [NIR_INTRINSIC_IDX_ACCESS] = 1
241 243 } }
242 244 }; };
245 /* CL-specific format queries */
246 struct nir_intrinsic nir_image_deref_format = {
247 .name = "image_deref_format",
248 .srcs_n = 1,
249 .src_components_n = {
250 1
251 },
252 .has_dest = true,
253 .dest_components_n = 1,
254 .idxs_n = 1,
255 .idxs_map = {
256 [NIR_INTRINSIC_IDX_ACCESS] = 1
257 },
258 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
259 };
260 /* CL-specific format queries */
261 struct nir_intrinsic nir_image_deref_order = {
262 .name = "image_deref_order",
263 .srcs_n = 1,
264 .src_components_n = {
265 1
266 },
267 .has_dest = true,
268 .dest_components_n = 1,
269 .idxs_n = 1,
270 .idxs_map = {
271 [NIR_INTRINSIC_IDX_ACCESS] = 1
272 },
273 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
274 };
243 275 /* deref version */ /* deref version */
244 276 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
245 277 /* plain version */ /* plain version */
 
... ... struct nir_intrinsic nir_image_load = {
250 282 1,4,1,1 1,4,1,1
251 283 }, },
252 284 .has_dest = true, .has_dest = true,
253 .idxs_n = 4,
285 .idxs_n = 5,
254 286 .idxs_map = { .idxs_map = {
255 287 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1, [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
256 288 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2, [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
257 289 [NIR_INTRINSIC_IDX_FORMAT] = 3, [NIR_INTRINSIC_IDX_FORMAT] = 3,
258 [NIR_INTRINSIC_IDX_ACCESS] = 4
290 [NIR_INTRINSIC_IDX_ACCESS] = 4,
291 [NIR_INTRINSIC_IDX_TYPE] = 5
259 292 }, },
260 293 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
261 294 }; };
 
... ... struct nir_intrinsic nir_image_store = {
265 298 .src_components_n = { .src_components_n = {
266 299 1,4,1,0,1 1,4,1,0,1
267 300 }, },
268 .idxs_n = 4,
301 .idxs_n = 5,
269 302 .idxs_map = { .idxs_map = {
270 303 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1, [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
271 304 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2, [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
272 305 [NIR_INTRINSIC_IDX_FORMAT] = 3, [NIR_INTRINSIC_IDX_FORMAT] = 3,
273 [NIR_INTRINSIC_IDX_ACCESS] = 4
306 [NIR_INTRINSIC_IDX_ACCESS] = 4,
307 [NIR_INTRINSIC_IDX_TYPE] = 5
274 308 } }
275 309 }; };
276 310 struct nir_intrinsic nir_image_atomic_add = { struct nir_intrinsic nir_image_atomic_add = {
 
... ... struct nir_intrinsic nir_image_atomic_dec_wrap = {
514 548 [NIR_INTRINSIC_IDX_ACCESS] = 4 [NIR_INTRINSIC_IDX_ACCESS] = 4
515 549 } }
516 550 }; };
551 /* CL-specific format queries */
552 struct nir_intrinsic nir_image_format = {
553 .name = "image_format",
554 .srcs_n = 1,
555 .src_components_n = {
556 1
557 },
558 .has_dest = true,
559 .dest_components_n = 1,
560 .idxs_n = 4,
561 .idxs_map = {
562 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
563 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
564 [NIR_INTRINSIC_IDX_FORMAT] = 3,
565 [NIR_INTRINSIC_IDX_ACCESS] = 4
566 },
567 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
568 };
569 /* CL-specific format queries */
570 struct nir_intrinsic nir_image_order = {
571 .name = "image_order",
572 .srcs_n = 1,
573 .src_components_n = {
574 1
575 },
576 .has_dest = true,
577 .dest_components_n = 1,
578 .idxs_n = 4,
579 .idxs_map = {
580 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
581 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
582 [NIR_INTRINSIC_IDX_FORMAT] = 3,
583 [NIR_INTRINSIC_IDX_ACCESS] = 4
584 },
585 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
586 };
517 587 /* plain version */ /* plain version */
518 588 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
519 589 /* bindless version */ /* bindless version */
 
... ... struct nir_intrinsic nir_bindless_image_load = {
524 594 1,4,1,1 1,4,1,1
525 595 }, },
526 596 .has_dest = true, .has_dest = true,
527 .idxs_n = 4,
597 .idxs_n = 5,
528 598 .idxs_map = { .idxs_map = {
529 599 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1, [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
530 600 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2, [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
531 601 [NIR_INTRINSIC_IDX_FORMAT] = 3, [NIR_INTRINSIC_IDX_FORMAT] = 3,
532 [NIR_INTRINSIC_IDX_ACCESS] = 4
602 [NIR_INTRINSIC_IDX_ACCESS] = 4,
603 [NIR_INTRINSIC_IDX_TYPE] = 5
533 604 }, },
534 605 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
535 606 }; };
 
... ... struct nir_intrinsic nir_bindless_image_store = {
539 610 .src_components_n = { .src_components_n = {
540 611 1,4,1,0,1 1,4,1,0,1
541 612 }, },
542 .idxs_n = 4,
613 .idxs_n = 5,
543 614 .idxs_map = { .idxs_map = {
544 615 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1, [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
545 616 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2, [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
546 617 [NIR_INTRINSIC_IDX_FORMAT] = 3, [NIR_INTRINSIC_IDX_FORMAT] = 3,
547 [NIR_INTRINSIC_IDX_ACCESS] = 4
618 [NIR_INTRINSIC_IDX_ACCESS] = 4,
619 [NIR_INTRINSIC_IDX_TYPE] = 5
548 620 } }
549 621 }; };
550 622 struct nir_intrinsic nir_bindless_image_atomic_add = { struct nir_intrinsic nir_bindless_image_atomic_add = {
 
... ... struct nir_intrinsic nir_bindless_image_atomic_dec_wrap = {
788 860 [NIR_INTRINSIC_IDX_ACCESS] = 4 [NIR_INTRINSIC_IDX_ACCESS] = 4
789 861 } }
790 862 }; };
863 /* CL-specific format queries */
864 struct nir_intrinsic nir_bindless_image_format = {
865 .name = "bindless_image_format",
866 .srcs_n = 1,
867 .src_components_n = {
868 1
869 },
870 .has_dest = true,
871 .dest_components_n = 1,
872 .idxs_n = 4,
873 .idxs_map = {
874 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
875 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
876 [NIR_INTRINSIC_IDX_FORMAT] = 3,
877 [NIR_INTRINSIC_IDX_ACCESS] = 4
878 },
879 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
880 };
881 /* CL-specific format queries */
882 struct nir_intrinsic nir_bindless_image_order = {
883 .name = "bindless_image_order",
884 .srcs_n = 1,
885 .src_components_n = {
886 1
887 },
888 .has_dest = true,
889 .dest_components_n = 1,
890 .idxs_n = 4,
891 .idxs_map = {
892 [NIR_INTRINSIC_IDX_IMAGE_DIM] = 1,
893 [NIR_INTRINSIC_IDX_IMAGE_ARRAY] = 2,
894 [NIR_INTRINSIC_IDX_FORMAT] = 3,
895 [NIR_INTRINSIC_IDX_ACCESS] = 4
896 },
897 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
898 };
791 899 /* bindless version */ /* bindless version */
792 900 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/load.c changed (mode: 100644) (index 61908b9..883b487)
11 11 * range (starting at base) of the data from which we are loading. If * range (starting at base) of the data from which we are loading. If
12 12 * range == 0, then the range is unknown. * range == 0, then the range is unknown.
13 13 * *
14 * UBO load operations have a nir_intrinsic_range_base() and
15 * nir_intrinsic_range() that specify the byte range [range_base,
16 * range_base+range] of the UBO that the src offset access must lie within.
17 *
14 18 * Some load operations such as UBO/SSBO load and per_vertex loads take an * Some load operations such as UBO/SSBO load and per_vertex loads take an
15 19 * additional source to specify which UBO/SSBO/vertex to load from. * additional source to specify which UBO/SSBO/vertex to load from.
16 20 * *
 
... ... struct nir_intrinsic nir_load_ubo = {
43 47 -1,1 -1,1
44 48 }, },
45 49 .has_dest = true, .has_dest = true,
46 .idxs_n = 3,
50 .idxs_n = 5,
47 51 .idxs_map = { .idxs_map = {
48 52 [NIR_INTRINSIC_IDX_ACCESS] = 1, [NIR_INTRINSIC_IDX_ACCESS] = 1,
49 53 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2, [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
50 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
54 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3,
55 [NIR_INTRINSIC_IDX_RANGE_BASE] = 4,
56 [NIR_INTRINSIC_IDX_RANGE] = 5
51 57 }, },
52 58 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
53 59 }; };
 
... ... struct nir_intrinsic nir_load_global = {
255 261 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE
256 262 }; };
257 263 /* src[] = { address } */ /* src[] = { address } */
264 struct nir_intrinsic nir_load_global_constant = {
265 .name = "load_global_constant",
266 .srcs_n = 1,
267 .src_components_n = {
268 1
269 },
270 .has_dest = true,
271 .idxs_n = 3,
272 .idxs_map = {
273 [NIR_INTRINSIC_IDX_ACCESS] = 1,
274 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
275 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
276 },
277 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
278 };
279 /* src[] = { address } */
258 280 struct nir_intrinsic nir_load_kernel_input = { struct nir_intrinsic nir_load_kernel_input = {
259 281 .name = "load_kernel_input", .name = "load_kernel_input",
260 282 .srcs_n = 1, .srcs_n = 1,
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/generic/system_values.c changed (mode: 100644) (index 7a3aa02..89b8a3d)
... ... static struct nir_intrinsic nir_load_scratch_base_ptr = {
449 449 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER, .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
450 450 .system_value = true .system_value = true
451 451 }; };
452 static struct nir_intrinsic nir_load_constant_base_ptr = {
453 .name = "load_constant_base_ptr",
454 .has_dest = true,
455 .dest_components_n = 0,
456 .bit_szs = 0x60,
457 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER,
458 .system_value = true
459 };
452 460 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
453 461 /* /*
454 462 * Driver-specific viewport scale/offset parameters. * Driver-specific viewport scale/offset parameters.
File builders/mesa-vulkan-0/contrib/generators/nir/intrinsics/intel/intel.c added (mode: 100644) (index 0000000..799d8a4)
1 /* Load a relocatable 32-bit value */
2 static struct nir_intrinsic nir_load_reloc_const_intel = {
3 .name = "load_reloc_const_intel",
4 .has_dest = true,
5 .dest_components_n = 1,
6 .bit_szs = 0x20,
7 .idxs_n = 1,
8 .idxs_map = {
9 [NIR_INTRINSIC_IDX_PARAM_IDX] = 1
10 },
11 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
12 };
File builders/mesa-vulkan-0/contrib/generators/nir/nir_database_alu.c changed (mode: 100644) (index 9f719b2..45eae97)
31 31 #define NIR_OP_INPUTS_N_MAX 16 #define NIR_OP_INPUTS_N_MAX 16
32 32 #define NIR_OP_ALGEBRAIC_PROPERTIES_2SRC_COMMUTATIVE 0x01 #define NIR_OP_ALGEBRAIC_PROPERTIES_2SRC_COMMUTATIVE 0x01
33 33 #define NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE 0x02 #define NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE 0x02
34 /* XXX: conversion field is used only by the intel driver for now */
34 35 struct nir_op { struct nir_op {
35 36 char *name; char *name;
36 37 u8 type; u8 type;
 
... ... static struct nir_op nir_f2fmp = {
323 324 NIR_TYPE_FLOAT16, NIR_TYPE_FLOAT16,
324 325 1, 1,
325 326 {0}, {0},
326 {NIR_TYPE_FLOAT},
327 {NIR_TYPE_FLOAT32},
327 328 0 0
328 329 }; };
329 330 static struct nir_op nir_i2imp = { static struct nir_op nir_i2imp = {
 
... ... static struct nir_op nir_i2imp = {
333 334 NIR_TYPE_INT16, NIR_TYPE_INT16,
334 335 1, 1,
335 336 {0}, {0},
336 {NIR_TYPE_INT},
337 {NIR_TYPE_INT32},
338 0
339 };
340 /* u2ump isn't defined, because the behavior is equal to i2imp */
341 static struct nir_op nir_f2imp = {
342 "f2imp",
343 NIR_OP_TYPE_ALU,
344 0,
345 NIR_TYPE_INT16,
346 1,
347 {0},
348 {NIR_TYPE_FLOAT32},
337 349 0 0
338 350 }; };
339 static struct nir_op nir_u2ump = {
340 "u2ump",
351 static struct nir_op nir_f2ump = {
352 "f2ump",
341 353 NIR_OP_TYPE_ALU, NIR_OP_TYPE_ALU,
342 354 0, 0,
343 355 NIR_TYPE_UINT16, NIR_TYPE_UINT16,
344 356 1, 1,
345 357 {0}, {0},
346 {NIR_TYPE_UINT},
358 {NIR_TYPE_FLOAT32},
359 0
360 };
361 static struct nir_op nir_i2fmp = {
362 "i2fmp",
363 NIR_OP_TYPE_ALU,
364 0,
365 NIR_TYPE_FLOAT16,
366 1,
367 {0},
368 {NIR_TYPE_INT32},
369 0
370 };
371 static struct nir_op nir_u2fmp = {
372 "u2fmp",
373 NIR_OP_TYPE_ALU,
374 0,
375 NIR_TYPE_FLOAT16,
376 1,
377 {0},
378 {NIR_TYPE_UINT32},
347 379 0 0
348 380 }; };
349 381 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
 
... ... static struct nir_op *nir_ops[] = {
2038 2070 &nir_unpack_32_4x8, &nir_unpack_32_4x8,
2039 2071 &nir_pack_32_4x8, &nir_pack_32_4x8,
2040 2072 &nir_i2imp, &nir_i2imp,
2041 &nir_u2ump,
2042 2073 &nir_fisnormal, &nir_fisnormal,
2043 2074 &nir_fisfinite, &nir_fisfinite,
2075 &nir_f2imp,
2076 &nir_f2ump,
2077 &nir_i2fmp,
2078 &nir_u2fmp,
2044 2079 }; };
File builders/mesa-vulkan-0/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index a3fea81..f548195)
14 14 * not constant. * not constant.
15 15 */ */
16 16 #define NIR_INTRINSIC_IDX_RANGE 5 #define NIR_INTRINSIC_IDX_RANGE 5
17 /*
18 * The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative
19 * to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't
20 * have the implicit addition of a base to the offset.
21 */
22 #define NIR_INTRINSIC_IDX_RANGE_BASE 6
17 23 /* /*
18 24 * The vulkan descriptor set binding for vulkan_resource_index * The vulkan descriptor set binding for vulkan_resource_index
19 25 * intrinsic * intrinsic
20 26 */ */
21 #define NIR_INTRINSIC_IDX_DESC_SET 6
27 #define NIR_INTRINSIC_IDX_DESC_SET 7
22 28 /* /*
23 29 * The vulkan descriptor set binding for vulkan_resource_index * The vulkan descriptor set binding for vulkan_resource_index
24 30 * intrinsic * intrinsic
25 31 */ */
26 #define NIR_INTRINSIC_IDX_BINDING 7
32 #define NIR_INTRINSIC_IDX_BINDING 8
27 33 /* Component offset */ /* Component offset */
28 #define NIR_INTRINSIC_IDX_COMPONENT 8
34 #define NIR_INTRINSIC_IDX_COMPONENT 9
29 35 /* Interpolation mode (only meaningful for FS inputs) */ /* Interpolation mode (only meaningful for FS inputs) */
30 #define NIR_INTRINSIC_IDX_INTERP_MODE 9
36 #define NIR_INTRINSIC_IDX_INTERP_MODE 10
31 37 /* A binary nir_op to use when performing a reduction or scan operation */ /* A binary nir_op to use when performing a reduction or scan operation */
32 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10
38 #define NIR_INTRINSIC_IDX_REDUCTION_OP 11
33 39 /* Cluster size for reduction operations */ /* Cluster size for reduction operations */
34 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11
40 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 12
35 41 /* Parameter index for a load_param intrinsic */ /* Parameter index for a load_param intrinsic */
36 #define NIR_INTRINSIC_IDX_PARAM_IDX 12
42 #define NIR_INTRINSIC_IDX_PARAM_IDX 13
37 43 /* Image dimensionality for image intrinsics */ /* Image dimensionality for image intrinsics */
38 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13
44 #define NIR_INTRINSIC_IDX_IMAGE_DIM 14
39 45 /* Non-zero if we are accessing an array image */ /* Non-zero if we are accessing an array image */
40 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14
46 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 15
41 47 /* Image format for image intrinsics */ /* Image format for image intrinsics */
42 #define NIR_INTRINSIC_IDX_FORMAT 15
48 #define NIR_INTRINSIC_IDX_FORMAT 16
43 49 /* Access qualifiers for image and memory access intrinsics */ /* Access qualifiers for image and memory access intrinsics */
44 #define NIR_INTRINSIC_IDX_ACCESS 16
45 #define NIR_INTRINSIC_IDX_DST_ACCESS 17
46 #define NIR_INTRINSIC_IDX_SRC_ACCESS 18
50 #define NIR_INTRINSIC_IDX_ACCESS 17
51 #define NIR_INTRINSIC_IDX_DST_ACCESS 18
52 #define NIR_INTRINSIC_IDX_SRC_ACCESS 19
47 53 /* Offset or address alignment */ /* Offset or address alignment */
48 #define NIR_INTRINSIC_IDX_ALIGN_MUL 19
49 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 20
54 #define NIR_INTRINSIC_IDX_ALIGN_MUL 20
55 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 21
50 56 /* The vulkan descriptor type for vulkan_resource_index */ /* The vulkan descriptor type for vulkan_resource_index */
51 #define NIR_INTRINSIC_IDX_DESC_TYPE 21
57 #define NIR_INTRINSIC_IDX_DESC_TYPE 22
52 58 /* The nir_alu_type of a uniform/input/output */ /* The nir_alu_type of a uniform/input/output */
53 #define NIR_INTRINSIC_IDX_TYPE 22
59 #define NIR_INTRINSIC_IDX_TYPE 23
54 60 /* The swizzle mask for quad_swizzle_amd & masked_swizzle_amd */ /* The swizzle mask for quad_swizzle_amd & masked_swizzle_amd */
55 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 23
61 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 24
56 62 /* Driver location of attribute */ /* Driver location of attribute */
57 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 24
63 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 25
58 64 /* ordering and visibility of a memory operation */ /* ordering and visibility of a memory operation */
59 #define NIR_INTRINSIC_IDX_MEMORY_SEMANTICS 25
65 #define NIR_INTRINSIC_IDX_MEMORY_SEMANTICS 26
60 66 /* Modes affected by a memory operation */ /* Modes affected by a memory operation */
61 #define NIR_INTRINSIC_IDX_MEMORY_MODES 26
67 #define NIR_INTRINSIC_IDX_MEMORY_MODES 27
62 68 /* Scope of a memory operation */ /* Scope of a memory operation */
63 #define NIR_INTRINSIC_IDX_MEMORY_SCOPE 27
69 #define NIR_INTRINSIC_IDX_MEMORY_SCOPE 28
64 70 /* Scope of a control operation */ /* Scope of a control operation */
65 #define NIR_INTRINSIC_IDX_EXECUTION_SCOPE 28
66 #define NIR_INTRINSIC_IDX_IO_SEMANTICS 29
67 #define NIR_INTRINSIC_IDXS_N_MAX 30
71 #define NIR_INTRINSIC_IDX_EXECUTION_SCOPE 29
72 #define NIR_INTRINSIC_IDX_IO_SEMANTICS 30
73 #define NIR_INTRINSIC_IDXS_N_MAX 31
68 74
69 75 static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = { static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = {
70 76 "UNKNOWN_IDX", "UNKNOWN_IDX",
 
... ... static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = {
73 79 "nir_intrinsic_idx_stream_id", "nir_intrinsic_idx_stream_id",
74 80 "nir_intrinsic_idx_ucp_id", "nir_intrinsic_idx_ucp_id",
75 81 "nir_intrinsic_idx_range", "nir_intrinsic_idx_range",
82 "nir_intrinsic_idx_range_base",
76 83 "nir_intrinsic_idx_desc_set", "nir_intrinsic_idx_desc_set",
77 84 "nir_intrinsic_idx_binding", "nir_intrinsic_idx_binding",
78 85 "nir_intrinsic_idx_component", "nir_intrinsic_idx_component",
 
... ... struct nir_intrinsic {
142 149 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
143 150 #include "intrinsics/v3d/v3d.c" #include "intrinsics/v3d/v3d.c"
144 151 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
152 #include "intrinsics/intel/intel.c"
145 153 #include "intrinsics/intel/image.c" #include "intrinsics/intel/image.c"
146 154 #include "intrinsics/intel/system_values.c" #include "intrinsics/intel/system_values.c"
147 155
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
493 501 &nir_load_base_work_group_id, &nir_load_base_work_group_id,
494 502 &nir_load_global_invocation_id_zero_base, &nir_load_global_invocation_id_zero_base,
495 503 &nir_load_base_global_invocation_id, &nir_load_base_global_invocation_id,
496 &nir_load_ubo_vec4
504 &nir_load_ubo_vec4,
505 &nir_bindless_image_format,
506 &nir_image_deref_format,
507 &nir_image_format,
508 &nir_bindless_image_order,
509 &nir_image_deref_order,
510 &nir_image_order,
511 &nir_load_constant_base_ptr,
512 &nir_load_global_constant,
513 &nir_load_reloc_const_intel
497 514 }; };
File builders/mesa-vulkan-0/contrib/generators/nir/nir_intrinsics_c.c changed (mode: 100644) (index 2251e96..dab7aab)
... ... static char *idx_str(u8 idx)
101 101 case NIR_INTRINSIC_IDX_STREAM_ID: return "NIR_INTRINSIC_STREAM_ID"; case NIR_INTRINSIC_IDX_STREAM_ID: return "NIR_INTRINSIC_STREAM_ID";
102 102 case NIR_INTRINSIC_IDX_UCP_ID: return "NIR_INTRINSIC_UCP_ID"; case NIR_INTRINSIC_IDX_UCP_ID: return "NIR_INTRINSIC_UCP_ID";
103 103 case NIR_INTRINSIC_IDX_RANGE: return "NIR_INTRINSIC_RANGE"; case NIR_INTRINSIC_IDX_RANGE: return "NIR_INTRINSIC_RANGE";
104 case NIR_INTRINSIC_IDX_RANGE_BASE: return "NIR_INTRINSIC_RANGE_BASE";
104 105 case NIR_INTRINSIC_IDX_DESC_SET: return "NIR_INTRINSIC_DESC_SET"; case NIR_INTRINSIC_IDX_DESC_SET: return "NIR_INTRINSIC_DESC_SET";
105 106 case NIR_INTRINSIC_IDX_BINDING: return "NIR_INTRINSIC_BINDING"; case NIR_INTRINSIC_IDX_BINDING: return "NIR_INTRINSIC_BINDING";
106 107 case NIR_INTRINSIC_IDX_COMPONENT: return "NIR_INTRINSIC_COMPONENT"; case NIR_INTRINSIC_IDX_COMPONENT: return "NIR_INTRINSIC_COMPONENT";
File builders/mesa-vulkan-0/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index 06e23b6..1f8f192)
... ... fi
147 147 # enable gcc attribute for atomic in src/util.c and thread emulation # enable gcc attribute for atomic in src/util.c and thread emulation
148 148 # HAVE_ENDIAN_H=1: # HAVE_ENDIAN_H=1:
149 149 # autoconf macro for the endian.h header used in src/util/u_endian.h # autoconf macro for the endian.h header used in src/util/u_endian.h
150 # HAVE_FLOCK=1:
151 # autoconf macro for src/util/disk_cache_os.c
150 152 # VK_USE_PLATFORM_XCB_KHR: # VK_USE_PLATFORM_XCB_KHR:
151 153 # vulkan macro enabling x11/xcb platform support, linked to # vulkan macro enabling x11/xcb platform support, linked to
152 154 # VK_USE_PLATFORM_XLIB_KHR in the code # VK_USE_PLATFORM_XLIB_KHR in the code
 
... ... linux_glibc_cppflags="\
237 239 -DHAVE_ENDIAN_H=1 \ -DHAVE_ENDIAN_H=1 \
238 240 -DHAVE_PROGRAM_INVOCATION_NAME=1 \ -DHAVE_PROGRAM_INVOCATION_NAME=1 \
239 241 -DHAVE_DLADDR=1 \ -DHAVE_DLADDR=1 \
242 -DHAVE_FLOCK=1 \
240 243 " "
241 244 mesa_cppflags="\ mesa_cppflags="\
242 245 -DNDEBUG \ -DNDEBUG \
 
... ... $ar $build_dir/libvulkan_wsi.a \
715 718 #------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
716 719 $python3 $src_dir/src/amd/common/sid_tables.py \ $python3 $src_dir/src/amd/common/sid_tables.py \
717 720 $src_dir/src/amd/common/sid.h \ $src_dir/src/amd/common/sid.h \
718 $src_dir/src/amd/registers/amdgfxregs.json \
719 $src_dir/src/amd/registers/pkt3.json \
721 $src_dir/src/amd/registers/gfx6.json \
722 $src_dir/src/amd/registers/gfx7.json \
723 $src_dir/src/amd/registers/gfx8.json \
724 $src_dir/src/amd/registers/gfx81.json \
725 $src_dir/src/amd/registers/gfx9.json \
720 726 $src_dir/src/amd/registers/gfx10.json \ $src_dir/src/amd/registers/gfx10.json \
721 727 $src_dir/src/amd/registers/gfx10-rsrc.json \ $src_dir/src/amd/registers/gfx10-rsrc.json \
728 $src_dir/src/amd/registers/gfx103.json \
729 $src_dir/src/amd/registers/pkt3.json \
730 $src_dir/src/amd/registers/registers-manually-defined.json \
722 731 >$build_dir/sid_tables.h & >$build_dir/sid_tables.h &
723 732
724 733 $python3 $src_dir/src/amd/registers/makeregheader.py \ $python3 $src_dir/src/amd/registers/makeregheader.py \
725 $src_dir/src/amd/registers/amdgfxregs.json \
726 $src_dir/src/amd/registers/pkt3.json \
734 $src_dir/src/amd/registers/gfx6.json \
735 $src_dir/src/amd/registers/gfx7.json \
736 $src_dir/src/amd/registers/gfx8.json \
737 $src_dir/src/amd/registers/gfx81.json \
738 $src_dir/src/amd/registers/gfx9.json \
727 739 $src_dir/src/amd/registers/gfx10.json \ $src_dir/src/amd/registers/gfx10.json \
728 740 $src_dir/src/amd/registers/gfx10-rsrc.json \ $src_dir/src/amd/registers/gfx10-rsrc.json \
741 $src_dir/src/amd/registers/gfx103.json \
742 $src_dir/src/amd/registers/pkt3.json \
743 $src_dir/src/amd/registers/registers-manually-defined.json \
729 744 --sort address \ --sort address \
730 745 --guard AMDGFXREGS_H \ --guard AMDGFXREGS_H \
731 746 >$build_dir/amdgfxregs.h & >$build_dir/amdgfxregs.h &
 
... ... libaco_files="\
1227 1242 $src_dir/src/amd/compiler/aco_dead_code_analysis.cpp \ $src_dir/src/amd/compiler/aco_dead_code_analysis.cpp \
1228 1243 $src_dir/src/amd/compiler/aco_dominance.cpp \ $src_dir/src/amd/compiler/aco_dominance.cpp \
1229 1244 $src_dir/src/amd/compiler/aco_instruction_selection.cpp \ $src_dir/src/amd/compiler/aco_instruction_selection.cpp \
1245 $src_dir/src/amd/compiler/aco_instruction_selection_setup.cpp \
1230 1246 $src_dir/src/amd/compiler/aco_interface.cpp \ $src_dir/src/amd/compiler/aco_interface.cpp \
1231 1247 $src_dir/src/amd/compiler/aco_assembler.cpp \ $src_dir/src/amd/compiler/aco_assembler.cpp \
1232 1248 $src_dir/src/amd/compiler/aco_insert_exec_mask.cpp \ $src_dir/src/amd/compiler/aco_insert_exec_mask.cpp \
 
... ... $src_dir/src/util/crc32.c \
1317 1333 $src_dir/src/util/dag.c \ $src_dir/src/util/dag.c \
1318 1334 $src_dir/src/util/debug.c \ $src_dir/src/util/debug.c \
1319 1335 $src_dir/src/util/disk_cache.c \ $src_dir/src/util/disk_cache.c \
1336 $src_dir/src/util/disk_cache_os.c \
1320 1337 $src_dir/src/util/double.c \ $src_dir/src/util/double.c \
1321 1338 $src_dir/src/util/fast_idiv_by_const.c \ $src_dir/src/util/fast_idiv_by_const.c \
1322 1339 $src_dir/src/util/half_float.c \ $src_dir/src/util/half_float.c \
 
... ... $src_dir/src/util/format/u_format_s3tc.c \
1354 1371 $src_dir/src/util/format/u_format_tests.c \ $src_dir/src/util/format/u_format_tests.c \
1355 1372 $src_dir/src/util/format/u_format_yuv.c \ $src_dir/src/util/format/u_format_yuv.c \
1356 1373 $src_dir/src/util/format/u_format_zs.c \ $src_dir/src/util/format/u_format_zs.c \
1374 $src_dir/src/util/u_idalloc.c \
1357 1375 $src_dir/src/util/u_math.c \ $src_dir/src/util/u_math.c \
1358 1376 $src_dir/src/util/u_mm.c \ $src_dir/src/util/u_mm.c \
1359 1377 $src_dir/src/util/u_process.c \ $src_dir/src/util/u_process.c \
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/intel/intel.c added (mode: 100644) (index 0000000..799d8a4)
1 /* Load a relocatable 32-bit value */
2 static struct nir_intrinsic nir_load_reloc_const_intel = {
3 .name = "load_reloc_const_intel",
4 .has_dest = true,
5 .dest_components_n = 1,
6 .bit_szs = 0x20,
7 .idxs_n = 1,
8 .idxs_map = {
9 [NIR_INTRINSIC_IDX_PARAM_IDX] = 1
10 },
11 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
12 };
File builders/mesa-vulkan/builder.sh changed (mode: 100644) (index 0d1c420..571337e)
... ... cp -r $src_dir $pkg_dir
9 9
10 10 cd $pkg_dir cd $pkg_dir
11 11
12 git checkout --force $git_commit
13 git reset --hard
12 if test "x$git_commit" != "x"; then
13 git checkout --force $git_commit
14 git reset --hard
15 fi
14 16
15 17 # install our canonical build system from the contrib dir # install our canonical build system from the contrib dir
16 18 cp -rf $nyan_root/builders/mesa-vulkan-$slot/contrib $pkg_dir cp -rf $nyan_root/builders/mesa-vulkan-$slot/contrib $pkg_dir
File builders/nyanmp-0/builder.sh changed (mode: 100644) (index baaea67..64301b0)
1 1 src_name=nyanmp src_name=nyanmp
2 git_commit=8c64f703eca6b8c54b4cb5c95231dd02aa394135
2 git_commit=b319e79f4f1b79670f6eef754142cc65c891ad4b
3 3 git_url0=git://repo.or.cz/$src_name git_url0=git://repo.or.cz/$src_name
4 4
5 5 slot=0 slot=0
File builders/xserver-1/builder.sh changed (mode: 100644) (index bd077ee..fe67766)
1 git_commit=2902b78535ecc6821cc027351818b28a5c7fdbdc
1 git_commit=97f858d336a85cb49de6275918793c773d5d9db1
2 2 slot=1 slot=1
3 3 . $nyan_root/builders/xserver/builder.sh . $nyan_root/builders/xserver/builder.sh
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/nyanlinux

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/nyanlinux

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main