sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
towards basic GPU programming 01acf921a2efddf521967487865a49347f3f4045 Sylvain BERTRAND 2012-08-16 00:28:19
triangle pattern plumbering 853a73e0052f48b9183f16d02ea9398a2556d040 Sylvain BERTRAND 2012-08-13 15:26:43
pattern ioctl, framebuffer fill pattern 9c59bb9b9c16bbb822587b2a44ab38f38a4371ac Sylvain BERTRAND 2012-08-12 10:51:09
context clear of command processors 9e02a78b903706e3df0af0abc24322c62317c13e Sylvain BERTRAND 2012-08-09 23:09:38
register love de4d6c0aa40f2ca9f2d69190d14bc651f7612b06 Sylvain BERTRAND 2012-08-09 22:55:11
mainly cosmetics 11a2377b2c41cc118078170e6e6fb589fc5937a0 Sylvain BERTRAND 2012-08-09 08:04:21
try to improve stability 25211097e7ecfd370feed5c5d682d26d80c96ae2 Sylvain BERTRAND 2012-08-05 18:40:17
wrong micro engine magic init magic numbers 0d2d45c69b909788418b0d87b7c6727292d2ef70 Sylvain BERTRAND 2012-08-05 16:57:34
relocate set pci master b62baf5e967e3ad6b4f4c5319beec6f7a5225de0 Sylvain BERTRAND 2012-08-04 21:10:37
don't be too hasty at dp hotplug connexion 17a2687ef35639fe70d860b46e45ed061b04999f Sylvain BERTRAND 2012-08-04 20:24:12
near-stateless drive code update finish aecf726cba83d6df6e1f49c88d69d2c9ccdda2a8 Sylvain BERTRAND 2012-08-04 14:51:30
PCI ids and ih start update and check 1508d1084e1878b57091a81177667709408d6c0d Sylvain BERTRAND 2012-08-02 12:34:20
IH init update efc2171f320006d9adfe3f06cc545b23ee180152 Sylvain BERTRAND 2012-08-02 10:24:11
RLC update b55639d2d423e6c90110470df9e05ffe3132fbaf Sylvain BERTRAND 2012-08-02 09:58:35
probe not freezing anymore 696553860664b34295d5628dc5afc89168483cac Sylvain BERTRAND 2012-08-01 18:49:14
DCE needs running MC 6afead30e8403aa0eab6c8a0db940a75fced6362 Sylvain BERTRAND 2012-08-01 18:32:17
dce6 online 9d9f1eaef5e5de789e992dc577c1d4f454da47f3 Sylvain BERTRAND 2012-07-31 22:59:41
update atombios set pixel mode 8b22745c66edd8ba7187bef3a96d7b2537b5b003 Sylvain BERTRAND 2012-07-29 22:40:06
si lut code 973e26e467bbe81e2e113aefa9fe35fd8dad18e2 Sylvain BERTRAND 2012-07-29 14:20:21
driver upgrade continued aade78ad4ccb4c1d59a59b6b9b265a58890fe733 Sylvain BERTRAND 2012-07-26 12:52:49
Commit 01acf921a2efddf521967487865a49347f3f4045 - towards basic GPU programming
Author: Sylvain BERTRAND
Author date (UTC): 2012-08-16 00:28
Committer name: Sylvain BERTRAND
Committer date (UTC): 2012-08-16 00:28
Parent(s): 853a73e0052f48b9183f16d02ea9398a2556d040
Signer:
Signing key:
Signing status: N
Tree: 5777c0d505e6826813a5ad976adce4832ae09ce2
File Lines added Lines deleted
drivers/gpu/alga/amd/ABBREVIATIONS 8 2
drivers/gpu/alga/amd/si/gpu/cps.c 62 51
drivers/gpu/alga/amd/si/gpu/cps.h 33 6
drivers/gpu/alga/amd/si/gpu/regs_ctx.h 402 1103
drivers/gpu/alga/amd/si/patterns/tri.c 448 0
drivers/gpu/alga/amd/si/silicium_blks/3d_basic_pipeline_programming 32 0
drivers/gpu/alga/amd/si/silicium_blks/README 2 1
drivers/gpu/alga/amd/si/silicium_blks/cb 98 0
drivers/gpu/alga/amd/si/silicium_blks/db 6 0
drivers/gpu/alga/amd/si/silicium_blks/gpu 56 0
drivers/gpu/alga/amd/si/silicium_blks/hdp 4 5
drivers/gpu/alga/amd/si/silicium_blks/mc 5 8
drivers/gpu/alga/amd/si/silicium_blks/others 4 76
drivers/gpu/alga/amd/si/silicium_blks/spi 8 0
drivers/gpu/alga/amd/si/silicium_blks/xrbm 1 1
File drivers/gpu/alga/amd/ABBREVIATIONS changed (mode: 100644) (index 8c22f31..415a3b3)
... ... cond condition
40 40 (sub)conn (sub)connector (sub)conn (sub)connector
41 41 cp Command Processor cp Command Processor
42 42 cp Clipper Plane cp Clipper Plane
43 cl CLipper (silicium block)
43 cl CLipper (in pa context)
44 44 cr clock recovery cr clock recovery
45 45 crtc Cathode Ray Tube Controller crtc Cathode Ray Tube Controller
46 46 cs Compute Shader cs Compute Shader
 
... ... obj(s) object(s)
157 157 obs obsolete obs obsolete
158 158 oem Original Equipment Manufacturer oem Original Equipment Manufacturer
159 159 of offset of offset
160 ovrd override
160 161 p path p path
161 162 pa Primitive Assembler (silicium block) pa Primitive Assembler (silicium block)
162 163 pa Physical Address (gpu address) pa Physical Address (gpu address)
 
... ... pkt packet
171 172 pll Phase Locked Loop pll Phase Locked Loop
172 173 pgm program (as shaders) pgm program (as shaders)
173 174 prim primitive prim primitive
175 poly polygon
174 176 pos position pos position
175 177 post Power-On Self Test post Power-On Self Test
176 178 pplib PowerPlay Library pplib PowerPlay Library
 
... ... simd Single instruction Multiple Data
220 222 smx Shader Memory eXchange smx Shader Memory eXchange
221 223 sN N is a the scratch pad register number sN N is a the scratch pad register number
222 224 (off)scr (off)screen (off)scr (off)screen
225 so stream out
223 226 sp Shader Pipe sp Shader Pipe
224 227 spi Shader Processor Interpolator (silicium context) spi Shader Processor Interpolator (silicium context)
225 228 srbm System Register Backbone Manager srbm System Register Backbone Manager
 
... ... sdvo Serial Digital Video Output
229 232 spd Serial Presence Detect (memory context) spd Serial Presence Detect (memory context)
230 233 str string str string
231 234 struct structure struct structure
232 su Setup Unit
235 su Setup Unit (in pa context)
233 236 surface(s) surf(s) surface(s) surf(s)
234 237 sw software sw software
235 238 sync synchronization sync synchronization
 
... ... tbl(s) table(s)
243 246 tc Texture Cache (silicium block) tc Texture Cache (silicium block)
244 247 tc Test Controller tc Test Controller
245 248 tdp Thermal Design Power tdp Thermal Design Power
249 te Transform Engine
246 250 tex texture tex texture
247 251 tgt target tgt target
248 252 thd(s) thread(s) thd(s) thread(s)
 
... ... vesa Video Electronics Standards Association
270 274 vga Video Graphic Array vga Video Graphic Array
271 275 vgt Vertex Grouper and Tessellator (silicium block) vgt Vertex Grouper and Tessellator (silicium block)
272 276 vgt Vertex Geometry Translator vgt Vertex Geometry Translator
277 vport viewport
273 278 vpost video post vpost video post
274 279 vram video ram vram video ram
275 280 vs voltage swing vs voltage swing
281 vte Viewport Transform Engine
276 282 vtx vertex vtx vertex
277 283 w width w width
278 284 wd(s) word(s) wd(s) word(s)
File drivers/gpu/alga/amd/si/gpu/cps.c changed (mode: 100644) (index 1387210..98d2683)
... ... static u32 ctx_clr_state[] = {
115 115 0xffffff36, 0xffffff36,
116 116 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
117 117 PKT3(PKT3_SET_CTX_REG, 35), PKT3(PKT3_SET_CTX_REG, 35),
118 CTX_REG_IDX(PA_SC_VPORT_SCISSOR_0_TL),
119 /* PA_SC_VPORT_SCISSOR_0_TL */
118 CTX_REG_IDX(PA_SC_VPORT_0_SCISSOR_TL),
119 /* PA_SC_VPORT_0_SCISSOR_TL */
120 120 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
121 /* PA_SC_VPORT_SCISSOR_0_BR */
121 /* PA_SC_VPORT_0_SCISSOR_BR */
122 122 0xffffff40, 0xffffff40,
123 /* PA_SC_VPORT_SCISSOR_1_TL */
123 /* PA_SC_VPORT_1_SCISSOR_TL */
124 124 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
125 /* PA_SC_VPORT_SCISSOR_1_BR */
125 /* PA_SC_VPORT_1_SCISSOR_BR */
126 126 0xffffff42, 0xffffff42,
127 /* PA_SC_VPORT_SCISSOR_2_TL */
127 /* PA_SC_VPORT_2_SCISSOR_TL */
128 128 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
129 /* PA_SC_VPORT_SCISSOR_2_BR */
129 /* PA_SC_VPORT_2_SCISSOR_BR */
130 130 0xffffff44, 0xffffff44,
131 /* PA_SC_VPORT_SCISSOR_3_TL */
131 /* PA_SC_VPORT_3_SCISSOR_TL */
132 132 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
133 /* PA_SC_VPORT_SCISSOR_3_BR */
133 /* PA_SC_VPORT_3_SCISSOR_BR */
134 134 0xffffff46, 0xffffff46,
135 /* PA_SC_VPORT_SCISSOR_4_TL */
135 /* PA_SC_VPORT_4_SCISSOR_TL */
136 136 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
137 /* PA_SC_VPORT_SCISSOR_4_BR */
137 /* PA_SC_VPORT_4_SCISSOR_BR */
138 138 0xffffff48, 0xffffff48,
139 /* PA_SC_VPORT_SCISSOR_5_TL */
139 /* PA_SC_VPORT_5_SCISSOR_TL */
140 140 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
141 /* PA_SC_VPORT_SCISSOR_5_BR */
141 /* PA_SC_VPORT_5_SCISSOR_BR */
142 142 0xffffff50, 0xffffff50,
143 /* PA_SC_VPORT_SCISSOR_6_TL */
143 /* PA_SC_VPORT_6_SCISSOR_TL */
144 144 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
145 /* PA_SC_VPORT_SCISSOR_6_BR */
145 /* PA_SC_VPORT_6_SCISSOR_BR */
146 146 0xffffff52, 0xffffff52,
147 /* PA_SC_VPORT_SCISSOR_7_TL */
147 /* PA_SC_VPORT_7_SCISSOR_TL */
148 148 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
149 /* PA_SC_VPORT_SCISSOR_7_BR */
149 /* PA_SC_VPORT_7_SCISSOR_BR */
150 150 0xffffff54, 0xffffff54,
151 /* PA_SC_VPORT_SCISSOR_8_TL */
151 /* PA_SC_VPORT_8_SCISSOR_TL */
152 152 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
153 /* PA_SC_VPORT_SCISSOR_8_BR */
153 /* PA_SC_VPORT_8_SCISSOR_BR */
154 154 0xffffff56, 0xffffff56,
155 /* PA_SC_VPORT_SCISSOR_9_TL */
155 /* PA_SC_VPORT_9_SCISSOR_TL */
156 156 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
157 /* PA_SC_VPORT_SCISSOR_9_BR */
157 /* PA_SC_VPORT_9_SCISSOR_BR */
158 158 0xffffff58, 0xffffff58,
159 /* PA_SC_VPORT_SCISSOR_A_TL */
159 /* PA_SC_VPORT_A_SCISSOR_TL */
160 160 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
161 /* PA_SC_VPORT_SCISSOR_A_BR */
161 /* PA_SC_VPORT_A_SCISSOR_BR */
162 162 0xffffff60, 0xffffff60,
163 /* PA_SC_VPORT_SCISSOR_B_TL */
163 /* PA_SC_VPORT_B_SCISSOR_TL */
164 164 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
165 /* PA_SC_VPORT_SCISSOR_B_BR */
165 /* PA_SC_VPORT_B_SCISSOR_BR */
166 166 0xffffff62, 0xffffff62,
167 /* PA_SC_VPORT_SCISSOR_C_TL */
167 /* PA_SC_VPORT_C_SCISSOR_TL */
168 168 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
169 /* PA_SC_VPORT_SCISSOR_C_BR */
169 /* PA_SC_VPORT_C_SCISSOR_BR */
170 170 0xffffff64, 0xffffff64,
171 /* PA_SC_VPORT_SCISSOR_D_TL */
171 /* PA_SC_VPORT_D_SCISSOR_TL */
172 172 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
173 /* PA_SC_VPORT_SCISSOR_D_BR */
173 /* PA_SC_VPORT_D_SCISSOR_BR */
174 174 0xffffff66, 0xffffff66,
175 /* PA_SC_VPORT_SCISSOR_E_TL */
175 /* PA_SC_VPORT_E_SCISSOR_TL */
176 176 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
177 /* PA_SC_VPORT_SCISSOR_E_BR */
177 /* PA_SC_VPORT_E_SCISSOR_BR */
178 178 0xffffff68, 0xffffff68,
179 /* PA_SC_VPORT_SCISSOR_F_TL */
179 /* PA_SC_VPORT_F_SCISSOR_TL */
180 180 PSVST_WND_OF_DIS, PSVST_WND_OF_DIS,
181 /* PA_SC_VPORT_SCISSOR_F_BR */
181 /* PA_SC_VPORT_F_SCISSOR_BR */
182 182 0xffffff70, 0xffffff70,
183 /* PA_SC_VPORT_ZMIN_0 */
183 /* PA_SC_VPORT_0_TE_ZMIN */
184 184 0x00000000, 0x00000000,
185 /* PA_SC_VPORT_ZMAX_0 */
186 0x3f800000,
185 /* PA_SC_VPORT_0_TE_ZMAX */
186 0xffffff72,
187 187 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
188 188 PKT3(PKT3_SET_CTX_REG, 3), PKT3(PKT3_SET_CTX_REG, 3),
189 189 CTX_REG_IDX(CP_RING_ID), CTX_REG_IDX(CP_RING_ID),
 
... ... static u32 ctx_clr_state[] = {
215 215 0x00000000, 0x00000000,
216 216 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
217 217 PKT3(PKT3_SET_CTX_REG, 2), PKT3(PKT3_SET_CTX_REG, 2),
218 CTX_REG_IDX(CB_BLEND_0_CTL),
219 /* CB_BLEND_0_CTL */
218 CTX_REG_IDX(CB_0_BLEND_CTL),
219 /* CB_0_BLEND_CTL: disable blending for CB 0 */
220 220 0x00000000, 0x00000000,
221 221 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
222 222 PKT3(PKT3_SET_CTX_REG, 15), PKT3(PKT3_SET_CTX_REG, 15),
 
... ... static u32 ctx_clr_state[] = {
233 233 PCCC_CLIP_DIS, PCCC_CLIP_DIS,
234 234 /* PA_SU_SC_MODE_CTL */ /* PA_SU_SC_MODE_CTL */
235 235 PSSMC_FACE, PSSMC_FACE,
236 /* PA_CL_VTE_CTL */
237 PCVC_VTX_XY_FMT,
236 /* PA_SC_VPORT_TE_CTL */
237 PSVTC_VTX_XY_FMT,
238 238 /* PA_CL_VS_OUT_CTL */ /* PA_CL_VS_OUT_CTL */
239 239 0x00000000, 0x00000000,
240 240 /* PA_CL_NANINF_CTL */ /* PA_CL_NANINF_CTL */
 
... ... static u32 ctx_clr_state[] = {
363 363 /* PA_SU_VTX_CTL */ /* PA_SU_VTX_CTL */
364 364 0xfffff169, 0xfffff169,
365 365 /* PA_CL_GB_VERT_CLIP_ADJ */ /* PA_CL_GB_VERT_CLIP_ADJ */
366 0x3f800000,
366 0xfffff170,
367 367 /* PA_CL_GB_VERT_DISC_ADJ */ /* PA_CL_GB_VERT_DISC_ADJ */
368 0x3f800000,
368 0xfffff171,
369 369 /* PA_CL_GB_HORZ_CLIP_ADJ */ /* PA_CL_GB_HORZ_CLIP_ADJ */
370 0x3f800000,
370 0xfffff172,
371 371 /* PA_CL_GB_HORZ_DISC_ADJ */ /* PA_CL_GB_HORZ_DISC_ADJ */
372 0x3f800000,
372 0xfffff173,
373 373 /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
374 374 0x00000000, 0x00000000,
375 375 /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 */ /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 */
 
... ... static void ctx_clr_state_init(void)
430 430 | set(PSE_ER_RECT, 0xa) | set(PSE_ER_LINE_LR, 0x2a) | set(PSE_ER_RECT, 0xa) | set(PSE_ER_LINE_LR, 0x2a)
431 431 | set(PSE_ER_LINE_RL, 0xa2) | set(PSE_ER_LINE_TB, 0xa) | set(PSE_ER_LINE_RL, 0xa2) | set(PSE_ER_LINE_TB, 0xa)
432 432 | set(PSE_ER_LINE_BT, 0xa); | set(PSE_ER_LINE_BT, 0xa);
433 /* CB_TGT_MASK: CB 0 will output all 4 color components to target */
433 434 ctx_clr_state[35] = set(CTM_TGT_0_ENA, 0xf); ctx_clr_state[35] = set(CTM_TGT_0_ENA, 0xf);
435 /*
436 * CB_SHADER_MASK: CB 0 will use the 4 color components from
437 * the pixel/fragment shader
438 */
434 439 ctx_clr_state[36] = set(CSM_OUTPUT_0_ENA, 0xf); ctx_clr_state[36] = set(CSM_OUTPUT_0_ENA, 0xf);
435 440 /* XXX: should probably be 16384 on SI */ /* XXX: should probably be 16384 on SI */
436 441 ctx_clr_state[40] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192); ctx_clr_state[40] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192);
 
... ... static void ctx_clr_state_init(void)
449 454 ctx_clr_state[66] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192); ctx_clr_state[66] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192);
450 455 ctx_clr_state[68] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192); ctx_clr_state[68] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192);
451 456 ctx_clr_state[70] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192); ctx_clr_state[70] = set(PSVSB_X, 8192) | set(PSVSB_Y, 8192);
452 ctx_clr_state[96] = set(CCC_MODE, 1)| set(CCC_ROP3, CCC_0XCC);
457 ctx_clr_state[72] = f2u(1.0f);
458 ctx_clr_state[96] = set(CCC_MODE, CCC_CB_NORMAL) | set(CCC_ROP3, CCC_0XCC);
453 459 ctx_clr_state[97] = set(DSC_Z_ORDER, DSC_EARLY_Z_THEN_LATE_Z) ctx_clr_state[97] = set(DSC_Z_ORDER, DSC_EARLY_Z_THEN_LATE_Z)
454 460 | DSC_EXEC_ON_HIER_FAIL; | DSC_EXEC_ON_HIER_FAIL;
455 461 ctx_clr_state[112] = set(PSLC_W, 8); ctx_clr_state[112] = set(PSLC_W, 8);
 
... ... static void ctx_clr_state_init(void)
467 473 | set(PSCP_DISTANCE_E, 0xe) | set(PSCP_DISTANCE_F, 0xf); | set(PSCP_DISTANCE_E, 0xe) | set(PSCP_DISTANCE_F, 0xf);
468 474 ctx_clr_state[169] = PSVC_PIX_CENTER ctx_clr_state[169] = PSVC_PIX_CENTER
469 475 | set(PSVC_ROUND_MODE, PSVC_ROUND_TO_EVEN); | set(PSVC_ROUND_MODE, PSVC_ROUND_TO_EVEN);
476 /* PA_CL_GB_...: disable GB (Guard Band) = setting 1.0f value */
477 ctx_clr_state[170] = f2u(1.0f);
478 ctx_clr_state[171] = f2u(1.0f);
479 ctx_clr_state[172] = f2u(1.0f);
480 ctx_clr_state[173] = f2u(1.0f);
470 481 ctx_clr_state[190] = set(PSAMXX_AA_MASK_X0Y0, 0xffff) ctx_clr_state[190] = set(PSAMXX_AA_MASK_X0Y0, 0xffff)
471 482 | set(PSAMXX_AA_MASK_X1Y0, 0xffff); | set(PSAMXX_AA_MASK_X1Y0, 0xffff);
472 483 ctx_clr_state[191] = set(PSAMXX_AA_MASK_X0Y1, 0xffff) ctx_clr_state[191] = set(PSAMXX_AA_MASK_X0Y1, 0xffff)
 
... ... void cps_init(struct pci_dev *dev)
797 808 cp2_init(dev); cp2_init(dev);
798 809 } }
799 810
800 inline void cp0_wr(struct pci_dev *dev, u32 v)
811 void cp0_wr(struct pci_dev *dev, u32 v)
801 812 { {
802 813 struct dev_drv_data *dd; struct dev_drv_data *dd;
803 814 u32 *r; u32 *r;
 
... ... inline void cp0_wr(struct pci_dev *dev, u32 v)
809 820 dd->cp0.wptr &= CP_RING_DW_MASK; dd->cp0.wptr &= CP_RING_DW_MASK;
810 821 } }
811 822
812 inline void cp0_commit(struct pci_dev *dev)
823 void cp0_commit(struct pci_dev *dev)
813 824 { {
814 825 struct dev_drv_data *dd; struct dev_drv_data *dd;
815 826 u32 *r; u32 *r;
 
... ... inline void cp0_commit(struct pci_dev *dev)
828 839 rr32(dev, CP_RB_0_WPTR); rr32(dev, CP_RB_0_WPTR);
829 840 } }
830 841
831 inline void cp1_wr(struct pci_dev *dev, u32 v)
842 void cp1_wr(struct pci_dev *dev, u32 v)
832 843 { {
833 844 struct dev_drv_data *dd; struct dev_drv_data *dd;
834 845 u32 *r; u32 *r;
 
... ... inline void cp1_wr(struct pci_dev *dev, u32 v)
840 851 dd->cp1.wptr &= CP_RING_DW_MASK; dd->cp1.wptr &= CP_RING_DW_MASK;
841 852 } }
842 853
843 inline void cp1_commit(struct pci_dev *dev)
854 void cp1_commit(struct pci_dev *dev)
844 855 { {
845 856 struct dev_drv_data *dd; struct dev_drv_data *dd;
846 857 u32 *r; u32 *r;
 
... ... inline void cp1_commit(struct pci_dev *dev)
859 870 rr32(dev, CP_RB_1_WPTR); rr32(dev, CP_RB_1_WPTR);
860 871 } }
861 872
862 inline void cp2_wr(struct pci_dev *dev, u32 v)
873 void cp2_wr(struct pci_dev *dev, u32 v)
863 874 { {
864 875 struct dev_drv_data *dd; struct dev_drv_data *dd;
865 876 u32 *r; u32 *r;
 
... ... inline void cp2_wr(struct pci_dev *dev, u32 v)
871 882 dd->cp2.wptr &= CP_RING_DW_MASK; dd->cp2.wptr &= CP_RING_DW_MASK;
872 883 } }
873 884
874 inline void cp2_commit(struct pci_dev *dev)
885 void cp2_commit(struct pci_dev *dev)
875 886 { {
876 887 struct dev_drv_data *dd; struct dev_drv_data *dd;
877 888 u32 *r; u32 *r;
File drivers/gpu/alga/amd/si/gpu/cps.h changed (mode: 100644) (index 8596054..0926737)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8
9 /* do get raw u32 value from a 32 bits float */
10 union f2u {
11 float f;
12 u32 u;
13 };
14 static inline u32 f2u(float f)
15 {
16 union f2u tmp;
17
18 tmp.f = f;
19 return tmp.u;
20 }
21
8 22 #define CP_RING_LOG2_QWS 17 #define CP_RING_LOG2_QWS 17
9 23 #define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1) #define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1)
10 24
 
26 40 #define PKT3_CE_PARTITION_BASE 3 #define PKT3_CE_PARTITION_BASE 3
27 41 #define PKT3_CLR_STATE 0x12 #define PKT3_CLR_STATE 0x12
28 42 #define PKT3_MODE_CTL 0x18 #define PKT3_MODE_CTL 0x18
43 #define PKT3_SET_PREDICATION 0x20
44 #define PRED_DRAW 0x00000100
45 #define PRED_DRAW_NOT_VISIBLE 0
46 #define PRED_DRAW_VISIBLE 1
47 #define PRED_HINT 0x00001000
48 #define PRED_HINT_WAIT 0
49 #define NOWAIT_DRAW 1
50 #define PRED_OP 0xffff0000
51 #define PRED_OP_CLR 0
52 #define PRED_OP_ZPASS 1
53 #define PRED_OP_PRIM_CNT 2
54 #define PRED_CONTINUE BIT(31)
29 55 #define PKT3_CTX_CTL 0x28 #define PKT3_CTX_CTL 0x28
30 56 #define PKT3_IB 0x32 #define PKT3_IB 0x32
31 57 #define PKT3_SURF_SYNC 0x43 #define PKT3_SURF_SYNC 0x43
 
63 89 #define PKT3_SET_CFG_REG 0x68 #define PKT3_SET_CFG_REG 0x68
64 90 #define PKT3_SET_CFG_REG_START 0x00008000 #define PKT3_SET_CFG_REG_START 0x00008000
65 91 #define PKT3_SET_CFG_REG_END 0x0000b000 #define PKT3_SET_CFG_REG_END 0x0000b000
92 #define CFG_REG_IDX(x) ((x - PKT3_SET_CFG_REG_START) >> 2)
66 93 #define PKT3_SET_CTX_REG 0x69 #define PKT3_SET_CTX_REG 0x69
67 94 #define PKT3_SET_CTX_REG_START 0x00028000 #define PKT3_SET_CTX_REG_START 0x00028000
68 95 #define PKT3_SET_CTX_REG_END 0x00029000 #define PKT3_SET_CTX_REG_END 0x00029000
 
... ... void cps_init(struct pci_dev *dev);
85 112 void cps_me_init(struct pci_dev *dev); void cps_me_init(struct pci_dev *dev);
86 113 void cps_enable(struct pci_dev *dev); void cps_enable(struct pci_dev *dev);
87 114 void cps_ctx_clr(struct pci_dev *dev); void cps_ctx_clr(struct pci_dev *dev);
88 inline void cp0_wr(struct pci_dev *dev, u32 v);
89 inline void cp0_commit(struct pci_dev *dev);
90 inline void cp1_wr(struct pci_dev *dev, u32 v);
91 inline void cp1_commit(struct pci_dev *dev);
92 inline void cp2_wr(struct pci_dev *dev, u32 v);
93 inline void cp2_commit(struct pci_dev *dev);
115 void cp0_wr(struct pci_dev *dev, u32 v);
116 void cp0_commit(struct pci_dev *dev);
117 void cp1_wr(struct pci_dev *dev, u32 v);
118 void cp1_commit(struct pci_dev *dev);
119 void cp2_wr(struct pci_dev *dev, u32 v);
120 void cp2_commit(struct pci_dev *dev);
94 121 #endif #endif
File drivers/gpu/alga/amd/si/gpu/regs_ctx.h changed (mode: 100644) (index e0ea754..8244fa7)
86 86 #define DSC_CLR 0x000000ff #define DSC_CLR 0x000000ff
87 87 #define DB_DEPTH_CLR 0x2802c #define DB_DEPTH_CLR 0x2802c
88 88
89 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
90 #define PSSST_X 0x00007fff
91 #define PSSST_Y 0x7fff0000
92 #define PA_SC_SCREEN_SCISSOR_BR 0x28034
93 #define PSSSB_X 0x00007fff
94 #define PSSSB_Y 0x7fff0000
95
89 96 #define DB_DEPTH_INFO 0x2803c #define DB_DEPTH_INFO 0x2803c
90 97 #define DDI_ADDR5_SWIZZLE_MASK 0x0000000f #define DDI_ADDR5_SWIZZLE_MASK 0x0000000f
91 98 #define DB_Z_INFO 0x28040 #define DB_Z_INFO 0x28040
 
110 117 #define PA_SC_WND_OF 0x28200 #define PA_SC_WND_OF 0x28200
111 118 #define PSWO_WND_X_OF 0x0000ffff #define PSWO_WND_X_OF 0x0000ffff
112 119 #define PSWO_WND_Y_OF 0xffff0000 #define PSWO_WND_Y_OF 0xffff0000
120 #define PA_SC_WND_SCISSOR_TL 0x28204
121 #define PSWST_X 0x00007fff
122 #define PSWST_Y 0x7fff0000
123 #define PSWST_WND_OF_DIS BIT(31)
124 #define PA_SC_WND_SCISSOR_BR 0x28208
125 #define PSWSB_X 0x00007fff
126 #define PSWSB_Y 0x7fff0000
127 #define PSWSB_WND_OF_DIS BIT(31)
113 128
114 129 #define PA_SC_CLIPRECT_RULE 0x2820c #define PA_SC_CLIPRECT_RULE 0x2820c
115 130 #define PSCR_CLIP_RULE 0x0000ffff #define PSCR_CLIP_RULE 0x0000ffff
 
120 135 #define PSCB_X 0x00007fff #define PSCB_X 0x00007fff
121 136 #define PSCB_Y 0x7fff0000 #define PSCB_Y 0x7fff0000
122 137 #define PA_SC_CLIPRECT_1_TL 0x28218 #define PA_SC_CLIPRECT_1_TL 0x28218
123 #define PSCT_X 0x00007fff
124 #define PSCT_Y 0x7fff0000
125 138 #define PA_SC_CLIPRECT_1_BR 0x2821c #define PA_SC_CLIPRECT_1_BR 0x2821c
126 #define PSCB_X 0x00007fff
127 #define PSCB_Y 0x7fff0000
128 139 #define PA_SC_CLIPRECT_2_TL 0x28220 #define PA_SC_CLIPRECT_2_TL 0x28220
129 #define PSCT_X 0x00007fff
130 #define PSCT_Y 0x7fff0000
131 140 #define PA_SC_CLIPRECT_2_BR 0x28224 #define PA_SC_CLIPRECT_2_BR 0x28224
132 #define PSCB_X 0x00007fff
133 #define PSCB_Y 0x7fff0000
134 141 #define PA_SC_CLIPRECT_3_TL 0x28228 #define PA_SC_CLIPRECT_3_TL 0x28228
135 #define PSCT_X 0x00007fff
136 #define PSCT_Y 0x7fff0000
137 142 #define PA_SC_CLIPRECT_3_BR 0x2822c #define PA_SC_CLIPRECT_3_BR 0x2822c
138 #define PSCB_X 0x00007fff
139 #define PSCB_Y 0x7fff0000
140 143 #define PA_SC_EDGERULE 0x28230 #define PA_SC_EDGERULE 0x28230
141 144 #define PSE_ER_TRI 0x0000000f #define PSE_ER_TRI 0x0000000f
142 145 #define PSE_ER_POINT 0x000000f0 #define PSE_ER_POINT 0x000000f0
 
150 153 #define PSHSO_Y_OF 0x01ff0000 #define PSHSO_Y_OF 0x01ff0000
151 154 #define CB_TGT_MASK 0x28238 #define CB_TGT_MASK 0x28238
152 155 #define CTM_TGT_0_ENA 0x0000000f #define CTM_TGT_0_ENA 0x0000000f
156 #define CTM_TGT_RED 0x1
157 #define CTM_TGT_GREEN 0x2
158 #define CTM_TGT_BLUE 0x4
159 #define CTM_TGT_ALPHA 0x8
153 160 #define CTM_TGT_1_ENA 0x000000f0 #define CTM_TGT_1_ENA 0x000000f0
154 161 #define CTM_TGT_2_ENA 0x00000f00 #define CTM_TGT_2_ENA 0x00000f00
155 162 #define CTM_TGT_3_ENA 0x0000f000 #define CTM_TGT_3_ENA 0x0000f000
 
159 166 #define CTM_TGT_7_ENA 0xf0000000 #define CTM_TGT_7_ENA 0xf0000000
160 167 #define CB_SHADER_MASK 0x2823c #define CB_SHADER_MASK 0x2823c
161 168 #define CSM_OUTPUT_0_ENA 0x0000000f #define CSM_OUTPUT_0_ENA 0x0000000f
169 #define CSM_OUTPUT_RED 0x1
170 #define CSM_OUTPUT_GREEN 0x2
171 #define CSM_OUTPUT_BLUE 0x4
172 #define CSM_OUTPUT_ALPHA 0x8
162 173 #define CSM_OUTPUT_1_ENA 0x000000f0 #define CSM_OUTPUT_1_ENA 0x000000f0
163 174 #define CSM_OUTPUT_2_ENA 0x00000f00 #define CSM_OUTPUT_2_ENA 0x00000f00
164 175 #define CSM_OUTPUT_3_ENA 0x0000f000 #define CSM_OUTPUT_3_ENA 0x0000f000
 
166 177 #define CSM_OUTPUT_5_ENA 0x00f00000 #define CSM_OUTPUT_5_ENA 0x00f00000
167 178 #define CSM_OUTPUT_6_ENA 0x0f000000 #define CSM_OUTPUT_6_ENA 0x0f000000
168 179 #define CSM_OUTPUT_7_ENA 0xf0000000 #define CSM_OUTPUT_7_ENA 0xf0000000
180 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
181 #define PSGST_X 0x00007fff
182 #define PSGST_Y 0x7fff0000
183 #define PSGST_WND_OF_DIS BIT(31)
184 #define PA_SC_GENERIC_SCISSOR_BR 0x28244
185 #define PSGSB_X 0x00007fff
186 #define PSGSB_Y 0x7fff0000
187 #define PSGSB_WND_OF_DIS BIT(31)
169 188
170 #define PA_SC_VPORT_SCISSOR_0_TL 0x28250
171 #define PSVST_X 0x00007fff
172 #define PSVST_Y 0x7fff0000
173 #define PSVST_WND_OF_DIS BIT(31)
174 #define PA_SC_VPORT_SCISSOR_0_BR 0x28254
175 #define PSVSB_X 0x00007fff
176 #define PSVSB_Y 0x7fff0000
177 #define PSVSB_WND_OF_DIS BIT(31)
178 #define PA_SC_VPORT_SCISSOR_1_TL 0x28258
179 #define PSVST_X 0x00007fff
180 #define PSVST_Y 0x7fff0000
181 #define PSVST_WND_OF_DIS BIT(31)
182 #define PA_SC_VPORT_SCISSOR_1_BR 0x2825c
183 #define PSVSB_X 0x00007fff
184 #define PSVSB_Y 0x7fff0000
185 #define PSVSB_WND_OF_DIS BIT(31)
186 #define PA_SC_VPORT_SCISSOR_2_TL 0x28260
187 #define PSVST_X 0x00007fff
188 #define PSVST_Y 0x7fff0000
189 #define PSVST_WND_OF_DIS BIT(31)
190 #define PA_SC_VPORT_SCISSOR_2_BR 0x28264
191 #define PSVSB_X 0x00007fff
192 #define PSVSB_Y 0x7fff0000
193 #define PSVSB_WND_OF_DIS BIT(31)
194 #define PA_SC_VPORT_SCISSOR_3_TL 0x28268
195 #define PSVST_X 0x00007fff
196 #define PSVST_Y 0x7fff0000
197 #define PSVST_WND_OF_DIS BIT(31)
198 #define PA_SC_VPORT_SCISSOR_3_BR 0x2826c
199 #define PSVSB_X 0x00007fff
200 #define PSVSB_Y 0x7fff0000
201 #define PSVSB_WND_OF_DIS BIT(31)
202 #define PA_SC_VPORT_SCISSOR_4_TL 0x28270
203 #define PSVST_X 0x00007fff
204 #define PSVST_Y 0x7fff0000
205 #define PSVST_WND_OF_DIS BIT(31)
206 #define PA_SC_VPORT_SCISSOR_4_BR 0x28274
207 #define PSVSB_X 0x00007fff
208 #define PSVSB_Y 0x7fff0000
209 #define PSVSB_WND_OF_DIS BIT(31)
210 #define PA_SC_VPORT_SCISSOR_5_TL 0x28278
211 #define PSVST_X 0x00007fff
212 #define PSVST_Y 0x7fff0000
213 #define PSVST_WND_OF_DIS BIT(31)
214 #define PA_SC_VPORT_SCISSOR_5_BR 0x2827c
215 #define PSVSB_X 0x00007fff
216 #define PSVSB_Y 0x7fff0000
217 #define PSVSB_WND_OF_DIS BIT(31)
218 #define PA_SC_VPORT_SCISSOR_6_TL 0x28280
219 #define PSVST_X 0x00007fff
220 #define PSVST_Y 0x7fff0000
221 #define PSVST_WND_OF_DIS BIT(31)
222 #define PA_SC_VPORT_SCISSOR_6_BR 0x28284
223 #define PSVSB_X 0x00007fff
224 #define PSVSB_Y 0x7fff0000
225 #define PSVSB_WND_OF_DIS BIT(31)
226 #define PA_SC_VPORT_SCISSOR_7_TL 0x28288
227 #define PSVST_X 0x00007fff
228 #define PSVST_Y 0x7fff0000
229 #define PSVST_WND_OF_DIS BIT(31)
230 #define PA_SC_VPORT_SCISSOR_7_BR 0x2828c
231 #define PSVSB_X 0x00007fff
232 #define PSVSB_Y 0x7fff0000
233 #define PSVSB_WND_OF_DIS BIT(31)
234 #define PA_SC_VPORT_SCISSOR_8_TL 0x28290
235 #define PSVST_X 0x00007fff
236 #define PSVST_Y 0x7fff0000
237 #define PSVST_WND_OF_DIS BIT(31)
238 #define PA_SC_VPORT_SCISSOR_8_BR 0x28294
239 #define PSVSB_X 0x00007fff
240 #define PSVSB_Y 0x7fff0000
241 #define PSVSB_WND_OF_DIS BIT(31)
242 #define PA_SC_VPORT_SCISSOR_9_TL 0x28298
243 #define PSVST_X 0x00007fff
244 #define PSVST_Y 0x7fff0000
245 #define PSVST_WND_OF_DIS BIT(31)
246 #define PA_SC_VPORT_SCISSOR_9_BR 0x2829c
247 #define PSVSB_X 0x00007fff
248 #define PSVSB_Y 0x7fff0000
249 #define PSVSB_WND_OF_DIS BIT(31)
250 #define PA_SC_VPORT_SCISSOR_A_TL 0x282a0
251 #define PSVST_X 0x00007fff
252 #define PSVST_Y 0x7fff0000
253 #define PSVST_WND_OF_DIS BIT(31)
254 #define PA_SC_VPORT_SCISSOR_A_BR 0x282a4
255 #define PSVSB_X 0x00007fff
256 #define PSVSB_Y 0x7fff0000
257 #define PSVSB_WND_OF_DIS BIT(31)
258 #define PA_SC_VPORT_SCISSOR_B_TL 0x282a8
259 #define PSVST_X 0x00007fff
260 #define PSVST_Y 0x7fff0000
261 #define PSVST_WND_OF_DIS BIT(31)
262 #define PA_SC_VPORT_SCISSOR_B_BR 0x282ac
263 #define PSVSB_X 0x00007fff
264 #define PSVSB_Y 0x7fff0000
265 #define PSVSB_WND_OF_DIS BIT(31)
266 #define PA_SC_VPORT_SCISSOR_C_TL 0x282b0
267 #define PSVST_X 0x00007fff
268 #define PSVST_Y 0x7fff0000
269 #define PSVST_WND_OF_DIS BIT(31)
270 #define PA_SC_VPORT_SCISSOR_C_BR 0x282b4
271 #define PSVSB_X 0x00007fff
272 #define PSVSB_Y 0x7fff0000
273 #define PSVSB_WND_OF_DIS BIT(31)
274 #define PA_SC_VPORT_SCISSOR_D_TL 0x282b8
275 #define PSVST_X 0x00007fff
276 #define PSVST_Y 0x7fff0000
277 #define PSVST_WND_OF_DIS BIT(31)
278 #define PA_SC_VPORT_SCISSOR_D_BR 0x282bc
279 #define PSVSB_X 0x00007fff
280 #define PSVSB_Y 0x7fff0000
281 #define PSVSB_WND_OF_DIS BIT(31)
282 #define PA_SC_VPORT_SCISSOR_E_TL 0x282c0
189
190 #define PA_SC_VPORT_0_SCISSOR_TL 0x28250
283 191 #define PSVST_X 0x00007fff #define PSVST_X 0x00007fff
284 192 #define PSVST_Y 0x7fff0000 #define PSVST_Y 0x7fff0000
285 193 #define PSVST_WND_OF_DIS BIT(31) #define PSVST_WND_OF_DIS BIT(31)
286 #define PA_SC_VPORT_SCISSOR_E_BR 0x282c4
194 #define PA_SC_VPORT_0_SCISSOR_BR 0x28254
287 195 #define PSVSB_X 0x00007fff #define PSVSB_X 0x00007fff
288 196 #define PSVSB_Y 0x7fff0000 #define PSVSB_Y 0x7fff0000
289 197 #define PSVSB_WND_OF_DIS BIT(31) #define PSVSB_WND_OF_DIS BIT(31)
290 #define PA_SC_VPORT_SCISSOR_F_TL 0x282c8
291 #define PSVST_X 0x00007fff
292 #define PSVST_Y 0x7fff0000
293 #define PSVST_WND_OF_DIS BIT(31)
294 #define PA_SC_VPORT_SCISSOR_F_BR 0x282cc
295 #define PA_SC_VPORT_ZMIN_0 0x282d0
296 #define PA_SC_VPORT_ZMAX_0 0x282d4
297 #define PA_SC_VPORT_ZMIN_1 0x282d8
298 #define PA_SC_VPORT_ZMAX_1 0x282dc
299 #define PA_SC_VPORT_ZMIN_2 0x282e0
300 #define PA_SC_VPORT_ZMAX_2 0x282e4
301 #define PA_SC_VPORT_ZMIN_3 0x282e8
302 #define PA_SC_VPORT_ZMAX_3 0x282ec
303 #define PA_SC_VPORT_ZMIN_4 0x282f0
304 #define PA_SC_VPORT_ZMAX_4 0x282f4
305 #define PA_SC_VPORT_ZMIN_5 0x282f8
306 #define PA_SC_VPORT_ZMAX_5 0x282fc
307 #define PA_SC_VPORT_ZMIN_6 0x28300
308 #define PA_SC_VPORT_ZMAX_6 0x28304
309 #define PA_SC_VPORT_ZMIN_7 0x28308
310 #define PA_SC_VPORT_ZMAX_7 0x2830c
311 #define PA_SC_VPORT_ZMIN_8 0x28310
312 #define PA_SC_VPORT_ZMAX_8 0x28314
313 #define PA_SC_VPORT_ZMIN_9 0x28318
314 #define PA_SC_VPORT_ZMAX_9 0x2831c
315 #define PA_SC_VPORT_ZMIN_A 0x28320
316 #define PA_SC_VPORT_ZMAX_A 0x28324
317 #define PA_SC_VPORT_ZMIN_B 0x28328
318 #define PA_SC_VPORT_ZMAX_B 0x2832c
319 #define PA_SC_VPORT_ZMIN_C 0x28330
320 #define PA_SC_VPORT_ZMAX_C 0x28334
321 #define PA_SC_VPORT_ZMIN_D 0x28338
322 #define PA_SC_VPORT_ZMAX_D 0x2833c
323 #define PA_SC_VPORT_ZMIN_E 0x28340
324 #define PA_SC_VPORT_ZMAX_E 0x28344
325 #define PA_SC_VPORT_ZMIN_F 0x28348
326 #define PA_SC_VPORT_ZMAX_F 0x2834c
198 #define PA_SC_VPORT_1_SCISSOR_TL 0x28258
199 #define PA_SC_VPORT_1_SCISSOR_BR 0x2825c
200 #define PA_SC_VPORT_2_SCISSOR_TL 0x28260
201 #define PA_SC_VPORT_2_SCISSOR_BR 0x28264
202 #define PA_SC_VPORT_3_SCISSOR_TL 0x28268
203 #define PA_SC_VPORT_3_SCISSOR_BR 0x2826c
204 #define PA_SC_VPORT_4_SCISSOR_TL 0x28270
205 #define PA_SC_VPORT_4_SCISSOR_BR 0x28274
206 #define PA_SC_VPORT_5_SCISSOR_TL 0x28278
207 #define PA_SC_VPORT_5_SCISSOR_BR 0x2827c
208 #define PA_SC_VPORT_6_SCISSOR_TL 0x28280
209 #define PA_SC_VPORT_6_SCISSOR_BR 0x28284
210 #define PA_SC_VPORT_7_SCISSOR_TL 0x28288
211 #define PA_SC_VPORT_7_SCISSOR_BR 0x2828c
212 #define PA_SC_VPORT_8_SCISSOR_TL 0x28290
213 #define PA_SC_VPORT_8_SCISSOR_BR 0x28294
214 #define PA_SC_VPORT_9_SCISSOR_TL 0x28298
215 #define PA_SC_VPORT_9_SCISSOR_BR 0x2829c
216 #define PA_SC_VPORT_A_SCISSOR_TL 0x282a0
217 #define PA_SC_VPORT_A_SCISSOR_BR 0x282a4
218 #define PA_SC_VPORT_B_SCISSOR_TL 0x282a8
219 #define PA_SC_VPORT_B_SCISSOR_BR 0x282ac
220 #define PA_SC_VPORT_C_SCISSOR_TL 0x282b0
221 #define PA_SC_VPORT_C_SCISSOR_BR 0x282b4
222 #define PA_SC_VPORT_D_SCISSOR_TL 0x282b8
223 #define PA_SC_VPORT_D_SCISSOR_BR 0x282bc
224 #define PA_SC_VPORT_E_SCISSOR_TL 0x282c0
225 #define PA_SC_VPORT_E_SCISSOR_BR 0x282c4
226 #define PA_SC_VPORT_F_SCISSOR_TL 0x282c8
227 #define PA_SC_VPORT_F_SCISSOR_BR 0x282cc
228 #define PA_SC_VPORT_0_TE_ZMIN 0x282d0
229 #define PA_SC_VPORT_0_TE_ZMAX 0x282d4
230 #define PA_SC_VPORT_1_TE_ZMIN 0x282d8
231 #define PA_SC_VPORT_1_TE_ZMAX 0x282dc
232 #define PA_SC_VPORT_2_TE_ZMIN 0x282e0
233 #define PA_SC_VPORT_2_TE_ZMAX 0x282e4
234 #define PA_SC_VPORT_3_TE_ZMIN 0x282e8
235 #define PA_SC_VPORT_3_TE_ZMAX 0x282ec
236 #define PA_SC_VPORT_4_TE_ZMIN 0x282f0
237 #define PA_SC_VPORT_4_TE_ZMAX 0x282f4
238 #define PA_SC_VPORT_5_TE_ZMIN 0x282f8
239 #define PA_SC_VPORT_5_TE_ZMAX 0x282fc
240 #define PA_SC_VPORT_6_TE_ZMIN 0x28300
241 #define PA_SC_VPORT_6_TE_ZMAX 0x28304
242 #define PA_SC_VPORT_7_TE_ZMIN 0x28308
243 #define PA_SC_VPORT_7_TE_ZMAX 0x2830c
244 #define PA_SC_VPORT_8_TE_ZMIN 0x28310
245 #define PA_SC_VPORT_8_TE_ZMAX 0x28314
246 #define PA_SC_VPORT_9_TE_ZMIN 0x28318
247 #define PA_SC_VPORT_9_TE_ZMAX 0x2831c
248 #define PA_SC_VPORT_A_TE_ZMIN 0x28320
249 #define PA_SC_VPORT_A_TE_ZMAX 0x28324
250 #define PA_SC_VPORT_B_TE_ZMIN 0x28328
251 #define PA_SC_VPORT_B_TE_ZMAX 0x2832c
252 #define PA_SC_VPORT_C_TE_ZMIN 0x28330
253 #define PA_SC_VPORT_C_TE_ZMAX 0x28334
254 #define PA_SC_VPORT_D_TE_ZMIN 0x28338
255 #define PA_SC_VPORT_D_TE_ZMAX 0x2833c
256 #define PA_SC_VPORT_E_TE_ZMIN 0x28340
257 #define PA_SC_VPORT_E_TE_ZMAX 0x28344
258 #define PA_SC_VPORT_F_TE_ZMIN 0x28348
259 #define PA_SC_VPORT_F_TE_ZMAX 0x2834c
327 260 #define PA_SC_RASTER_CFG 0x28350 #define PA_SC_RASTER_CFG 0x28350
328 261 #define PSRC_RB_MAP_PKR_0 0x00000003 #define PSRC_RB_MAP_PKR_0 0x00000003
329 262 #define PSRC_RB_MAP_0 0 #define PSRC_RB_MAP_0 0
330 263 #define PSRC_RB_MAP_1 1 #define PSRC_RB_MAP_1 1
331 264 #define PSRC_RB_MAP_2 2 #define PSRC_RB_MAP_2 2
332 #define PSRC_RB_MAP_3 3
333 #define PSRC_RB_MAP_PKR_1 0x0000000c
334 #define PSRC_RB_MAP_0 0
335 #define PSRC_RB_MAP_1 1
336 #define PSRC_RB_MAP_2 2
337 #define PSRC_RB_MAP_3 3
338 #define PSRC_RB_XSEL_2 0x00000030
339 #define PSRC_RB_XSEL_2_0 0
340 #define PSRC_RB_XSEL_2_1 1
341 #define PSRC_RB_XSEL_2_2 2
342 #define PSRC_RB_XSEL_2_3 3
343 #define PSRC_RB_XSEL BIT(6)
344 #define PSRC_RB_YSEL BIT(7)
345 #define PSRC_PKR_MAP 0x00000300
346 #define PSRC_PKR_MAP_0 0
347 #define PSRC_PKR_MAP_1 1
348 #define PSRC_PKR_MAP_2 2
349 #define PSRC_PKR_MAP_3 3
350 #define PSRC_PKR_XSEL 0x00000c00
351 #define PSRC_PKR_XSEL_0 0
352 #define PSRC_PKR_XSEL_1 1
353 #define PSRC_PKR_XSEL_2 2
354 #define PSRC_PKR_XSEL_3 3
355 #define PSRC_PKR_YSEL 0x00003000
356 #define PSRC_PKR_YSEL_0 0
357 #define PSRC_PKR_YSEL_1 1
358 #define PSRC_PKR_YSEL_2 2
359 #define PSRC_PKR_YSEL_3 3
360 #define PSRC_SC_MAP 0x00030000
361 #define PSRC_SC_MAP_0 0
362 #define PSRC_SC_MAP_1 1
363 #define PSRC_SC_MAP_2 2
364 #define PSRC_SC_MAP_3 3
365 #define PSRC_SC_XSEL 0x000c0000
366 #define PSRC_SC_XSEL_8_WIDE_TILE 0
367 #define PSRC_SC_XSEL_16_WIDE_TILE 1
368 #define PSRC_SC_XSEL_32_WIDE_TILE 2
369 #define PSRC_SC_XSEL_64_WIDE_TILE 3
370 #define PSRC_SC_YSEL 0x00300000
371 #define PSRC_SC_YSEL_8_WIDE_TILE 0
372 #define PSRC_SC_YSEL_16_WIDE_TILE 1
373 #define PSRC_SC_YSEL_32_WIDE_TILE 2
374 #define PSRC_SC_YSEL_64_WIDE_TILE 3
375 #define PSRC_SE_MAP 0x03000000
376 #define PSRC_SE_MAP_0 0
377 #define PSRC_SE_MAP_1 1
378 #define PSRC_SE_MAP_2 2
379 #define PSRC_SE_MAP_3 3
380 #define PSRC_SE_XSEL 0x0c000000
381 #define PSRC_SE_XSEL_8_WIDE_TILE 0
382 #define PSRC_SE_XSEL_16_WIDE_TILE 1
383 #define PSRC_SE_XSEL_32_WIDE_TILE 2
384 #define PSRC_SE_XSEL_64_WIDE_TILE 3
385 #define PSRC_SE_YSEL 0x30000000
386 #define PSRC_SE_YSEL_8_WIDE_TILE 0
387 #define PSRC_SE_YSEL_16_WIDE_TILE 1
388 #define PSRC_SE_YSEL_32_WIDE_TILE 2
389 #define PSRC_SE_YSEL_64_WIDE_TILE 3
390
391 #define CP_RING_ID 0x28364
392 #define CP_VM_ID 0x28368
393
394 #define VGT_MAX_VTX_IDX 0x28400
395 #define VGT_MIN_VTX_IDX 0x28404
396 #define VGT_IDX_OF 0x28408
397 #define VGT_MULTI_PRIM_IB_RESET_IDX 0x2840c
398
399 #define CB_BLEND_RED 0x28414
400 #define CB_BLEND_GREEN 0x28418
401 #define CB_BLEND_BLUE 0x2841c
402 #define CB_BLEND_ALPHA 0x28420
403
404 #define CB_BLEND_0_CTL 0x28780
405 #define CBC_COLOR_SRC_BLEND 0x0000001f
406 #define CBC_BLEND_ZERO 0x00
407 #define CBC_BLEND_ONE 0x01
408 #define CBC_BLEND_SRC_COLOR 0x02
409 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
410 #define CBC_BLEND_SRC_ALPHA 0x04
411 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
412 #define CBC_BLEND_DST_ALPHA 0x06
413 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
414 #define CBC_BLEND_DST_COLOR 0x08
415 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
416 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
417 #define CBC_BLEND_CONSTANT_COLOR 0x0d
418 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
419 #define CBC_BLEND_SRC_1_COLOR 0x0f
420 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
421 #define CBC_BLEND_SRC_1_ALPHA 0x11
422 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
423 #define CBC_BLEND_CONSTANT_ALPHA 0x13
424 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
425 #define CBC_COLOR_COMB_FCN 0x00000e0
426 #define CBC_COMB_DST_PLUS_SRC 0
427 #define CBC_COMB_SRC_MINUS_DST 1
428 #define CBC_COMB_MIN_DST_SRC 2
429 #define CBC_COMB_MAX_DST_SRC 3
430 #define CBC_COMB_DST_MINUS_SRC 4
431 #define CBC_COLOR_DST_BLEND 0x00001f00
432 #define CBC_BLEND_ZERO 0x00
433 #define CBC_BLEND_ONE 0x01
434 #define CBC_BLEND_SRC_COLOR 0x02
435 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
436 #define CBC_BLEND_SRC_ALPHA 0x04
437 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
438 #define CBC_BLEND_DST_ALPHA 0x06
439 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
440 #define CBC_BLEND_DST_COLOR 0x08
441 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
442 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
443 #define CBC_BLEND_CONSTANT_COLOR 0x0d
444 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
445 #define CBC_BLEND_SRC_1_COLOR 0x0f
446 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
447 #define CBC_BLEND_SRC_1_ALPHA 0x11
448 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
449 #define CBC_BLEND_CONSTANT_ALPHA 0x13
450 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
451 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
452 #define CBC_BLEND_ZERO 0x00
453 #define CBC_BLEND_ONE 0x01
454 #define CBC_BLEND_SRC_COLOR 0x02
455 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
456 #define CBC_BLEND_SRC_ALPHA 0x04
457 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
458 #define CBC_BLEND_DST_ALPHA 0x06
459 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
460 #define CBC_BLEND_DST_COLOR 0x08
461 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
462 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
463 #define CBC_BLEND_CONSTANT_COLOR 0x0d
464 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
465 #define CBC_BLEND_SRC_1_COLOR 0x0f
466 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
467 #define CBC_BLEND_SRC_1_ALPHA 0x11
468 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
469 #define CBC_BLEND_CONSTANT_ALPHA 0x13
470 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
471 #define CBC_ALPHA_COMB_FCN 0x00e00000
472 #define CBC_COMB_DST_PLUS_SRC 0
473 #define CBC_COMB_SRC_MINUS_DST 1
474 #define CBC_COMB_MIN_DST_SRC 2
475 #define CBC_COMB_MAX_DST_SRC 3
476 #define CBC_COMB_DST_MINUS_SRC 4
477 #define CBC_ALPHA_DST_BLEND 0x1f000000
478 #define CBC_BLEND_ZERO 0x00
479 #define CBC_BLEND_ONE 0x01
480 #define CBC_BLEND_SRC_COLOR 0x02
481 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
482 #define CBC_BLEND_SRC_ALPHA 0x04
483 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
484 #define CBC_BLEND_DST_ALPHA 0x06
485 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
486 #define CBC_BLEND_DST_COLOR 0x08
487 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
488 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
489 #define CBC_BLEND_CONSTANT_COLOR 0x0d
490 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
491 #define CBC_BLEND_SRC_1_COLOR 0x0f
492 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
493 #define CBC_BLEND_SRC_1_ALPHA 0x11
494 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
495 #define CBC_BLEND_CONSTANT_ALPHA 0x13
496 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
497 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
498 #define CBC_CB_BLEND_ENA BIT(30)
499 #define CBC_ROP3_DIS BIT(31)
500 #define CB_BLEND_1_CTL 0x28784
501 #define CBC_COLOR_SRC_BLEND 0x0000001f
502 #define CBC_BLEND_ZERO 0x00
503 #define CBC_BLEND_ONE 0x01
504 #define CBC_BLEND_SRC_COLOR 0x02
505 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
506 #define CBC_BLEND_SRC_ALPHA 0x04
507 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
508 #define CBC_BLEND_DST_ALPHA 0x06
509 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
510 #define CBC_BLEND_DST_COLOR 0x08
511 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
512 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
513 #define CBC_BLEND_CONSTANT_COLOR 0x0d
514 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
515 #define CBC_BLEND_SRC_1_COLOR 0x0f
516 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
517 #define CBC_BLEND_SRC_1_ALPHA 0x11
518 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
519 #define CBC_BLEND_CONSTANT_ALPHA 0x13
520 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
521 #define CBC_COLOR_COMB_FCN 0x00000e0
522 #define CBC_COMB_DST_PLUS_SRC 0
523 #define CBC_COMB_SRC_MINUS_DST 1
524 #define CBC_COMB_MIN_DST_SRC 2
525 #define CBC_COMB_MAX_DST_SRC 3
526 #define CBC_COMB_DST_MINUS_SRC 4
527 #define CBC_COLOR_DST_BLEND 0x00001f00
528 #define CBC_BLEND_ZERO 0x00
529 #define CBC_BLEND_ONE 0x01
530 #define CBC_BLEND_SRC_COLOR 0x02
531 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
532 #define CBC_BLEND_SRC_ALPHA 0x04
533 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
534 #define CBC_BLEND_DST_ALPHA 0x06
535 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
536 #define CBC_BLEND_DST_COLOR 0x08
537 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
538 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
539 #define CBC_BLEND_CONSTANT_COLOR 0x0d
540 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
541 #define CBC_BLEND_SRC_1_COLOR 0x0f
542 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
543 #define CBC_BLEND_SRC_1_ALPHA 0x11
544 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
545 #define CBC_BLEND_CONSTANT_ALPHA 0x13
546 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
547 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
548 #define CBC_BLEND_ZERO 0x00
549 #define CBC_BLEND_ONE 0x01
550 #define CBC_BLEND_SRC_COLOR 0x02
551 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
552 #define CBC_BLEND_SRC_ALPHA 0x04
553 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
554 #define CBC_BLEND_DST_ALPHA 0x06
555 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
556 #define CBC_BLEND_DST_COLOR 0x08
557 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
558 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
559 #define CBC_BLEND_CONSTANT_COLOR 0x0d
560 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
561 #define CBC_BLEND_SRC_1_COLOR 0x0f
562 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
563 #define CBC_BLEND_SRC_1_ALPHA 0x11
564 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
565 #define CBC_BLEND_CONSTANT_ALPHA 0x13
566 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
567 #define CBC_ALPHA_COMB_FCN 0x00e00000
568 #define CBC_COMB_DST_PLUS_SRC 0
569 #define CBC_COMB_SRC_MINUS_DST 1
570 #define CBC_COMB_MIN_DST_SRC 2
571 #define CBC_COMB_MAX_DST_SRC 3
572 #define CBC_COMB_DST_MINUS_SRC 4
573 #define CBC_ALPHA_DST_BLEND 0x1f000000
574 #define CBC_BLEND_ZERO 0x00
575 #define CBC_BLEND_ONE 0x01
576 #define CBC_BLEND_SRC_COLOR 0x02
577 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
578 #define CBC_BLEND_SRC_ALPHA 0x04
579 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
580 #define CBC_BLEND_DST_ALPHA 0x06
581 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
582 #define CBC_BLEND_DST_COLOR 0x08
583 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
584 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
585 #define CBC_BLEND_CONSTANT_COLOR 0x0d
586 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
587 #define CBC_BLEND_SRC_1_COLOR 0x0f
588 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
589 #define CBC_BLEND_SRC_1_ALPHA 0x11
590 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
591 #define CBC_BLEND_CONSTANT_ALPHA 0x13
592 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
593 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
594 #define CBC_CB_BLEND_ENA BIT(30)
595 #define CBC_ROP3_DIS BIT(31)
596 #define CB_BLEND_2_CTL 0x28788
597 #define CBC_COLOR_SRC_BLEND 0x0000001f
598 #define CBC_BLEND_ZERO 0x00
599 #define CBC_BLEND_ONE 0x01
600 #define CBC_BLEND_SRC_COLOR 0x02
601 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
602 #define CBC_BLEND_SRC_ALPHA 0x04
603 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
604 #define CBC_BLEND_DST_ALPHA 0x06
605 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
606 #define CBC_BLEND_DST_COLOR 0x08
607 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
608 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
609 #define CBC_BLEND_CONSTANT_COLOR 0x0d
610 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
611 #define CBC_BLEND_SRC_1_COLOR 0x0f
612 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
613 #define CBC_BLEND_SRC_1_ALPHA 0x11
614 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
615 #define CBC_BLEND_CONSTANT_ALPHA 0x13
616 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
617 #define CBC_COLOR_COMB_FCN 0x00000e0
618 #define CBC_COMB_DST_PLUS_SRC 0
619 #define CBC_COMB_SRC_MINUS_DST 1
620 #define CBC_COMB_MIN_DST_SRC 2
621 #define CBC_COMB_MAX_DST_SRC 3
622 #define CBC_COMB_DST_MINUS_SRC 4
623 #define CBC_COLOR_DST_BLEND 0x00001f00
624 #define CBC_BLEND_ZERO 0x00
625 #define CBC_BLEND_ONE 0x01
626 #define CBC_BLEND_SRC_COLOR 0x02
627 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
628 #define CBC_BLEND_SRC_ALPHA 0x04
629 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
630 #define CBC_BLEND_DST_ALPHA 0x06
631 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
632 #define CBC_BLEND_DST_COLOR 0x08
633 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
634 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
635 #define CBC_BLEND_CONSTANT_COLOR 0x0d
636 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
637 #define CBC_BLEND_SRC_1_COLOR 0x0f
638 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
639 #define CBC_BLEND_SRC_1_ALPHA 0x11
640 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
641 #define CBC_BLEND_CONSTANT_ALPHA 0x13
642 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
643 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
644 #define CBC_BLEND_ZERO 0x00
645 #define CBC_BLEND_ONE 0x01
646 #define CBC_BLEND_SRC_COLOR 0x02
647 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
648 #define CBC_BLEND_SRC_ALPHA 0x04
649 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
650 #define CBC_BLEND_DST_ALPHA 0x06
651 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
652 #define CBC_BLEND_DST_COLOR 0x08
653 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
654 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
655 #define CBC_BLEND_CONSTANT_COLOR 0x0d
656 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
657 #define CBC_BLEND_SRC_1_COLOR 0x0f
658 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
659 #define CBC_BLEND_SRC_1_ALPHA 0x11
660 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
661 #define CBC_BLEND_CONSTANT_ALPHA 0x13
662 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
663 #define CBC_ALPHA_COMB_FCN 0x00e00000
664 #define CBC_COMB_DST_PLUS_SRC 0
665 #define CBC_COMB_SRC_MINUS_DST 1
666 #define CBC_COMB_MIN_DST_SRC 2
667 #define CBC_COMB_MAX_DST_SRC 3
668 #define CBC_COMB_DST_MINUS_SRC 4
669 #define CBC_ALPHA_DST_BLEND 0x1f000000
670 #define CBC_BLEND_ZERO 0x00
671 #define CBC_BLEND_ONE 0x01
672 #define CBC_BLEND_SRC_COLOR 0x02
673 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
674 #define CBC_BLEND_SRC_ALPHA 0x04
675 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
676 #define CBC_BLEND_DST_ALPHA 0x06
677 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
678 #define CBC_BLEND_DST_COLOR 0x08
679 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
680 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
681 #define CBC_BLEND_CONSTANT_COLOR 0x0d
682 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
683 #define CBC_BLEND_SRC_1_COLOR 0x0f
684 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
685 #define CBC_BLEND_SRC_1_ALPHA 0x11
686 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
687 #define CBC_BLEND_CONSTANT_ALPHA 0x13
688 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
689 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
690 #define CBC_CB_BLEND_ENA BIT(30)
691 #define CBC_ROP3_DIS BIT(31)
692 #define CB_BLEND_3_CTL 0x2878c
693 #define CBC_COLOR_SRC_BLEND 0x0000001f
694 #define CBC_BLEND_ZERO 0x00
695 #define CBC_BLEND_ONE 0x01
696 #define CBC_BLEND_SRC_COLOR 0x02
697 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
698 #define CBC_BLEND_SRC_ALPHA 0x04
699 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
700 #define CBC_BLEND_DST_ALPHA 0x06
701 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
702 #define CBC_BLEND_DST_COLOR 0x08
703 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
704 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
705 #define CBC_BLEND_CONSTANT_COLOR 0x0d
706 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
707 #define CBC_BLEND_SRC_1_COLOR 0x0f
708 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
709 #define CBC_BLEND_SRC_1_ALPHA 0x11
710 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
711 #define CBC_BLEND_CONSTANT_ALPHA 0x13
712 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
713 #define CBC_COLOR_COMB_FCN 0x00000e0
714 #define CBC_COMB_DST_PLUS_SRC 0
715 #define CBC_COMB_SRC_MINUS_DST 1
716 #define CBC_COMB_MIN_DST_SRC 2
717 #define CBC_COMB_MAX_DST_SRC 3
718 #define CBC_COMB_DST_MINUS_SRC 4
719 #define CBC_COLOR_DST_BLEND 0x00001f00
720 #define CBC_BLEND_ZERO 0x00
721 #define CBC_BLEND_ONE 0x01
722 #define CBC_BLEND_SRC_COLOR 0x02
723 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
724 #define CBC_BLEND_SRC_ALPHA 0x04
725 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
726 #define CBC_BLEND_DST_ALPHA 0x06
727 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
728 #define CBC_BLEND_DST_COLOR 0x08
729 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
730 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
731 #define CBC_BLEND_CONSTANT_COLOR 0x0d
732 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
733 #define CBC_BLEND_SRC_1_COLOR 0x0f
734 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
735 #define CBC_BLEND_SRC_1_ALPHA 0x11
736 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
737 #define CBC_BLEND_CONSTANT_ALPHA 0x13
738 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
739 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
740 #define CBC_BLEND_ZERO 0x00
741 #define CBC_BLEND_ONE 0x01
742 #define CBC_BLEND_SRC_COLOR 0x02
743 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
744 #define CBC_BLEND_SRC_ALPHA 0x04
745 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
746 #define CBC_BLEND_DST_ALPHA 0x06
747 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
748 #define CBC_BLEND_DST_COLOR 0x08
749 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
750 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
751 #define CBC_BLEND_CONSTANT_COLOR 0x0d
752 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
753 #define CBC_BLEND_SRC_1_COLOR 0x0f
754 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
755 #define CBC_BLEND_SRC_1_ALPHA 0x11
756 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
757 #define CBC_BLEND_CONSTANT_ALPHA 0x13
758 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
759 #define CBC_ALPHA_COMB_FCN 0x00e00000
760 #define CBC_COMB_DST_PLUS_SRC 0
761 #define CBC_COMB_SRC_MINUS_DST 1
762 #define CBC_COMB_MIN_DST_SRC 2
763 #define CBC_COMB_MAX_DST_SRC 3
764 #define CBC_COMB_DST_MINUS_SRC 4
765 #define CBC_ALPHA_DST_BLEND 0x1f000000
766 #define CBC_BLEND_ZERO 0x00
767 #define CBC_BLEND_ONE 0x01
768 #define CBC_BLEND_SRC_COLOR 0x02
769 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
770 #define CBC_BLEND_SRC_ALPHA 0x04
771 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
772 #define CBC_BLEND_DST_ALPHA 0x06
773 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
774 #define CBC_BLEND_DST_COLOR 0x08
775 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
776 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
777 #define CBC_BLEND_CONSTANT_COLOR 0x0d
778 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
779 #define CBC_BLEND_SRC_1_COLOR 0x0f
780 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
781 #define CBC_BLEND_SRC_1_ALPHA 0x11
782 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
783 #define CBC_BLEND_CONSTANT_ALPHA 0x13
784 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
785 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
786 #define CBC_CB_BLEND_ENA BIT(30)
787 #define CBC_ROP3_DIS BIT(31)
788 #define CB_BLEND_4_CTL 0x28790
789 #define CBC_COLOR_SRC_BLEND 0x0000001f
790 #define CBC_BLEND_ZERO 0x00
791 #define CBC_BLEND_ONE 0x01
792 #define CBC_BLEND_SRC_COLOR 0x02
793 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
794 #define CBC_BLEND_SRC_ALPHA 0x04
795 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
796 #define CBC_BLEND_DST_ALPHA 0x06
797 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
798 #define CBC_BLEND_DST_COLOR 0x08
799 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
800 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
801 #define CBC_BLEND_CONSTANT_COLOR 0x0d
802 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
803 #define CBC_BLEND_SRC_1_COLOR 0x0f
804 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
805 #define CBC_BLEND_SRC_1_ALPHA 0x11
806 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
807 #define CBC_BLEND_CONSTANT_ALPHA 0x13
808 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
809 #define CBC_COLOR_COMB_FCN 0x00000e0
810 #define CBC_COMB_DST_PLUS_SRC 0
811 #define CBC_COMB_SRC_MINUS_DST 1
812 #define CBC_COMB_MIN_DST_SRC 2
813 #define CBC_COMB_MAX_DST_SRC 3
814 #define CBC_COMB_DST_MINUS_SRC 4
815 #define CBC_COLOR_DST_BLEND 0x00001f00
816 #define CBC_BLEND_ZERO 0x00
817 #define CBC_BLEND_ONE 0x01
818 #define CBC_BLEND_SRC_COLOR 0x02
819 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
820 #define CBC_BLEND_SRC_ALPHA 0x04
821 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
822 #define CBC_BLEND_DST_ALPHA 0x06
823 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
824 #define CBC_BLEND_DST_COLOR 0x08
825 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
826 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
827 #define CBC_BLEND_CONSTANT_COLOR 0x0d
828 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
829 #define CBC_BLEND_SRC_1_COLOR 0x0f
830 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
831 #define CBC_BLEND_SRC_1_ALPHA 0x11
832 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
833 #define CBC_BLEND_CONSTANT_ALPHA 0x13
834 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
835 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
836 #define CBC_BLEND_ZERO 0x00
837 #define CBC_BLEND_ONE 0x01
838 #define CBC_BLEND_SRC_COLOR 0x02
839 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
840 #define CBC_BLEND_SRC_ALPHA 0x04
841 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
842 #define CBC_BLEND_DST_ALPHA 0x06
843 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
844 #define CBC_BLEND_DST_COLOR 0x08
845 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
846 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
847 #define CBC_BLEND_CONSTANT_COLOR 0x0d
848 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
849 #define CBC_BLEND_SRC_1_COLOR 0x0f
850 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
851 #define CBC_BLEND_SRC_1_ALPHA 0x11
852 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
853 #define CBC_BLEND_CONSTANT_ALPHA 0x13
854 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
855 #define CBC_ALPHA_COMB_FCN 0x00e00000
856 #define CBC_COMB_DST_PLUS_SRC 0
857 #define CBC_COMB_SRC_MINUS_DST 1
858 #define CBC_COMB_MIN_DST_SRC 2
859 #define CBC_COMB_MAX_DST_SRC 3
860 #define CBC_COMB_DST_MINUS_SRC 4
861 #define CBC_ALPHA_DST_BLEND 0x1f000000
862 #define CBC_BLEND_ZERO 0x00
863 #define CBC_BLEND_ONE 0x01
864 #define CBC_BLEND_SRC_COLOR 0x02
865 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
866 #define CBC_BLEND_SRC_ALPHA 0x04
867 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
868 #define CBC_BLEND_DST_ALPHA 0x06
869 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
870 #define CBC_BLEND_DST_COLOR 0x08
871 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
872 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
873 #define CBC_BLEND_CONSTANT_COLOR 0x0d
874 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
875 #define CBC_BLEND_SRC_1_COLOR 0x0f
876 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
877 #define CBC_BLEND_SRC_1_ALPHA 0x11
878 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
879 #define CBC_BLEND_CONSTANT_ALPHA 0x13
880 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
881 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
882 #define CBC_CB_BLEND_ENA BIT(30)
883 #define CBC_ROP3_DIS BIT(31)
884 #define CB_BLEND_5_CTL 0x28794
885 #define CBC_COLOR_SRC_BLEND 0x0000001f
886 #define CBC_BLEND_ZERO 0x00
887 #define CBC_BLEND_ONE 0x01
888 #define CBC_BLEND_SRC_COLOR 0x02
889 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
890 #define CBC_BLEND_SRC_ALPHA 0x04
891 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
892 #define CBC_BLEND_DST_ALPHA 0x06
893 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
894 #define CBC_BLEND_DST_COLOR 0x08
895 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
896 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
897 #define CBC_BLEND_CONSTANT_COLOR 0x0d
898 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
899 #define CBC_BLEND_SRC_1_COLOR 0x0f
900 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
901 #define CBC_BLEND_SRC_1_ALPHA 0x11
902 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
903 #define CBC_BLEND_CONSTANT_ALPHA 0x13
904 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
905 #define CBC_COLOR_COMB_FCN 0x00000e0
906 #define CBC_COMB_DST_PLUS_SRC 0
907 #define CBC_COMB_SRC_MINUS_DST 1
908 #define CBC_COMB_MIN_DST_SRC 2
909 #define CBC_COMB_MAX_DST_SRC 3
910 #define CBC_COMB_DST_MINUS_SRC 4
911 #define CBC_COLOR_DST_BLEND 0x00001f00
912 #define CBC_BLEND_ZERO 0x00
913 #define CBC_BLEND_ONE 0x01
914 #define CBC_BLEND_SRC_COLOR 0x02
915 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
916 #define CBC_BLEND_SRC_ALPHA 0x04
917 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
918 #define CBC_BLEND_DST_ALPHA 0x06
919 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
920 #define CBC_BLEND_DST_COLOR 0x08
921 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
922 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
923 #define CBC_BLEND_CONSTANT_COLOR 0x0d
924 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
925 #define CBC_BLEND_SRC_1_COLOR 0x0f
926 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
927 #define CBC_BLEND_SRC_1_ALPHA 0x11
928 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
929 #define CBC_BLEND_CONSTANT_ALPHA 0x13
930 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
931 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
932 #define CBC_BLEND_ZERO 0x00
933 #define CBC_BLEND_ONE 0x01
934 #define CBC_BLEND_SRC_COLOR 0x02
935 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
936 #define CBC_BLEND_SRC_ALPHA 0x04
937 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
938 #define CBC_BLEND_DST_ALPHA 0x06
939 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
940 #define CBC_BLEND_DST_COLOR 0x08
941 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
942 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
943 #define CBC_BLEND_CONSTANT_COLOR 0x0d
944 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
945 #define CBC_BLEND_SRC_1_COLOR 0x0f
946 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
947 #define CBC_BLEND_SRC_1_ALPHA 0x11
948 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
949 #define CBC_BLEND_CONSTANT_ALPHA 0x13
950 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
951 #define CBC_ALPHA_COMB_FCN 0x00e00000
952 #define CBC_COMB_DST_PLUS_SRC 0
953 #define CBC_COMB_SRC_MINUS_DST 1
954 #define CBC_COMB_MIN_DST_SRC 2
955 #define CBC_COMB_MAX_DST_SRC 3
956 #define CBC_COMB_DST_MINUS_SRC 4
957 #define CBC_ALPHA_DST_BLEND 0x1f000000
958 #define CBC_BLEND_ZERO 0x00
959 #define CBC_BLEND_ONE 0x01
960 #define CBC_BLEND_SRC_COLOR 0x02
961 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
962 #define CBC_BLEND_SRC_ALPHA 0x04
963 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
964 #define CBC_BLEND_DST_ALPHA 0x06
965 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
966 #define CBC_BLEND_DST_COLOR 0x08
967 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
968 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
969 #define CBC_BLEND_CONSTANT_COLOR 0x0d
970 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
971 #define CBC_BLEND_SRC_1_COLOR 0x0f
972 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
973 #define CBC_BLEND_SRC_1_ALPHA 0x11
974 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
975 #define CBC_BLEND_CONSTANT_ALPHA 0x13
976 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
977 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
978 #define CBC_CB_BLEND_ENA BIT(30)
979 #define CBC_ROP3_DIS BIT(31)
980 #define CB_BLEND_6_CTL 0x28798
981 #define CBC_COLOR_SRC_BLEND 0x0000001f
982 #define CBC_BLEND_ZERO 0x00
983 #define CBC_BLEND_ONE 0x01
984 #define CBC_BLEND_SRC_COLOR 0x02
985 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
986 #define CBC_BLEND_SRC_ALPHA 0x04
987 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
988 #define CBC_BLEND_DST_ALPHA 0x06
989 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
990 #define CBC_BLEND_DST_COLOR 0x08
991 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
992 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
993 #define CBC_BLEND_CONSTANT_COLOR 0x0d
994 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
995 #define CBC_BLEND_SRC_1_COLOR 0x0f
996 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
997 #define CBC_BLEND_SRC_1_ALPHA 0x11
998 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
999 #define CBC_BLEND_CONSTANT_ALPHA 0x13
1000 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
1001 #define CBC_COLOR_COMB_FCN 0x00000e0
1002 #define CBC_COMB_DST_PLUS_SRC 0
1003 #define CBC_COMB_SRC_MINUS_DST 1
1004 #define CBC_COMB_MIN_DST_SRC 2
1005 #define CBC_COMB_MAX_DST_SRC 3
1006 #define CBC_COMB_DST_MINUS_SRC 4
1007 #define CBC_COLOR_DST_BLEND 0x00001f00
1008 #define CBC_BLEND_ZERO 0x00
1009 #define CBC_BLEND_ONE 0x01
1010 #define CBC_BLEND_SRC_COLOR 0x02
1011 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
1012 #define CBC_BLEND_SRC_ALPHA 0x04
1013 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
1014 #define CBC_BLEND_DST_ALPHA 0x06
1015 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
1016 #define CBC_BLEND_DST_COLOR 0x08
1017 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
1018 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
1019 #define CBC_BLEND_CONSTANT_COLOR 0x0d
1020 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
1021 #define CBC_BLEND_SRC_1_COLOR 0x0f
1022 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
1023 #define CBC_BLEND_SRC_1_ALPHA 0x11
1024 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
1025 #define CBC_BLEND_CONSTANT_ALPHA 0x13
1026 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
1027 #define CBC_COLOR_ALPHA_SRC_BLEND 0x001f0000
1028 #define CBC_BLEND_ZERO 0x00
1029 #define CBC_BLEND_ONE 0x01
1030 #define CBC_BLEND_SRC_COLOR 0x02
1031 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
1032 #define CBC_BLEND_SRC_ALPHA 0x04
1033 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
1034 #define CBC_BLEND_DST_ALPHA 0x06
1035 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
1036 #define CBC_BLEND_DST_COLOR 0x08
1037 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
1038 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
1039 #define CBC_BLEND_CONSTANT_COLOR 0x0d
1040 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
1041 #define CBC_BLEND_SRC_1_COLOR 0x0f
1042 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
1043 #define CBC_BLEND_SRC_1_ALPHA 0x11
1044 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
1045 #define CBC_BLEND_CONSTANT_ALPHA 0x13
1046 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
1047 #define CBC_ALPHA_COMB_FCN 0x00e00000
1048 #define CBC_COMB_DST_PLUS_SRC 0
1049 #define CBC_COMB_SRC_MINUS_DST 1
1050 #define CBC_COMB_MIN_DST_SRC 2
1051 #define CBC_COMB_MAX_DST_SRC 3
1052 #define CBC_COMB_DST_MINUS_SRC 4
1053 #define CBC_ALPHA_DST_BLEND 0x1f000000
1054 #define CBC_BLEND_ZERO 0x00
1055 #define CBC_BLEND_ONE 0x01
1056 #define CBC_BLEND_SRC_COLOR 0x02
1057 #define CBC_BLEND_ONE_MINUS_SRC_COLOR 0x03
1058 #define CBC_BLEND_SRC_ALPHA 0x04
1059 #define CBC_BLEND_ONE_MINUS_SRC_ALPHA 0x05
1060 #define CBC_BLEND_DST_ALPHA 0x06
1061 #define CBC_BLEND_ONE_MINUS_DST_ALPHA 0x07
1062 #define CBC_BLEND_DST_COLOR 0x08
1063 #define CBC_BLEND_ONE_MINUS_DST_COLOR 0x09
1064 #define CBC_BLEND_SRC_ALPHA_SATURATE 0x0a
1065 #define CBC_BLEND_CONSTANT_COLOR 0x0d
1066 #define CBC_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0e
1067 #define CBC_BLEND_SRC_1_COLOR 0x0f
1068 #define CBC_BLEND_INV_SRC_1_COLOR 0x10
1069 #define CBC_BLEND_SRC_1_ALPHA 0x11
1070 #define CBC_BLEND_INV_SRC_1_ALPHA 0x12
1071 #define CBC_BLEND_CONSTANT_ALPHA 0x13
1072 #define CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
1073 #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
1074 #define CBC_CB_BLEND_ENA BIT(30)
1075 #define CBC_ROP3_DIS BIT(31)
1076 #define CB_BLEND_7_CTL 0x2879c
265 #define PSRC_RB_MAP_3 3
266 #define PSRC_RB_MAP_PKR_1 0x0000000c
267 #define PSRC_RB_XSEL_2 0x00000030
268 #define PSRC_RB_XSEL_2_0 0
269 #define PSRC_RB_XSEL_2_1 1
270 #define PSRC_RB_XSEL_2_2 2
271 #define PSRC_RB_XSEL_2_3 3
272 #define PSRC_RB_XSEL BIT(6)
273 #define PSRC_RB_YSEL BIT(7)
274 #define PSRC_PKR_MAP 0x00000300
275 #define PSRC_PKR_MAP_0 0
276 #define PSRC_PKR_MAP_1 1
277 #define PSRC_PKR_MAP_2 2
278 #define PSRC_PKR_MAP_3 3
279 #define PSRC_PKR_XSEL 0x00000c00
280 #define PSRC_PKR_XSEL_0 0
281 #define PSRC_PKR_XSEL_1 1
282 #define PSRC_PKR_XSEL_2 2
283 #define PSRC_PKR_XSEL_3 3
284 #define PSRC_PKR_YSEL 0x00003000
285 #define PSRC_PKR_YSEL_0 0
286 #define PSRC_PKR_YSEL_1 1
287 #define PSRC_PKR_YSEL_2 2
288 #define PSRC_PKR_YSEL_3 3
289 #define PSRC_SC_MAP 0x00030000
290 #define PSRC_SC_MAP_0 0
291 #define PSRC_SC_MAP_1 1
292 #define PSRC_SC_MAP_2 2
293 #define PSRC_SC_MAP_3 3
294 #define PSRC_SC_XSEL 0x000c0000
295 #define PSRC_SC_XSEL_8_WIDE_TILE 0
296 #define PSRC_SC_XSEL_16_WIDE_TILE 1
297 #define PSRC_SC_XSEL_32_WIDE_TILE 2
298 #define PSRC_SC_XSEL_64_WIDE_TILE 3
299 #define PSRC_SC_YSEL 0x00300000
300 #define PSRC_SC_YSEL_8_WIDE_TILE 0
301 #define PSRC_SC_YSEL_16_WIDE_TILE 1
302 #define PSRC_SC_YSEL_32_WIDE_TILE 2
303 #define PSRC_SC_YSEL_64_WIDE_TILE 3
304 #define PSRC_SE_MAP 0x03000000
305 #define PSRC_SE_MAP_0 0
306 #define PSRC_SE_MAP_1 1
307 #define PSRC_SE_MAP_2 2
308 #define PSRC_SE_MAP_3 3
309 #define PSRC_SE_XSEL 0x0c000000
310 #define PSRC_SE_XSEL_8_WIDE_TILE 0
311 #define PSRC_SE_XSEL_16_WIDE_TILE 1
312 #define PSRC_SE_XSEL_32_WIDE_TILE 2
313 #define PSRC_SE_XSEL_64_WIDE_TILE 3
314 #define PSRC_SE_YSEL 0x30000000
315 #define PSRC_SE_YSEL_8_WIDE_TILE 0
316 #define PSRC_SE_YSEL_16_WIDE_TILE 1
317 #define PSRC_SE_YSEL_32_WIDE_TILE 2
318 #define PSRC_SE_YSEL_64_WIDE_TILE 3
319
320 #define CP_RING_ID 0x28364
321 #define CP_VM_ID 0x28368
322
323 #define VGT_MAX_VTX_IDX 0x28400
324 #define VGT_MIN_VTX_IDX 0x28404
325 #define VGT_IDX_OF 0x28408
326 #define VGT_MULTI_PRIM_IB_RESET_IDX 0x2840c
327
328 #define CB_BLEND_RED 0x28414
329 #define CB_BLEND_GREEN 0x28418
330 #define CB_BLEND_BLUE 0x2841c
331 #define CB_BLEND_ALPHA 0x28420
332
333 #define PA_SC_VPORT_0_TE_X_SCALE 0x2843c
334 #define PA_SC_VPORT_0_TE_X_OF 0x28440
335 #define PA_SC_VPORT_0_TE_Y_SCALE 0x2843c
336 #define PA_SC_VPORT_0_TE_Y_OF 0x28440
337 #define PA_SC_VPORT_0_TE_Z_SCALE 0x2843c
338 #define PA_SC_VPORT_0_TE_Z_OF 0x28440
339
340 #define SPI_INTERPOL_CTL_0 0x286d4
341 #define SIC_FLAT_SHADE_ENA BIT(0)
342 #define SIC_POINT_SPRITE_ENA BIT(1)
343 #define SIC_POINT_SPRITE_OVRD_X 0x0000001c
344 #define SIC_POINT_SPRITE_OVRD_SEL_0 0
345 #define SIC_POINT_SPRITE_OVRD_SEL_1 1
346 #define SIC_POINT_SPRITE_OVRD_SEL_S 2
347 #define SIC_POINT_SPRITE_OVRD_SEL_T 3
348 #define SIC_POINT_SPRITE_OVRD_SEL_NONE 4
349 #define SIC_POINT_SPRITE_OVRD_Y 0x000000e0
350 #define SIC_POINT_SPRITE_OVRD_Z 0x00000700
351 #define SIC_POINT_SPRITE_OVRD_W 0x00003800
352 #define SIC_POINT_SPRITE_TOP_1 BIT(14)
353
354 #define CB_0_BLEND_CTL 0x28780
1077 355 #define CBC_COLOR_SRC_BLEND 0x0000001f #define CBC_COLOR_SRC_BLEND 0x0000001f
1078 356 #define CBC_BLEND_ZERO 0x00 #define CBC_BLEND_ZERO 0x00
1079 357 #define CBC_BLEND_ONE 0x01 #define CBC_BLEND_ONE 0x01
 
1169 447 #define CBC_SEPARATE_ALPHA_BLEND BIT(29) #define CBC_SEPARATE_ALPHA_BLEND BIT(29)
1170 448 #define CBC_CB_BLEND_ENA BIT(30) #define CBC_CB_BLEND_ENA BIT(30)
1171 449 #define CBC_ROP3_DIS BIT(31) #define CBC_ROP3_DIS BIT(31)
450 #define CB_1_BLEND_CTL 0x28784
451 #define CB_2_BLEND_CTL 0x28788
452 #define CB_3_BLEND_CTL 0x2878c
453 #define CB_4_BLEND_CTL 0x28790
454 #define CB_5_BLEND_CTL 0x28794
455 #define CB_6_BLEND_CTL 0x28798
456 #define CB_7_BLEND_CTL 0x2879c
1172 457
1173 458 #define DB_DEPTH_CTL 0x28800 #define DB_DEPTH_CTL 0x28800
1174 459 #define DDC_STENCIL_ENA BIT(0) #define DDC_STENCIL_ENA BIT(0)
 
1195 480 #define DDC_STENCILFUNC_GEQUAL 6 #define DDC_STENCILFUNC_GEQUAL 6
1196 481 #define DDC_STENCILFUNC_ALWAYS 7 #define DDC_STENCILFUNC_ALWAYS 7
1197 482 #define DDC_STENCILFUNC_BF 0x00700000 #define DDC_STENCILFUNC_BF 0x00700000
1198 #define DDC_STENCILFUNC_NEVER 0
1199 #define DDC_STENCILFUNC_LESS 1
1200 #define DDC_STENCILFUNC_EQUAL 2
1201 #define DDC_STENCILFUNC_LEQUAL 3
1202 #define DDC_STENCILFUNC_GREATER 4
1203 #define DDC_STENCILFUNC_NOTEQUAL 5
1204 #define DDC_STENCILFUNC_GEQUAL 6
1205 #define DDC_STENCILFUNC_ALWAYS 7
1206 483 #define DDC_COLOR_WRITES_ON_DEPTH_FAIL_ENA BIT(30) #define DDC_COLOR_WRITES_ON_DEPTH_FAIL_ENA BIT(30)
1207 484 #define DDC_COLOR_WRITES_ON_DEPTH_PASS_DIS BIT(31) #define DDC_COLOR_WRITES_ON_DEPTH_PASS_DIS BIT(31)
1208 485 #define DB_EQAA 0x28804 #define DB_EQAA 0x28804
 
1297 574 #define PSSMC_PROVOKING_VTX_LAST BIT(19) #define PSSMC_PROVOKING_VTX_LAST BIT(19)
1298 575 #define PSSMC_PERSP_CORR_DIS BIT(20) #define PSSMC_PERSP_CORR_DIS BIT(20)
1299 576 #define PSSMC_MULTI_PRIM_IB_ENA BIT(21) #define PSSMC_MULTI_PRIM_IB_ENA BIT(21)
1300 #define PA_CL_VTE_CTL 0x28818
1301 #define PCVC_VPORT_X_SCALE_ENA BIT(0)
1302 #define PCVC_VPORT_X_OF_ENA BIT(1)
1303 #define PCVC_VPORT_Y_SCALE_ENA BIT(2)
1304 #define PCVC_VPORT_Y_OF_ENA BIT(3)
1305 #define PCVC_VPORT_Z_SCALE_ENA BIT(4)
1306 #define PCVC_VPORT_Z_OF_ENA BIT(5)
1307 #define PCVC_VTX_XY_FMT BIT(8)
1308 #define PCVC_VTX_Z_FMT BIT(9)
1309 #define PCVC_VTX_W0_FMT BIT(10)
577 #define PA_SC_VPORT_TE_CTL 0x28818
578 #define PSVTC_VPORT_X_SCALE_ENA BIT(0)
579 #define PSVTC_VPORT_X_OF_ENA BIT(1)
580 #define PSVTC_VPORT_Y_SCALE_ENA BIT(2)
581 #define PSVTC_VPORT_Y_OF_ENA BIT(3)
582 #define PSVTC_VPORT_Z_SCALE_ENA BIT(4)
583 #define PSVTC_VPORT_Z_OF_ENA BIT(5)
584 #define PSVTC_VTX_XY_FMT BIT(8)
585 #define PSVTC_VTX_Z_FMT BIT(9)
586 #define PSVTC_VTX_W0_FMT BIT(10)
1310 587 #define PA_CL_VS_OUT_CTL 0x2881c #define PA_CL_VS_OUT_CTL 0x2881c
1311 588 #define PCVOC_CLIP_DIST_ENA_0 BIT(0) #define PCVOC_CLIP_DIST_ENA_0 BIT(0)
1312 589 #define PCVOC_CLIP_DIST_ENA_1 BIT(1) #define PCVOC_CLIP_DIST_ENA_1 BIT(1)
 
1436 713 #define VGVC_STRIDE 0x0000ff00 #define VGVC_STRIDE 0x0000ff00
1437 714 #define VGVC_SHIFT 0x00ff0000 #define VGVC_SHIFT 0x00ff0000
1438 715 #define VGT_GROUP_VECT_1_CTL 0x28a34 #define VGT_GROUP_VECT_1_CTL 0x28a34
1439 #define VGVC_COMP_X_ENA BIT(0)
1440 #define VGVC_COMP_Y_ENA BIT(1)
1441 #define VGVC_COMP_Z_ENA BIT(2)
1442 #define VGVC_COMP_W_ENA BIT(3)
1443 #define VGVC_STRIDE 0x0000ff00
1444 #define VGVC_SHIFT 0x00ff0000
1445 716 #define VGT_GROUP_VECT_0_FMT_CTL 0x28a38 #define VGT_GROUP_VECT_0_FMT_CTL 0x28a38
1446 717 #define VGVFC_X_CONV 0x0000000f #define VGVFC_X_CONV 0x0000000f
1447 718 #define VGVFC_IDX_16 0 #define VGVFC_IDX_16 0
 
1455 726 #define VGVFC_FIX_1_23_TO_FLOAT 8 #define VGVFC_FIX_1_23_TO_FLOAT 8
1456 727 #define VGVFC_X_OF 0x000000f0 #define VGVFC_X_OF 0x000000f0
1457 728 #define VGVFC_Y_CONV 0x00000f00 #define VGVFC_Y_CONV 0x00000f00
1458 #define VGVFC_IDX_16 0
1459 #define VGVFC_IDX_32 1
1460 #define VGVFC_UINT16 2
1461 #define VGVFC_UINT32 3
1462 #define VGVFC_SINT16 4
1463 #define VGVFC_SINT32 5
1464 #define VGVFC_FLOAT32 6
1465 #define VGVFC_AUTO_PRIM 7
1466 #define VGVFC_FIX_1_23_TO_FLOAT 8
1467 729 #define VGVFC_Y_OF 0x0000f000 #define VGVFC_Y_OF 0x0000f000
1468 730 #define VGVFC_Z_CONV 0x000f0000 #define VGVFC_Z_CONV 0x000f0000
1469 #define VGVFC_IDX_16 0
1470 #define VGVFC_IDX_32 1
1471 #define VGVFC_UINT16 2
1472 #define VGVFC_UINT32 3
1473 #define VGVFC_SINT16 4
1474 #define VGVFC_SINT32 5
1475 #define VGVFC_FLOAT32 6
1476 #define VGVFC_AUTO_PRIM 7
1477 #define VGVFC_FIX_1_23_TO_FLOAT 8
1478 731 #define VGVFC_Z_OF 0x00f00000 #define VGVFC_Z_OF 0x00f00000
1479 732 #define VGVFC_W_CONV 0x0f000000 #define VGVFC_W_CONV 0x0f000000
1480 #define VGVFC_IDX_16 0
1481 #define VGVFC_IDX_32 1
1482 #define VGVFC_UINT16 2
1483 #define VGVFC_UINT32 3
1484 #define VGVFC_SINT16 4
1485 #define VGVFC_SINT32 5
1486 #define VGVFC_FLOAT32 6
1487 #define VGVFC_AUTO_PRIM 7
1488 #define VGVFC_FIX_1_23_TO_FLOAT 8
1489 733 #define VGVFC_W_OF 0xf0000000 #define VGVFC_W_OF 0xf0000000
1490 734 #define VGT_GROUP_VECT_1_FMT_CTL 0x28a3c #define VGT_GROUP_VECT_1_FMT_CTL 0x28a3c
1491 #define VGVFC_X_CONV 0x0000000f
1492 #define VGVFC_IDX_16 0
1493 #define VGVFC_IDX_32 1
1494 #define VGVFC_UINT16 2
1495 #define VGVFC_UINT32 3
1496 #define VGVFC_SINT16 4
1497 #define VGVFC_SINT32 5
1498 #define VGVFC_FLOAT32 6
1499 #define VGVFC_AUTO_PRIM 7
1500 #define VGVFC_FIX_1_23_TO_FLOAT 8
1501 #define VGVFC_X_OF 0x000000f0
1502 #define VGVFC_Y_CONV 0x00000f00
1503 #define VGVFC_IDX_16 0
1504 #define VGVFC_IDX_32 1
1505 #define VGVFC_UINT16 2
1506 #define VGVFC_UINT32 3
1507 #define VGVFC_SINT16 4
1508 #define VGVFC_SINT32 5
1509 #define VGVFC_FLOAT32 6
1510 #define VGVFC_AUTO_PRIM 7
1511 #define VGVFC_FIX_1_23_TO_FLOAT 8
1512 #define VGVFC_Y_OF 0x0000f000
1513 #define VGVFC_Z_CONV 0x000f0000
1514 #define VGVFC_IDX_16 0
1515 #define VGVFC_IDX_32 1
1516 #define VGVFC_UINT16 2
1517 #define VGVFC_UINT32 3
1518 #define VGVFC_SINT16 4
1519 #define VGVFC_SINT32 5
1520 #define VGVFC_FLOAT32 6
1521 #define VGVFC_AUTO_PRIM 7
1522 #define VGVFC_FIX_1_23_TO_FLOAT 8
1523 #define VGVFC_Z_OF 0x00f00000
1524 #define VGVFC_W_CONV 0x0f000000
1525 #define VGVFC_IDX_16 0
1526 #define VGVFC_IDX_32 1
1527 #define VGVFC_UINT16 2
1528 #define VGVFC_UINT32 3
1529 #define VGVFC_SINT16 4
1530 #define VGVFC_SINT32 5
1531 #define VGVFC_FLOAT32 6
1532 #define VGVFC_AUTO_PRIM 7
1533 #define VGVFC_FIX_1_23_TO_FLOAT 8
1534 #define VGVFC_W_OF 0xf0000000
1535 735 #define VGT_GS_MODE 0x28a40 #define VGT_GS_MODE 0x28a40
1536 736 #define VGS_MODE 0x00000003 #define VGS_MODE 0x00000003
1537 737 #define VGS_OFF 0 #define VGS_OFF 0
 
1586 786 #define VPIE_PRIM_ID_ENA BIT(0) #define VPIE_PRIM_ID_ENA BIT(0)
1587 787 #define VPIE_RESET_ON_EOI_DIS BIT(1) #define VPIE_RESET_ON_EOI_DIS BIT(1)
1588 788
789 #define VGT_PRIM_ID_RESET 0x28a8c
790
1589 791 #define VGT_MULTI_PRIM_IB_RESET_ENA 0x28a94 #define VGT_MULTI_PRIM_IB_RESET_ENA 0x28a94
1590 792 #define VMPIRE_RESET_ENA BIT(0) #define VMPIRE_RESET_ENA BIT(0)
1591 793
1592 794 #define VGT_INST_STEP_RATE_0 0x28aa0 #define VGT_INST_STEP_RATE_0 0x28aa0
1593 795 #define VGT_INST_STEP_RATE_1 0x28aa4 #define VGT_INST_STEP_RATE_1 0x28aa4
796 #define IA_MULTI_VGT_PARAM 0x28aa8
797 #define IMVP_PRIM_GROUP_SZ 0x0000ffff
798 #define IMVP_PARTIAL_VS_WAVE_ON BIT(16)
799 #define IMVP_SWITCH_ON_EOP BIT(17)
800 #define IMVP_PARTIAL_ES_WAVE_ON BIT(18)
801 #define IMVP_SWITCH_ON_EOI BIT(19)
1594 802
1595 803 #define VGT_REUSE_OFF 0x28ab4 #define VGT_REUSE_OFF 0x28ab4
1596 804 #define VRO_OFF BIT(0) #define VRO_OFF BIT(0)
 
1702 910 #define PSASLPX_S_2_X 0x000f0000 #define PSASLPX_S_2_X 0x000f0000
1703 911 #define PSASLPX_S_2_Y 0x00f00000 #define PSASLPX_S_2_Y 0x00f00000
1704 912 #define PSASLPX_S_3_X 0x0f000000 #define PSASLPX_S_3_X 0x0f000000
1705 #define PSASLPX_S_3_Y 0x70000000
913 #define PSASLPX_S_3_Y 0xf0000000
1706 914 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x28bfc #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x28bfc
1707 915 #define PSASLPX_S_4_X 0x0000000f #define PSASLPX_S_4_X 0x0000000f
1708 916 #define PSASLPX_S_4_Y 0x000000f0 #define PSASLPX_S_4_Y 0x000000f0
 
1711 919 #define PSASLPX_S_6_X 0x000f0000 #define PSASLPX_S_6_X 0x000f0000
1712 920 #define PSASLPX_S_6_Y 0x00f00000 #define PSASLPX_S_6_Y 0x00f00000
1713 921 #define PSASLPX_S_7_X 0x0f000000 #define PSASLPX_S_7_X 0x0f000000
1714 #define PSASLPX_S_7_Y 0x70000000
922 #define PSASLPX_S_7_Y 0xf0000000
1715 923 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x28c00 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x28c00
1716 924 #define PSASLPX_S_8_X 0x0000000f #define PSASLPX_S_8_X 0x0000000f
1717 925 #define PSASLPX_S_8_Y 0x000000f0 #define PSASLPX_S_8_Y 0x000000f0
 
1720 928 #define PSASLPX_S_A_X 0x000f0000 #define PSASLPX_S_A_X 0x000f0000
1721 929 #define PSASLPX_S_A_Y 0x00f00000 #define PSASLPX_S_A_Y 0x00f00000
1722 930 #define PSASLPX_S_B_X 0x0f000000 #define PSASLPX_S_B_X 0x0f000000
1723 #define PSASLPX_S_B_Y 0x70000000
931 #define PSASLPX_S_B_Y 0xf0000000
1724 932 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x28c04 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x28c04
1725 933 #define PSASLPX_S_C_X 0x0000000f #define PSASLPX_S_C_X 0x0000000f
1726 934 #define PSASLPX_S_C_Y 0x000000f0 #define PSASLPX_S_C_Y 0x000000f0
 
1729 937 #define PSASLPX_S_E_X 0x000f0000 #define PSASLPX_S_E_X 0x000f0000
1730 938 #define PSASLPX_S_E_Y 0x00f00000 #define PSASLPX_S_E_Y 0x00f00000
1731 939 #define PSASLPX_S_F_X 0x0f000000 #define PSASLPX_S_F_X 0x0f000000
1732 #define PSASLPX_S_F_Y 0x70000000
940 #define PSASLPX_S_F_Y 0xf0000000
1733 941 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
1734 #define PSASLPX_S_0_X 0x0000000f
1735 #define PSASLPX_S_0_Y 0x000000f0
1736 #define PSASLPX_S_1_X 0x00000f00
1737 #define PSASLPX_S_1_Y 0x0000f000
1738 #define PSASLPX_S_2_X 0x000f0000
1739 #define PSASLPX_S_2_Y 0x00f00000
1740 #define PSASLPX_S_3_X 0x0f000000
1741 #define PSASLPX_S_3_Y 0x70000000
1742 942 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x28c0c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x28c0c
1743 #define PSASLPX_S_4_X 0x0000000f
1744 #define PSASLPX_S_4_Y 0x000000f0
1745 #define PSASLPX_S_5_X 0x00000f00
1746 #define PSASLPX_S_5_Y 0x0000f000
1747 #define PSASLPX_S_6_X 0x000f0000
1748 #define PSASLPX_S_6_Y 0x00f00000
1749 #define PSASLPX_S_7_X 0x0f000000
1750 #define PSASLPX_S_7_Y 0x70000000
1751 943 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x28c10 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x28c10
1752 #define PSASLPX_S_8_X 0x0000000f
1753 #define PSASLPX_S_8_Y 0x000000f0
1754 #define PSASLPX_S_9_X 0x00000f00
1755 #define PSASLPX_S_9_Y 0x0000f000
1756 #define PSASLPX_S_A_X 0x000f0000
1757 #define PSASLPX_S_A_Y 0x00f00000
1758 #define PSASLPX_S_B_X 0x0f000000
1759 #define PSASLPX_S_B_Y 0x70000000
1760 944 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x28c14 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x28c14
1761 #define PSASLPX_S_C_X 0x0000000f
1762 #define PSASLPX_S_C_Y 0x000000f0
1763 #define PSASLPX_S_D_X 0x00000f00
1764 #define PSASLPX_S_D_Y 0x0000f000
1765 #define PSASLPX_S_E_X 0x000f0000
1766 #define PSASLPX_S_E_Y 0x00f00000
1767 #define PSASLPX_S_F_X 0x0f000000
1768 #define PSASLPX_S_F_Y 0x70000000
1769 945 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
1770 #define PSASLPX_S_0_X 0x0000000f
1771 #define PSASLPX_S_0_Y 0x000000f0
1772 #define PSASLPX_S_1_X 0x00000f00
1773 #define PSASLPX_S_1_Y 0x0000f000
1774 #define PSASLPX_S_2_X 0x000f0000
1775 #define PSASLPX_S_2_Y 0x00f00000
1776 #define PSASLPX_S_3_X 0x0f000000
1777 #define PSASLPX_S_3_Y 0x70000000
1778 946 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x28c1c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x28c1c
1779 #define PSASLPX_S_4_X 0x0000000f
1780 #define PSASLPX_S_4_Y 0x000000f0
1781 #define PSASLPX_S_5_X 0x00000f00
1782 #define PSASLPX_S_5_Y 0x0000f000
1783 #define PSASLPX_S_6_X 0x000f0000
1784 #define PSASLPX_S_6_Y 0x00f00000
1785 #define PSASLPX_S_7_X 0x0f000000
1786 #define PSASLPX_S_7_Y 0x70000000
1787 947 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x28c20 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x28c20
1788 #define PSASLPX_S_8_X 0x0000000f
1789 #define PSASLPX_S_8_Y 0x000000f0
1790 #define PSASLPX_S_9_X 0x00000f00
1791 #define PSASLPX_S_9_Y 0x0000f000
1792 #define PSASLPX_S_A_X 0x000f0000
1793 #define PSASLPX_S_A_Y 0x00f00000
1794 #define PSASLPX_S_B_X 0x0f000000
1795 #define PSASLPX_S_B_Y 0x70000000
1796 948 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x28c24 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x28c24
1797 #define PSASLPX_S_C_X 0x0000000f
1798 #define PSASLPX_S_C_Y 0x000000f0
1799 #define PSASLPX_S_D_X 0x00000f00
1800 #define PSASLPX_S_D_Y 0x0000f000
1801 #define PSASLPX_S_E_X 0x000f0000
1802 #define PSASLPX_S_E_Y 0x00f00000
1803 #define PSASLPX_S_F_X 0x0f000000
1804 #define PSASLPX_S_F_Y 0x70000000
1805 949 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
1806 #define PSASLPX_S_0_X 0x0000000f
1807 #define PSASLPX_S_0_Y 0x000000f0
1808 #define PSASLPX_S_1_X 0x00000f00
1809 #define PSASLPX_S_1_Y 0x0000f000
1810 #define PSASLPX_S_2_X 0x000f0000
1811 #define PSASLPX_S_2_Y 0x00f00000
1812 #define PSASLPX_S_3_X 0x0f000000
1813 #define PSASLPX_S_3_Y 0x70000000
1814 950 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x28c2c #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x28c2c
1815 #define PSASLPX_S_4_X 0x0000000f
1816 #define PSASLPX_S_4_Y 0x000000f0
1817 #define PSASLPX_S_5_X 0x00000f00
1818 #define PSASLPX_S_5_Y 0x0000f000
1819 #define PSASLPX_S_6_X 0x000f0000
1820 #define PSASLPX_S_6_Y 0x00f00000
1821 #define PSASLPX_S_7_X 0x0f000000
1822 #define PSASLPX_S_7_Y 0x70000000
1823 951 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x28c30 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x28c30
1824 #define PSASLPX_S_8_X 0x0000000f
1825 #define PSASLPX_S_8_Y 0x000000f0
1826 #define PSASLPX_S_9_X 0x00000f00
1827 #define PSASLPX_S_9_Y 0x0000f000
1828 #define PSASLPX_S_A_X 0x000f0000
1829 #define PSASLPX_S_A_Y 0x00f00000
1830 #define PSASLPX_S_B_X 0x0f000000
1831 #define PSASLPX_S_B_Y 0x70000000
1832 952 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x28c34 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x28c34
1833 #define PSASLPX_S_C_X 0x0000000f
1834 #define PSASLPX_S_C_Y 0x000000f0
1835 #define PSASLPX_S_D_X 0x00000f00
1836 #define PSASLPX_S_D_Y 0x0000f000
1837 #define PSASLPX_S_E_X 0x000f0000
1838 #define PSASLPX_S_E_Y 0x00f00000
1839 #define PSASLPX_S_F_X 0x0f000000
1840 #define PSASLPX_S_F_Y 0x70000000
1841 953 #define PA_SC_AA_MASK_X0Y0_X1Y0 0x28c38 #define PA_SC_AA_MASK_X0Y0_X1Y0 0x28c38
1842 954 #define PSAMXX_AA_MASK_X0Y0 0x0000ffff #define PSAMXX_AA_MASK_X0Y0 0x0000ffff
1843 955 #define PSAMXX_AA_MASK_X1Y0 0xffff0000 #define PSAMXX_AA_MASK_X1Y0 0xffff0000
 
1849 961 #define VVRBC_VTX_REUSE_DEPTH 0x000000ff #define VVRBC_VTX_REUSE_DEPTH 0x000000ff
1850 962 #define VGT_OUT_DEALLOC_CTL 0x28c5c #define VGT_OUT_DEALLOC_CTL 0x28c5c
1851 963 #define VODC_DEALLOC_DIST 0x0000007f #define VODC_DEALLOC_DIST 0x0000007f
964 #define CB_0_COLOR_BASE 0x28c60
965 #define CB_0_COLOR_PITCH 0x28c64
966 #define CCP_TILE_MAX 0x000007ff
967 #define CB_0_COLOR_SLICE 0x28c68
968 #define CCS_TILE_MAX 0x003fffff
969 #define CB_0_COLOR_VIEW 0x28c6c
970 #define CCV_SLICE_START 0x000007ff
971 #define CCV_SLICE_MAX 0x00ffe000
972 #define CB_0_COLOR_INFO 0x28c70
973 #define CCI_ENDIAN 0x00000003
974 #define CCI_ENDIAN_NONE 0
975 #define CCI_ENDIAN_8IN16 1
976 #define CCI_ENDIAN_8IN32 2
977 #define CCI_ENDIAN_8IN64 3
978 #define CCI_FMT 0x0000007c
979 #define CCI_COLOR_INVALID 0
980 #define CCI_COLOR_8 1
981 #define CCI_COLOR_16 2
982 #define CCI_COLOR_8_8 3
983 #define CCI_COLOR_32 4
984 #define CCI_COLOR_16_16 5
985 #define CCI_COLOR_10_11_11 6
986 #define CCI_COLOR_11_11_10 7
987 #define CCI_COLOR_10_10_10_2 8
988 #define CCI_COLOR_2_10_10_10 9
989 #define CCI_COLOR_8_8_8_8 10
990 #define CCI_COLOR_32_32 11
991 #define CCI_COLOR_16_16_16_16 12
992 #define CCI_COLOR_32_32_32_32 14
993 #define CCI_COLOR_5_6_5 16
994 #define CCI_COLOR_1_5_5_5 17
995 #define CCI_COLOR_5_5_5_1 18
996 #define CCI_COLOR_4_4_4_4 19
997 #define CCI_COLOR_8_24 20
998 #define CCI_COLOR_24_8 21
999 #define CCI_COLOR_X24_8_32_FLOAT 22
1000 #define CCI_LINEAR_GENERAL BIT(7)
1001 #define CCI_NUMBER_TYPE 0x00000700
1002 #define CCI_NUMBER_UNORM 0
1003 #define CCI_NUMBER_SNORM 1
1004 #define CCI_NUMBER_UINT 4
1005 #define CCI_NUMBER_SINT 5
1006 #define CCI_NUMBER_SRGB 6
1007 #define CCI_NUMBER_FLOAT 7
1008 #define CCI_COMP_SWAP 0x00001800
1009 #define CCI_SWAP_STD 0
1010 #define CCI_SWAP_ALT 1
1011 #define CCI_SWAP_STD_REV 2
1012 #define CCI_SWAP_ALT_REV 3
1013 #define CCI_FAST_CLR BIT(13)
1014 #define CCI_COMPRESSION BIT(14)
1015 #define CCI_BLEND_CLAMP BIT(15)
1016 #define CCI_BLEND_BYPASS BIT(16)
1017 #define CCI_SIMPLE_FLOAT BIT(17)
1018 #define CCI_ROUND_MODE BIT(18)
1019 #define CCI_CMASK_IS_LINEAR BIT(19)
1020 #define CCI_BLEND_OPT_DONT_RD_DST 0x00700000
1021 #define CCI_FORCE_OPT_AUTO 0
1022 #define CCI_FORCE_OPT_DIS 1
1023 #define CCI_FORCE_OPT_ENA_IF_SRC_A_0 2
1024 #define CCI_FORCE_OPT_ENA_IF_SRC_RGB_0 3
1025 #define CCI_FORCE_OPT_ENA_IF_SRC_ARGB_0 4
1026 #define CCI_FORCE_OPT_ENA_IF_SRC_A_1 5
1027 #define CCI_FORCE_OPT_ENA_IF_SRC_RGB_1 6
1028 #define CCI_FORCE_OPT_ENA_IF_SRC_ARGB_1 7
1029 #define CCI_BLEND_OPT_DISCARD_PIXEL 0x01800000
1030 #define CCI_FORCE_OPT_AUTO 0
1031 #define CCI_FORCE_OPT_DIS 1
1032 #define CCI_FORCE_OPT_ENA_IF_SRC_A_0 2
1033 #define CCI_FORCE_OPT_ENA_IF_SRC_RGB_0 3
1034 #define CCI_FORCE_OPT_ENA_IF_SRC_ARGB_0 4
1035 #define CCI_FORCE_OPT_ENA_IF_SRC_A_1 5
1036 #define CCI_FORCE_OPT_ENA_IF_SRC_RGB_1 6
1037 #define CCI_FORCE_OPT_ENA_IF_SRC_ARGB_1 7
1038 #define CB_0_COLOR_ATTRIB 0x28c74
1039 #define CCA_TILE_MODE_IDX 0x0000001f
1040 #define CCA_FMASK_TILE_MODE_IDX 0x000003e0
1041 #define CCA_SAMPLES_N 0x00007000
1042 #define CCA_FRAGMENTS_N 0x00018000
1043 #define CCA_FORCE_DST_ALPHA_1 BIT(17)
1044
1045 #define CB_0_COLOR_CMASK 0x28c7c
1046 #define CCC_TILE_MAX 0x00003fff
1047 #define CB_0_COLOR_FMASK 0x28c84
1048 #define CB_0_COLOR_FMASK_SLICE 0x28c88
1049 #define CCFS_TILE_MAX 0x003fffff
1050
1051 #define CB_0_COLOR_CLR_WORD_0 0x28c8c
1052 #define CB_0_COLOR_CLR_WORD_1 0x28c90
1053
1054 #define CB_1_COLOR_BASE 0x28c9c
1055 #define CB_1_COLOR_PITCH 0x28ca0
1056 #define CB_1_COLOR_SLICE 0x28ca4
1057 #define CB_1_COLOR_VIEW 0x28ca8
1058 #define CB_1_COLOR_INFO 0x28cac
1059 #define CB_1_COLOR_ATTRIB 0x28cb0
1060
1061 #define CB_1_COLOR_CMASK 0x28cb8
1062 #define CB_1_COLOR_CMASK_SLICE 0x28cbc
1063 #define CB_1_COLOR_FMASK 0x28cc0
1064 #define CB_1_COLOR_FMASK_SLICE 0x28cc4
1065 #define CB_1_COLOR_CLR_WORD_0 0x28cc8
1066 #define CB_1_COLOR_CLR_WORD_1 0x28ccc
1067
1068 #define CB_2_COLOR_BASE 0x28cd8
1069 #define CB_2_COLOR_PITCH 0x28cdc
1070 #define CB_2_COLOR_SLICE 0x28ce0
1071 #define CB_2_COLOR_VIEW 0x28ce4
1072 #define CB_2_COLOR_INFO 0x28ce8
1073 #define CB_2_COLOR_ATTRIB 0x28cec
1074
1075 #define CB_2_COLOR_CMASK 0x28cf4
1076 #define CB_2_COLOR_CMASK_SLICE 0x28cf8
1077 #define CB_2_COLOR_FMASK 0x28cfc
1078 #define CB_2_COLOR_FMASK_SLICE 0x28d00
1079 #define CB_2_COLOR_CLR_WORD_0 0x28d04
1080 #define CB_2_COLOR_CLR_WORD_1 0x28d08
1081
1082 #define CB_3_COLOR_BASE 0x28d14
1083 #define CB_3_COLOR_PITCH 0x28d18
1084 #define CB_3_COLOR_SLICE 0x28d1c
1085 #define CB_3_COLOR_VIEW 0x28d20
1086 #define CB_3_COLOR_INFO 0x28d24
1087 #define CB_3_COLOR_ATTRIB 0x28d28
1088
1089 #define CB_3_COLOR_CMASK 0x28d30
1090 #define CB_3_COLOR_CMASK_SLICE 0x28d34
1091 #define CB_3_COLOR_FMASK 0x28d38
1092 #define CB_3_COLOR_FMASK_SLICE 0x28d3c
1093 #define CB_3_COLOR_CLR_WORD_0 0x28d40
1094 #define CB_3_COLOR_CLR_WORD_1 0x28d44
1095
1096 #define CB_4_COLOR_BASE 0x28d50
1097 #define CB_4_COLOR_PITCH 0x28d54
1098 #define CB_4_COLOR_SLICE 0x28d58
1099 #define CB_4_COLOR_VIEW 0x28d5c
1100 #define CB_4_COLOR_INFO 0x28d60
1101 #define CB_4_COLOR_ATTRIB 0x28d64
1102
1103 #define CB_4_COLOR_CMASK 0x28d6c
1104 #define CB_4_COLOR_CMASK_SLICE 0x28d70
1105 #define CB_4_COLOR_FMASK 0x28d74
1106 #define CB_4_COLOR_FMASK_SLICE 0x28d78
1107 #define CB_4_COLOR_CLR_WORD_0 0x28d7c
1108 #define CB_4_COLOR_CLR_WORD_1 0x28d80
1109
1110 #define CB_5_COLOR_BASE 0x28d8c
1111 #define CB_5_COLOR_PITCH 0x28d90
1112 #define CB_5_COLOR_SLICE 0x28d94
1113 #define CB_5_COLOR_VIEW 0x28d98
1114 #define CB_5_COLOR_INFO 0x28d9c
1115 #define CB_5_COLOR_ATTRIB 0x28da0
1116
1117 #define CB_5_COLOR_CMASK 0x28da8
1118 #define CB_5_COLOR_CMASK_SLICE 0x28dac
1119 #define CB_5_COLOR_FMASK 0x28db0
1120 #define CB_5_COLOR_FMASK_SLICE 0x28db4
1121 #define CB_5_COLOR_CLR_WORD_0 0x28db8
1122 #define CB_5_COLOR_CLR_WORD_1 0x28dbc
1123
1124 #define CB_6_COLOR_BASE 0x28dc8
1125 #define CB_6_COLOR_PITCH 0x28dcc
1126 #define CB_6_COLOR_SLICE 0x28dd0
1127 #define CB_6_COLOR_VIEW 0x28dd4
1128 #define CB_6_COLOR_INFO 0x28dd8
1129 #define CB_6_COLOR_ATTRIB 0x28ddc
1130
1131 #define CB_6_COLOR_CMASK 0x28de4
1132 #define CB_6_COLOR_CMASK_SLICE 0x28de8
1133 #define CB_6_COLOR_FMASK 0x28dec
1134 #define CB_6_COLOR_FMASK_SLICE 0x28df0
1135 #define CB_6_COLOR_CLR_WORD_0 0x28df4
1136 #define CB_6_COLOR_CLR_WORD_1 0x28df8
1137
1138 #define CB_7_COLOR_BASE 0x28e04
1139 #define CB_7_COLOR_PITCH 0x28e08
1140 #define CB_7_COLOR_SLICE 0x28e0c
1141 #define CB_7_COLOR_VIEW 0x28e10
1142 #define CB_7_COLOR_INFO 0x28e14
1143 #define CB_7_COLOR_ATTRIB 0x28e18
1144
1145 #define CB_7_COLOR_CMASK 0x28e20
1146 #define CB_7_COLOR_CMASK_SLICE 0x28e24
1147 #define CB_7_COLOR_FMASK 0x28e28
1148 #define CB_7_COLOR_FMASK_SLICE 0x28e2c
1149 #define CB_7_COLOR_CLR_WORD_0 0x28e30
1150 #define CB_7_COLOR_CLR_WORD_1 0x28e34
1852 1151 #endif #endif
File drivers/gpu/alga/amd/si/patterns/tri.c changed (mode: 100644) (index 2b4b6a3..8977945)
24 24 #include "gpu/gpu.h" #include "gpu/gpu.h"
25 25 #include "drv.h" #include "drv.h"
26 26
27 struct vertex {
28 float position[4];
29 float color[4];
30 };
31
32 static struct vertex vertices[3] = {
33 {
34 { 0.0f, -0.9f, 0.0f, 1.0f },
35 { 1.0f, 0.0f, 0.0f, 1.0f }
36 },
37 {
38 { -0.9f, 0.9f, 0.0f, 1.0f },
39 { 0.0f, 1.0f, 0.0f, 1.0f }
40 },
41 {
42 { 0.9f, 0.9f, 0.0f, 1.0f },
43 { 0.0f, 0.0f, 1.0f, 1.0f }
44 }
45 };
46
47 static void spi(struct pci_dev *dev)
48 {
49 /* SPI (Shader Processor Interpolator) */
50 /* disable the point primitive sprite */
51 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
52 cp0_wr(dev, CTX_REG_IDX(SPI_INTERPOL_CTL_0));
53 /* SPI_INTERPOL_CTL_0 */
54 cp0_wr(dev, 0);
55 }
56
57 static void dbs(struct pci_dev *dev)
58 {
59 /* DBs (Depth Blocks) */
60 /* disable the depth stencil/z-buffer */
61 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
62 cp0_wr(dev, CTX_REG_IDX(DB_Z_INFO));
63 /* DB_Z_INFO */
64 cp0_wr(dev, 0);
65 /* DB_STENCIL_INFO */
66 cp0_wr(dev, 0);
67 }
68
69 static void cb_0(struct pci_dev *dev, struct ptn_tri *p)
70 {
71 /* CB 0 (Color Block 0) */
72 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
73 cp0_wr(dev, CTX_REG_IDX(CB_0_BLEND_CTL));
74 /* CB_0_BLEND_0_CTL: disable blending */
75 cp0_wr(dev, 0);
76
77 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 7));
78 cp0_wr(dev, CTX_REG_IDX(CB_0_COLOR_BASE));
79 /* CB_0_COLOR_BASE */
80 cp0_wr(dev, p->fb_gpu_addr >> 8);
81 /* CB_0_COLOR_PITCH: a thin1 tile is 8x8 pixels */
82 cp0_wr(dev, set(CCP_TILE_MAX, p->w / 8 - 1));
83 /* CB_0_COLOR_SLICE: a thin1 tile is 8x8 pixels */
84 cp0_wr(dev, set(CCS_TILE_MAX, p->w * p->h / 64 - 1));
85 /* CB_0_COLOR_VIEW: 0, or last tile index for an array of slices */
86 cp0_wr(dev, 0);
87 /* CB_0_COLOR_INFO */
88 cp0_wr(dev, set(CCI_ENDIAN, CCI_ENDIAN_NONE)
89 | set(CCI_FMT, CCI_COLOR_8_8_8_8)
90 | set(CCI_COMP_SWAP, CCI_SWAP_STD)
91 | set(CCI_NUMBER_TYPE, CCI_NUMBER_UINT)
92 | CCI_BLEND_BYPASS);
93 /* CB_0_COLOR_ATTRIB: see gpu/tiling.c */
94 cp0_wr(dev, set(CCA_TILE_MODE_IDX, 8));
95 }
96
97 static void cbs(struct pci_dev *dev, struct ptn_tri *p)
98 {
99 /* CBs (Color Blocks) */
100 cb_0(dev, p);
101
102 /*
103 * do enable all color components (RGBA) from the pixel/fragment shader
104 * to be used by the CB 0 and do enable CB 0 to output all computed
105 * color components to target (here our framebuffer)
106 */
107 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
108 cp0_wr(dev, CTX_REG_IDX(CB_TGT_MASK));
109 /* CB_TGT_MASK */
110 cp0_wr(dev, set(CTM_TGT_0_ENA, CTM_TGT_RED | CTM_TGT_GREEN
111 | CTM_TGT_BLUE | CTM_TGT_ALPHA));
112 /* CB_SHADER_MASK */
113 cp0_wr(dev, set(CSM_OUTPUT_0_ENA, CSM_OUTPUT_RED | CSM_OUTPUT_GREEN
114 | CSM_OUTPUT_BLUE | CSM_OUTPUT_ALPHA));
115
116 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
117 cp0_wr(dev, CTX_REG_IDX(CB_COLOR_CTL));
118 /* CB_COLOR_CTL: switch normal mode for all CBs */
119 cp0_wr(dev, set(CCC_MODE, CCC_CB_NORMAL) | set(CCC_ROP3, CCC_0XCC));
120 }
121
122 static void pa_su(struct pci_dev *dev)
123 {
124 /* PA (Primitive Assembler) SU (Setup Unit) */
125 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
126 cp0_wr(dev, CTX_REG_IDX(PA_SU_VTX_CTL));
127 /*
128 * PA_SU_VTX_CTL: tells the PA (Primitive Assembler) SU (Setup Unit)
129 * to place the(?) pixel at the center of the vertex?
130 */
131 cp0_wr(dev, PSVC_PIX_CENTER);
132
133 /*
134 * setup for the PA (Primitive Assembler) SU (Setup Unit) for the
135 * point/line primitive rendering: we do not render point
136 * or line primitives.
137 */
138 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 4));
139 cp0_wr(dev, CTX_REG_IDX(PA_SU_POINT_SZ));
140 /* PA_SU_POINT_SZ */
141 cp0_wr(dev, 0);
142 /* PA_SU_POINT_MINMAX */
143 cp0_wr(dev, 0);
144 /* PA_SU_LINE_CTL */
145 cp0_wr(dev, 0);
146
147 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
148 cp0_wr(dev, CTX_REG_IDX(PA_SU_POLY_OF_CLAMP));
149 /*
150 * PA_SU_POLY_OF_CLAMP: tell the PA (Primitive Assembler) SU
151 * (Setup Unit) for polygon not to clamp something ?
152 */
153 cp0_wr(dev, 0);
154 }
155
156 static void pa_cl(struct pci_dev *dev)
157 {
158 /* PA (Primitive Assembler) CL (CLipper) */
159 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 5));
160 cp0_wr(dev, CTX_REG_IDX(PA_CL_GB_VERT_CLIP_ADJ));
161 /* disable GB (Guard Band) by setting those registers to 1.0f */
162 /* PA_CL_GB_VERT_CLIP_ADJ */
163 cp0_wr(dev, f2u(1.0f));
164 /* PA_CL_GB_VERT_DISC_ADJ */
165 cp0_wr(dev, f2u(1.0f));
166 /* PA_CL_GB_HORZ_CLIP_ADJ */
167 cp0_wr(dev, f2u(1.0f));
168 /* PA_CL_GB_HORZ_DISC_ADJ */
169 cp0_wr(dev, f2u(1.0f));
170
171 /*
172 * define the way the PA (Primitive Assembler) CL (CLipper) will
173 * behave regarding NAN (Not A Number) and INF (INFinity) values
174 */
175 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
176 cp0_wr(dev, CTX_REG_IDX(PA_CL_NANINF_CTL));
177 /* PA_CL_NANINF_CTL: to hardware default behaviour */
178 cp0_wr(dev, 0);
179 }
180
181 static void pa_sc_vport_0_te(struct pci_dev *dev, struct ptn_tri *p)
182 {
183 float near;
184 float far;
185
186 /* need for the sample to run */
187 near = 30.0f;
188 far = 1000.0f;
189
190 /*
191 * PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) 0 TE
192 * (Transform Engine)
193 */
194 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 7));
195 cp0_wr(dev, CTX_REG_IDX(PA_SC_VPORT_0_TE_X_SCALE));
196 /* PA_SC_VPORT_0_TE_SCALE */
197 cp0_wr(dev, f2u(p->w / 2.0f));
198 /* PA_SC_VPORT_0_TE_X_OF */
199 cp0_wr(dev, f2u(p->w / 2.0f));
200 /* PA_SC_VPORT_0_TE_Y_SCALE */
201 cp0_wr(dev, f2u(p->h / 2.0f));
202 /* PA_SC_VPORT_0_TE_Y_OF */
203 cp0_wr(dev, f2u(p->h / 2.0f));
204 /* PA_SC_VPORT_0_TE_Z_SCALE */
205 cp0_wr(dev, f2u((far - near) / 2.0f));
206 /* PA_SC_VPORT_0_TE_Z_OF */
207 cp0_wr(dev, f2u((far - near) / 2.0f + near));
208
209 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
210 cp0_wr(dev, CTX_REG_IDX(PA_SC_VPORT_0_TE_ZMIN));
211 /* PA_SC_VPORT_0_TE_ZMIN: min Z value from VPORT TE */
212 cp0_wr(dev, 0);
213 /* PA_SC_VPORT_0_TE_ZMAX: max Z value from VPORT TE */
214 cp0_wr(dev, f2u(1.0f));
215 }
216
217 static void pa_sc_vport_0(struct pci_dev *dev, struct ptn_tri *p)
218 {
219 /* PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) 0 */
220 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
221 cp0_wr(dev, CTX_REG_IDX(PA_SC_VPORT_0_SCISSOR_TL));
222 /* PA_SC_VPORT_0_SCISSOR_TL */
223 cp0_wr(dev, set(PSVST_X, 0) | set(PSVST_Y, 0));
224 /* PA_SC_VPORT_0_SCISSOR_BR */
225 cp0_wr(dev, set(PSVSB_X, p->w) | set(PSVSB_Y, p->h));
226
227 pa_sc_vport_0_te(dev, p);
228 }
229
230 static void pa_sc_vports_te(struct pci_dev *dev)
231 {
232 /*
233 * PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT)
234 * TE (Transform Engine)
235 */
236 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
237 cp0_wr(dev, CTX_REG_IDX(PA_SC_VPORT_TE_CTL));
238 /* PA_SC_VPORT_TE_CTL: XXX bit 14 not defined but set */
239 cp0_wr(dev, PSVTC_VPORT_X_SCALE_ENA | PSVTC_VPORT_X_OF_ENA
240 | PSVTC_VPORT_Y_SCALE_ENA | PSVTC_VPORT_Y_OF_ENA
241 | PSVTC_VPORT_Z_SCALE_ENA | PSVTC_VPORT_Z_OF_ENA
242 | (1 << 14));
243 }
244
245 static void pa_sc_vports(struct pci_dev *dev, struct ptn_tri *p)
246 {
247 /* PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) */
248 pa_sc_vport_0(dev, p);
249 pa_sc_vports_te(dev);
250 }
251
252 static void pa_sc(struct pci_dev *dev, struct ptn_tri *p)
253 {
254 /* PA (Primitive Assembler) SC (Scan Converter) */
255 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
256 cp0_wr(dev, CTX_REG_IDX(PA_SC_MODE_CTL_1));
257 /* PA_SC_MODE_CTL_1 */
258 cp0_wr(dev, 0);
259
260 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
261 cp0_wr(dev, CTX_REG_IDX(PA_SC_RASTER_CFG));
262 /* PA_SC_RASTER_CFG */
263 cp0_wr(dev, 0);
264
265 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
266 cp0_wr(dev, CTX_REG_IDX(PA_SC_CENTROID_PRIORITY_0));
267 /* PA_SC_CENTROID_PRIORITY_0 */
268 cp0_wr(dev, 0x76543210);
269 /* PA_SC_CENTROID_PRIORITY_1 */
270 cp0_wr(dev, 0xfedcba98);
271
272 /* defines how to render the edge of primitives */
273 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
274 cp0_wr(dev, CTX_REG_IDX(PA_SC_EDGERULE));
275 /* PA_SC_EDGERULE */
276 cp0_wr(dev, 0xaaaaaaaa);
277
278 /*--------------------------------------------------------------------*/
279 /* Anti-Aliasing... probably */
280 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
281 cp0_wr(dev, CTX_REG_IDX(PA_SC_AA_CFG));
282 /* PA_SC_AA_CFG */
283 cp0_wr(dev, 0);
284
285 /* do something AA related */
286 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
287 cp0_wr(dev, CTX_REG_IDX(PA_SC_AA_MASK_X0Y0_X1Y0));
288 /* PA_SC_AA_MASK_X0Y0_X1Y0 */
289 cp0_wr(dev, 0xffffffff);
290 /* PA_SC_AA_MASK_X0Y1_X1Y1 */
291 cp0_wr(dev, 0xffffffff);
292 /*--------------------------------------------------------------------*/
293
294 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
295 cp0_wr(dev, CTX_REG_IDX(PA_SC_CLIPRECT_RULE));
296 /*
297 * PA_SC_CLIPRECT_RULE: no scissor required then clip rule
298 * is 0xffff (no specs provided)
299 */
300 cp0_wr(dev, set(PSCR_CLIP_RULE, 0xffff));
301
302 /*--------------------------------------------------------------------*/
303 /*
304 * Tells the SC (Scan Converter/rasteriser) we don't use
305 * line stipple since we do not render line primitives.
306 * XXX: ORed register? Because if not will set all bits to 0!
307 * We only want to set to 0 LINE_STIPPLE_ENA.
308 */
309 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
310 cp0_wr(dev, CTX_REG_IDX(PA_SC_LINE_STIPPLE));
311 /* PA_SC_LINE_STIPPLE */
312 cp0_wr(dev, 0);
313
314 /*
315 * Even if we are not rendering line primitives, tells the
316 * PA (Primitive Assembler) SC (scan converter/rasteriser)
317 * to do "something with the last pixel
318 */
319 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
320 cp0_wr(dev, CTX_REG_IDX(PA_SC_LINE_CTL));
321 /* PA_SC_LINE_CTL */
322 cp0_wr(dev, PSLC_LAST_PIXEL);
323 /*--------------------------------------------------------------------*/
324
325 /*--------------------------------------------------------------------*/
326 /* set the value of the scissors */
327 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
328 cp0_wr(dev, CTX_REG_IDX(PA_SC_GENERIC_SCISSOR_TL));
329 /* PA_SC_GENERIC_SCISSOR_TL */
330 cp0_wr(dev, set(PSGST_X, 0) | set(PSGST_Y, 0));
331 /* PA_SC_GENERIC_SCISSOR_BR */
332 cp0_wr(dev, set(PSGSB_X, p->w) | set(PSGSB_Y, p->h));
333
334 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
335 cp0_wr(dev, CTX_REG_IDX(PA_SC_SCREEN_SCISSOR_TL));
336 /* PA_SC_SCREEN_SCISSOR_TL */
337 cp0_wr(dev, set(PSSST_X, 0) | set(PSSST_Y, 0));
338 /* PA_SC_SCREEN_SCISSOR_BR */
339 cp0_wr(dev, set(PSSSB_X, p->w) | set(PSSSB_Y, p->h));
340
341 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
342 cp0_wr(dev, CTX_REG_IDX(PA_SC_WND_OF));
343 /*
344 * PA_SC_WND_OF: the window offset in the screen which can be used by
345 * many scissors.
346 */
347 cp0_wr(dev, 0);
348 /* PA_SC_WND_SCISSOR_TL */
349 cp0_wr(dev, set(PSWST_X, 0) | set(PSWST_Y, 0));
350 /* PA_SC_WND_SCISSOR_BR */
351 cp0_wr(dev, set(PSWSB_X, p->w) | set(PSWSB_Y, p->h));
352 /*--------------------------------------------------------------------*/
353
354 pa_sc_vports(dev, p);
355 }
356
357 static void pa(struct pci_dev *dev, struct ptn_tri *p)
358 {
359 /* PA (Primitive Assembler) */
360 pa_su(dev);
361 pa_cl(dev);
362 pa_sc(dev, p);
363 }
364
365 void misc_init(struct pci_dev *dev)
366 {
367 /* basic init GPU context, XXX: not using the CLR_CTX command ??? */
368 /*
369 * XXX: this is a config reg then the pipeline is then doomed
370 * and should be flushed, before accessing it.
371 */
372 cp0_wr(dev, PKT3(PKT3_SET_CFG_REG, 2));
373 cp0_wr(dev, CFG_REG_IDX(PA_CL_ENHANCE));
374 /* PA_CL_ENHANCE */
375 cp0_wr(dev, PCE_CLIPPED_PRIM_SEQ_STALL | PCE_CLIP_VTX_REORDER_ENA);
376
377 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 13));
378 cp0_wr(dev, CTX_REG_IDX(VGT_HOS_CTL));
379 /* VGT_HOS_CTL */
380 cp0_wr(dev, 0);
381 /* VGT_HOS_MAX_TESS_LVL */
382 cp0_wr(dev, 0);
383 /* VGT_HOS_MIN_TESS_LVL */
384 cp0_wr(dev, 0);
385 /* VGT_HOS_REUSE_DEPTH */
386 cp0_wr(dev, 0);
387 /* VGT_GROUP_PRIM_TYPE */
388 cp0_wr(dev, 0);
389 /* VGT_GROUP_FIRST_DECR */
390 cp0_wr(dev, 0);
391 /* VGT_GROUP_DECR */
392 cp0_wr(dev, 0);
393 /* VGT_GROUP_VECT_0_CTL */
394 cp0_wr(dev, 0);
395 /* VGT_GROUP_VECT_1_CTL */
396 cp0_wr(dev, 0);
397 /* VGT_GROUP_VECT_0_FMT_CTL */
398 cp0_wr(dev, 0);
399 /* VGT_GROUP_VECT_1_FMT_CTL */
400 cp0_wr(dev, 0);
401 /* VGT_GS_MODE */
402 cp0_wr(dev, 0);
403
404 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
405 cp0_wr(dev, CTX_REG_IDX(VGT_PRIM_ID_ENA));
406 /* VGT_PRIM_ID_ENA */
407 cp0_wr(dev, 0);
408
409 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
410 cp0_wr(dev, CTX_REG_IDX(VGT_PRIM_ID_RESET));
411 /* VGT_PRIM_ID_RESET */
412 cp0_wr(dev, 0);
413
414 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
415 cp0_wr(dev, CTX_REG_IDX(VGT_STRMOUT_CFG));
416 /* VGT_STRMOUT_CFG */
417 cp0_wr(dev, 0);
418 /* VGT_STRMOUT_BUF_CFG */
419 cp0_wr(dev, 0);
420
421 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
422 cp0_wr(dev, CTX_REG_IDX(IA_MULTI_VGT_PARAM));
423 /* IA_MULTI_VGT_PARAM */
424 cp0_wr(dev, IMVP_SWITCH_ON_EOP | IMVP_PARTIAL_VS_WAVE_ON
425 | set(IMVP_PRIM_GROUP_SZ, 63));
426
427 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 3));
428 cp0_wr(dev, CTX_REG_IDX(VGT_REUSE_OFF));
429 /* VGT_REUSE_OFF */
430 cp0_wr(dev, 0);
431 /* VGT_VTX_CNT_ENA */
432 cp0_wr(dev, 0);
433
434 cp0_wr(dev, PKT3(PKT3_SET_CTX_REG, 2));
435 cp0_wr(dev, CTX_REG_IDX(VGT_SHADER_STAGES_ENA));
436 /* VGT_SHADER_STAGES_ENA */
437 cp0_wr(dev, 0);
438 /*--------------------------------------------------------------------*/
439
440 /*--------------------------------------------------------------------*/
441 /* disable predicate rendering */
442 cp0_wr(dev, PKT3(PKT3_SET_PREDICATION, 2));
443 cp0_wr(dev, 0);
444 cp0_wr(dev, set(PRED_OP, PRED_OP_CLR));
445 /*--------------------------------------------------------------------*/
446 }
447
27 448 /* build raw commands and raw buffer to render a basic triangle primitive */ /* build raw commands and raw buffer to render a basic triangle primitive */
28 449 int ptn_tri(struct pci_dev *dev, struct ptn_tri *p) int ptn_tri(struct pci_dev *dev, struct ptn_tri *p)
29 450 { {
451 struct dev_drv_data *dd;
452 u64 vtx_buf;
453 int r;
454
455 dd = pci_get_drvdata(dev);
456
457 r = rng_alloc_align(&vtx_buf, &dd->vram.mng, sizeof(vertices), 4 * 4);
458 if (r != 0) {
459 dev_err(&dev->dev, "pattern triangle: unable to allocate vertex buffer in"
460 "(v)ram\n");
461 return -ENOMEM;
462 }
463 /* copy the vertex array in vram */
464 memcpy(dd->vram.bar0 + vtx_buf, &vertices, sizeof(vertices));
465
466 /* this is mandatory at the start */
467 cp0_wr(dev, PKT3(PKT3_CTX_CTL, 2));
468 cp0_wr(dev, 0x80000000);
469 cp0_wr(dev, 0x80000000);
470
471 misc_init(dev);
472 spi(dev);
473 dbs(dev);
474 cbs(dev, p);
475 pa(dev, p);
476
477 cp0_commit(dev);
30 478 return 0; return 0;
31 479 } }
File drivers/gpu/alga/amd/si/silicium_blks/3d_basic_pipeline_programming added (mode: 100644) (index 0000000..f3018d3)
1 The basic 3D pipeline is:
2
3 vertex data
4 |
5 V
6 VGT
7 |
8 V
9 VERTEX SHADER
10 |
11 V
12 SCAN CONVERTER/POLY(rasteriser)<--->DB<--->hearly Z etc.
13 |
14 V
15 DB
16 |
17 V
18 PIXEL/FRAGMENT SHADER
19 |
20 V
21 CB
22 |
23 V
24 DB
25 |
26 V
27 framebuffer
28
29 --------------------------------------------------------------------------------
30 Setting up a CB (Color Buffer) for the framebuffer, see cb file, programming
31 section
32 --------------------------------------------------------------------------------
File drivers/gpu/alga/amd/si/silicium_blks/README changed (mode: 100644) (index 7c75d77..e40e7c3)
... ... hardware blocks related to each other:
15 15 - A GPU block: - A GPU block:
16 16 - Some 3D pipeline blocks. - Some 3D pipeline blocks.
17 17 - Some shader engine blocks. - Some shader engine blocks.
18 - Some render backend blocks.
18 - Some render backend blocks with their color sub-blocks and depth
19 sub-blocks.
19 20
20 21 ... ...
21 22
File drivers/gpu/alga/amd/si/silicium_blks/cb added (mode: 100644) (index 0000000..e845249)
1 COLOR BLOCK
2 see information hints from outdated register reference in R6xx_3D_Registers.pdf
3
4 A CB (Color Block) is part of a render backend block. This is the piece of
5 hardware in charge of computing and writing in (v)ram the pixel value.
6
7 A CB takes its inputs from the pixel/fragment shader exports. Usually, for a
8 pixel it gets a pixel color value. The content of CB_SHADER_MASK register
9 decides which of the color components (RGBA) will be used by the CB.
10 It outputs to "targets" (usually a framebuffer in (v)ram).
11
12 It can perform "blending" namely blend output or "target" content with the
13 output of the pixel/fragment shader.
14
15 Units used in many CB registers is 8x8 pixel block index or number.
16
17 If you want to output pixels in a framebuffer, you must program one of the
18 CBs before emitting a draw command with the 3D CP (Command Processor).
19
20 The output or "target" of a CB is an array of 2D slices. One slice is defined by
21 its pitch and total size using index in 8x8 pixel block units
22 (CB_COLOR_[0-7]_PITCH and CB_COLOR_[0-7]_SLICE). The total size of the array
23 is defined using the last 8x8 pixel block index of the array.
24
25 last pitch 8x8 pixel block index
26 |
27 V
28 +--------------------+
29 | slice 0 |
30 | +-----------+ |
31 | | | |
32 | | | |
33 | | 8x8 pixels| ... |
34 | | | |
35 | | | |
36 | +-----------+ |
37 | . |
38 | . |
39 | . |
40 +--------------------+ <-- slice last 8x8 pixel block index
41 .
42 .
43 .
44 +--------------------+
45 | slice n |
46 | +-----------+ |
47 | | | |
48 | | | |
49 | | 8x8 pixels| ... |
50 | | | |
51 | | | |
52 | +-----------+ |
53 | . |
54 | . |
55 | . |
56 +--------------------+ <-- slice array last 8x8 pixel block index
57
58 Of course, the array of slices content can be tiled using the tiling engine.
59
60 --------------------------------------------------------------------------------
61 PROGRAMMING:
62 see information hints from outdated register reference in R6xx_3D_Registers.pdf
63
64 It is done using the 3D command ring. Its registers are in the context area of
65 the GPU, then are pipelined.
66
67 Set those GPU context registers:
68
69 * CB_BLEND_[0-7]_CTL: set them to 0 in order to disable blending.
70
71 * CB_SHADER_MASK: select the color components to pass from the pixel/fragment
72 shader exports to the CB. Since it deals with all CBs, program it once you
73 known how many CBs you use and which color components to use for each
74 used CB.
75
76 * CB_TGT_MASK: select the color components to output (usually into the
77 framebuffer). Same constraint than CB_SHADER_MASK
78
79 * CB_COLOR_CTL: this is a major control switch. Set its mode to normal and the
80 standard mode 0xcc.
81
82 * CB_COLOR_0_BASE: usually, this is the "256 bytes block index" of the tile
83 aligned (see tiling selection in CB_COLOR_0_ATTRIB) base address of the
84 framebuffer).
85
86 * CB_COLOR_0_PITCH: contains the index of the last 8x8 pixel block of a
87 destination slice pitch (whatever is the tiling mode!)
88
89 * CB_COLOR_0_SLICE: contains the index of the last 8x8 pixel block tile index
90 of a destination slice (whatever is the tiling mode!)
91
92 * CB_COLOR_0_VIEW: if you use an array of slices, set it with the last 8x8
93 pixel block index of the array, or 0 if you don't use an array.
94
95 * CB_COLOR0_INFO: there you describe the pixel format which will be used to
96 write to the "target", and more.
97
98 * CB_COLOR_0_ATTRIB: there you select the proper tiling index and more.
File drivers/gpu/alga/amd/si/silicium_blks/db added (mode: 100644) (index 0000000..d955fe6)
1 DEPTH BLOCK
2 see information hints from outdated register reference in R6xx_3D_Registers.pdf
3
4 A DB (Depth Block) is part of a render backend block. This is the piece of
5 hardware in charge of computing/writing/reading depth values and deciding
6 to clip a pixel based on depth.
File drivers/gpu/alga/amd/si/silicium_blks/gpu changed (mode: 100644) (index 82f16ff..16e73e4)
... ... registers) are specific to one "draw" operation.
13 13 Usually, you configure the registers specific to your "draw" operation, then Usually, you configure the registers specific to your "draw" operation, then
14 14 your submit it to the pipeline. If you want to modify the pipeline global your submit it to the pipeline. If you want to modify the pipeline global
15 15 registers, then you must flush the pipeline first. registers, then you must flush the pipeline first.
16
17 GPU blocks are:
18 - vgt (Vertex Grouper and Tessellator)
19 - tc (Texture Cache)
20 - spi (Shader Processor Interpolator)
21 - db (Depth Block)
22 - cb (Color Block)
23 - pa (Primitive Assembler)
24 - sc (Scan Convertor/rasteriser)
25 - ta (Texture Addresser)
26 - cp (Command Processor)
27
28 o CPs, Command Processors
29
30 The first CP is for 3D and compute commands. The second and third CPs are for
31 compute only.
32 It requires 3 pieces of firmware to be loaded: DE/ME, DE is the new name of
33 the ME (micro-engine), CE (Constant engine), PFP (prefetch engine).
34 Nethertheless, its basic control silicium block does not need the firmware to
35 be loaded in order to work.
36 GPU side, the ring buffer is in bus aperture. CPU side is backed with RAM.
37 The GPU fetches CPU side RAM (bus master).
38 The ring buffer works with blocks of 16 dwords. Each "commit" must have a size
39 padded on blocks of 16 dwords. 16 dwords is the "fetch size", dealed by the
40 prefetcher of the cp. A padding dword should be filled with the 2 << 30 value
41 which is a type 2 packet which is actually a filler packet.
42
43 <-----ring size (power of 2)----->
44 +--------------------------------+
45 | 16 dws | 16 dws | ... | 16 dws |
46 +--------------------------------+
47
48 The ring size is defined in power of two of quadwords (64 bits). Also the
49 GPU page size is used as "inner blocks". A GPU page is 4096 bytes then
50 2^9 quadwords exactly.
51
52 <--------------2^17 qws------------->
53 +-----------------------------------+
54 | 2^9 qws | 2^9 qws | ... | 2^9 qws |
55 +-----------------------------------+
56
57 Of course, the prefectch size is aligned on 2^9 qws, namely 16 dws is 2^3 qws:
58
59 <--------------2^9 qws-------------->
60 +-----------------------------------+
61 | 2^3 qws | 2^3 qws | ... | 2^3 qws |
62 +-----------------------------------+
63
64 The write pointer of the ring is managed by the CPU. This pointer is a dword
65 index. When the write pointer is committed to the GPU, it must point to the
66 dword right after the last fetch block dword (16 dwords).
67
68 The CP has a clear context. Namely a set of GPU register values which defines
69 the "clear" state. It is programmed using a type 3 packet PKT3_PREAMBLE_CTL
70 and that state is set using the type 3 packet PKT3_CLEAR_STATE. Only need
71 to be programmed on CP0 and will be valid for all command rings.
File drivers/gpu/alga/amd/si/silicium_blks/hdp changed (mode: 100644) (index abb1295..6fafc7c)
... ... address to use in HDP_NONSURFACE_BASE, some "information" in HDP_NONSURFACE_INFO
4 4 and the size in HDP_NONSURFACE_SIZE. and the size in HDP_NONSURFACE_SIZE.
5 5
6 6 HDP_MEM_COHERENCY_FLUSH_CTL register is used to flush HDP cache after PCI bar 0 HDP_MEM_COHERENCY_FLUSH_CTL register is used to flush HDP cache after PCI bar 0
7 transactions.
8 HDP_REG_COHERENCY_FLUSH_CTL register is used to flush HDP cache after HDP
9 register changes.
7 transactions (prefetchable memory).
8 HDP_REG_COHERENCY_FLUSH_CTL register is used to flush HDP cache after PCI bar 2
9 transactions (non-cachable memory).
10 10
11 HDP_MISC_CTL with the HDP_FLUSH_INVALIDATE_CACHE do what is says. What is the
12 relationship with the caches above?
11 HDP_MISC_CTL with the HDP_FLUSH_INVALIDATE_CACHE do what is says.
13 12
14 13 There is a set of HDP registers not related to memory bus architecture: There is a set of HDP registers not related to memory bus architecture:
15 14 from 0x2c14, 32 blocks of 0x18 bytes in size (FIFOs/TLB) from 0x2c14, 32 blocks of 0x18 bytes in size (FIFOs/TLB)
File drivers/gpu/alga/amd/si/silicium_blks/mc changed (mode: 100644) (index 540c0a4..876a223)
... ... compatible with the previoulsy chosen addresses for the memory controller.
30 30 If there is no page in order to map a GPU address from a request to a bus If there is no page in order to map a GPU address from a request to a bus
31 31 address, the bus address stored in VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR address, the bus address stored in VM_CTX_0_PROTECTION_FAULT_DEFAULT_ADDR
32 32 is used. The VM has several read/write clients from the MD block and the MB is used. The VM has several read/write clients from the MD block and the MB
33 block. Those clients are configured using MC_VM_MD_L1_TLB_X_CTL (X from 0 to 3)
34 and MC_VM_MB_L1_TLB_X_CTL (X from 0 to 3). Those clients uses the CTX0, and the
35 programming memory model is programmed in those latest register (see
36 NOT_IN_SYS and SYS_APER_UNMAPPED_ACCESS with PASS_THRU).
33 block. Those clients are configured using MC_VM_MX_L1_TLB_N_CTL (N from 0 to 3
34 and X denotes this register targets D and B block clients).
35 Those clients uses the CTX0, and the programming memory model is programmed in
36 those latest register (see NOT_IN_SYS and SYS_APER_UNMAPPED_ACCESS with
37 PASS_THRU).
37 38
38 39 o The configuration of the VRAM modules is in ARB_RAMCFG register. There you o The configuration of the VRAM modules is in ARB_RAMCFG register. There you
39 40 have the number of the classic channels/ranks/banks/rows/columns with the have the number of the classic channels/ranks/banks/rows/columns with the
 
... ... o The arbiter is the silicium block which manages the accesses to the mc from
63 64 - DMIF (DMIF_ADDR_CFG register) - DMIF (DMIF_ADDR_CFG register)
64 65 - GB (GB_ADDR_CFG register) - GB (GB_ADDR_CFG register)
65 66
66 o swizzled data is tiled organized data.
67
68 o the tiling unit seems to be based on VRAM burst lenght.
69
70 67 o VRAM module configuration: o VRAM module configuration:
71 68 o MC_SHARED_CHMAP (memory controller shared VRAM channel map): o MC_SHARED_CHMAP (memory controller shared VRAM channel map):
72 69 CHANS_N: CHANS_N:
File drivers/gpu/alga/amd/si/silicium_blks/others changed (mode: 100644) (index b1b6a1a..6c91c6b)
1 o SP (Shader Pipe)
2 seems to have some simd units
3
4 o vgt (Vertex Grouper and Tessellator)
5 o tc (Texture Cache)
6 o vc (Vertex Cache)
7 o sx (Shader Export)
8 o spi (Shader Processor Interpolator)
9 o db (Depth Block)
10 o cb (Color Block)
11 o pa (Primitive Assembler)
12 o sc (Scan Convertor)
13 o sh (Sequencer instruction cache)
14 o ta (Texture Addresser)
15 see R6xx_R7xx_3D.pdf
16
17 crtc/cur/lut/grph/viewport
1 o DCE (Display Control Engine) and its sub-blocks
18 2
19 3 o RLC o RLC
20
21 Seems related to interrupts. There is multiplexing among "instances" and
22 shader engines. You need to select using RLC_GFX_IDX the "instances" and
23 shader engines which are intended to be programed.
24
25 o CP is the Command Processor
26
27 It requires a firmware to be loaded and is dealed through a ring buffer.
28 Nethertheless, its basic control silicium block does not need the firmware to
29 be loaded in order to work.
30 GPU side, the ring buffer is in bus aperture. CPU side is backed with RAM.
31 The GPU fetches CPU side RAM (bus master).
32 The ring buffer works with blocks of 16 dwords. Each "commit" must have a size
33 padded on blocks of 16 dwords. 16 dwords is the "fetch size", dealed by the
34 prefetcher of the cp. A padding dword should be filled with the 2 << 30 value
35 which is a type 2 packet which is actually a filler packet.
36
37 <-----ring size (power of 2)----->
38 +--------------------------------+
39 | 16 dws | 16 dws | ... | 16 dws |
40 +--------------------------------+
41
42 The ring size is defined in power of two of quadwords (64 bits). Also the
43 GPU page size is used as "inner blocks". A GPU page is 4096 bytes then
44 2^9 quadwords exactly.
45
46 <--------------2^17 qws------------->
47 +-----------------------------------+
48 | 2^9 qws | 2^9 qws | ... | 2^9 qws |
49 +-----------------------------------+
50
51 Of course, the prefectch size is aligned on 2^9 qws, namely 16 dws is 2^3 qws:
52
53 <--------------2^9 qws-------------->
54 +-----------------------------------+
55 | 2^3 qws | 2^3 qws | ... | 2^3 qws |
56 +-----------------------------------+
57
58 The write pointer of the ring is managed by the CPU. This pointer is a dword
59 index. When the write pointer is committed to the GPU, it must point to the
60 dword right after the last fetch block dword (16 dwords).
61
62 The CP has a clear context. Namely a set of GPU register values which defines
63 the "clear" state. It is programmed using a type 3 packet PKT3_PREAMBLE_CTL
64 and that state is set using the type 3 packet PKT3_CLEAR_STATE.
4 Seems related to interrupts and timestamping.
65 5
66 6 o IH is the Interrupt Handler. o IH is the Interrupt Handler.
67 7
68 Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty the same
69 as the CP ring buffer, but in reverse. Rather than the CPU writing to the
8 Interrupts use a ring buffer. It works pretty the same
9 as the CP ring buffers, but in reverse. Rather than the CPU writing to the
70 10 ring and the GPU consuming, the GPU writes to the ring and host consumes. As ring and the GPU consuming, the GPU writes to the ring and host consumes. As
71 11 the host irq handler processes interrupts, it increments the rptr. When the the host irq handler processes interrupts, it increments the rptr. When the
72 12 rptr catches up with the wptr, all the current interrupts have been processed. rptr catches up with the wptr, all the current interrupts have been processed.
 
... ... o scratch registers
98 38 | WRITE BACK GPU PAGE | | WRITE BACK GPU PAGE |
99 39 +----------------------------------------------------------------------------+ +----------------------------------------------------------------------------+
100 40 <----------------------------------4kB---------------------------------------> <----------------------------------4kB--------------------------------------->
101
102 o fences
103
104 Fences uses a scratch register. The 32 bits event place holder in the write
105 back page receive a sequence number, inited to 0 by the CPU.
106
107 A fence has 3 states:
108 - created
109 - emited
110 - signaled
111
112 At first, a fence is created, but neither emited nor signaled.
File drivers/gpu/alga/amd/si/silicium_blks/spi added (mode: 100644) (index 0000000..42a8c31)
1 SHADER PROCESSOR INTERPOLATOR
2
3 --------------------------------------------------------------------------------
4 It manages the point primitive sprite:
5 In SPI_INTERPOL_CTL_0 you can enable the use of the point primitive sprite.
6 if the point primitive sprite coordinates are provided as the top/left
7 coodinate you have to set the POINT_SPRITE_TOP_1 bit.
8 --------------------------------------------------------------------------------
File drivers/gpu/alga/amd/si/silicium_blks/xrbm changed (mode: 100644) (index 7d50a1e..623d863)
1 Those blockis manage the registers. The PCI bar 2 decodes bus transactions to be
1 Those blocks manage the registers. The PCI bar 2 decodes bus transactions to be
2 2 forwarded to proper Xrbm block. forwarded to proper Xrbm block.
3 3
4 4 o Xrbm (X Register Backbone Manager) where X is G or S o Xrbm (X Register Backbone Manager) where X is G or S
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