File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index d98782b..155a675) |
... |
... |
static irqreturn_t irq(int irq, void *dev_id) |
601 |
601 |
return IRQ_NONE; |
return IRQ_NONE; |
602 |
602 |
} |
} |
603 |
603 |
|
|
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604 |
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static void rlc_stop(struct pci_dev *dev) |
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605 |
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{ |
|
606 |
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wr32(dev, 0, RLC_CTL); |
|
607 |
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} |
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608 |
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609 |
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static void rlc_start(struct pci_dev *dev) |
|
610 |
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{ |
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611 |
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wr32(dev, RLC_ENA, RLC_CTL); |
|
612 |
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} |
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613 |
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614 |
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static void rlc_free(struct pci_dev *dev) |
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615 |
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{ |
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616 |
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struct dev_drv_data *dd; |
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617 |
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dd = pci_get_drvdata(dev); |
|
618 |
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rng_free(&dd->vram.mng, dd->rlc.save_and_restore); |
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619 |
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rng_free(&dd->vram.mng, dd->rlc.clr_and_restore); |
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620 |
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} |
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621 |
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622 |
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static int rlc_alloc(struct pci_dev *dev) |
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623 |
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{ |
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624 |
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struct dev_drv_data *dd; |
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625 |
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int r; |
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626 |
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627 |
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dd = pci_get_drvdata(dev); |
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628 |
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629 |
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r = rng_alloc_align(&dd->rlc.save_and_restore, &dd->vram.mng, |
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630 |
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GPU_PAGE_SZ, GPU_PAGE_SZ); |
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631 |
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if (r != 0) { |
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632 |
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dev_err(&dev->dev, "unable to alloc GPU RLC save and restore" |
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633 |
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" page\n"); |
|
634 |
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return -SI_ERR; |
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635 |
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} |
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636 |
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637 |
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r = rng_alloc_align(&dd->rlc.clr_and_restore, &dd->vram.mng, |
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638 |
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GPU_PAGE_SZ, GPU_PAGE_SZ); |
|
639 |
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if (r != 0) { |
|
640 |
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dev_err(&dev->dev, "unable to alloc GPU RLC clear and restore" |
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641 |
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" page\n"); |
|
642 |
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goto free_save_and_restore; |
|
643 |
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} |
|
644 |
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return 0; |
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645 |
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646 |
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free_save_and_restore: |
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647 |
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rng_free(&dd->vram.mng, dd->rlc.save_and_restore); |
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648 |
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return -SI_ERR; |
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649 |
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} |
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650 |
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604 |
651 |
/* override the memory configuration */ |
/* override the memory configuration */ |
605 |
652 |
static void addr_cfg_compute(struct pci_dev *dev, u32 *addr_cfg, |
static void addr_cfg_compute(struct pci_dev *dev, u32 *addr_cfg, |
606 |
653 |
unsigned *mem_row_sz_kb) |
unsigned *mem_row_sz_kb) |
|
... |
... |
static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id) |
754 |
801 |
cps_engines_stop(dev); |
cps_engines_stop(dev); |
755 |
802 |
ih_stop(dev); |
ih_stop(dev); |
756 |
803 |
ih_reset(dev); |
ih_reset(dev); |
|
804 |
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rlc_stop(dev); |
757 |
805 |
intrs_reset(dev); |
intrs_reset(dev); |
758 |
806 |
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759 |
807 |
err = request_threaded_irq(dev->irq, irq, irq_thd, 0, pci_name(dev), |
err = request_threaded_irq(dev->irq, irq, irq_thd, 0, pci_name(dev), |
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... |
... |
static int __devinit probe(struct pci_dev *dev, const struct pci_device_id *id) |
803 |
851 |
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804 |
852 |
gpu_init(dev, addr_cfg, mem_row_sz_kb); |
gpu_init(dev, addr_cfg, mem_row_sz_kb); |
805 |
853 |
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854 |
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err = rlc_alloc(dev); |
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855 |
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if (err) |
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856 |
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goto err_shutdown_dce6; |
806 |
857 |
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807 |
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////KEEP GOING HERE |
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808 |
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809 |
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810 |
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//ucode_rlc_program(dev); |
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858 |
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ucode_rlc_program(dev); |
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859 |
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rlc_start(dev); |
811 |
860 |
//ih_init(dev); |
//ih_init(dev); |
812 |
861 |
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813 |
862 |
//ih_start(dev); |
//ih_start(dev); |
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... |
... |
err_cdev_del: |
842 |
891 |
err_stop_cps_engines: |
err_stop_cps_engines: |
843 |
892 |
cps_engines_stop(dev); |
cps_engines_stop(dev); |
844 |
893 |
ih_stop(dev); |
ih_stop(dev); |
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894 |
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rlc_stop(dev); |
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895 |
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rlc_free(dev); |
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896 |
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897 |
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err_shutdown_dce6: |
845 |
898 |
dce6_shutdown(dd->dce); |
dce6_shutdown(dd->dce); |
846 |
899 |
|
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847 |
900 |
err_ba_unmap: |
err_ba_unmap: |
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... |
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static void __devexit remove(struct pci_dev *dev) |
906 |
959 |
cps_engines_stop(dev); |
cps_engines_stop(dev); |
907 |
960 |
ih_stop(dev); |
ih_stop(dev); |
908 |
961 |
ih_reset(dev); |
ih_reset(dev); |
|
962 |
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rlc_stop(dev); |
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963 |
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rlc_free(dev); |
909 |
964 |
dce6_shutdown(dd->dce); |
dce6_shutdown(dd->dce); |
910 |
965 |
kfree(dd->dce); |
kfree(dd->dce); |
911 |
966 |
free_irq(dev->irq, (void*)dev); |
free_irq(dev->irq, (void*)dev); |
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 44dd7d2..6a28ce3) |
841 |
841 |
#define RLC_LB_CTL 0xc30c |
#define RLC_LB_CTL 0xc30c |
842 |
842 |
#define RLC_SAVE_AND_RESTORE_BASE 0xc310 |
#define RLC_SAVE_AND_RESTORE_BASE 0xc310 |
843 |
843 |
#define RLC_LB_CNTR_MAX 0xc314 |
#define RLC_LB_CNTR_MAX 0xc314 |
844 |
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#define RLC_LB_CNTR_INT 0xc318 |
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844 |
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#define RLC_LB_CNTR_INIT 0xc318 |
845 |
845 |
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846 |
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#define RLC_CLR_STATE_RESTORE_BASE 0xc320 |
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846 |
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#define RLC_CLR_AND_RESTORE_BASE 0xc320 |
847 |
847 |
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848 |
848 |
#define RLC_UCODE_ADDR 0xc32c |
#define RLC_UCODE_ADDR 0xc32c |
849 |
849 |
#define RLC_UCODE_DATA 0xc330 |
#define RLC_UCODE_DATA 0xc330 |
File drivers/gpu/alga/amd/si/ucode.c changed (mode: 100644) (index 37f3f15..f03e634) |
... |
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out: |
179 |
179 |
return err; |
return err; |
180 |
180 |
} |
} |
181 |
181 |
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182 |
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//void ucode_rlc_program(struct pci_dev *dev) |
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183 |
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//{ |
|
184 |
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// u32 i; |
|
185 |
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// const __be32 *fw_data; |
|
186 |
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// struct dev_drv_data *dd; |
|
187 |
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// |
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188 |
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// dd = pci_get_drvdata(dev); |
|
189 |
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// |
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190 |
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// wr32(dev, 0, RLC_CTL); |
|
191 |
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// |
|
192 |
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// wr32(dev, 0, RLC_HB_BASE); |
|
193 |
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// wr32(dev, 0, RLC_HB_CTL); |
|
194 |
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// wr32(dev, 0, RLC_HB_RPTR); |
|
195 |
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// wr32(dev, 0, RLC_HB_WPTR); |
|
196 |
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// wr32(dev, 0, RLC_HB_WPTR_LSB_ADDR); |
|
197 |
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// wr32(dev, 0, RLC_HB_WPTR_MSB_ADDR); |
|
198 |
|
// wr32(dev, 0, RLC_MC_CTL); |
|
199 |
|
// wr32(dev, 0, RLC_UCODE_CTL); |
|
200 |
|
// |
|
201 |
|
// fw_data = (const __be32 *)dd->ucode.rlc->data; |
|
202 |
|
// for (i = 0; i < RLC_DWS; ++i) { |
|
203 |
|
// wr32(dev, i, RLC_UCODE_ADDR); |
|
204 |
|
// wr32(dev, be32_to_cpup(fw_data++), RLC_UCODE_DATA); |
|
205 |
|
// } |
|
206 |
|
// wr32(dev, 0, RLC_UCODE_ADDR); |
|
207 |
|
// |
|
208 |
|
// wr32(dev, RLC_ENA, RLC_CTL); |
|
209 |
|
//} |
|
|
182 |
|
void ucode_rlc_program(struct pci_dev *dev) |
|
183 |
|
{ |
|
184 |
|
u32 i; |
|
185 |
|
const __be32 *fw_data; |
|
186 |
|
struct dev_drv_data *dd; |
|
187 |
|
|
|
188 |
|
dd = pci_get_drvdata(dev); |
|
189 |
|
|
|
190 |
|
wr32(dev, 0, RLC_RL_BASE); |
|
191 |
|
wr32(dev, 0, RLC_RL_SZ); |
|
192 |
|
wr32(dev, 0, RLC_LB_CTL); |
|
193 |
|
wr32(dev, 0xffffffff, RLC_LB_CNTR_MAX); |
|
194 |
|
wr32(dev, 0, RLC_LB_CNTR_INIT); |
|
195 |
|
|
|
196 |
|
wr32(dev, dd->rlc.save_and_restore >> 8, RLC_SAVE_AND_RESTORE_BASE); |
|
197 |
|
wr32(dev, dd->rlc.clr_and_restore >> 8, RLC_CLR_AND_RESTORE_BASE); |
|
198 |
|
|
|
199 |
|
wr32(dev, 0, RLC_MC_CTL); |
|
200 |
|
wr32(dev, 0, RLC_UCODE_CTL); |
|
201 |
|
|
|
202 |
|
fw_data = (const __be32 *)dd->ucode.rlc->data; |
|
203 |
|
for (i = 0; i < RLC_DWS; ++i) { |
|
204 |
|
wr32(dev, i, RLC_UCODE_ADDR); |
|
205 |
|
wr32(dev, be32_to_cpup(fw_data++), RLC_UCODE_DATA); |
|
206 |
|
} |
|
207 |
|
wr32(dev, 0, RLC_UCODE_ADDR); |
|
208 |
|
} |
210 |
209 |
|
|
211 |
210 |
//void ucode_cp_program(struct pci_dev *dev) |
//void ucode_cp_program(struct pci_dev *dev) |
212 |
211 |
//{ |
//{ |