sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
upstream golden registers 2d9afbd743277f615e089c50ee186a149978b5a5 Sylvain BERTRAND 2013-06-12 23:32:12
suspend-to-ram and gpu context loss support 7a9840cd7d37c89624149f14b44222160f7311ff Sylvain BERTRAND 2013-05-23 19:23:36
verde gpu config upstream fix 05afeb06a76317f028061b8efc66b215338b211d Sylvain BERTRAND 2013-05-21 20:35:16
finally, pp state description index fixed b03152e5f8253db7b01f6d507ed18eb71d4d2a17 Sylvain BERTRAND 2013-05-01 22:27:53
power management continued e8e2e1e2a8dc438a1f15ec3d7ec72b2ecd431f08 Sylvain BERTRAND 2013-05-01 00:57:09
powerplay preliminary support e65cce387d8aed980f48b0f58092bea31175b79d Sylvain BERTRAND 2013-04-26 17:48:11
dce sysfs: remove obsolete crtc word 288dd69b5196b3848b90e993b4d45383d7d0c972 Sylvain BERTRAND 2013-04-26 13:54:02
dce:i te idx 74e29494f7283fa105fef53291053e3630b605bf Sylvain BERTRAND 2013-04-26 13:28:37
upstream: new pci ids dda82ff321c33e0d7123dd06b0466775d9f96141 Sylvain BERTRAND 2013-04-26 12:22:27
cleaner error handling f853e060408068567efa895448ebc5807b5e5485 Sylvain BERTRAND 2013-03-22 01:28:11
alga cosmetics a8b013ce129bb7218fbf5a331f09828322219ac6 Sylvain BERTRAND 2013-03-22 01:21:27
massive comestics f0ff31f57512bd63b707a34d8f6252091facb632 Sylvain BERTRAND 2013-03-22 01:02:42
sysfs discret_vram property cf1c115de509b4449d7e1af1e21bf26010904c46 Sylvain BERTRAND 2013-03-19 00:56:39
dce6 crtc attribute 8f7a977603c22668c56d36c59868b74426fcf371 Sylvain BERTRAND 2013-03-12 17:02:51
ioctl edid not big enough fa9570a5821514fdb281d81ce801c2c86592dc69 Sylvain BERTRAND 2013-03-11 22:14:17
edid override has ioctl d0e628fe0d9e43cdebb3ce32cf04e53f4e36239e Sylvain BERTRAND 2013-03-11 20:48:26
forgot to remove the edid binary attribute fe3bf78e0ef1919315c1ba4da75dd3a320140061 Sylvain BERTRAND 2013-03-07 16:48:36
finally switch to binary attr for edid 739827ff0f69bacbda2bc18c19ab3cf9a7b96a5b Sylvain BERTRAND 2013-03-07 16:30:46
display properties with edid patching e43106768022d2d37e2120f4748e1bbe294f2fb9 Sylvain BERTRAND 2013-03-07 03:33:05
first shot at sysfs for display hotplug 411ae25ba5390aa8cb43d104fc7942781c036758 Sylvain BERTRAND 2013-03-06 02:10:12
Commit 2d9afbd743277f615e089c50ee186a149978b5a5 - upstream golden registers
Author: Sylvain BERTRAND
Author date (UTC): 2013-06-12 23:32
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-06-12 23:32
Parent(s): 7a9840cd7d37c89624149f14b44222160f7311ff
Signer:
Signing key:
Signing status: N
Tree: e7b4496b73e366af3895235b786c597f923a9c7d
File Lines added Lines deleted
drivers/gpu/alga/amd/si/Makefile 2 2
drivers/gpu/alga/amd/si/drv.c 2 0
drivers/gpu/alga/amd/si/golden.c 1049 0
drivers/gpu/alga/amd/si/golden.h 3 3
drivers/gpu/alga/amd/si/gpu/regs_cfg.h 13 1
drivers/gpu/alga/amd/si/gpu/regs_ctx.h 1 1
drivers/gpu/alga/amd/si/regs.h 16 5
File drivers/gpu/alga/amd/si/Makefile changed (mode: 100644) (index 54c02b6..82baf88)
1 si-y := drv.o intr_irq.o mc.o ih.o rlc.o ucode.o fops.o gpu/gpu.o gpu/cps.o gpu/tiling.o bus/ba.o bus/hdp.o \
2 bus/bif.o
1 si-y := drv.o intr_irq.o mc.o ih.o rlc.o ucode.o fops.o gpu/gpu.o gpu/cps.o \
2 gpu/tiling.o bus/ba.o bus/hdp.o bus/bif.o golden.o
3 3 si-$(CONFIG_ALGA_AMD_SI_PATTERNS)+=patterns/fb_fill.o patterns/tri.o si-$(CONFIG_ALGA_AMD_SI_PATTERNS)+=patterns/fb_fill.o patterns/tri.o
4 4 obj-$(CONFIG_ALGA_AMD_SI)+= si.o obj-$(CONFIG_ALGA_AMD_SI)+= si.o
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index 160a408..7bfb47f)
37 37 #include "intr_irq.h" #include "intr_irq.h"
38 38 #include "bus/hdp.h" #include "bus/hdp.h"
39 39 #include "bus/bif.h" #include "bus/bif.h"
40 #include "golden.h"
40 41
41 42 #define GPUS_MAX 256 #define GPUS_MAX 256
42 43 static DEFINE_IDA(ida); static DEFINE_IDA(ida);
 
... ... static long asic_init(struct pci_dev *dev)
296 297 dev_err(&dev->dev, "atombios failed to init the asic\n"); dev_err(&dev->dev, "atombios failed to init the asic\n");
297 298 goto err; goto err;
298 299 } }
300 golden_regs(dev);
299 301
300 302 /* CFG_MEM_SZ is now valid */ /* CFG_MEM_SZ is now valid */
301 303 dev_info(&dev->dev, "vram size is %uMB\n", rr32(dev, CFG_MEM_SZ)); dev_info(&dev->dev, "vram size is %uMB\n", rr32(dev, CFG_MEM_SZ));
File drivers/gpu/alga/amd/si/golden.c added (mode: 100644) (index 0000000..898f71a)
1 /*
2 author Sylvain Bertrand <digital.ragnarok@gmail.com>
3 Protected by GNU Affero GPL v3 with some exceptions.
4 See README at root of alga tree.
5 */
6 #include <linux/pci.h>
7 #include <linux/cdev.h>
8
9 #include <alga/rng_mng.h>
10
11 #include "regs.h"
12 #include "gpu/regs_cfg.h"
13
14 #include "mc.h"
15 #include "rlc.h"
16 #include "ih.h"
17 #include "bus/ba.h"
18 #include "gpu/cps.h"
19 #include "gpu/gpu.h"
20 #include "drv.h"
21
22 static u32 tahiti_golden_rlc_regs[] = {
23 0xc424, 0xffffffff, 0x00601005,
24 0xc47c, 0xffffffff, 0x10104040,
25 0xc488, 0xffffffff, 0x0100000a,
26 RLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
27 RLC_LB_CTL, 0xffffffff, 0x800000f4,
28 0xf4a8, 0xffffffff, 0x00000000
29 };
30
31 static u32 tahiti_golden_regs_0[] = {
32 0x9a10, 0x00010000, 0x00018208,
33 0x9830, 0xffffffff, 0x00000000,
34 0x9834, 0xf00fffff, 0x00000400,
35 0x9838, 0x0002021c, 0x00020200,
36 0xc78, 0x00000080, 0x00000000,
37 0xd030, 0x000300c0, 0x00800040,
38 0xd830, 0x000300c0, 0x00800040,
39 0x5bb0, 0x000000f0, 0x00000070,
40 0x5bc0, 0x00200000, 0x50100000,
41 0x7030, 0x31000311, 0x00000011,
42 0x277c, 0x00000003, 0x000007ff,
43 0x240c, 0x000007ff, 0x00000000,
44 0x0000, 0x00000000, 0x00000000,
45 0x0000, 0x00000000, 0x00000000,
46 PA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
47 0x0000, 0x00000000, 0x00000000,
48 0x0000, 0x00000000, 0x00000000,
49 0x30, 0x000000ff, 0x0040,
50 0x34, 0x00000040, 0x00004040,
51 SPI_CFG_CTL_0, 0x07ffffff, SCC_ENA_SQG_TOP_EVENTS
52 | SCC_EN_SQG_BOP_EVENTS,
53 0x8e88, 0x01ff1f3f, 0x00000000,
54 0x8e84, 0x01ff1f3f, 0x00000000,
55 0x9060, 0x0000007f, 0x00000020,
56 TA_CTL_AUX, 0x00010000, 0x00010000,
57 0xac14, 0x00000200, 0x000002fb,
58 TCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
59 TCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
60 0x88d0, 0xffffffff, 0x000fff40,
61 0x0000, 0x00000000, 0x00000000,
62 0x0000, 0x00000000, 0x00000000,
63 0x15c0, 0x000c0fc0, 0x000c0400
64 };
65
66 static u32 tahiti_golden_regs_1[] = {
67 0xc64, 0x00000001, 0x00000001
68 };
69
70 static u32 pitcairn_golden_rlc_regs[] = {
71 0xc424, 0xffffffff, 0x00601004,
72 0xc47c, 0xffffffff, 0x10102020,
73 0xc488, 0xffffffff, 0x01000020,
74 RLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
75 RLC_LB_CTL, 0xffffffff, 0x800000a4
76 };
77
78 static u32 pitcairn_golden_regs[] = {
79 0x9a10, 0x00010000, 0x00018208,
80 0x9830, 0xffffffff, 0x00000000,
81 0x9834, 0xf00fffff, 0x00000400,
82 0x9838, 0x0002021c, 0x00020200,
83 0xc78, 0x00000080, 0x00000000,
84 0xd030, 0x000300c0, 0x00800040,
85 0xd830, 0x000300c0, 0x00800040,
86 0x5bb0, 0x000000f0, 0x00000070,
87 0x5bc0, 0x00200000, 0x50100000,
88 0x7030, 0x31000311, 0x00000011,
89 0x2ae4, 0x00073ffe, 0x000022a2,
90 0x240c, 0x000007ff, 0x00000000,
91 0x0000, 0x00000000, 0x00000000,
92 0x0000, 0x00000000, 0x00000000,
93 PA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
94 0x0000, 0x00000000, 0x00000000,
95 0x0000, 0x00000000, 0x00000000,
96 0x30, 0x000000ff, 0x0040,
97 0x34, 0x00000040, 0x00004040,
98 SPI_CFG_CTL_0, 0x07ffffff, SCC_ENA_SQG_TOP_EVENTS
99 | SCC_EN_SQG_BOP_EVENTS,
100 0x9060, 0x0000007f, 0x00000020,
101 TA_CTL_AUX, 0x00010000, 0x00010000,
102 0xac14, 0x000003ff, 0x000000f7,
103 TCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
104 TCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
105 0x0000, 0x00000000, 0x00000000,
106 0x15c0, 0x000c0fc0, 0x000c0400
107 };
108
109 static u32 verde_golden_rlc_regs[] = {
110 0xc424, 0xffffffff, 0x033f1005,
111 0xc47c, 0xffffffff, 0x10808020,
112 0xc488, 0xffffffff, 0x00800008,
113 RLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
114 RLC_LB_CTL, 0xffffffff, 0x80010014
115 };
116
117 static u32 verde_golden_regs[] = {
118 0x9a10, 0x00010000, 0x00018208,
119 0x9830, 0xffffffff, 0x00000000,
120 0x9834, 0xf00fffff, 0x00000400,
121 0x9838, 0x0002021c, 0x00020200,
122 0xc78, 0x00000080, 0x00000000,
123 0xd030, 0x000300c0, 0x00800040,
124 0xd030, 0x000300c0, 0x00800040,
125 0xd830, 0x000300c0, 0x00800040,
126 0xd830, 0x000300c0, 0x00800040,
127 0x5bb0, 0x000000f0, 0x00000070,
128 0x5bc0, 0x00200000, 0x50100000,
129 0x7030, 0x31000311, 0x00000011,
130 0x2ae4, 0x00073ffe, 0x000022a2,
131 0x2ae4, 0x00073ffe, 0x000022a2,
132 0x2ae4, 0x00073ffe, 0x000022a2,
133 0x240c, 0x000007ff, 0x00000000,
134 0x240c, 0x000007ff, 0x00000000,
135 0x240c, 0x000007ff, 0x00000000,
136 0x0000, 0x00000000, 0x00000000,
137 0x0000, 0x00000000, 0x00000000,
138 0x0000, 0x00000000, 0x00000000,
139 0x0000, 0x00000000, 0x00000000,
140 PA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
141 0x0000, 0x00000000, 0x00000000,
142 0x0000, 0x00000000, 0x00000000,
143 0x0000, 0x00000000, 0x00000000,
144 0x0000, 0x00000000, 0x00000000,
145 0x30, 0x000000ff, 0x0040,
146 0x34, 0x00000040, 0x00004040,
147 SPI_CFG_CTL_0, 0x07ffffff, SCC_ENA_SQG_TOP_EVENTS
148 | SCC_EN_SQG_BOP_EVENTS,
149 SPI_CFG_CTL_0, 0x07ffffff, SCC_ENA_SQG_TOP_EVENTS
150 | SCC_EN_SQG_BOP_EVENTS,
151 0x8e88, 0x01ff1f3f, 0x00000000,
152 0x8e88, 0x01ff1f3f, 0x00000000,
153 0x8e88, 0x01ff1f3f, 0x00000000,
154 0x8e84, 0x01ff1f3f, 0x00000000,
155 0x8e84, 0x01ff1f3f, 0x00000000,
156 0x8e84, 0x01ff1f3f, 0x00000000,
157 0x9060, 0x0000007f, 0x00000020,
158 TA_CTL_AUX, 0x00010000, 0x00010000,
159 0xac14, 0x000003ff, 0x00000003,
160 0xac14, 0x000003ff, 0x00000003,
161 0xac14, 0x000003ff, 0x00000003,
162 TCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
163 TCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
164 TCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
165 TCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
166 TCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
167 TCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
168 0x0000, 0x00000000, 0x00000000,
169 0x0000, 0x00000000, 0x00000000,
170 0x0000, 0x00000000, 0x00000000,
171 0x15c0, 0x000c0fc0, 0x000c0400
172 };
173
174 static u32 oland_golden_rlc_regs[] = {
175 0xc424, 0xffffffff, 0x00601005,
176 0xc47c, 0xffffffff, 0x10104040,
177 0xc488, 0xffffffff, 0x0100000a,
178 RLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
179 RLC_LB_CTL, 0xffffffff, 0x800000f4
180 };
181
182 static u32 oland_golden_regs[] = {
183 0x9a10, 0x00010000, 0x00018208,
184 0x9830, 0xffffffff, 0x00000000,
185 0x9834, 0xf00fffff, 0x00000400,
186 0x9838, 0x0002021c, 0x00020200,
187 0xc78, 0x00000080, 0x00000000,
188 0xd030, 0x000300c0, 0x00800040,
189 0xd830, 0x000300c0, 0x00800040,
190 0x5bb0, 0x000000f0, 0x00000070,
191 0x5bc0, 0x00200000, 0x50100000,
192 0x7030, 0x31000311, 0x00000011,
193 0x2ae4, 0x00073ffe, 0x000022a2,
194 0x240c, 0x000007ff, 0x00000000,
195 0x0000, 0x00000000, 0x00000000,
196 0x0000, 0x00000000, 0x00000000,
197 PA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
198 0x0000, 0x00000000, 0x00000000,
199 0x0000, 0x00000000, 0x00000000,
200 0x30, 0x000000ff, 0x0040,
201 0x34, 0x00000040, 0x00004040,
202 SPI_CFG_CTL_0, 0x07ffffff, SCC_ENA_SQG_TOP_EVENTS
203 | SCC_EN_SQG_BOP_EVENTS,
204 0x9060, 0x0000007f, 0x00000020,
205 TA_CTL_AUX, 0x00010000, 0x00010000,
206 0xac14, 0x000003ff, 0x000000f3,
207 TCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
208 TCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
209 0x0000, 0x00000000, 0x00000000,
210 0x15c0, 0x000c0fc0, 0x000c0400
211 };
212
213 static u32 tahiti_mgcg_cgcg_init[] = {
214 0xc400, 0xffffffff, 0xfffffffc,
215 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
216 | GGI_SH_BROADCAST_WRS,
217 0x9a60, 0xffffffff, 0x00000100,
218 0x92a4, 0xffffffff, 0x00000100,
219 0xc164, 0xffffffff, 0x00000100,
220 0x9774, 0xffffffff, 0x00000100,
221 0x8984, 0xffffffff, 0x06000100,
222 0x8a18, 0xffffffff, 0x00000100,
223 0x92a0, 0xffffffff, 0x00000100,
224 0xc380, 0xffffffff, 0x00000100,
225 0x8b28, 0xffffffff, 0x00000100,
226 0x9144, 0xffffffff, 0x00000100,
227 0x8d88, 0xffffffff, 0x00000100,
228 0x8d8c, 0xffffffff, 0x00000100,
229 0x9030, 0xffffffff, 0x00000100,
230 0x9034, 0xffffffff, 0x00000100,
231 0x9038, 0xffffffff, 0x00000100,
232 0x903c, 0xffffffff, 0x00000100,
233 0xad80, 0xffffffff, 0x00000100,
234 0xac54, 0xffffffff, 0x00000100,
235 0x897c, 0xffffffff, 0x06000100,
236 0x9868, 0xffffffff, 0x00000100,
237 0x9510, 0xffffffff, 0x00000100,
238 0xaf04, 0xffffffff, 0x00000100,
239 0xae04, 0xffffffff, 0x00000100,
240 0x949c, 0xffffffff, 0x00000100,
241 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
242 | GGI_SH_BROADCAST_WRS,
243 0x9160, 0xffffffff, 0x00010000,
244 0x9164, 0xffffffff, 0x00030002,
245 0x9168, 0xffffffff, 0x00040007,
246 0x916c, 0xffffffff, 0x00060005,
247 0x9170, 0xffffffff, 0x00090008,
248 0x9174, 0xffffffff, 0x00020001,
249 0x9178, 0xffffffff, 0x00040003,
250 0x917c, 0xffffffff, 0x00000007,
251 0x9180, 0xffffffff, 0x00060005,
252 0x9184, 0xffffffff, 0x00090008,
253 0x9188, 0xffffffff, 0x00030002,
254 0x918c, 0xffffffff, 0x00050004,
255 0x9190, 0xffffffff, 0x00000008,
256 0x9194, 0xffffffff, 0x00070006,
257 0x9198, 0xffffffff, 0x000a0009,
258 0x919c, 0xffffffff, 0x00040003,
259 0x91a0, 0xffffffff, 0x00060005,
260 0x91a4, 0xffffffff, 0x00000009,
261 0x91a8, 0xffffffff, 0x00080007,
262 0x91ac, 0xffffffff, 0x000b000a,
263 0x91b0, 0xffffffff, 0x00050004,
264 0x91b4, 0xffffffff, 0x00070006,
265 0x91b8, 0xffffffff, 0x0008000b,
266 0x91bc, 0xffffffff, 0x000a0009,
267 0x91c0, 0xffffffff, 0x000d000c,
268 0x91c4, 0xffffffff, 0x00060005,
269 0x91c8, 0xffffffff, 0x00080007,
270 0x91cc, 0xffffffff, 0x0000000b,
271 0x91d0, 0xffffffff, 0x000a0009,
272 0x91d4, 0xffffffff, 0x000d000c,
273 0x91d8, 0xffffffff, 0x00070006,
274 0x91dc, 0xffffffff, 0x00090008,
275 0x91e0, 0xffffffff, 0x0000000c,
276 0x91e4, 0xffffffff, 0x000b000a,
277 0x91e8, 0xffffffff, 0x000e000d,
278 0x91ec, 0xffffffff, 0x00080007,
279 0x91f0, 0xffffffff, 0x000a0009,
280 0x91f4, 0xffffffff, 0x0000000d,
281 0x91f8, 0xffffffff, 0x000c000b,
282 0x91fc, 0xffffffff, 0x000f000e,
283 0x9200, 0xffffffff, 0x00090008,
284 0x9204, 0xffffffff, 0x000b000a,
285 0x9208, 0xffffffff, 0x000c000f,
286 0x920c, 0xffffffff, 0x000e000d,
287 0x9210, 0xffffffff, 0x00110010,
288 0x9214, 0xffffffff, 0x000a0009,
289 0x9218, 0xffffffff, 0x000c000b,
290 0x921c, 0xffffffff, 0x0000000f,
291 0x9220, 0xffffffff, 0x000e000d,
292 0x9224, 0xffffffff, 0x00110010,
293 0x9228, 0xffffffff, 0x000b000a,
294 0x922c, 0xffffffff, 0x000d000c,
295 0x9230, 0xffffffff, 0x00000010,
296 0x9234, 0xffffffff, 0x000f000e,
297 0x9238, 0xffffffff, 0x00120011,
298 0x923c, 0xffffffff, 0x000c000b,
299 0x9240, 0xffffffff, 0x000e000d,
300 0x9244, 0xffffffff, 0x00000011,
301 0x9248, 0xffffffff, 0x0010000f,
302 0x924c, 0xffffffff, 0x00130012,
303 0x9250, 0xffffffff, 0x000d000c,
304 0x9254, 0xffffffff, 0x000f000e,
305 0x9258, 0xffffffff, 0x00100013,
306 0x925c, 0xffffffff, 0x00120011,
307 0x9260, 0xffffffff, 0x00150014,
308 0x9264, 0xffffffff, 0x000e000d,
309 0x9268, 0xffffffff, 0x0010000f,
310 0x926c, 0xffffffff, 0x00000013,
311 0x9270, 0xffffffff, 0x00120011,
312 0x9274, 0xffffffff, 0x00150014,
313 0x9278, 0xffffffff, 0x000f000e,
314 0x927c, 0xffffffff, 0x00110010,
315 0x9280, 0xffffffff, 0x00000014,
316 0x9284, 0xffffffff, 0x00130012,
317 0x9288, 0xffffffff, 0x00160015,
318 0x928c, 0xffffffff, 0x0010000f,
319 0x9290, 0xffffffff, 0x00120011,
320 0x9294, 0xffffffff, 0x00000015,
321 0x9298, 0xffffffff, 0x00140013,
322 0x929c, 0xffffffff, 0x00170016,
323 0x9150, 0xffffffff, 0x96940200,
324 0x8708, 0xffffffff, 0x00900100,
325 0xc478, 0xffffffff, 0x00000080,
326 0xc404, 0xffffffff, 0x0020003f,
327 0x30, 0xffffffff, 0x0000001c,
328 0x34, 0x000f0000, 0x000f0000,
329 0x160c, 0xffffffff, 0x00000100,
330 0x1024, 0xffffffff, 0x00000100,
331 0x102c, 0x00000101, 0x00000000,
332 0x20a8, 0xffffffff, 0x00000104,
333 0x264c, 0x000c0000, 0x000c0000,
334 0x2648, 0x000c0000, 0x000c0000,
335 0x55e4, 0xff000fff, 0x00000100,
336 0x55e8, 0x00000001, 0x00000001,
337 0x2f50, 0x00000001, 0x00000001,
338 0x30cc, 0xc0000fff, 0x00000104,
339 0xc1e4, 0x00000001, 0x00000001,
340 0xd0c0, 0xfffffff0, 0x00000100,
341 0xd8c0, 0xfffffff0, 0x00000100
342 };
343
344 static u32 pitcairn_mgcg_cgcg_init[] = {
345 0xc400, 0xffffffff, 0xfffffffc,
346 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
347 | GGI_SH_BROADCAST_WRS,
348 0x9a60, 0xffffffff, 0x00000100,
349 0x92a4, 0xffffffff, 0x00000100,
350 0xc164, 0xffffffff, 0x00000100,
351 0x9774, 0xffffffff, 0x00000100,
352 0x8984, 0xffffffff, 0x06000100,
353 0x8a18, 0xffffffff, 0x00000100,
354 0x92a0, 0xffffffff, 0x00000100,
355 0xc380, 0xffffffff, 0x00000100,
356 0x8b28, 0xffffffff, 0x00000100,
357 0x9144, 0xffffffff, 0x00000100,
358 0x8d88, 0xffffffff, 0x00000100,
359 0x8d8c, 0xffffffff, 0x00000100,
360 0x9030, 0xffffffff, 0x00000100,
361 0x9034, 0xffffffff, 0x00000100,
362 0x9038, 0xffffffff, 0x00000100,
363 0x903c, 0xffffffff, 0x00000100,
364 0xad80, 0xffffffff, 0x00000100,
365 0xac54, 0xffffffff, 0x00000100,
366 0x897c, 0xffffffff, 0x06000100,
367 0x9868, 0xffffffff, 0x00000100,
368 0x9510, 0xffffffff, 0x00000100,
369 0xaf04, 0xffffffff, 0x00000100,
370 0xae04, 0xffffffff, 0x00000100,
371 0x949c, 0xffffffff, 0x00000100,
372 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
373 | GGI_SH_BROADCAST_WRS,
374 0x9160, 0xffffffff, 0x00010000,
375 0x9164, 0xffffffff, 0x00030002,
376 0x9168, 0xffffffff, 0x00040007,
377 0x916c, 0xffffffff, 0x00060005,
378 0x9170, 0xffffffff, 0x00090008,
379 0x9174, 0xffffffff, 0x00020001,
380 0x9178, 0xffffffff, 0x00040003,
381 0x917c, 0xffffffff, 0x00000007,
382 0x9180, 0xffffffff, 0x00060005,
383 0x9184, 0xffffffff, 0x00090008,
384 0x9188, 0xffffffff, 0x00030002,
385 0x918c, 0xffffffff, 0x00050004,
386 0x9190, 0xffffffff, 0x00000008,
387 0x9194, 0xffffffff, 0x00070006,
388 0x9198, 0xffffffff, 0x000a0009,
389 0x919c, 0xffffffff, 0x00040003,
390 0x91a0, 0xffffffff, 0x00060005,
391 0x91a4, 0xffffffff, 0x00000009,
392 0x91a8, 0xffffffff, 0x00080007,
393 0x91ac, 0xffffffff, 0x000b000a,
394 0x91b0, 0xffffffff, 0x00050004,
395 0x91b4, 0xffffffff, 0x00070006,
396 0x91b8, 0xffffffff, 0x0008000b,
397 0x91bc, 0xffffffff, 0x000a0009,
398 0x91c0, 0xffffffff, 0x000d000c,
399 0x9200, 0xffffffff, 0x00090008,
400 0x9204, 0xffffffff, 0x000b000a,
401 0x9208, 0xffffffff, 0x000c000f,
402 0x920c, 0xffffffff, 0x000e000d,
403 0x9210, 0xffffffff, 0x00110010,
404 0x9214, 0xffffffff, 0x000a0009,
405 0x9218, 0xffffffff, 0x000c000b,
406 0x921c, 0xffffffff, 0x0000000f,
407 0x9220, 0xffffffff, 0x000e000d,
408 0x9224, 0xffffffff, 0x00110010,
409 0x9228, 0xffffffff, 0x000b000a,
410 0x922c, 0xffffffff, 0x000d000c,
411 0x9230, 0xffffffff, 0x00000010,
412 0x9234, 0xffffffff, 0x000f000e,
413 0x9238, 0xffffffff, 0x00120011,
414 0x923c, 0xffffffff, 0x000c000b,
415 0x9240, 0xffffffff, 0x000e000d,
416 0x9244, 0xffffffff, 0x00000011,
417 0x9248, 0xffffffff, 0x0010000f,
418 0x924c, 0xffffffff, 0x00130012,
419 0x9250, 0xffffffff, 0x000d000c,
420 0x9254, 0xffffffff, 0x000f000e,
421 0x9258, 0xffffffff, 0x00100013,
422 0x925c, 0xffffffff, 0x00120011,
423 0x9260, 0xffffffff, 0x00150014,
424 0x9150, 0xffffffff, 0x96940200,
425 0x8708, 0xffffffff, 0x00900100,
426 0xc478, 0xffffffff, 0x00000080,
427 0xc404, 0xffffffff, 0x0020003f,
428 0x30, 0xffffffff, 0x0000001c,
429 0x34, 0x000f0000, 0x000f0000,
430 0x160c, 0xffffffff, 0x00000100,
431 0x1024, 0xffffffff, 0x00000100,
432 0x102c, 0x00000101, 0x00000000,
433 0x20a8, 0xffffffff, 0x00000104,
434 0x55e4, 0xff000fff, 0x00000100,
435 0x55e8, 0x00000001, 0x00000001,
436 0x2f50, 0x00000001, 0x00000001,
437 0x30cc, 0xc0000fff, 0x00000104,
438 0xc1e4, 0x00000001, 0x00000001,
439 0xd0c0, 0xfffffff0, 0x00000100,
440 0xd8c0, 0xfffffff0, 0x00000100
441 };
442
443 static u32 verde_mgcg_cgcg_init[] = {
444 0xc400, 0xffffffff, 0xfffffffc,
445 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
446 | GGI_SH_BROADCAST_WRS,
447 0x9a60, 0xffffffff, 0x00000100,
448 0x92a4, 0xffffffff, 0x00000100,
449 0xc164, 0xffffffff, 0x00000100,
450 0x9774, 0xffffffff, 0x00000100,
451 0x8984, 0xffffffff, 0x06000100,
452 0x8a18, 0xffffffff, 0x00000100,
453 0x92a0, 0xffffffff, 0x00000100,
454 0xc380, 0xffffffff, 0x00000100,
455 0x8b28, 0xffffffff, 0x00000100,
456 0x9144, 0xffffffff, 0x00000100,
457 0x8d88, 0xffffffff, 0x00000100,
458 0x8d8c, 0xffffffff, 0x00000100,
459 0x9030, 0xffffffff, 0x00000100,
460 0x9034, 0xffffffff, 0x00000100,
461 0x9038, 0xffffffff, 0x00000100,
462 0x903c, 0xffffffff, 0x00000100,
463 0xad80, 0xffffffff, 0x00000100,
464 0xac54, 0xffffffff, 0x00000100,
465 0x897c, 0xffffffff, 0x06000100,
466 0x9868, 0xffffffff, 0x00000100,
467 0x9510, 0xffffffff, 0x00000100,
468 0xaf04, 0xffffffff, 0x00000100,
469 0xae04, 0xffffffff, 0x00000100,
470 0x949c, 0xffffffff, 0x00000100,
471 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
472 | GGI_SH_BROADCAST_WRS,
473 0x9160, 0xffffffff, 0x00010000,
474 0x9164, 0xffffffff, 0x00030002,
475 0x9168, 0xffffffff, 0x00040007,
476 0x916c, 0xffffffff, 0x00060005,
477 0x9170, 0xffffffff, 0x00090008,
478 0x9174, 0xffffffff, 0x00020001,
479 0x9178, 0xffffffff, 0x00040003,
480 0x917c, 0xffffffff, 0x00000007,
481 0x9180, 0xffffffff, 0x00060005,
482 0x9184, 0xffffffff, 0x00090008,
483 0x9188, 0xffffffff, 0x00030002,
484 0x918c, 0xffffffff, 0x00050004,
485 0x9190, 0xffffffff, 0x00000008,
486 0x9194, 0xffffffff, 0x00070006,
487 0x9198, 0xffffffff, 0x000a0009,
488 0x919c, 0xffffffff, 0x00040003,
489 0x91a0, 0xffffffff, 0x00060005,
490 0x91a4, 0xffffffff, 0x00000009,
491 0x91a8, 0xffffffff, 0x00080007,
492 0x91ac, 0xffffffff, 0x000b000a,
493 0x91b0, 0xffffffff, 0x00050004,
494 0x91b4, 0xffffffff, 0x00070006,
495 0x91b8, 0xffffffff, 0x0008000b,
496 0x91bc, 0xffffffff, 0x000a0009,
497 0x91c0, 0xffffffff, 0x000d000c,
498 0x9200, 0xffffffff, 0x00090008,
499 0x9204, 0xffffffff, 0x000b000a,
500 0x9208, 0xffffffff, 0x000c000f,
501 0x920c, 0xffffffff, 0x000e000d,
502 0x9210, 0xffffffff, 0x00110010,
503 0x9214, 0xffffffff, 0x000a0009,
504 0x9218, 0xffffffff, 0x000c000b,
505 0x921c, 0xffffffff, 0x0000000f,
506 0x9220, 0xffffffff, 0x000e000d,
507 0x9224, 0xffffffff, 0x00110010,
508 0x9228, 0xffffffff, 0x000b000a,
509 0x922c, 0xffffffff, 0x000d000c,
510 0x9230, 0xffffffff, 0x00000010,
511 0x9234, 0xffffffff, 0x000f000e,
512 0x9238, 0xffffffff, 0x00120011,
513 0x923c, 0xffffffff, 0x000c000b,
514 0x9240, 0xffffffff, 0x000e000d,
515 0x9244, 0xffffffff, 0x00000011,
516 0x9248, 0xffffffff, 0x0010000f,
517 0x924c, 0xffffffff, 0x00130012,
518 0x9250, 0xffffffff, 0x000d000c,
519 0x9254, 0xffffffff, 0x000f000e,
520 0x9258, 0xffffffff, 0x00100013,
521 0x925c, 0xffffffff, 0x00120011,
522 0x9260, 0xffffffff, 0x00150014,
523 0x9150, 0xffffffff, 0x96940200,
524 0x8708, 0xffffffff, 0x00900100,
525 0xc478, 0xffffffff, 0x00000080,
526 0xc404, 0xffffffff, 0x0020003f,
527 0x30, 0xffffffff, 0x0000001c,
528 0x34, 0x000f0000, 0x000f0000,
529 0x160c, 0xffffffff, 0x00000100,
530 0x1024, 0xffffffff, 0x00000100,
531 0x102c, 0x00000101, 0x00000000,
532 0x20a8, 0xffffffff, 0x00000104,
533 0x264c, 0x000c0000, 0x000c0000,
534 0x2648, 0x000c0000, 0x000c0000,
535 0x55e4, 0xff000fff, 0x00000100,
536 0x55e8, 0x00000001, 0x00000001,
537 0x2f50, 0x00000001, 0x00000001,
538 0x30cc, 0xc0000fff, 0x00000104,
539 0xc1e4, 0x00000001, 0x00000001,
540 0xd0c0, 0xfffffff0, 0x00000100,
541 0xd8c0, 0xfffffff0, 0x00000100
542 };
543
544 static u32 oland_mgcg_cgcg_init[] =
545 {
546 0xc400, 0xffffffff, 0xfffffffc,
547 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
548 | GGI_SH_BROADCAST_WRS,
549 0x9a60, 0xffffffff, 0x00000100,
550 0x92a4, 0xffffffff, 0x00000100,
551 0xc164, 0xffffffff, 0x00000100,
552 0x9774, 0xffffffff, 0x00000100,
553 0x8984, 0xffffffff, 0x06000100,
554 0x8a18, 0xffffffff, 0x00000100,
555 0x92a0, 0xffffffff, 0x00000100,
556 0xc380, 0xffffffff, 0x00000100,
557 0x8b28, 0xffffffff, 0x00000100,
558 0x9144, 0xffffffff, 0x00000100,
559 0x8d88, 0xffffffff, 0x00000100,
560 0x8d8c, 0xffffffff, 0x00000100,
561 0x9030, 0xffffffff, 0x00000100,
562 0x9034, 0xffffffff, 0x00000100,
563 0x9038, 0xffffffff, 0x00000100,
564 0x903c, 0xffffffff, 0x00000100,
565 0xad80, 0xffffffff, 0x00000100,
566 0xac54, 0xffffffff, 0x00000100,
567 0x897c, 0xffffffff, 0x06000100,
568 0x9868, 0xffffffff, 0x00000100,
569 0x9510, 0xffffffff, 0x00000100,
570 0xaf04, 0xffffffff, 0x00000100,
571 0xae04, 0xffffffff, 0x00000100,
572 0x949c, 0xffffffff, 0x00000100,
573 GRBM_GFX_IDX, 0xffffffff, GGI_SE_BROADCAST_WRS | GGI_INST_BROADCAST_WRS
574 | GGI_SH_BROADCAST_WRS,
575 0x9160, 0xffffffff, 0x00010000,
576 0x9164, 0xffffffff, 0x00030002,
577 0x9168, 0xffffffff, 0x00040007,
578 0x916c, 0xffffffff, 0x00060005,
579 0x9170, 0xffffffff, 0x00090008,
580 0x9174, 0xffffffff, 0x00020001,
581 0x9178, 0xffffffff, 0x00040003,
582 0x917c, 0xffffffff, 0x00000007,
583 0x9180, 0xffffffff, 0x00060005,
584 0x9184, 0xffffffff, 0x00090008,
585 0x9188, 0xffffffff, 0x00030002,
586 0x918c, 0xffffffff, 0x00050004,
587 0x9190, 0xffffffff, 0x00000008,
588 0x9194, 0xffffffff, 0x00070006,
589 0x9198, 0xffffffff, 0x000a0009,
590 0x919c, 0xffffffff, 0x00040003,
591 0x91a0, 0xffffffff, 0x00060005,
592 0x91a4, 0xffffffff, 0x00000009,
593 0x91a8, 0xffffffff, 0x00080007,
594 0x91ac, 0xffffffff, 0x000b000a,
595 0x91b0, 0xffffffff, 0x00050004,
596 0x91b4, 0xffffffff, 0x00070006,
597 0x91b8, 0xffffffff, 0x0008000b,
598 0x91bc, 0xffffffff, 0x000a0009,
599 0x91c0, 0xffffffff, 0x000d000c,
600 0x91c4, 0xffffffff, 0x00060005,
601 0x91c8, 0xffffffff, 0x00080007,
602 0x91cc, 0xffffffff, 0x0000000b,
603 0x91d0, 0xffffffff, 0x000a0009,
604 0x91d4, 0xffffffff, 0x000d000c,
605 0x9150, 0xffffffff, 0x96940200,
606 0x8708, 0xffffffff, 0x00900100,
607 0xc478, 0xffffffff, 0x00000080,
608 0xc404, 0xffffffff, 0x0020003f,
609 0x30, 0xffffffff, 0x0000001c,
610 0x34, 0x000f0000, 0x000f0000,
611 0x160c, 0xffffffff, 0x00000100,
612 0x1024, 0xffffffff, 0x00000100,
613 0x102c, 0x00000101, 0x00000000,
614 0x20a8, 0xffffffff, 0x00000104,
615 0x264c, 0x000c0000, 0x000c0000,
616 0x2648, 0x000c0000, 0x000c0000,
617 0x55e4, 0xff000fff, 0x00000100,
618 0x55e8, 0x00000001, 0x00000001,
619 0x2f50, 0x00000001, 0x00000001,
620 0x30cc, 0xc0000fff, 0x00000104,
621 0xc1e4, 0x00000001, 0x00000001,
622 0xd0c0, 0xfffffff0, 0x00000100,
623 0xd8c0, 0xfffffff0, 0x00000100
624 };
625
626 static u32 verde_pg_init[] = {
627 0x353c, 0xffffffff, 0x40000,
628 0x3538, 0xffffffff, 0x200010ff,
629 0x353c, 0xffffffff, 0x0,
630 0x353c, 0xffffffff, 0x0,
631 0x353c, 0xffffffff, 0x0,
632 0x353c, 0xffffffff, 0x0,
633 0x353c, 0xffffffff, 0x0,
634 0x353c, 0xffffffff, 0x7007,
635 0x3538, 0xffffffff, 0x300010ff,
636 0x353c, 0xffffffff, 0x0,
637 0x353c, 0xffffffff, 0x0,
638 0x353c, 0xffffffff, 0x0,
639 0x353c, 0xffffffff, 0x0,
640 0x353c, 0xffffffff, 0x0,
641 0x353c, 0xffffffff, 0x400000,
642 0x3538, 0xffffffff, 0x100010ff,
643 0x353c, 0xffffffff, 0x0,
644 0x353c, 0xffffffff, 0x0,
645 0x353c, 0xffffffff, 0x0,
646 0x353c, 0xffffffff, 0x0,
647 0x353c, 0xffffffff, 0x0,
648 0x353c, 0xffffffff, 0x120200,
649 0x3538, 0xffffffff, 0x500010ff,
650 0x353c, 0xffffffff, 0x0,
651 0x353c, 0xffffffff, 0x0,
652 0x353c, 0xffffffff, 0x0,
653 0x353c, 0xffffffff, 0x0,
654 0x353c, 0xffffffff, 0x0,
655 0x353c, 0xffffffff, 0x1e1e16,
656 0x3538, 0xffffffff, 0x600010ff,
657 0x353c, 0xffffffff, 0x0,
658 0x353c, 0xffffffff, 0x0,
659 0x353c, 0xffffffff, 0x0,
660 0x353c, 0xffffffff, 0x0,
661 0x353c, 0xffffffff, 0x0,
662 0x353c, 0xffffffff, 0x171f1e,
663 0x3538, 0xffffffff, 0x700010ff,
664 0x353c, 0xffffffff, 0x0,
665 0x353c, 0xffffffff, 0x0,
666 0x353c, 0xffffffff, 0x0,
667 0x353c, 0xffffffff, 0x0,
668 0x353c, 0xffffffff, 0x0,
669 0x353c, 0xffffffff, 0x0,
670 0x3538, 0xffffffff, 0x9ff,
671 0x3500, 0xffffffff, 0x0,
672 0x3504, 0xffffffff, 0x10000800,
673 0x3504, 0xffffffff, 0xf,
674 0x3504, 0xffffffff, 0xf,
675 0x3500, 0xffffffff, 0x4,
676 0x3504, 0xffffffff, 0x1000051e,
677 0x3504, 0xffffffff, 0xffff,
678 0x3504, 0xffffffff, 0xffff,
679 0x3500, 0xffffffff, 0x8,
680 0x3504, 0xffffffff, 0x80500,
681 0x3500, 0xffffffff, 0x12,
682 0x3504, 0xffffffff, 0x9050c,
683 0x3500, 0xffffffff, 0x1d,
684 0x3504, 0xffffffff, 0xb052c,
685 0x3500, 0xffffffff, 0x2a,
686 0x3504, 0xffffffff, 0x1053e,
687 0x3500, 0xffffffff, 0x2d,
688 0x3504, 0xffffffff, 0x10546,
689 0x3500, 0xffffffff, 0x30,
690 0x3504, 0xffffffff, 0xa054e,
691 0x3500, 0xffffffff, 0x3c,
692 0x3504, 0xffffffff, 0x1055f,
693 0x3500, 0xffffffff, 0x3f,
694 0x3504, 0xffffffff, 0x10567,
695 0x3500, 0xffffffff, 0x42,
696 0x3504, 0xffffffff, 0x1056f,
697 0x3500, 0xffffffff, 0x45,
698 0x3504, 0xffffffff, 0x10572,
699 0x3500, 0xffffffff, 0x48,
700 0x3504, 0xffffffff, 0x20575,
701 0x3500, 0xffffffff, 0x4c,
702 0x3504, 0xffffffff, 0x190801,
703 0x3500, 0xffffffff, 0x67,
704 0x3504, 0xffffffff, 0x1082a,
705 0x3500, 0xffffffff, 0x6a,
706 0x3504, 0xffffffff, 0x1b082d,
707 0x3500, 0xffffffff, 0x87,
708 0x3504, 0xffffffff, 0x310851,
709 0x3500, 0xffffffff, 0xba,
710 0x3504, 0xffffffff, 0x891,
711 0x3500, 0xffffffff, 0xbc,
712 0x3504, 0xffffffff, 0x893,
713 0x3500, 0xffffffff, 0xbe,
714 0x3504, 0xffffffff, 0x20895,
715 0x3500, 0xffffffff, 0xc2,
716 0x3504, 0xffffffff, 0x20899,
717 0x3500, 0xffffffff, 0xc6,
718 0x3504, 0xffffffff, 0x2089d,
719 0x3500, 0xffffffff, 0xca,
720 0x3504, 0xffffffff, 0x8a1,
721 0x3500, 0xffffffff, 0xcc,
722 0x3504, 0xffffffff, 0x8a3,
723 0x3500, 0xffffffff, 0xce,
724 0x3504, 0xffffffff, 0x308a5,
725 0x3500, 0xffffffff, 0xd3,
726 0x3504, 0xffffffff, 0x6d08cd,
727 0x3500, 0xffffffff, 0x142,
728 0x3504, 0xffffffff, 0x2000095a,
729 0x3504, 0xffffffff, 0x1,
730 0x3500, 0xffffffff, 0x144,
731 0x3504, 0xffffffff, 0x301f095b,
732 0x3500, 0xffffffff, 0x165,
733 0x3504, 0xffffffff, 0xc094d,
734 0x3500, 0xffffffff, 0x173,
735 0x3504, 0xffffffff, 0xf096d,
736 0x3500, 0xffffffff, 0x184,
737 0x3504, 0xffffffff, 0x15097f,
738 0x3500, 0xffffffff, 0x19b,
739 0x3504, 0xffffffff, 0xc0998,
740 0x3500, 0xffffffff, 0x1a9,
741 0x3504, 0xffffffff, 0x409a7,
742 0x3500, 0xffffffff, 0x1af,
743 0x3504, 0xffffffff, 0xcdc,
744 0x3500, 0xffffffff, 0x1b1,
745 0x3504, 0xffffffff, 0x800,
746 0x3508, 0xffffffff, 0x6c9b2000,
747 0x3510, 0xfc00, 0x2000,
748 0x3544, 0xffffffff, 0xfc0,
749 0x28d4, 0x00000100, 0x100
750 };
751
752 static void sequence_program(struct pci_dev *dev, u32 *regs, u32 array_sz)
753 {
754 u32 tmp;
755 u32 reg;
756 u32 and_mask;
757 u32 or_mask;
758 u16 i;
759
760 if (array_sz % 3)
761 return;
762
763 for (i = 0; i < array_sz; i +=3) {
764 reg = regs[i + 0];
765 and_mask = regs[i + 1];
766 or_mask = regs[i + 2];
767
768 if (and_mask == 0xffffffff) {
769 tmp = or_mask;
770 } else {
771 tmp = rr32(dev, reg);
772 tmp &= ~and_mask;
773 tmp |= or_mask;
774 }
775 wr32(dev, tmp, reg);
776 }
777 }
778
779 static void init(struct pci_dev *dev)
780 {
781 struct dev_drv_data *dd;
782
783 dd = pci_get_drvdata(dev);
784
785 switch (dd->family) {
786 case TAHITI:
787 tahiti_golden_regs_0[12 * 3] = PA_CL_ENHANCE;
788 tahiti_golden_regs_0[12 * 3 + 1] = 0xf000001f;
789 tahiti_golden_regs_0[12 * 3 + 2] = PCE_CLIP_VTX_REORDER_ENA
790 | set(PCE_CLIP_SEQ_N, 3);
791
792 tahiti_golden_regs_0[13 * 3] = PA_SC_FORCE_EOV_MAX_CNTS;
793 tahiti_golden_regs_0[13 * 3 + 1] = 0xffffffff;
794 tahiti_golden_regs_0[13 * 3 + 2] =
795 set(PSFEMC_FORCE_EOV_MAX_CLK_CNT, 0xffff)
796 | set(PSFEMC_FORCE_EOV_MAX_REZ_CNT, 0xff);
797
798 tahiti_golden_regs_0[15 * 3] = PA_SC_MODE_CTL_1;
799 tahiti_golden_regs_0[15 * 3 + 1] = 0x07ffffff;
800 tahiti_golden_regs_0[15 * 3 + 2] =
801 set(PSMC_OUT_OF_ORDER_WATER_MARK, 4)
802 | PSMC_OUT_OF_ORDER_PRIM_ENA
803 | PSMC_FORCE_EOV_REZ_ENA
804 | PSMC_FORCE_EOV_CNTDWN_ENA;
805
806 tahiti_golden_regs_0[16 * 3] = PA_SC_RASTER_CFG;
807 tahiti_golden_regs_0[16 * 3 + 1] = 0x3f3f3fff;
808 tahiti_golden_regs_0[16 * 3 + 2] =
809 set(PSRC_RB_MAP_PKR_0, PSRC_RB_MAP_2)
810 | set(PSRC_RB_MAP_PKR_1, PSRC_RB_MAP_2)
811 | set(PSRC_RB_XSEL_2, PSRC_RB_XSEL_2_2)
812 | PSRC_RB_XSEL
813 | set(PSRC_PKR_MAP, PSRC_PKR_MAP_2)
814 | set(PSRC_PKR_XSEL, PSRC_PKR_XSEL_0)
815 | set(PSRC_PKR_YSEL, PSRC_PKR_YSEL_1)
816 | set(PSRC_SC_MAP, PSRC_SC_MAP_0)
817 | set(PSRC_SC_XSEL, PSRC_SC_XSEL_8_WIDE_TILE)
818 | set(PSRC_SC_YSEL, PSRC_SC_YSEL_8_WIDE_TILE)
819 | set(PSRC_SE_MAP, PSRC_SE_MAP_2)
820 | set(PSRC_SE_XSEL, PSRC_SE_XSEL_32_WIDE_TILE)
821 | set(PSRC_SE_YSEL, PSRC_SE_YSEL_32_WIDE_TILE);
822
823 tahiti_golden_regs_0[28 * 3] = VGT_GS_VTX_REUSE;
824 tahiti_golden_regs_0[28 * 3 + 1] = 0x0000001f;
825 tahiti_golden_regs_0[28 * 3 + 2] =
826 set(VGVR_VGT_GS_VTX_REUSE, 16);
827
828 tahiti_golden_regs_0[29 * 3] = VM_CTX_0_CTL_0;
829 tahiti_golden_regs_0[29 * 3 + 1] = 0x20000000;
830 tahiti_golden_regs_0[29 * 3 + 2] = set(VCC_PT_DEPTH, 0)
831 | VCC_RANGE_PROTECTION_FAULT_ENA_INT
832 | VCC_RNG_PROTECTION_FAULT_ENA_DEFAULT
833 | VCC_DUMMY_PAGE_PROTECTION_FAULT_ENA_INT
834 | VCC_DUMMY_PAGE_PROTECTION_FAULT_ENA_DEFAULT
835 | VCC_PDE0_PROTECTION_FAULT_ENA_INT
836 | VCC_PDE0_PROTECTION_FAULT_ENA_DEFAULT
837 | BIT(11)
838 | VCC_VALID_PROTECTION_FAULT_ENA_INT
839 | VCC_VALID_PROTECTION_FAULT_ENA_DEFAULT
840 | BIT(14)
841 | VCC_RD_PROTECTION_FAULT_ENA_INT
842 | VCC_RD_PROTECTION_FAULT_ENA_DEFAULT
843 | BIT(17)
844 | VCC_WR_PROTECTION_FAULT_ENA_INT
845 | VCC_WR_PROTECTION_FAULT_ENA_DEFAULT
846 | 0x20f00000;
847 break;
848 case PITCAIRN:
849 pitcairn_golden_regs[12 * 3] = PA_CL_ENHANCE;
850 pitcairn_golden_regs[12 * 3 + 1] = 0xf000001f;
851 pitcairn_golden_regs[12 * 3 + 2] = PCE_CLIP_VTX_REORDER_ENA
852 | set(PCE_CLIP_SEQ_N, 3);
853
854 pitcairn_golden_regs[13 * 3] = PA_SC_FORCE_EOV_MAX_CNTS;
855 pitcairn_golden_regs[13 * 3 + 1] = 0xffffffff;
856 pitcairn_golden_regs[13 * 3 + 2] =
857 set(PSFEMC_FORCE_EOV_MAX_CLK_CNT, 0xffff)
858 | set(PSFEMC_FORCE_EOV_MAX_REZ_CNT, 0xff);
859
860 pitcairn_golden_regs[15 * 3] = PA_SC_MODE_CTL_1;
861 pitcairn_golden_regs[15 * 3 + 1] = 0x07ffffff;
862 pitcairn_golden_regs[15 * 3 + 2] =
863 set(PSMC_OUT_OF_ORDER_WATER_MARK, 4)
864 | PSMC_OUT_OF_ORDER_PRIM_ENA
865 | PSMC_FORCE_EOV_REZ_ENA
866 | PSMC_FORCE_EOV_CNTDWN_ENA;
867
868 pitcairn_golden_regs[16 * 3] = PA_SC_RASTER_CFG;
869 pitcairn_golden_regs[16 * 3 + 1] = 0x3f3f3fff;
870 pitcairn_golden_regs[16 * 3 + 2] =
871 set(PSRC_RB_MAP_PKR_0, PSRC_RB_MAP_2)
872 | set(PSRC_RB_MAP_PKR_1, PSRC_RB_MAP_2)
873 | set(PSRC_RB_XSEL_2, PSRC_RB_XSEL_2_2)
874 | PSRC_RB_XSEL
875 | set(PSRC_PKR_MAP, PSRC_PKR_MAP_2)
876 | set(PSRC_PKR_XSEL, PSRC_PKR_XSEL_0)
877 | set(PSRC_PKR_YSEL, PSRC_PKR_YSEL_1)
878 | set(PSRC_SC_MAP, PSRC_SC_MAP_0)
879 | set(PSRC_SC_XSEL, PSRC_SC_XSEL_8_WIDE_TILE)
880 | set(PSRC_SC_YSEL, PSRC_SC_YSEL_8_WIDE_TILE)
881 | set(PSRC_SE_MAP, PSRC_SE_MAP_2)
882 | set(PSRC_SE_XSEL, PSRC_SE_XSEL_32_WIDE_TILE)
883 | set(PSRC_SE_YSEL, PSRC_SE_YSEL_32_WIDE_TILE);
884
885 pitcairn_golden_regs[25 * 3] = VGT_GS_VTX_REUSE;
886 pitcairn_golden_regs[25 * 3 + 1] = 0x0000001f;
887 pitcairn_golden_regs[25 * 3 + 2] =
888 set(VGVR_VGT_GS_VTX_REUSE, 16);
889 break;
890 case VERDE:
891 verde_golden_regs[18 * 3] = PA_CL_ENHANCE;
892 verde_golden_regs[18 * 3 + 1] = 0xf000001f;
893 verde_golden_regs[18 * 3 + 2] = PCE_CLIP_VTX_REORDER_ENA
894 | set(PCE_CLIP_SEQ_N, 3);
895 verde_golden_regs[19 * 3] = PA_CL_ENHANCE;
896 verde_golden_regs[19 * 3 + 1] = 0xf000001f;
897 verde_golden_regs[19 * 3 + 2] = verde_golden_regs[18 * 3 + 2];
898 verde_golden_regs[20 * 3] = PA_CL_ENHANCE;
899 verde_golden_regs[20 * 3 + 1] = 0xf000001f;
900 verde_golden_regs[20 * 3 + 2] = verde_golden_regs[18 * 3 + 2];
901
902 verde_golden_regs[21 * 3] = PA_SC_FORCE_EOV_MAX_CNTS;
903 verde_golden_regs[21 * 3 + 1] = 0xffffffff;
904 verde_golden_regs[21 * 3 + 2] =
905 set(PSFEMC_FORCE_EOV_MAX_CLK_CNT, 0xffff)
906 | set(PSFEMC_FORCE_EOV_MAX_REZ_CNT, 0xff);
907
908 verde_golden_regs[23 * 3] = PA_SC_MODE_CTL_1;
909 verde_golden_regs[23 * 3 + 1] = 0x07ffffff;
910 verde_golden_regs[23 * 3 + 2] =
911 set(PSMC_OUT_OF_ORDER_WATER_MARK, 4)
912 | PSMC_OUT_OF_ORDER_PRIM_ENA
913 | PSMC_FORCE_EOV_REZ_ENA
914 | PSMC_FORCE_EOV_CNTDWN_ENA;
915
916 verde_golden_regs[24 * 3] = PA_SC_RASTER_CFG;
917 verde_golden_regs[24 * 3 + 1] = 0x3f3f3fff;
918 verde_golden_regs[24 * 3 + 2] =
919 set(PSRC_RB_MAP_PKR_0, PSRC_RB_MAP_2)
920 | set(PSRC_RB_MAP_PKR_1, PSRC_RB_MAP_2)
921 | set(PSRC_RB_XSEL_2, PSRC_RB_XSEL_2_0)
922 | PSRC_RB_XSEL
923 | set(PSRC_PKR_MAP, PSRC_PKR_MAP_2)
924 | set(PSRC_PKR_XSEL, PSRC_PKR_XSEL_0)
925 | set(PSRC_PKR_YSEL, PSRC_PKR_YSEL_1)
926 | set(PSRC_SC_MAP, PSRC_SC_MAP_0)
927 | set(PSRC_SC_XSEL, PSRC_SC_XSEL_8_WIDE_TILE)
928 | set(PSRC_SC_YSEL, PSRC_SC_YSEL_8_WIDE_TILE)
929 | set(PSRC_SE_MAP, PSRC_SE_MAP_0)
930 | set(PSRC_SE_XSEL,PSRC_SE_XSEL_8_WIDE_TILE)
931 | set(PSRC_SE_YSEL, PSRC_SE_YSEL_8_WIDE_TILE);
932 verde_golden_regs[25 * 3] = PA_SC_RASTER_CFG;
933 verde_golden_regs[25 * 3 + 1] = 0x3f3f3fff;
934 verde_golden_regs[25 * 3 + 2] = verde_golden_regs[24 * 3 + 2];
935 verde_golden_regs[26 * 3] = PA_SC_RASTER_CFG;
936 verde_golden_regs[26 * 3 + 1] = 0x3f3f3fff;
937 verde_golden_regs[26 * 3 + 2] = verde_golden_regs[24 * 3 + 2];
938
939 verde_golden_regs[48 * 3] = VGT_GS_VTX_REUSE;
940 verde_golden_regs[48 * 3 + 1] = 0x0000001f;
941 verde_golden_regs[48 * 3 + 2] = set(VGVR_VGT_GS_VTX_REUSE, 16);
942 verde_golden_regs[49 * 3] = VGT_GS_VTX_REUSE;
943 verde_golden_regs[49 * 3 + 1] = 0x0000001f;
944 verde_golden_regs[49 * 3 + 2] = set(VGVR_VGT_GS_VTX_REUSE, 16);
945 verde_golden_regs[50 * 3] = VGT_GS_VTX_REUSE;
946 verde_golden_regs[50 * 3 + 1] = 0x0000001f;
947 verde_golden_regs[50 * 3 + 2] = set(VGVR_VGT_GS_VTX_REUSE, 16);
948 break;
949 case OLAND:
950 oland_golden_regs[12 * 3] = PA_CL_ENHANCE;
951 oland_golden_regs[12 * 3 + 1] = 0xf000001f;
952 oland_golden_regs[12 * 3 + 2] = PCE_CLIP_VTX_REORDER_ENA
953 | set(PCE_CLIP_SEQ_N, 3);
954
955 oland_golden_regs[13 * 3] = PA_SC_FORCE_EOV_MAX_CNTS;
956 oland_golden_regs[13 * 3 + 1] = 0xffffffff;
957 oland_golden_regs[13 * 3 + 2] =
958 set(PSFEMC_FORCE_EOV_MAX_CLK_CNT, 0xffff)
959 | set(PSFEMC_FORCE_EOV_MAX_REZ_CNT, 0xff);
960
961 oland_golden_regs[15 * 3] = PA_SC_MODE_CTL_1;
962 oland_golden_regs[15 * 3 + 1] = 0x07ffffff;
963 oland_golden_regs[15 * 3 + 2] =
964 set(PSMC_OUT_OF_ORDER_WATER_MARK, 4)
965 | PSMC_OUT_OF_ORDER_PRIM_ENA
966 | PSMC_FORCE_EOV_REZ_ENA
967 | PSMC_FORCE_EOV_CNTDWN_ENA;
968
969 oland_golden_regs[16 * 3] = PA_SC_RASTER_CFG;
970 oland_golden_regs[16 * 3 + 1] = 0x3f3f3fff;
971 oland_golden_regs[16 * 3 + 2] =
972 set(PSRC_RB_MAP_PKR_0, PSRC_RB_MAP_2)
973 | set(PSRC_RB_MAP_PKR_1, PSRC_RB_MAP_0)
974 | set(PSRC_RB_XSEL_2, PSRC_RB_XSEL_2_0)
975 | PSRC_RB_YSEL
976 | set(PSRC_PKR_MAP, PSRC_PKR_MAP_2)
977 | set(PSRC_PKR_XSEL, PSRC_PKR_XSEL_0)
978 | set(PSRC_PKR_YSEL, PSRC_PKR_YSEL_0)
979 | set(PSRC_SC_MAP, PSRC_SC_MAP_0)
980 | set(PSRC_SC_XSEL, PSRC_SC_XSEL_8_WIDE_TILE)
981 | set(PSRC_SC_YSEL, PSRC_SC_YSEL_8_WIDE_TILE)
982 | set(PSRC_SE_MAP, PSRC_SE_MAP_0)
983 | set(PSRC_SE_XSEL,PSRC_SE_XSEL_8_WIDE_TILE)
984 | set(PSRC_SE_YSEL, PSRC_SE_YSEL_8_WIDE_TILE);
985
986 oland_golden_regs[25 * 3] = VGT_GS_VTX_REUSE;
987 oland_golden_regs[25 * 3 + 1] = 0x0000001f;
988 oland_golden_regs[25 * 3 + 2] = set(VGVR_VGT_GS_VTX_REUSE, 16);
989 break;
990 default:
991 /* XXX: HAINAN ? */
992 break;
993 }
994 }
995
996 static void program(struct pci_dev *dev)
997 {
998 struct dev_drv_data *dd;
999
1000 dd = pci_get_drvdata(dev);
1001
1002 switch (dd->family) {
1003 case TAHITI:
1004 sequence_program(dev, tahiti_golden_regs_0,
1005 ARRAY_SIZE(tahiti_golden_regs_0));
1006 sequence_program(dev, tahiti_golden_rlc_regs,
1007 ARRAY_SIZE(tahiti_golden_rlc_regs));
1008 sequence_program(dev, tahiti_mgcg_cgcg_init,
1009 ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1010 sequence_program(dev, tahiti_golden_regs_1,
1011 ARRAY_SIZE(tahiti_golden_regs_1));
1012 break;
1013 case PITCAIRN:
1014 sequence_program(dev, pitcairn_golden_regs,
1015 ARRAY_SIZE(pitcairn_golden_regs));
1016 sequence_program(dev, pitcairn_golden_rlc_regs,
1017 ARRAY_SIZE(pitcairn_golden_rlc_regs));
1018 sequence_program(dev, pitcairn_mgcg_cgcg_init,
1019 ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1020 break;
1021 case VERDE:
1022 sequence_program(dev, verde_golden_regs,
1023 ARRAY_SIZE(verde_golden_regs));
1024 sequence_program(dev, verde_golden_rlc_regs,
1025 ARRAY_SIZE(verde_golden_rlc_regs));
1026 sequence_program(dev, verde_mgcg_cgcg_init,
1027 ARRAY_SIZE(verde_mgcg_cgcg_init));
1028 sequence_program(dev, verde_pg_init,
1029 ARRAY_SIZE(verde_pg_init));
1030 break;
1031 case OLAND:
1032 sequence_program(dev, oland_golden_regs,
1033 ARRAY_SIZE(oland_golden_regs));
1034 sequence_program(dev, oland_golden_rlc_regs,
1035 ARRAY_SIZE(oland_golden_rlc_regs));
1036 sequence_program(dev, oland_mgcg_cgcg_init,
1037 ARRAY_SIZE(oland_mgcg_cgcg_init));
1038 break;
1039 default:
1040 /* XXX: HAINAN ? */
1041 break;
1042 }
1043 }
1044
1045 void golden_regs(struct pci_dev *dev)
1046 {
1047 init(dev);
1048 program(dev);
1049 }
File drivers/gpu/alga/amd/si/golden.h copied from file include/alga/alga.h (similarity 68%) (mode: 100644) (index 5ff4816..92380ff)
1 #ifndef _ALGA_H
2 #define _ALGA_H
1 #ifndef GOLDEN_H
2 #define GOLDEN_H
3 3 /* /*
4 4 author Sylvain Bertrand <digital.ragnarok@gmail.com> author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 #define ALGA_ERR 900
8 void golden_regs(struct pci_dev *dev);
9 9 #endif #endif
File drivers/gpu/alga/amd/si/gpu/regs_cfg.h changed (mode: 100644) (index f29b3b9..5ecf28c)
203 203 #define PSLSS_CUR_CNT 0x0000ff00 #define PSLSS_CUR_CNT 0x0000ff00
204 204
205 205 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
206 #define PSFEMC_FORCE_EOV_MAX_CLK_CNT 0xffffffff
206 #define PSFEMC_FORCE_EOV_MAX_CLK_CNT 0x0000ffff
207 207 #define PSFEMC_FORCE_EOV_MAX_REZ_CNT 0xffff0000 #define PSFEMC_FORCE_EOV_MAX_REZ_CNT 0xffff0000
208 208
209 209 #define PA_SC_FIFO_SZ 0x8bcc #define PA_SC_FIFO_SZ 0x8bcc
 
218 218
219 219 #define SPI_STATIC_THD_MGMT_2 0x90e8 #define SPI_STATIC_THD_MGMT_2 0x90e8
220 220
221 #define SPI_CFG_CTL_0 0x9100
222 #define SCC_GPR_WR_PRIORITY 0x001fffff
223 #define SCC_EXP_PRIORITY_ORDER 0x00e00000
224 #define SCC_ENA_SQG_TOP_EVENTS BIT(24)
225 #define SCC_EN_SQG_BOP_EVENTS BIT(25)
226 #define SCC_RSRC_MGMT_RESET BIT(26)
227
221 228 #define SPI_CFG_CTL_1 0x913c #define SPI_CFG_CTL_1 0x913c
222 229 #define SCC_VTX_DONE_DELAY 0x0000000f #define SCC_VTX_DONE_DELAY 0x0000000f
223 230 #define SCC_DELAY_14_CLKS 0x0 #define SCC_DELAY_14_CLKS 0x0
 
241 248 #define SCC_PC_LIMIT_STRICT BIT(7) #define SCC_PC_LIMIT_STRICT BIT(7)
242 249 #define SCC_PC_LIMIT_SZ 0xffff0000 #define SCC_PC_LIMIT_SZ 0xffff0000
243 250
251 #define TA_CTL_AUX 0x9508
252
244 253 /* related to GC_USER_RB_BACKEND_DIS */ /* related to GC_USER_RB_BACKEND_DIS */
245 254 #define CC_RB_BACKEND_DIS 0x98f4 #define CC_RB_BACKEND_DIS 0x98f4
246 255 #define CRBD_BACKEND_DIS_VALID BIT(0) #define CRBD_BACKEND_DIS_VALID BIT(0)
 
350 359 /* related to CC_RB_BACKEND_DIS */ /* related to CC_RB_BACKEND_DIS */
351 360 #define GC_USER_RB_BACKEND_DIS 0x9b7c #define GC_USER_RB_BACKEND_DIS 0x9b7c
352 361 #define GURBD_BACKEND_DIS 0x00ff0000 #define GURBD_BACKEND_DIS 0x00ff0000
362
363 #define TCP_CHAN_STEER_LO 0xac0c
364 #define TCP_CHAN_STEER_HI 0xac10
353 365 #endif #endif
File drivers/gpu/alga/amd/si/gpu/regs_ctx.h changed (mode: 100644) (index 63aad21..5423750)
967 967 #define PSMC_FORCE_EOV_CNTDWN_ENA BIT(25) #define PSMC_FORCE_EOV_CNTDWN_ENA BIT(25)
968 968 #define PSMC_FORCE_EOV_REZ_ENA BIT(26) #define PSMC_FORCE_EOV_REZ_ENA BIT(26)
969 969 #define PSMC_OUT_OF_ORDER_PRIM_ENA BIT(27) #define PSMC_OUT_OF_ORDER_PRIM_ENA BIT(27)
970 #define PSMC_OUT_OF_ORDER_WATER_MARK BIT(28)
970 #define PSMC_OUT_OF_ORDER_WATER_MARK 0x70000000
971 971
972 972 #define VGT_PRIM_ID_ENA 0x28a84 #define VGT_PRIM_ID_ENA 0x28a84
973 973 #define VPIE_PRIM_ID_ENA BIT(0) #define VPIE_PRIM_ID_ENA BIT(0)
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index cb4c9b5..84a1ab6)
1 #ifndef _REGS_H
2 #define _REGS_H
1 #ifndef REGS_H
2 #define REGS_H
3 3 /* /*
4 4 author Sylvain Bertrand <digital.ragnarok@gmail.com> author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
 
... ... static inline u32 get(u32 mask, u32 v)
58 58 #define VLS_L2_BUSY BIT(0) #define VLS_L2_BUSY BIT(0)
59 59
60 60 #define VM_CTX_0_CTL_0 0x1410 #define VM_CTX_0_CTL_0 0x1410
61 #define VCC_ENA_CTX BIT(0)
62 #define VCC_PT_DEPTH 0x00000006
63 #define VCC_RNG_PROTECTION_FAULT_ENA_DEFAULT BIT(4)
61 #define VCC_ENA_CTX BIT(0)
62 #define VCC_PT_DEPTH 0x00000006
63 #define VCC_RANGE_PROTECTION_FAULT_ENA_INT BIT(3)
64 #define VCC_RNG_PROTECTION_FAULT_ENA_DEFAULT BIT(4)
65 #define VCC_DUMMY_PAGE_PROTECTION_FAULT_ENA_INT BIT(6)
66 #define VCC_DUMMY_PAGE_PROTECTION_FAULT_ENA_DEFAULT BIT(7)
67 #define VCC_PDE0_PROTECTION_FAULT_ENA_INT BIT(9)
68 #define VCC_PDE0_PROTECTION_FAULT_ENA_DEFAULT BIT(10)
69 #define VCC_VALID_PROTECTION_FAULT_ENA_INT BIT(12)
70 #define VCC_VALID_PROTECTION_FAULT_ENA_DEFAULT BIT(13)
71 #define VCC_RD_PROTECTION_FAULT_ENA_INT BIT(15)
72 #define VCC_RD_PROTECTION_FAULT_ENA_DEFAULT BIT(16)
73 #define VCC_WR_PROTECTION_FAULT_ENA_INT BIT(18)
74 #define VCC_WR_PROTECTION_FAULT_ENA_DEFAULT BIT(19)
64 75 #define VM_CTX_1_CTL_0 0x1414 #define VM_CTX_1_CTL_0 0x1414
65 76 #define VM_CTX_0_CTL_1 0x1430 #define VM_CTX_0_CTL_1 0x1430
66 77 #define VM_CTX_1_CTL_1 0x1434 #define VM_CTX_1_CTL_1 0x1434
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