sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
3D userland works then remove kernel patterns 4c321ff140297a07d0ba4e8fdb3a25a6ffb78441 Sylvain BERTRAND 2013-08-23 12:12:35
missing pci ids b4d10f83ff4f1606e6f16092bcfc457b1e189fcd Sylvain BERTRAND 2013-08-21 22:40:36
first version of 3d userland API 3d3f50a321e0867f0da5e2478d710ae756ea1378 Sylvain BERTRAND 2013-08-21 16:57:22
cp0->c0 cp1->c1 074f981d4d7829b260ff9508b61a38b57474b266 Sylvain BERTRAND 2013-08-21 13:26:02
cp0->gfx 468c65f13f7c967e3481f9c75307cfcb398b909b Sylvain BERTRAND 2013-08-21 13:15:02
cpu aperture to gpu aperture ba4c412fd6afed7ef3094eb6fb060ab43e0fb8c2 Sylvain BERTRAND 2013-08-21 13:06:18
a bit more dma generalization 281fcfd54820d7cf7059cdbf8e198e648642d960 Sylvain BERTRAND 2013-08-19 23:04:52
dma for pt update and l2l byte dma cpy b0542ee460a4f92ad2ad0ffa42293f9fe6d57928 Sylvain BERTRAND 2013-08-10 03:03:17
switch from msleep to usleep_range 3c42fa181b3777dd79bbe1dd0f5a98ed656fb4d5 Sylvain BERTRAND 2013-08-07 13:32:23
GPU is little endian, fimware big endian 13ebc6d59b5ba620db1a974f5920ff88f2ca3174 Sylvain BERTRAND 2013-08-07 13:20:10
naive ring free space wait system b196b09a6adbf72a417ef6e5adb34cff92732018 Sylvain BERTRAND 2013-08-07 12:39:39
mini fence system for DMA 5d183e5998d9f7b7b684ecac253c3cde50dad84f Sylvain BERTRAND 2013-08-06 20:54:12
mainly sg_user mapping 990ec94cf03256d6d2ce5375ea336acdd99fbcf1 Sylvain BERTRAND 2013-08-02 14:36:54
added core DMA mapping methods 677ff382bc0fb7bab3e119f4057fd5fcf40481fc Sylvain BERTRAND 2013-07-31 20:49:30
dma engines, and partial user bus mapping 4c82cabbe66ec9a1c940af37d8954ed87cbfb9eb Sylvain BERTRAND 2013-07-30 15:10:29
add some things to the aperture 695d6688db8ea6ce2145636ed0fb7fa5d6aaebcf Sylvain BERTRAND 2013-07-22 20:11:59
stop mapping vram pci bar 9e32ff2c145282e49503bea50391cb82b926780f Sylvain BERTRAND 2013-07-22 18:30:18
cleanup vram access of patterns 98758af7283b56a9782cb6f0bc2440e3dd54952a Sylvain BERTRAND 2013-07-22 15:33:43
indirect access love d95a68ed1cd564f3a58df468ea6774b53a04f474 Sylvain BERTRAND 2013-07-22 14:23:53
all vram in bus aperture d1c02a0dd98d424ff214d25a245ab6f4aeb277b0 Sylvain BERTRAND 2013-07-22 13:30:40
Commit 4c321ff140297a07d0ba4e8fdb3a25a6ffb78441 - 3D userland works then remove kernel patterns
Author: Sylvain BERTRAND
Author date (UTC): 2013-08-23 12:12
Committer name: Sylvain BERTRAND
Committer date (UTC): 2013-08-23 12:12
Parent(s): b4d10f83ff4f1606e6f16092bcfc457b1e189fcd
Signer:
Signing key:
Signing status: N
Tree: 027495d837ba1c749a22147027b3cc421018aa47
File Lines added Lines deleted
README 4 1
drivers/gpu/alga/amd/si/Kconfig 0 6
drivers/gpu/alga/amd/si/Makefile 0 1
drivers/gpu/alga/amd/si/fops/fops.c 5 42
drivers/gpu/alga/amd/si/fops/mmap.c 2 0
drivers/gpu/alga/amd/si/golden.c 0 1
drivers/gpu/alga/amd/si/gpu/cps.c 4 2
drivers/gpu/alga/amd/si/gpu/cps.h 2 89
drivers/gpu/alga/amd/si/gpu/tiling.c 2 0
drivers/gpu/alga/amd/si/ih.c 30 2
drivers/gpu/alga/amd/si/patterns/fb_fill.c 0 137
drivers/gpu/alga/amd/si/patterns/patterns.h 0 10
drivers/gpu/alga/amd/si/patterns/tri.c 0 1028
drivers/gpu/alga/amd/si/regs.h 3 3
include/alga/amd/si/ioctl.h 4 29
include/alga/amd/si/pkt.h 8 41
include/alga/amd/si/regs_cfg.h 11 2
include/alga/amd/si/regs_ctx.h 12 2
include/alga/amd/si/regs_sh.h 11 2
File README changed (mode: 100644) (index eadf76f..b5301c1)
... ... Current goals (not set in ice):
17 17
18 18 Those are really different from official DRM goals. Those are really different from official DRM goals.
19 19
20 User space programing examples should be provided in a projet not too far from
21 this one.
22
20 23 The target license is GNU Affero GPL v3 with a similar exception than The target license is GNU Affero GPL v3 with a similar exception than
21 24 the current Linux GNU GPLv2. the current Linux GNU GPLv2.
22 25
 
... ... To make things clear:user space programs which do contain significant hardware
28 31 programming knowledge, are *not* "normal" user space programs, then are programming knowledge, are *not* "normal" user space programs, then are
29 32 covered by the GNU GPL. An exception will be added to allow permissive covered by the GNU GPL. An exception will be added to allow permissive
30 33 linking to user space "compat" stubs, which will be covered probably by the linking to user space "compat" stubs, which will be covered probably by the
31 GNU Affero GPLv3 with a library exception (for linking).
34 GNU Affero GPLv3 with a lesser exception (for linking).
32 35
33 36 -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
34 37
File drivers/gpu/alga/amd/si/Kconfig changed (mode: 100644) (index 267e8cc..04c157b)
... ... config ALGA_AMD_SI
8 8 don't need to choose this to run the Radeon in plain VGA mode. don't need to choose this to run the Radeon in plain VGA mode.
9 9
10 10 If M is selected, the module will be called si. If M is selected, the module will be called si.
11
12 config ALGA_AMD_SI_PATTERNS
13 bool "patterns"
14 depends on ALGA_AMD_SI
15 help
16 Support for basic patterns will be compiled in the module
File drivers/gpu/alga/amd/si/Makefile changed (mode: 100644) (index b86cc92..83d3d63)
... ... si-y := drv.o intr_irq.o mc.o ih.o rlc.o ucode.o gpu/gpu.o gpu/cps.o \
2 2 gpu/tiling.o bus/core_coherent.o bus/core_sg_kernel.o bus/sg_user.o bus/ba.o \ gpu/tiling.o bus/core_coherent.o bus/core_sg_kernel.o bus/sg_user.o bus/ba.o \
3 3 bus/hdp.o bus/bif.o golden.o dmas.o fence.o ring.o fops/fops.o fops/mmap.o \ bus/hdp.o bus/bif.o golden.o dmas.o fence.o ring.o fops/fops.o fops/mmap.o \
4 4 fops/dma.o fops/dce.o fops/dma.o fops/dce.o
5 si-$(CONFIG_ALGA_AMD_SI_PATTERNS)+=patterns/fb_fill.o patterns/tri.o
6 5 obj-$(CONFIG_ALGA_AMD_SI)+= si.o obj-$(CONFIG_ALGA_AMD_SI)+= si.o
File drivers/gpu/alga/amd/si/fops/fops.c changed (mode: 100644) (index 76e5786..a50b3c8)
24 24 #include <alga/amd/dce6/dce6.h> #include <alga/amd/dce6/dce6.h>
25 25 #include <alga/amd/si/ioctl.h> #include <alga/amd/si/ioctl.h>
26 26
27 #include <alga/amd/si/pkt.h>
28
27 29 #include "mc.h" #include "mc.h"
28 30 #include "rlc.h" #include "rlc.h"
29 31 #include "ih.h" #include "ih.h"
 
42 44 #include "fops/dma.h" #include "fops/dma.h"
43 45 #include "fops/dce.h" #include "fops/dce.h"
44 46
45 #ifdef CONFIG_ALGA_AMD_SI_PATTERNS
46 #include "patterns/patterns.h"
47 #endif
48
49 47 #include "regs.h" #include "regs.h"
50 48
51 49 dev_t devt_region; dev_t devt_region;
 
... ... static void si_mem_free(struct pci_dev *dev, u64 __user *user_gpu_addr)
113 111 rng_free(&dd->vram.mng, gpu_addr); rng_free(&dd->vram.mng, gpu_addr);
114 112 } }
115 113
116 #ifdef CONFIG_ALGA_AMD_SI_PATTERNS
117 static long si_patterns(struct pci_dev *dev, struct si_patterns __user *user_p)
118 {
119 struct si_patterns p;
120 long r;
121
122 if(copy_from_user(&p, user_p, sizeof(p)))
123 return -EFAULT;
124
125 r = 0;
126 switch (p.id) {
127 case PATTERN_ID_DB_FB_FILL:
128 r = ptn_db_fb_fill(dev, &p.ptn_db_fb_fill);
129 if (r != 0)
130 r = -ENODEV;
131 break;
132 case PATTERN_ID_TRI:
133 r = ptn_tri(dev, &p.ptn_tri);
134 if (r != 0)
135 r = -ENODEV;
136 };
137 return r;
138 }
139 #endif
140
141 114 static long si_dma(struct pci_dev *dev, struct si_dma __user *user_dma) static long si_dma(struct pci_dev *dev, struct si_dma __user *user_dma)
142 115 { {
143 116 struct si_dma dma; struct si_dma dma;
 
... ... static long si_gfx_fence(struct pci_dev *dev)
252 225 gfx_wr(dev, 0); gfx_wr(dev, 0);
253 226 gfx_wr(dev, PKT3(PKT3_SURF_SYNC, 4)); gfx_wr(dev, PKT3(PKT3_SURF_SYNC, 4));
254 227 /* CP_COHER_CTL_0 */ /* CP_COHER_CTL_0 */
255 gfx_wr(dev, CCC_CB0_DEST_BASE_ENA | CCC_CB1_DEST_BASE_ENA
256 | CCC_CB2_DEST_BASE_ENA | CCC_CB3_DEST_BASE_ENA
257 | CCC_CB4_DEST_BASE_ENA | CCC_CB5_DEST_BASE_ENA
258 | CCC_CB6_DEST_BASE_ENA | CCC_CB7_DEST_BASE_ENA
259 | CCC_DB_DEST_BASE_ENA | CCC_DB_ACTION_ENA | CCC_TCL1_ACTION_ENA
260 | CCC_TC_ACTION_ENA | CCC_SH_KCACHE_ACTION_ENA
261 | CCC_SH_ICACHE_ACTION_ENA);
228 gfx_wr(dev, CCC_TCL1_ACTION_ENA | CCC_TC_ACTION_ENA
229 | CCC_SH_KCACHE_ACTION_ENA | CCC_SH_ICACHE_ACTION_ENA);
262 230 /* CP_COHER_SZ */ /* CP_COHER_SZ */
263 231 gfx_wr(dev, 0xffffffff); gfx_wr(dev, 0xffffffff);
264 232 /* CP_COHER_BASE */ /* CP_COHER_BASE */
 
... ... static long si_gfx_fence(struct pci_dev *dev)
271 239 VEI_CACHE_FLUSH_AND_INV_TS_EVENT)); VEI_CACHE_FLUSH_AND_INV_TS_EVENT));
272 240 gfx_wr(dev, lower_32_bits(wb_fence_gpu_addr)); gfx_wr(dev, lower_32_bits(wb_fence_gpu_addr));
273 241 gfx_wr(dev, upper_32_bits(wb_fence_gpu_addr) gfx_wr(dev, upper_32_bits(wb_fence_gpu_addr)
274 | set(PKT3_DATA_SEL, 2) | set(PKT3_INT_SEL, 2));
242 | set(PKT3_DATA_SEL, 1) | set(PKT3_INT_SEL, 2));
275 243 gfx_wr(dev, fence_seq_n); gfx_wr(dev, fence_seq_n);
276 244 gfx_wr(dev, 0); gfx_wr(dev, 0);
277 245 gfx_commit(dev); gfx_commit(dev);
 
... ... static long unlocked_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
347 315 case SI_GFX_FENCE: case SI_GFX_FENCE:
348 316 r = si_gfx_fence(dev); r = si_gfx_fence(dev);
349 317 break; break;
350 #ifdef CONFIG_ALGA_AMD_SI_PATTERNS
351 case SI_PATTERN:
352 r = si_patterns(dev, (struct si_patterns __user *)arg);
353 break;
354 #endif
355 318 case SI_DMA: case SI_DMA:
356 319 r = si_dma(dev, (struct si_dma __user *)arg); r = si_dma(dev, (struct si_dma __user *)arg);
357 320 break; break;
File drivers/gpu/alga/amd/si/fops/mmap.c changed (mode: 100644) (index d349303..8ec64d2)
24 24 #include <alga/amd/dce6/dce6.h> #include <alga/amd/dce6/dce6.h>
25 25 #include <alga/amd/si/ioctl.h> #include <alga/amd/si/ioctl.h>
26 26
27 #include <alga/amd/si/pkt.h>
28
27 29 #include "mc.h" #include "mc.h"
28 30 #include "rlc.h" #include "rlc.h"
29 31 #include "ih.h" #include "ih.h"
File drivers/gpu/alga/amd/si/golden.c changed (mode: 100644) (index 3a474c0..3971082)
20 20 #include "drv.h" #include "drv.h"
21 21
22 22 #include "regs.h" #include "regs.h"
23 #include "gpu/regs_cfg.h"
24 23
25 24 static u32 tahiti_golden_rlc_regs[] = { static u32 tahiti_golden_rlc_regs[] = {
26 25 0xc424, 0xffffffff, 0x00601005, 0xc424, 0xffffffff, 0x00601005,
File drivers/gpu/alga/amd/si/gpu/cps.c changed (mode: 100644) (index 93fdd0d..2057074)
14 14 #include <alga/pixel_fmts.h> #include <alga/pixel_fmts.h>
15 15 #include <alga/amd/dce6/dce6.h> #include <alga/amd/dce6/dce6.h>
16 16
17 #include <alga/amd/si/pkt.h>
18
17 19 #include "mc.h" #include "mc.h"
18 20 #include "rlc.h" #include "rlc.h"
19 21 #include "ih.h" #include "ih.h"
 
... ... static void c0_init(struct pci_dev *dev)
770 772 wr32(dev, lower_32_bits(cp_rb_1_rptr_addr), CP_RB_1_RPTR_ADDR_LO); wr32(dev, lower_32_bits(cp_rb_1_rptr_addr), CP_RB_1_RPTR_ADDR_LO);
771 773 wr32(dev, upper_32_bits(cp_rb_1_rptr_addr), CP_RB_1_RPTR_ADDR_HI); wr32(dev, upper_32_bits(cp_rb_1_rptr_addr), CP_RB_1_RPTR_ADDR_HI);
772 774
773 fence_init(&dd->gfx.fence, dd->ba.wb_map->cpu_addr + WB_C_0_RPTR_OF);
775 fence_init(&dd->c0.fence, dd->ba.wb_map->cpu_addr + WB_C_0_RPTR_OF);
774 776
775 777 mdelay(1); mdelay(1);
776 778 wr32(dev, cp_rb_1_ctl, CP_RB_1_CTL); wr32(dev, cp_rb_1_ctl, CP_RB_1_CTL);
 
... ... static void c1_init(struct pci_dev *dev)
807 809 wr32(dev, lower_32_bits(cp_rb_2_rptr_addr), CP_RB_2_RPTR_ADDR_LO); wr32(dev, lower_32_bits(cp_rb_2_rptr_addr), CP_RB_2_RPTR_ADDR_LO);
808 810 wr32(dev, upper_32_bits(cp_rb_2_rptr_addr), CP_RB_2_RPTR_ADDR_HI); wr32(dev, upper_32_bits(cp_rb_2_rptr_addr), CP_RB_2_RPTR_ADDR_HI);
809 811
810 fence_init(&dd->gfx.fence, dd->ba.wb_map->cpu_addr + WB_C_1_RPTR_OF);
812 fence_init(&dd->c1.fence, dd->ba.wb_map->cpu_addr + WB_C_1_RPTR_OF);
811 813
812 814 mdelay(1); mdelay(1);
813 815 wr32(dev, cp_rb_2_ctl, CP_RB_2_CTL); wr32(dev, cp_rb_2_ctl, CP_RB_2_CTL);
File drivers/gpu/alga/amd/si/gpu/cps.h changed (mode: 100644) (index 8108209..3ad7d15)
1 #ifndef _GPU_CPS_H
2 #define _GPU_CPS_H
1 #ifndef GPU_CPS_H
2 #define GPU_CPS_H
3 3 /* /*
4 4 author Sylvain Bertrand <digital.ragnarok@gmail.com> author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
 
... ... static inline u32 f2u(float f)
23 23 #define CP_RING_LOG2_DWS (CP_RING_LOG2_QWS + 1) #define CP_RING_LOG2_DWS (CP_RING_LOG2_QWS + 1)
24 24 #define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1) #define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1)
25 25
26 #define CP_RING_PFP_DWS 16
27 #define CP_RING_PFP_DW_MASK (CP_RING_PFP_DWS - 1)
28
29 #define PKT_TYPE2 2
30 #define PKT_TYPE3 3
31 #define PKT2 (PKT_TYPE2 << 30)
32 #define PKT3(op,n) ((PKT_TYPE3 << 30) \
33 | (((op) & 0xff) << 8) \
34 | (((n - 1) & 0x3fff) << 16))
35 #define PKT3_COMPUTE(op,n) (PKT3(op,n) | (1 << 1))
36
37 /* packet 3 operations */
38
39 #define PKT3_SET_BASE 0x11
40 #define PKT3_BASE_IDX 0xffffffff
41 #define PKT3_GDS_PARTITION_BASE 2
42 #define PKT3_CE_PARTITION_BASE 3
43 #define PKT3_CLR_STATE 0x12
44 #define PKT3_MODE_CTL 0x18
45 #define PKT3_SET_PREDICATION 0x20
46 #define PRED_DRAW 0x00000100
47 #define PRED_DRAW_NOT_VISIBLE 0
48 #define PRED_DRAW_VISIBLE 1
49 #define PRED_HINT 0x00001000
50 #define PRED_HINT_WAIT 0
51 #define NOWAIT_DRAW 1
52 #define PRED_OP 0xffff0000
53 #define PRED_OP_CLR 0
54 #define PRED_OP_ZPASS 1
55 #define PRED_OP_PRIM_CNT 2
56 #define PRED_CONTINUE BIT(31)
57 #define PKT3_CTX_CTL 0x28
58 #define PKT3_IDX_TYPE 0x2a
59 #define PKT3_SZ 0x00000001
60 #define PKT3_16BITS 0
61 #define PKT3_32BITS 1
62 #define PKT3_SWAP_MODE 0x0000000c
63 #define PKT3_DRAW_IDX_AUTO 0x2d
64 #define PKT3_INST_N 0x2f
65 #define PKT3_IB 0x32
66 #define PKT3_SURF_SYNC 0x43
67 #define PKT3_ME_INIT 0x44
68 #define PKT3_ME_INIT_DEV_ID 0xffff0000
69 #define PKT3_EVENT_WR 0x46
70 #define PKT3_EVENT_IDX 0x00000700
71 /*
72 * 0 - any non-TS event
73 * 1 - ZPASS_DONE
74 * 2 - SAMPLE_PIPELINESTAT
75 * 3 - SAMPLE_STREAMOUTSTAT*
76 * 4 - *S_PARTIAL_FLUSH
77 * 5 - EOP events
78 * 6 - EOS events
79 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
80 */
81 #define PKT3_INV_L2 BIT(20)
82 /* INV TC L2 cache when PKT3_EVENT_IDX = 7 */
83 #define PKT3_EVENT_WR_EOP 0x47
84 #define PKT3_DATA_SEL 0x60000000
85 /*
86 * 0 - discard
87 * 1 - send low 32bit data
88 * 2 - send 64bit data
89 * 3 - send 64bit counter value
90 */
91 #define PKT3_INT_SEL 0x03000000
92 /*
93 * 0 - none
94 * 1 - interrupt only (DATA_SEL = 0)
95 * 2 - interrupt when data write is confirmed
96 */
97 #define PKT3_PREAMBLE_CTL 0x4a
98 #define PKT3_PREAMBLE_BEGIN_CLR_STATE (2 << 28)
99 #define PKT3_PREAMBLE_END_CLR_STATE (3 << 28)
100 #define PKT3_SET_CFG_REG 0x68
101 #define PKT3_SET_CFG_REG_START 0x00008000
102 #define PKT3_SET_CFG_REG_END 0x0000b000
103 #define CFG_REG_IDX(x) ((x - PKT3_SET_CFG_REG_START) >> 2)
104 #define PKT3_SET_CTX_REG 0x69
105 #define PKT3_SET_CTX_REG_START 0x00028000
106 #define PKT3_SET_CTX_REG_END 0x00029000
107 #define CTX_REG_IDX(x) ((x - PKT3_SET_CTX_REG_START) >> 2)
108 #define PKT3_SET_SH_REG 0x76
109 #define PKT3_SET_SH_REG_START 0x0000b000
110 #define PKT3_SET_SH_REG_END 0x0000c000
111 #define SH_REG_IDX(x) ((x - PKT3_SET_SH_REG_START) >> 2)
112
113 26 struct cp struct cp
114 27 { {
115 28 struct fence fence; struct fence fence;
File drivers/gpu/alga/amd/si/gpu/tiling.c changed (mode: 100644) (index 2f9bf2e..29fcb17)
12 12 #include <alga/amd/atombios/atb.h> #include <alga/amd/atombios/atb.h>
13 13 #include <alga/amd/dce6/dce6.h> #include <alga/amd/dce6/dce6.h>
14 14
15 #include <alga/amd/si/pkt.h>
16
15 17 #include "mc.h" #include "mc.h"
16 18 #include "rlc.h" #include "rlc.h"
17 19 #include "ih.h" #include "ih.h"
File drivers/gpu/alga/amd/si/ih.c changed (mode: 100644) (index 469751c..2f07ff8)
... ... void ih_init(struct pci_dev *dev)
126 126 #define VECTOR_ID_D5 6 #define VECTOR_ID_D5 6
127 127 #define Dx_VBLANK 0 #define Dx_VBLANK 0
128 128 #define VECTOR_ID_HPD 42 #define VECTOR_ID_HPD 42
129 #define VECTOR_ID_EOP 181
129 130 #define VECTOR_ID_DMA_0 224 #define VECTOR_ID_DMA_0 224
130 131 #define VECTOR_ID_DMA_1 244 #define VECTOR_ID_DMA_1 244
131 132
 
... ... void ih_init(struct pci_dev *dev)
139 140 * [79:72] - VMID * [79:72] - VMID
140 141 * [127:80] - reserved * [127:80] - reserved
141 142 */ */
142 static void vector(struct pci_dev *dev, u32 id, u32 data, u8 *irq_thd)
143 static void vector(struct pci_dev *dev, u32 id, u32 data, u8 ring_id,
144 u8 *irq_thd)
143 145 { {
144 146 struct dev_drv_data *dd; struct dev_drv_data *dd;
147
145 148 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
146 149
147 150 switch (id) { switch (id) {
 
... ... static void vector(struct pci_dev *dev, u32 id, u32 data, u8 *irq_thd)
160 163 *irq_thd = IRQ_THD_ENA; *irq_thd = IRQ_THD_ENA;
161 164 } }
162 165 break; break;
166 case VECTOR_ID_EOP:
167 switch(ring_id) {
168 case 0:
169 atomic_set(&dd->gfx.fence.bottom,
170 le32_to_cpup(dd->gfx.fence.cpu_addr));
171
172 wake_up(&dd->gfx.fence.wait_queue);
173 break;
174 case 1:
175 atomic_set(&dd->c0.fence.bottom,
176 le32_to_cpup(dd->c0.fence.cpu_addr));
177
178 wake_up(&dd->c0.fence.wait_queue);
179 break;
180 case 2:
181 atomic_set(&dd->c1.fence.bottom,
182 le32_to_cpup(dd->c1.fence.cpu_addr));
183
184 wake_up(&dd->c1.fence.wait_queue);
185 break;
186 };
187 break;
163 188 case VECTOR_ID_DMA_0: case VECTOR_ID_DMA_0:
164 189 atomic_set(&dd->dmas[0].fence.bottom, atomic_set(&dd->dmas[0].fence.bottom,
165 190 le32_to_cpup(dd->dmas[0].fence.cpu_addr)); le32_to_cpup(dd->dmas[0].fence.cpu_addr));
 
... ... u8 ih_parse(struct pci_dev *dev)
228 253 do { do {
229 254 u32 id; u32 id;
230 255 u32 data; u32 data;
256 u8 ring_id;
231 257
232 258 id = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp) id = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp)
233 259 & 0xff; & 0xff;
234 260 data = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp data = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp
235 261 + sizeof(id)) & 0xfffffff; + sizeof(id)) & 0xfffffff;
262 ring_id = le32_to_cpup(dd->ba.ih_ring_map->cpu_addr + rp
263 + sizeof(id) + sizeof(data)) & 0xff;
236 264
237 vector(dev, id, data, &irq_thd);
265 vector(dev, id, data, ring_id, &irq_thd);
238 266
239 267 rp += VECTOR_SZ; rp += VECTOR_SZ;
240 268 rp &= IH_RING_MASK; rp &= IH_RING_MASK;
File drivers/gpu/alga/amd/si/patterns/fb_fill.c deleted (index af293b4..0000000)
1 /*
2 author Sylvain Bertrand <digital.ragnarok@gmail.com>
3 Protected by GNU Affero GPL v3 with some exceptions.
4 See README at root of alga tree.
5 */
6 #include <linux/module.h>
7 #include <linux/pci.h>
8 #include <linux/cdev.h>
9
10 #include <alga/rng_mng.h>
11 #include <alga/pixel_fmts.h>
12 #include <alga/timing.h>
13 #include <alga/amd/atombios/atb.h>
14 #include <alga/amd/dce6/dce6.h>
15 #include <alga/amd/si/ioctl.h>
16
17 #include "mc.h"
18 #include "rlc.h"
19 #include "ih.h"
20 #include "fence.h"
21 #include "ring.h"
22 #include "dmas.h"
23 #include "bus/ba.h"
24 #include "gpu/cps.h"
25 #include "gpu/gpu.h"
26 #include "drv.h"
27
28 #include "regs.h"
29
30 static void argb8888_px_set_red(struct pci_dev *dev, u64 px)
31 {
32 vram_w32(dev, 0x00ff0000, px);
33 }
34
35 static void argb8888_px_set_blue(struct pci_dev *dev, u64 px)
36 {
37 vram_w32(dev, 0x000000ff, px);
38 }
39
40 static void argb8888_px_set_green(struct pci_dev *dev, u64 px)
41 {
42 vram_w32(dev, 0x0000ff00, px);
43 }
44
45 static void argb8888_px_set_white(struct pci_dev *dev, u64 px)
46 {
47 vram_w32(dev, 0x00ffffff, px);
48 }
49
50 void (*px_set_red[])(struct pci_dev *dev, u64 px) = {
51 [ALGA_PIXEL_FMT_INVALID]= NULL,
52 [ALGA_ARGB6666] = NULL,
53 [ALGA_ARGB8888] = argb8888_px_set_red,
54 [ALGA_ARGB2101010] = NULL
55 };
56
57 void (*px_set_blue[])(struct pci_dev *dev, u64 px) = {
58 [ALGA_PIXEL_FMT_INVALID]= NULL,
59 [ALGA_ARGB6666] = NULL,
60 [ALGA_ARGB8888] = argb8888_px_set_blue,
61 [ALGA_ARGB2101010] = NULL
62 };
63
64 void (*px_set_green[])(struct pci_dev *dev, u64 px) = {
65 [ALGA_PIXEL_FMT_INVALID]= NULL,
66 [ALGA_ARGB6666] = NULL,
67 [ALGA_ARGB8888] = argb8888_px_set_green,
68 [ALGA_ARGB2101010] = NULL
69 };
70
71 void (*px_set_white[])(struct pci_dev *dev, u64 px) = {
72 [ALGA_PIXEL_FMT_INVALID]= NULL,
73 [ALGA_ARGB6666] = NULL,
74 [ALGA_ARGB8888] = argb8888_px_set_white,
75 [ALGA_ARGB2101010] = NULL
76 };
77
78 /*
79 * This will fill the top half front frame buffer red and the bottom half front
80 * buffer blue.
81 */
82 long ptn_db_fb_fill(struct pci_dev *dev, struct ptn_db_fb_fill *p)
83 {
84 struct dev_drv_data *dd;
85
86 u64 px;
87 u64 px_fb_half_last;
88 u64 px_fb_last;
89
90 dd = pci_get_drvdata(dev);
91
92 dev_info(&dev->dev,
93 "db_fb_fill:front=0x%016llx,back=0x%016llx,w=%u,h=%u,pixel_fmt=%s\n",
94 p->front_gpu_addr, p->back_gpu_addr,p->w, p->h,
95 alga_pixel_fmts_str[p->pixel_fmt]);
96
97
98 /* indirect vram access must be dword aligned */
99 if (alga_pixel_fmts_sz[p->pixel_fmt] & 0x3) {
100 dev_err(&dev->dev,
101 "db_fb_fill:pixel size (=%u bytes) must be dword aligned\n",
102 alga_pixel_fmts_sz[p->pixel_fmt]);
103
104 return -EINVAL;
105 }
106
107 /* front buffer */
108 px = p->front_gpu_addr;
109 px_fb_half_last = px + (p->w * p->h / 2 - 1)
110 * alga_pixel_fmts_sz[p->pixel_fmt];
111 px_fb_last = px + (p->w * p->h - 1)
112 * alga_pixel_fmts_sz[p->pixel_fmt];
113 while (px <= px_fb_half_last) {
114 (px_set_red[p->pixel_fmt])(dev, px);
115 px += alga_pixel_fmts_sz[p->pixel_fmt];
116 }
117 while (px <= px_fb_last) {
118 (px_set_blue[p->pixel_fmt])(dev, px);
119 px += alga_pixel_fmts_sz[p->pixel_fmt];
120 }
121
122 /* back buffer */
123 px = p->back_gpu_addr;
124 px_fb_half_last = px + (p->w * p->h / 2 - 1)
125 * alga_pixel_fmts_sz[p->pixel_fmt];
126 px_fb_last = px + (p->w * p->h - 1)
127 * alga_pixel_fmts_sz[p->pixel_fmt];
128 while (px <= px_fb_half_last) {
129 (px_set_green[p->pixel_fmt])(dev, px);
130 px += alga_pixel_fmts_sz[p->pixel_fmt];
131 }
132 while (px <= px_fb_last) {
133 (px_set_white[p->pixel_fmt])(dev, px);
134 px += alga_pixel_fmts_sz[p->pixel_fmt];
135 }
136 return 0;
137 }
File drivers/gpu/alga/amd/si/patterns/patterns.h deleted (index a286326..0000000)
1 #ifndef _PATTERNS_PATTERNS_H
2 #define _PATTERNS_PATTERNS_H
3 /*
4 author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 Protected by GNU Affero GPL v3 with some exceptions.
6 See README at root of alga tree.
7 */
8 long ptn_db_fb_fill(struct pci_dev *dev, struct ptn_db_fb_fill *p);
9 long ptn_tri(struct pci_dev *dev, struct ptn_tri *p);
10 #endif
File drivers/gpu/alga/amd/si/patterns/tri.c deleted (index 0601d0e..0000000)
1 /*
2 author Sylvain Bertrand <digital.ragnarok@gmail.com>
3 Protected by GNU Affero GPL v3 with some exceptions.
4 See README at root of alga tree.
5 */
6 #include <linux/module.h>
7 #include <linux/pci.h>
8 #include <linux/cdev.h>
9
10 #include <alga/rng_mng.h>
11 #include <alga/pixel_fmts.h>
12 #include <alga/timing.h>
13 #include <alga/amd/atombios/atb.h>
14 #include <alga/amd/dce6/dce6.h>
15 #include <alga/amd/si/ioctl.h>
16
17 #include "mc.h"
18 #include "rlc.h"
19 #include "ih.h"
20 #include "fence.h"
21 #include "ring.h"
22 #include "dmas.h"
23 #include "bus/ba.h"
24 #include "gpu/cps.h"
25 #include "gpu/gpu.h"
26 #include "drv.h"
27
28 #include "regs.h"
29
30 /*
31 * XXX:This code is made to work on little endian 64 bits host systems.
32 */
33
34 #define IB_DWS_N_MAX (16 * 64)
35 struct ib {
36 u64 gpu_addr;
37 u32 dws;
38 u32 d[IB_DWS_N_MAX];
39 };
40
41 static u64 vtx_buf;
42 static u64 vs_buf;
43 static u64 ps_buf;
44 static struct ib ib;
45
46 struct vertex {
47 float position[4];
48 float param0[4];
49 };
50
51 static struct vertex vertices[4] = {
52 {
53 { -0.2f, -0.9f, 0.0f, 1.0f },
54 { 1.0f, 0.0f, 0.0f, 1.0f }
55 },
56 {
57 { -0.9f, 0.9f, 0.0f, 1.0f },
58 { 0.0f, 1.0f, 0.0f, 1.0f }
59 },
60 {
61 { 0.9f, 0.9f, 0.0f, 1.0f },
62 { 0.0f, 0.0f, 1.0f, 1.0f }
63 },
64 {
65 { 0, 0, 0, 0 },
66 { 0, 0, 0, 0 }
67 }
68 };
69
70 static u32 buf_res_descs[] = {
71 /* init with the vram lower 32 bits vertex position buffer address */
72 0x00000000,
73 /*
74 * oring the upper 8 remaining bits of buffer address.
75 * stride=0x20 (8 floats (4 position+4 color components) of 4 bytes.
76 */
77 0x00200000,
78 /* 4 records, namely 4 vertices, the last one in "null" */
79 0x00000004,
80 /*
81 * dst_sel_x=4(x) dst_sel_y=5(y) dst_sel_z=6(z) dest_sel_w=7(w)
82 * nfmt=7(float) dfmt=14(32_32_32_32)
83 */
84 0x00077fac,
85 /*--------------------------------------------------------------------*/
86 /* init with the vram lower 32 bits vertex param 0 buffer address */
87 0x00000000,
88 /*
89 * oring the upper 8 remaining bits of buffer address.
90 * stride=0x20 (8 floats (4 position+4 param 0 components) of 4 bytes.
91 */
92 0x00200000,
93 /* 4 records, namely 4 vertices, the last one in "null" */
94 0x00000004,
95 /*
96 * dst_sel_x=4(r) dst_sel_y=5(g) dst_sel_z=6(b) dst_sel_w=7(a)
97 * (customary to use color terminology for params)
98 * nfmt=7(float) dfmt=14(32_32_32_32)
99 */
100 0x00077fac
101 };
102
103 /*
104 * o USER_SGPR[3:0]<--buffer resouce descriptor of the buffer of vertex
105 * positions
106 * o USER_SGPR[7:4]<--buffer resouce descriptor of the buffer of vertex
107 * parameter 0 (unused here)
108 * note: the done bit in export instructions is only for vertex positions.
109 */
110 static const u8 vs_vgprs_n=9;
111 static const u8 vs_user_sgprs_n=8;
112 static const u8 vs_sgprs_n=8;/* at least vs_user_sgprs_n */
113 static const u8 vs_exported_params_n=1;
114 static u32 vs[] = {
115 0xe00c2000,/* buffer_load_format_xyzw idxen=1 */
116 0x80000100,/* soffset=128(=0) vdata=1 */
117 0xbf8c0000,/* s_waitcnt */
118 0xe00c2000,/* buffer_load_format_xyzw idxen=1 */
119 0x80010500,/* soffset=128(=0) srsrc=1(sgprs[4:7]) vdata=5 */
120 0xbf8c0000,/* s_waitcnt */
121 0xf80008cf,/* export en=0b1111 done=1 tgt=12(pos0) */
122 0x04030201,/* vsrc0=1 vsrc1=2 vsrc2=3 vsrc3=4 */
123 0xbf8c0000,/* s_waitcnt */
124 0xf800020f,/* export en=0b1111 tgt=32(param0) */
125 0x08070605,/* vsrc0=5 vsrc1=6 vsrc2=7 vsrc3=8 */
126 0xbf8c0000,/* s_waitcnt */
127 0xbf810000/* s_endpgm */
128 };
129
130 /*
131 * m0 is put by the spi right after the last user pre-loaded sgprs. m0 must
132 * be loaded in order to index properly the parameters in lds.
133 * note: we don't deal with the "valid mask" for pixer en exec register.
134 */
135 static const u8 ps_vgprs_n=4;
136 static const u8 ps_user_sgprs_n=0;
137 static const u8 ps_sgprs_n=0;/* at least ps_user_sgprs_n */
138 static u32 ps[] = {
139 0x7e0002f2,/* v_mov_b32 src0=242(1.0f) vdst=0 */
140 0xbf8c0000,/* s_waitcnt */
141 0x7e0202f2,/* v_mov_b32 src0=242(1.0f) vdst=1 */
142 0xbf8c0000,/* s_waitcnt */
143 0x7e0402f2,/* v_mov_b32 src0=242(1.0f) vdst=2 */
144 0xbf8c0000,/* s_waitcnt */
145 0x7e0602f2,/* v_mov_b32 src0=242(1.0f) vdst=3 */
146 0xbf8c0000,/* s_waitcnt */
147 0x5e000300,/* v_cvt_pkrtz_f16_f32 vdst=0 vsrc1=1 src0=256(vgpr0) */
148 0x5e020702,/* v_cvt_pkrtz_f16_f32 vdst=1 vsrc1=3 src0=258(vgpr2) */
149 0xf8001c0f,/* exp vm=1 done=1 compr=1 en=0x1111 */
150 0x01000100,/* vsrc3=1 vsrc2=0 vsrc1=1 vsrc0=0 */
151 0xbf8c0000,/* s_waitcnt */
152 0xbf810000/* s_endpgm */
153 };
154
155 static void ctx_vgt(struct pci_dev *dev)
156 {
157 /* VGT (Vertex Grouper and Tesselator block) */
158 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 5);
159 ib.d[ib.dws++]=CTX_REG_IDX(VGT_MAX_VTX_IDX);
160 /* VGT_MAX_VTX_IDX */
161 ib.d[ib.dws++]=~0;
162 /* VGT_MIN_VTX_IDX */
163 ib.d[ib.dws++]=0;
164 /* VGT_IDX_OF */
165 ib.d[ib.dws++]=0;
166 /* VGT_MULTI_PRIM_IB_RESET_IDX */
167 ib.d[ib.dws++]=0;
168
169 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
170 ib.d[ib.dws++]=CTX_REG_IDX(VGT_MULTI_PRIM_IB_RESET_ENA);
171 /* VGT_MULTI_PRIM_IB_RESET_ENA */
172 ib.d[ib.dws++]=0;
173 }
174
175 static void ctx_spi_sh_vs(struct pci_dev *dev)
176 {
177 /* setup specific for the vertex shader */
178
179 /* Tell the spi to pre-load the buffer descriptors in user sgprs */
180 ib.d[ib.dws++]=PKT3(PKT3_SET_SH_REG,9);
181 ib.d[ib.dws++]=SH_REG_IDX(SPI_SH_USER_DATA_VS_0);
182 /* SPI_SH_USER_DATA_VS_0 */
183 ib.d[ib.dws++]=buf_res_descs[0];
184 /* SPI_SH_USER_DATA_VS_1 */
185 ib.d[ib.dws++]=buf_res_descs[1];
186 /* SPI_SH_USER_DATA_VS_2 */
187 ib.d[ib.dws++]=buf_res_descs[2];
188 /* SPI_SH_USER_DATA_VS_3 */
189 ib.d[ib.dws++]=buf_res_descs[3];
190 /* SPI_SH_USER_DATA_VS_4 */
191 ib.d[ib.dws++]=buf_res_descs[4];
192 /* SPI_SH_USER_DATA_VS_5 */
193 ib.d[ib.dws++]=buf_res_descs[5];
194 /* SPI_SH_USER_DATA_VS_6 */
195 ib.d[ib.dws++]=buf_res_descs[6];
196 /* SPI_SH_USER_DATA_VS_7 */
197 ib.d[ib.dws++]=buf_res_descs[7];
198
199 ib.d[ib.dws++]=PKT3(PKT3_SET_SH_REG, 5);
200 ib.d[ib.dws++]=SH_REG_IDX(SPI_SH_PGM_LO_VS);
201 /* SPI_SH_PGM_LO_VS */
202 ib.d[ib.dws++]=lower_32_bits(vs_buf>>8);
203 /* SPI_SH_PGM_HI_VS */
204 ib.d[ib.dws++]=set(SSPHV_MEM_BASE, upper_32_bits(vs_buf>>8));
205 /*
206 * SPI_SH_PGM_RSRC_VS_0: the vgrs are allocated using units of 4 vgprs,
207 * sgprs using units of 8 sgprs. Don't forget to book 2 additionnal
208 * sgprs for vcc. Both counts are minus one unit.
209 */
210 ib.d[ib.dws++]=set(SSPRV_VGPRS, ((vs_vgprs_n - 1) / 4))
211 | set (SSPRV_SGPRS, ((vs_sgprs_n + 2) - 1) / 8);
212 /*
213 * SPI_SH_PGM_RSRC_VS_1: tell the spi the count of sgprs which are not
214 * vcc.
215 */
216 ib.d[ib.dws++]=set(SSPRV_USER_SGPR, vs_user_sgprs_n);
217
218 /* our vertex shader export only the color as parameter */
219 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
220 ib.d[ib.dws++]=CTX_REG_IDX(SPI_VS_OUT_CFG);
221 /* SPI_VS_OUT_CFG */
222 ib.d[ib.dws++]=set(SVOC_VS_PARAM_EXPORT_COUNT,
223 vs_exported_params_n - 1);
224
225 /*
226 * The spi needs to be told what packing format is used by the vertex
227 * shader to export the position.
228 */
229 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
230 ib.d[ib.dws++]=CTX_REG_IDX(SPI_SH_POS_FMT);
231 /* SPI_SH_POS_FMT */
232 ib.d[ib.dws++]=set(SSPF_POS_0_EXPORT_FMT, SSPF_4COMP);
233 }
234
235 static void ctx_spi_sh_ps(struct pci_dev *dev)
236 {
237 /* setup specific for the pixel/fragment shader */
238 ib.d[ib.dws++]=PKT3(PKT3_SET_SH_REG, 5);
239 ib.d[ib.dws++]=SH_REG_IDX(SPI_SH_PGM_LO_PS);
240 /* SPI_SH_PGM_LO_PS */
241 ib.d[ib.dws++]=lower_32_bits(ps_buf>>8);
242 /* SPI_SH_PGM_HI_PS */
243 ib.d[ib.dws++]=set(SSPHP_MEM_BASE, upper_32_bits(ps_buf>>8));
244 /*
245 * SPI_SH_PGM_RSRC_PS_0: we must account 1 additional sgpr for m0 since
246 * which will be loaded in the sgpr right after the last user sgpr.
247 */
248 ib.d[ib.dws++]=set(SSPRP_VGPRS, ((ps_vgprs_n - 1) / 4))
249 | set(SSPRP_SGPRS, ((ps_sgprs_n + 1 + 2) - 1) / 8);
250 /*
251 * SPI_SH_PGM_RSRC_PS_1: same constrains than the vertex shaders
252 * plus the fact the spi will load the m0 in the first sgpr after the
253 * last user loaded sgpr, namely sgpr6 in this case.
254 */
255 ib.d[ib.dws++]=set(SSPRP_USER_SGPR, ps_sgprs_n);
256
257 /*
258 * tell the spi the pixel/fragment shader will need perpective center
259 * interpolation data in input (mandatory or gpu hang)
260 */
261 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
262 ib.d[ib.dws++]=CTX_REG_IDX(SPI_PS_INPUT_ENA);
263 /* SPI_PS_INPUT_ENA */
264 ib.d[ib.dws++]=SPIE_PERSP_CENTER_ENA;
265 /* SPI_PS_INPUT_ADDR */
266 ib.d[ib.dws++]=SPIA_PERSP_CENTER_ENA;
267
268 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
269 ib.d[ib.dws++]=CTX_REG_IDX(SPI_PS_IN_CTL);
270 /* SPI_PS_IN_CTL: 1 parameter to interpolate. Must have at least one */
271 ib.d[ib.dws++]=set(SPIC_INTERP_N, 1);
272
273 /* don't care about z depth export */
274 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
275 ib.d[ib.dws++]=CTX_REG_IDX(SPI_SH_Z_FMT);
276 /* SPI_SH_Z_FMT */
277 ib.d[ib.dws++]=set(SSZF_Z_EXPORT_FMT, SSZF_ZERO);
278
279 /* only 1 input param on 32, then only SPI_PS_INPUT_CTL_00 */
280 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
281 ib.d[ib.dws++]=CTX_REG_IDX(SPI_PS_INPUT_CTL_00);
282 /* SPI_PS_INPUT_CTL_00 */
283 ib.d[ib.dws++]=0;
284
285 /*
286 * The spi sends the pixel color exported by a pixel/fragment shader to
287 * a cb, it needs to be told about the special color packing format the
288 * shader used.
289 */
290 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
291 ib.d[ib.dws++]=CTX_REG_IDX(SPI_SH_COLOR_FMT);
292 /* SPI_SH_COLOR_FMT */
293 ib.d[ib.dws++]=set(SSCF_COLOR_0_EXPORT_FMT, SSCF_FP16_ABGR);
294 }
295
296 static void ctx_spi_sh(struct pci_dev *dev)
297 {
298 /* SH (SHader block) */
299 ctx_spi_sh_vs(dev);
300 ctx_spi_sh_ps(dev);
301 }
302
303 static void ctx_spi(struct pci_dev *dev)
304 {
305 /* SPI (Shader Processor Interpolator) */
306 /* disable the point primitive sprite */
307 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
308 ib.d[ib.dws++]=CTX_REG_IDX(SPI_INTERPOL_CTL_0);
309 /* SPI_INTERPOL_CTL_0 */
310 ib.d[ib.dws++]=0;
311
312 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
313 ib.d[ib.dws++]=CTX_REG_IDX(SPI_BARYC_CTL);
314 /* SPI_BARYC_CTL: want 0 in working sample */
315 ib.d[ib.dws++]=0;
316
317 ctx_spi_sh(dev);
318 }
319
320 static void ctx_dbs(struct pci_dev *dev)
321 {
322 /* DBs (Depth Blocks) */
323 /* disable the depth stencil/z-buffer */
324 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
325 ib.d[ib.dws++]=CTX_REG_IDX(DB_Z_INFO);
326 /* DB_Z_INFO */
327 ib.d[ib.dws++]=0;
328 /* DB_STENCIL_INFO */
329 ib.d[ib.dws++]=0;
330
331 /* even if disabled, setup some clean values in a few regs */
332
333 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
334 ib.d[ib.dws++]=CTX_REG_IDX(DB_DEPTH_CTL);
335 /* DB_DEPTH_CTL */
336 ib.d[ib.dws++]=0;
337
338 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 5);
339 ib.d[ib.dws++]=CTX_REG_IDX(DB_DEPTH_BOUNDS_MIN);
340 /* DB_DEPTH_BOUNDS_MIN */
341 ib.d[ib.dws++]=0;
342 /* DB_DEPTH_BOUNDS_MAX */
343 ib.d[ib.dws++]=0;
344 /* DB_STENCIL_CLR */
345 ib.d[ib.dws++]=0;
346 /* DB_DEPTH_CLR */
347 ib.d[ib.dws++]=f2u(1.0f);
348
349 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
350 ib.d[ib.dws++]=CTX_REG_IDX(DB_RENDER_CTL);
351 /* DB_RENDER_CTL */
352 ib.d[ib.dws++]=0;
353
354 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
355 ib.d[ib.dws++]=CTX_REG_IDX(DB_RENDER_OVERRIDE_0);
356 /* DB_RENDER_OVERRIDE_0 */
357 ib.d[ib.dws++]=set(DRO_FORCE_HIZ_ENA, DRO_FORCE_DIS)
358 | set(DRO_FORCE_HIS_ENA_0, DRO_FORCE_DIS)
359 | set(DRO_FORCE_HIS_ENA_1, DRO_FORCE_DIS);
360
361 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
362 ib.d[ib.dws++]=CTX_REG_IDX(DB_STENCIL_CTL);
363 /* DB_STENCIL_CTL */
364 ib.d[ib.dws++]=0;
365
366 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 4);
367 ib.d[ib.dws++]=CTX_REG_IDX(DB_SRESULTS_CMP_STATE_0);
368 /* DB_SRESULTS_CMP_STATE_0 */
369 ib.d[ib.dws++]=0;
370 /* DB_SRESULTS_CMP_STATE_1 */
371 ib.d[ib.dws++]=0;
372 /* DB_PRELOAD_CTL */
373 ib.d[ib.dws++]=0;
374
375 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
376 ib.d[ib.dws++]=CTX_REG_IDX(DB_ALPHA_TO_MASK);
377 /* DB_ALPHA_TO_MASK */
378 ib.d[ib.dws++]=set(DATM_ALPHA_TO_MASK_OF_0, 2)
379 | set(DATM_ALPHA_TO_MASK_OF_1, 2)
380 | set(DATM_ALPHA_TO_MASK_OF_2, 2)
381 | set(DATM_ALPHA_TO_MASK_OF_3, 2);
382
383 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
384 ib.d[ib.dws++]=CTX_REG_IDX(DB_STENCILREFMASK);
385 /* DB_STENCILREFMASK */
386 ib.d[ib.dws++]=0;
387 /* DB_STENCILREFMASK_BF */
388 ib.d[ib.dws++]=0;
389
390 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
391 ib.d[ib.dws++]=CTX_REG_IDX(DB_SH_CTL);
392 /* DB_SH_CTL */
393 ib.d[ib.dws++]=set(DSC_Z_ORDER, DSC_EARLY_Z_THEN_LATE_Z);
394 }
395
396 static void ctx_cb_0(struct pci_dev *dev, struct ptn_tri *p)
397 {
398 /* CB 0 (Color Block 0) */
399 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 7);
400 ib.d[ib.dws++]=CTX_REG_IDX(CB_0_COLOR_BASE);
401 /* CB_0_COLOR_BASE */
402 ib.d[ib.dws++]=p->fb_gpu_addr >> 8;
403 /* CB_0_COLOR_PITCH: a thin1 tile is 8x8 pixels */
404 ib.d[ib.dws++]=set(CCP_TILE_MAX, p->w / 8 - 1);
405 /* CB_0_COLOR_SLICE: a thin1 tile is 8x8 pixels */
406 ib.d[ib.dws++]=set(CCS_TILE_MAX, p->w * p->h / 64 - 1);
407 /* CB_0_COLOR_VIEW: 0, or last tile index for an array of slices */
408 ib.d[ib.dws++]=0;
409 /*
410 * CB_0_COLOR_INFO: for sRGB color space, in 8 bits little endian argb,
411 * the color component swap is ALT for the color components from the
412 * pixel/fragment shader and value must be clamped before and after
413 * blending to mrt range.
414 */
415 ib.d[ib.dws++]=set(CCI_ENDIAN, CCI_ENDIAN_NONE)
416 | set(CCI_FMT, CCI_COLOR_8_8_8_8)
417 | set(CCI_COMP_SWAP, CCI_SWAP_ALT)
418 | set(CCI_NUMBER_TYPE, CCI_NUMBER_UNORM)
419 | CCI_BLEND_CLAMP;
420 /* CB_0_COLOR_ATTRIB: see gpu/tiling.c */
421 ib.d[ib.dws++]=set(CCA_TILE_MODE_IDX, 8);
422 }
423
424 static void ctx_cbs_blend(struct pci_dev *dev)
425 {
426 /* blend blocks of CBs (Color Blocks) */
427 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 9);
428 ib.d[ib.dws++]=CTX_REG_IDX(CB_0_BLEND_CTL);
429 /* CB_0_BLEND_CTL: disable blending */
430 ib.d[ib.dws++]=0;
431 /* CB_1_BLEND_CTL: disable blending */
432 ib.d[ib.dws++]=0;
433 /* CB_2_BLEND_CTL: disable blending */
434 ib.d[ib.dws++]=0;
435 /* CB_3_BLEND_CTL: disable blending */
436 ib.d[ib.dws++]=0;
437 /* CB_4_BLEND_CTL: disable blending */
438 ib.d[ib.dws++]=0;
439 /* CB_5_BLEND_CTL: disable blending */
440 ib.d[ib.dws++]=0;
441 /* CB_6_BLEND_CTL: disable blending */
442 ib.d[ib.dws++]=0;
443 /* CB_7_BLEND_CTL: disable blending */
444 ib.d[ib.dws++]=0;
445 }
446
447 static void ctx_cbs(struct pci_dev *dev, struct ptn_tri *p)
448 {
449 /* CBs (Color Blocks) */
450 ctx_cbs_blend(dev);
451
452 ctx_cb_0(dev, p);
453
454 /*
455 * do enable all color components (RGBA) from the pixel/fragment shader
456 * to be used by the CB 0 and do enable CB 0 to output all computed
457 * color components to target (here our framebuffer)
458 */
459 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
460 ib.d[ib.dws++]=CTX_REG_IDX(CB_TGT_MASK);
461 /* CB_TGT_MASK */
462 ib.d[ib.dws++]=set(CTM_TGT_0_ENA, CTM_TGT_RED | CTM_TGT_GREEN
463 | CTM_TGT_BLUE | CTM_TGT_ALPHA);
464 /* CB_SH_MASK */
465 ib.d[ib.dws++]=set(CSM_OUTPUT_0_ENA, CSM_OUTPUT_RED | CSM_OUTPUT_GREEN
466 | CSM_OUTPUT_BLUE | CSM_OUTPUT_ALPHA);
467
468 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
469 ib.d[ib.dws++]=CTX_REG_IDX(CB_COLOR_CTL);
470 /* CB_COLOR_CTL: switch normal mode for all CBs */
471 ib.d[ib.dws++]=set(CCC_MODE, CCC_CB_NORMAL) | set(CCC_ROP3, CCC_0XCC);
472 }
473
474 static void ctx_pa_su(struct pci_dev *dev)
475 {
476 /* PA (Primitive Assembler) SU (Setup Unit) */
477 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
478 ib.d[ib.dws++]=CTX_REG_IDX(PA_SU_VTX_CTL);
479 /*
480 * PA_SU_VTX_CTL: tells the PA (Primitive Assembler) SU (Setup Unit)
481 * to place the(?) pixel at the center of the vertex?
482 */
483 ib.d[ib.dws++]=PSVC_PIX_CENTER;
484
485 /*
486 * setup for the PA (Primitive Assembler) SU (Setup Unit) for the
487 * point/line primitive rendering: we do not render point
488 * or line primitives.
489 * Set it to 8 like in working samples
490 */
491 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 4);
492 ib.d[ib.dws++]=CTX_REG_IDX(PA_SU_POINT_SZ);
493 /* PA_SU_POINT_SZ */
494 ib.d[ib.dws++]=set(PSPS_H, 8) | set(PSPS_W, 8);
495 /* PA_SU_POINT_MINMAX */
496 ib.d[ib.dws++]=set(PSPM_MIN, 8) | set(PSPM_MAX, 8);
497 /* PA_SU_LINE_CTL */
498 ib.d[ib.dws++]=set(PSLC_W, 8);
499
500 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
501 ib.d[ib.dws++]=CTX_REG_IDX(PA_SU_POLY_OF_CLAMP);
502 /*
503 * PA_SU_POLY_OF_CLAMP: tell the PA (Primitive Assembler) SU
504 * (Setup Unit) for polygon not to clamp something ?
505 */
506 ib.d[ib.dws++]=0;
507
508 /* related to the SC (Scan Converter) */
509 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
510 ib.d[ib.dws++]=CTX_REG_IDX(PA_SU_SC_MODE_CTL);
511 /* PA_SU_SC_MODE_CTL: removed FACE to follow working samples */
512 ib.d[ib.dws++]=set(PSSMC_POLY_MODE_FRONT_PTYPE, PSSMC_DRAW_TRIANGLES)
513 | set(PSSMC_POLY_MODE_BACK_PTYPE, PSSMC_DRAW_TRIANGLES)
514 | PSSMC_PROVOKING_VTX_LAST;
515
516 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
517 ib.d[ib.dws++]=CTX_REG_IDX(PA_SU_PRIM_FILTER_CTL);
518 /* PA_SU_PRIM_FILTER_CTL */
519 ib.d[ib.dws++]=0;
520 }
521
522 static void ctx_pa_cl(struct pci_dev *dev)
523 {
524 /* PA (Primitive Assembler) CL (CLipper) */
525 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 5);
526 ib.d[ib.dws++]=CTX_REG_IDX(PA_CL_GB_VERT_CLIP_ADJ);
527 /* disable GB (Guard Band) by setting those registers to 1.0f */
528 /* PA_CL_GB_VERT_CLIP_ADJ */
529 ib.d[ib.dws++]=f2u(1.0f);
530 /* PA_CL_GB_VERT_DISC_ADJ */
531 ib.d[ib.dws++]=f2u(1.0f);
532 /* PA_CL_GB_HORZ_CLIP_ADJ */
533 ib.d[ib.dws++]=f2u(1.0f);
534 /* PA_CL_GB_HORZ_DISC_ADJ */
535 ib.d[ib.dws++]=f2u(1.0f);
536
537 /*
538 * define the way the PA (Primitive Assembler) CL (CLipper) will
539 * behave regarding NAN (Not A Number) and INF (INFinity) values
540 */
541 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
542 ib.d[ib.dws++]=CTX_REG_IDX(PA_CL_NANINF_CTL);
543 /* PA_CL_NANINF_CTL: to hardware default behaviour */
544 ib.d[ib.dws++]=0;
545
546 /* no clipping done on the input from the vertex shader */
547 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
548 ib.d[ib.dws++]=CTX_REG_IDX(PA_CL_VS_OUT_CTL);
549 /* PA_CL_VS_OUT_CTL */
550 ib.d[ib.dws++]=0;
551
552 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
553 ib.d[ib.dws++]=CTX_REG_IDX(PA_CL_CLIP_CTL);
554 /* PA_CL_CLIP_CTL: ucp mode 3=always expand and clip as trifan */
555 ib.d[ib.dws++]=set(PCCC_PS_UCP_MODE, 3) | PCCC_DX_LINEAR_ATTR_CLIP_ENA;
556 }
557
558 static void ctx_pa_sc_vport_0_te(struct pci_dev *dev, struct ptn_tri *p)
559 {
560 /*
561 * PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) 0 TE
562 * (Transform Engine)
563 */
564 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 7);
565 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_VPORT_0_TE_X_SCALE);
566 /* PA_SC_VPORT_0_TE_X_SCALE */
567 ib.d[ib.dws++]=f2u(p->w / 2.0f);
568 /* PA_SC_VPORT_0_TE_X_OF */
569 ib.d[ib.dws++]=f2u(p->w / 2.0f);
570 /* PA_SC_VPORT_0_TE_Y_SCALE */
571 ib.d[ib.dws++]=f2u(p->h / 2.0f);
572 /* PA_SC_VPORT_0_TE_Y_OF */
573 ib.d[ib.dws++]=f2u(p->h / 2.0f);
574 /* PA_SC_VPORT_0_TE_Z_SCALE: stick to working sample values */
575 ib.d[ib.dws++]=f2u(0.5f);
576 /* PA_SC_VPORT_0_TE_Z_OF: stick to working sample values */
577 ib.d[ib.dws++]=f2u(0.5f);
578
579 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
580 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_VPORT_0_TE_ZMIN);
581 /* PA_SC_VPORT_0_TE_ZMIN: min Z value from VPORT TE */
582 ib.d[ib.dws++]=f2u(0.0f);
583 /* PA_SC_VPORT_0_TE_ZMAX: max Z value from VPORT TE */
584 ib.d[ib.dws++]=f2u(1.0f);
585 }
586
587 static void ctx_pa_sc_vport_0(struct pci_dev *dev, struct ptn_tri *p)
588 {
589 /* PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) 0 */
590 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
591 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_VPORT_0_SCISSOR_TL);
592 /* PA_SC_VPORT_0_SCISSOR_TL */
593 ib.d[ib.dws++]=set(PSVST_X, 0) | set(PSVST_Y, 0);
594 /* PA_SC_VPORT_0_SCISSOR_BR */
595 ib.d[ib.dws++]=set(PSVSB_X, p->w) | set(PSVSB_Y, p->h);
596
597 ctx_pa_sc_vport_0_te(dev, p);
598 }
599
600 static void ctx_pa_sc_vports_te(struct pci_dev *dev)
601 {
602 /*
603 * PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT)
604 * TE (Transform Engine)
605 */
606 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
607 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_VPORT_TE_CTL);
608 /* PA_SC_VPORT_TE_CTL: no so called perpective division */
609 ib.d[ib.dws++]=PSVTC_VPORT_X_SCALE_ENA | PSVTC_VPORT_X_OF_ENA
610 | PSVTC_VPORT_Y_SCALE_ENA | PSVTC_VPORT_Y_OF_ENA
611 | PSVTC_VPORT_Z_SCALE_ENA | PSVTC_VPORT_Z_OF_ENA
612 | PSVTC_VTX_W0_FMT;
613 }
614
615 static void ctx_pa_sc_vports(struct pci_dev *dev, struct ptn_tri *p)
616 {
617 /* PA (Primitive Assembler) SC (Scan Converter) VPORT (ViewPORT) */
618 ctx_pa_sc_vport_0(dev, p);
619 ctx_pa_sc_vports_te(dev);
620 }
621
622 static void ctx_pa_sc(struct pci_dev *dev, struct ptn_tri *p)
623 {
624 /* PA (Primitive Assembler) SC (Scan Converter) */
625 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
626 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_MODE_CTL_0);
627 /* PA_SC_MODE_CTL_0 */
628 ib.d[ib.dws++]=0;
629 /* PA_SC_MODE_CTL_1 */
630 ib.d[ib.dws++]=0;
631
632 /* defines how to render the edge of primitives */
633 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
634 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_EDGERULE);
635 /* PA_SC_EDGERULE */
636 ib.d[ib.dws++]=0xaaaaaaaa;
637
638 /*--------------------------------------------------------------------*/
639 /* Anti-Aliasing... probably */
640 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
641 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_AA_CFG);
642 /* PA_SC_AA_CFG */
643 ib.d[ib.dws++]=0;
644
645 /* do something AA related */
646 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
647 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_AA_MASK_X0Y0_X1Y0);
648 /* PA_SC_AA_MASK_X0Y0_X1Y0 */
649 ib.d[ib.dws++]=0xffffffff;
650 /* PA_SC_AA_MASK_X0Y1_X1Y1 */
651 ib.d[ib.dws++]=0xffffffff;
652 /*--------------------------------------------------------------------*/
653
654 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 10);
655 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_CLIPRECT_RULE);
656 /*
657 * PA_SC_CLIPRECT_RULE: no scissor required then clip rule
658 * is 0xffff (no specs provided)
659 */
660 ib.d[ib.dws++]=set(PSCR_CLIP_RULE, 0xffff);
661 /* PA_SC_CLIPRECT_0_TL */
662 ib.d[ib.dws++]=0;
663 /* PA_SC_CLIPRECT_0_BR */
664 ib.d[ib.dws++]=set(PSCB_X, p->w) | set(PSCB_Y, p->h);
665 /* PA_SC_CLIPRECT_1_TL */
666 ib.d[ib.dws++]=0;
667 /* PA_SC_CLIPRECT_1_BR */
668 ib.d[ib.dws++]=set(PSCB_X, p->w) | set(PSCB_Y, p->h);
669 /* PA_SC_CLIPRECT_2_TL */
670 ib.d[ib.dws++]=0;
671 /* PA_SC_CLIPRECT_2_BR */
672 ib.d[ib.dws++]=set(PSCB_X, p->w) | set(PSCB_Y, p->h);
673 /* PA_SC_CLIPRECT_3_TL */
674 ib.d[ib.dws++]=0;
675 /* PA_SC_CLIPRECT_3_BR */
676 ib.d[ib.dws++]=set(PSCB_X, p->w) | set(PSCB_Y, p->h);
677
678 /*--------------------------------------------------------------------*/
679 /*
680 * Tells the SC (Scan Converter/rasteriser) we don't use
681 * line stipple since we do not render line primitives.
682 * XXX: ORed register? Because if not will set all bits to 0!
683 * We only want to set to 0 LINE_STIPPLE_ENA.
684 */
685 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
686 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_LINE_STIPPLE);
687 /* PA_SC_LINE_STIPPLE */
688 ib.d[ib.dws++]=0;
689
690 /*
691 * Even if we are not rendering line primitives, tells the
692 * PA (Primitive Assembler) SC (scan converter/rasteriser)
693 * to do "something with the last pixel
694 */
695 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
696 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_LINE_CTL);
697 /* PA_SC_LINE_CTL */
698 ib.d[ib.dws++]=PSLC_LAST_PIXEL;
699 /*--------------------------------------------------------------------*/
700
701 /*--------------------------------------------------------------------*/
702 /* set the value of the scissors */
703 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
704 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_GENERIC_SCISSOR_TL);
705 /* PA_SC_GENERIC_SCISSOR_TL */
706 ib.d[ib.dws++]=set(PSGST_X, 0) | set(PSGST_Y, 0);
707 /* PA_SC_GENERIC_SCISSOR_BR */
708 ib.d[ib.dws++]=set(PSGSB_X, p->w) | set(PSGSB_Y, p->h);
709
710 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
711 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_SCREEN_SCISSOR_TL);
712 /* PA_SC_SCREEN_SCISSOR_TL */
713 ib.d[ib.dws++]=set(PSSST_X, 0) | set(PSSST_Y, 0);
714 /* PA_SC_SCREEN_SCISSOR_BR */
715 ib.d[ib.dws++]=set(PSSSB_X, p->w) | set(PSSSB_Y, p->h);
716
717 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 4);
718 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_WND_OF);
719 /*
720 * PA_SC_WND_OF: the window offset in the screen which can be used by
721 * many scissors.
722 */
723 ib.d[ib.dws++]=0;
724 /* PA_SC_WND_SCISSOR_TL */
725 ib.d[ib.dws++]=set(PSWST_X, 0) | set(PSWST_Y, 0);
726 /* PA_SC_WND_SCISSOR_BR */
727 ib.d[ib.dws++]=set(PSWSB_X, p->w) | set(PSWSB_Y, p->h);
728 /*--------------------------------------------------------------------*/
729
730 ctx_pa_sc_vports(dev, p);
731 }
732
733 static void ctx_pa(struct pci_dev *dev, struct ptn_tri *p)
734 {
735 /* PA (Primitive Assembler) */
736 ctx_pa_su(dev);
737 ctx_pa_cl(dev);
738 ctx_pa_sc(dev, p);
739 }
740
741 void ctx_misc_init(struct pci_dev *dev)
742 {
743 /*--------------------------------------------------------------------*/
744 /* basic init GPU context, XXX: not using the CLR_CTX command ??? */
745 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 14);
746 ib.d[ib.dws++]=CTX_REG_IDX(VGT_OUTPUT_PATH_CTL);
747 /* VGT_OUTPUT_PATH_CTL */
748 ib.d[ib.dws++]=0;
749 /* VGT_HOS_CTL */
750 ib.d[ib.dws++]=0;
751 /* VGT_HOS_MAX_TESS_LVL */
752 ib.d[ib.dws++]=0;
753 /* VGT_HOS_MIN_TESS_LVL */
754 ib.d[ib.dws++]=0;
755 /* VGT_HOS_REUSE_DEPTH */
756 ib.d[ib.dws++]=0;
757 /* VGT_GROUP_PRIM_TYPE */
758 ib.d[ib.dws++]=0;
759 /* VGT_GROUP_FIRST_DECR */
760 ib.d[ib.dws++]=0;
761 /* VGT_GROUP_DECR */
762 ib.d[ib.dws++]=0;
763 /* VGT_GROUP_VECT_0_CTL */
764 ib.d[ib.dws++]=0;
765 /* VGT_GROUP_VECT_1_CTL */
766 ib.d[ib.dws++]=0;
767 /* VGT_GROUP_VECT_0_FMT_CTL */
768 ib.d[ib.dws++]=0;
769 /* VGT_GROUP_VECT_1_FMT_CTL */
770 ib.d[ib.dws++]=0;
771 /* VGT_GS_MODE */
772 ib.d[ib.dws++]=0;
773
774 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
775 ib.d[ib.dws++]=CTX_REG_IDX(VGT_PRIM_ID_ENA);
776 /* VGT_PRIM_ID_ENA */
777 ib.d[ib.dws++]=0;
778
779 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
780 ib.d[ib.dws++]=CTX_REG_IDX(VGT_PRIM_ID_RESET);
781 /* VGT_PRIM_ID_RESET */
782 ib.d[ib.dws++]=0;
783
784 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
785 ib.d[ib.dws++]=CTX_REG_IDX(VGT_STRMOUT_CFG);
786 /* VGT_STRMOUT_CFG */
787 ib.d[ib.dws++]=0;
788 /* VGT_STRMOUT_BUF_CFG */
789 ib.d[ib.dws++]=0;
790
791 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
792 ib.d[ib.dws++]=CTX_REG_IDX(IA_MULTI_VGT_PARAM);
793 /* IA_MULTI_VGT_PARAM */
794 ib.d[ib.dws++]=IMVP_SWITCH_ON_EOP | IMVP_PARTIAL_VS_WAVE_ON
795 | set(IMVP_PRIM_GROUP_SZ, 63);
796
797 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
798 ib.d[ib.dws++]=CTX_REG_IDX(VGT_REUSE_OFF);
799 /* VGT_REUSE_OFF */
800 ib.d[ib.dws++]=0;
801 /* VGT_VTX_CNT_ENA */
802 ib.d[ib.dws++]=0;
803
804 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
805 ib.d[ib.dws++]=CTX_REG_IDX(VGT_SHADER_STAGES_ENA);
806 /* VGT_SHADER_STAGES_ENA */
807 ib.d[ib.dws++]=0;
808
809 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 3);
810 ib.d[ib.dws++]=CTX_REG_IDX(PA_SC_CENTROID_PRIORITY_0);
811 /* PA_SC_CENTROID_PRIORITY_0 */
812 ib.d[ib.dws++]=0x76543210;
813 /* PA_SC_CENTROID_PRIORITY_1 */
814 ib.d[ib.dws++]=0xfedcba98;
815
816 ib.d[ib.dws++]=PKT3(PKT3_SET_CTX_REG, 2);
817 ib.d[ib.dws++]=CTX_REG_IDX(DB_EQAA);
818 /* DB_EQAA */
819 ib.d[ib.dws++]=0x00110000;
820 /*--------------------------------------------------------------------*/
821 }
822
823 /*
824 * Config reg programming, then, in theory, flushing before modifiying their
825 * values. If same value for *ALL* accel code, should go into the linux
826 * module to be set once and for all.
827 */
828 static void cfg(struct pci_dev *dev, struct ptn_tri *p)
829 {
830 /*--------------------------------------------------------------------*/
831 /* VGT (Vertex Grouper and Tesselator block) */
832 ib.d[ib.dws++]=PKT3(PKT3_SET_CFG_REG, 2);
833 ib.d[ib.dws++]=CFG_REG_IDX(VGT_PRIM_TYPE);
834 /* VGT_PRIM_TYPE */
835 ib.d[ib.dws++]=set(VPT_PRIM_TYPE, VPT_TRILIST);
836 /*--------------------------------------------------------------------*/
837
838 /*--------------------------------------------------------------------*/
839 /* PA (Primitive Assembler) CL (CLipper) */
840 ib.d[ib.dws++]=PKT3(PKT3_SET_CFG_REG, 2);
841 ib.d[ib.dws++]=CFG_REG_IDX(PA_CL_ENHANCE);
842 /* PA_CL_ENHANCE */
843 ib.d[ib.dws++]=set(PCE_CLIP_SEQ_N, 3) | PCE_CLIP_VTX_REORDER_ENA;
844 /*--------------------------------------------------------------------*/
845 }
846
847 static void ctx(struct pci_dev *dev, struct ptn_tri *p)
848 {
849 ctx_misc_init(dev);
850 ctx_vgt(dev);
851 ctx_spi(dev);
852 ctx_pa(dev, p);
853 ctx_dbs(dev);
854 ctx_cbs(dev, p);
855 }
856
857 static void indirect_cpy(struct pci_dev *dev, u64 dst, u32 *src, u64 dws)
858 {
859 while (dws--) {
860 vram_w32(dev, *src, dst);
861 ++src;
862 dst += sizeof(u32);
863 }
864 }
865
866 /* build raw commands and raw buffer to render a basic triangle primitive */
867 long ptn_tri(struct pci_dev *dev, struct ptn_tri *p)
868 {
869 struct dev_drv_data *dd;
870 long r;
871
872 dev_info(&dev->dev, "pattern triangle:fb=0x%016llx,w=%u,h=%u,pixel_fmt=%s\n",
873 p->fb_gpu_addr, p->w, p->h, alga_pixel_fmts_str[p->pixel_fmt]);
874 dd = pci_get_drvdata(dev);
875
876 /*--------------------------------------------------------------------*/
877 /* copy the vertex array (position + color ) in vram */
878 r = rng_alloc_align(&vtx_buf, &dd->vram.mng, sizeof(vertices), 4 * 4);
879 if (r != 0) {
880 dev_err(&dev->dev, "pattern triangle:unable to allocate vertex buffer in (v)ram\n");
881 return -ENOMEM;
882 }
883 if (sizeof(vertices) & 0x3) {
884 dev_err(&dev->dev, "pattern triangle:vertices size not dword aligned\n");
885 return -EINVAL;
886 }
887 indirect_cpy(dev, vtx_buf, (u32*)&vertices[0], sizeof(vertices) >> 2);
888 /*--------------------------------------------------------------------*/
889
890 /*--------------------------------------------------------------------*/
891 /* copy the buffer resource descriptors in vram */
892
893 /* vertex position buffer start address */
894 buf_res_descs[0] = lower_32_bits(vtx_buf);
895 buf_res_descs[1] |= upper_32_bits(vtx_buf);
896 /* vertex color buffer start address */
897 buf_res_descs[4] = lower_32_bits(vtx_buf + 4 * sizeof(float));
898 buf_res_descs[5] |= upper_32_bits(vtx_buf + 4 * sizeof(float));
899 /*--------------------------------------------------------------------*/
900
901 /*--------------------------------------------------------------------*/
902 /* copy the vertex shader in vram */
903 r = rng_alloc_align(&vs_buf, &dd->vram.mng, sizeof(vs), 256);
904 if (r != 0) {
905 dev_err(&dev->dev, "pattern triangle:unable to allocate vertex shader buffer in (v)ram\n");
906 return -ENOMEM;
907 }
908 if (sizeof(vs) & 0x3) {
909 dev_err(&dev->dev, "pattern triangle:vertex shader size not dword aligned\n");
910 return -EINVAL;
911 }
912 indirect_cpy(dev, vs_buf, &vs[0], sizeof(vs) >> 2);
913 /*--------------------------------------------------------------------*/
914
915 /*--------------------------------------------------------------------*/
916 /* copy the pixel/fragment shader in vram */
917 r = rng_alloc_align(&ps_buf, &dd->vram.mng, sizeof(ps), 256);
918 if (r != 0) {
919 dev_err(&dev->dev, "pattern triangle:unable to allocate pixel/fragment shader buffer in (v)ram\n");
920 return -ENOMEM;
921 }
922 if (sizeof(ps) & 0x3) {
923 dev_err(&dev->dev, "pattern triangle:pixel/fragment shader size not dword aligned\n");
924 return -EINVAL;
925 }
926 indirect_cpy(dev, ps_buf, &ps[0], sizeof(ps) >> 2);
927 /*--------------------------------------------------------------------*/
928
929 /*--------------------------------------------------------------------*/
930 /* create the indirect buffer */
931 r = rng_alloc_align(&ib.gpu_addr, &dd->vram.mng, sizeof(ib.d), 16 * 4);
932 if (r != 0) {
933 dev_err(&dev->dev, "pattern triangle:unable to indirect buffer in (v)ram\n");
934 return -ENOMEM;
935 }
936 ib.dws=0;
937 /*--------------------------------------------------------------------*/
938
939 /*--------------------------------------------------------------------*/
940 /* sync shader caches, texture cache, color block caches */
941 ib.d[ib.dws++]=PKT3(PKT3_SET_CFG_REG, 2);
942 ib.d[ib.dws++]=CFG_REG_IDX(CP_COHER_CTL_1);
943 ib.d[ib.dws++]=0;
944 ib.d[ib.dws++]=PKT3(PKT3_SURF_SYNC, 4);
945 /* CP_COHER_CTL_0 */
946 ib.d[ib.dws++]=CCC_SH_ICACHE_ACTION_ENA | CCC_SH_KCACHE_ACTION_ENA
947 | CCC_TC_ACTION_ENA | CCC_CB_ACTION_ENA
948 | CCC_CB0_DEST_BASE_ENA;
949 /* CP_COHER_SZ */
950 ib.d[ib.dws++]=0xffffffff;
951 /* CP_COHER_BASE */
952 ib.d[ib.dws++]=0;
953 ib.d[ib.dws++]=0x0000000a;/* polling interval, 0xa(10) * 16 clocks */
954 /*--------------------------------------------------------------------*/
955
956 /*--------------------------------------------------------------------*/
957 /* seems mandatory at the start of a command stream */
958 ib.d[ib.dws++]=PKT3(PKT3_CTX_CTL, 2);
959 ib.d[ib.dws++]=0x80000000;
960 ib.d[ib.dws++]=0x80000000;
961 /*--------------------------------------------------------------------*/
962
963 /*====================================================================*/
964 /* the real thing is here */
965 cfg(dev, p);
966 ctx(dev, p);
967 /*====================================================================*/
968
969 /*--------------------------------------------------------------------*/
970 /* the draw command launch */
971 ib.d[ib.dws++]=PKT3(PKT3_IDX_TYPE, 1);
972 ib.d[ib.dws++]=set(PKT3_SZ, PKT3_16BITS);
973
974 ib.d[ib.dws++]=PKT3(PKT3_INST_N, 1);
975 ib.d[ib.dws++]=1;
976
977 ib.d[ib.dws++]=PKT3(PKT3_DRAW_IDX_AUTO, 2);
978 /* 3 indices to generate */
979 ib.d[ib.dws++]=3;
980 /* VGT_DRAW_INITIATOR */
981 ib.d[ib.dws++]=set(VDI_SRC_SELECT, VDI_AUTO_IDX);
982 /*--------------------------------------------------------------------*/
983
984 /*--------------------------------------------------------------------*/
985 /* flush CBs and DB, XXX: miss the main CB? */
986 ib.d[ib.dws++]=PKT3(PKT3_SET_CFG_REG, 2);
987 ib.d[ib.dws++]=CFG_REG_IDX(CP_COHER_CTL_1);
988 ib.d[ib.dws++]=0;
989 ib.d[ib.dws++]=PKT3(PKT3_SURF_SYNC, 4);
990 /* CP_COHER_CTL_0 */
991 ib.d[ib.dws++]=CCC_CB0_DEST_BASE_ENA | CCC_CB1_DEST_BASE_ENA
992 | CCC_CB2_DEST_BASE_ENA | CCC_CB3_DEST_BASE_ENA
993 | CCC_CB4_DEST_BASE_ENA | CCC_CB5_DEST_BASE_ENA
994 | CCC_CB6_DEST_BASE_ENA | CCC_CB7_DEST_BASE_ENA
995 | CCC_DB_DEST_BASE_ENA | CCC_DB_ACTION_ENA | CCC_TCL1_ACTION_ENA
996 | CCC_TC_ACTION_ENA | CCC_SH_KCACHE_ACTION_ENA
997 | CCC_SH_ICACHE_ACTION_ENA;
998 /* CP_COHER_SZ */
999 ib.d[ib.dws++]=0xffffffff;
1000 /* CP_COHER_BASE */
1001 ib.d[ib.dws++]=0;
1002 ib.d[ib.dws++]=0x0000000a;/* polling interval, 0xa(10) * 16 clocks */
1003 /*--------------------------------------------------------------------*/
1004
1005 /*--------------------------------------------------------------------*/
1006 /* EOP event with some caches flush and invalidation */
1007 ib.d[ib.dws++]=PKT3(PKT3_EVENT_WR_EOP, 5);
1008 ib.d[ib.dws++]=set(PKT3_EVENT_IDX, 5) | set(VEI_EVENT_TYPE,
1009 VEI_CACHE_FLUSH_AND_INV_TS_EVENT);
1010 ib.d[ib.dws++]=lower_32_bits(p->fb_gpu_addr);
1011 ib.d[ib.dws++]=upper_32_bits(p->fb_gpu_addr)
1012 | set(PKT3_DATA_SEL, 2) | set(PKT3_INT_SEL, 2);
1013 ib.d[ib.dws++]=0xdeadbeef;
1014 ib.d[ib.dws++]=0xcafedead;
1015 /*--------------------------------------------------------------------*/
1016
1017 /* align size, upload and run the indirect buffer */
1018 while ((ib.dws & CP_RING_PFP_DW_MASK) != 0)
1019 ib.d[ib.dws++] = PKT2;
1020 indirect_cpy(dev, ib.gpu_addr, (u32*)&ib.d[0], ib.dws);
1021
1022 gfx_wr(dev, PKT3(PKT3_IB, 3));
1023 gfx_wr(dev, lower_32_bits(ib.gpu_addr));
1024 gfx_wr(dev, upper_32_bits(ib.gpu_addr));
1025 gfx_wr(dev, ib.dws);
1026 gfx_commit(dev);
1027 return 0;
1028 }
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 5d4d40f..2a0be5d)
... ... static inline u32 get(u32 mask, u32 v)
260 260 #define BHE_HDP_WR_ENA BIT(1) #define BHE_HDP_WR_ENA BIT(1)
261 261 #define HDP_REG_COHERENCY_FLUSH_CTL 0x54a0 #define HDP_REG_COHERENCY_FLUSH_CTL 0x54a0
262 262
263 #include "gpu/regs_cfg.h"
264 #include "gpu/regs_sh.h"
263 #include <alga/amd/si/regs_cfg.h>
264 #include <alga/amd/si/regs_sh.h>
265 265 #include "gpu/regs_cps.h" #include "gpu/regs_cps.h"
266 266 #include "regs_rlc.h" #include "regs_rlc.h"
267 267 #include "regs_dma.h" #include "regs_dma.h"
268 #include "gpu/regs_ctx.h"
268 #include <alga/amd/si/regs_ctx.h>
269 269
270 270 #define VM_CTXS_N 16 #define VM_CTXS_N 16
271 271 static u32 regs_vm_ctx_pt_base_addr[VM_CTXS_N] __attribute__ ((unused)) = { static u32 regs_vm_ctx_pt_base_addr[VM_CTXS_N] __attribute__ ((unused)) = {
File include/alga/amd/si/ioctl.h changed (mode: 100644) (index 1705d18..39df302)
16 16 #define SI_MEM_ALLOC 7 #define SI_MEM_ALLOC 7
17 17 #define SI_MEM_FREE 8 #define SI_MEM_FREE 8
18 18 #define SI_INFO 9 #define SI_INFO 9
19 #define SI_PATTERN 10
20 #define SI_DMA 11
21 #define SI_CPU_ADDR_TO_GPU_ADDR 12
22 #define SI_GFX_IB 13
23 #define SI_GFX_FENCE 14
19 #define SI_DMA 10
20 #define SI_CPU_ADDR_TO_GPU_ADDR 11
21 #define SI_GFX_IB 12
22 #define SI_GFX_FENCE 13
24 23
25 24 #define SI_CONTEXT_LOST 1/* for instance, back from suspend */ #define SI_CONTEXT_LOST 1/* for instance, back from suspend */
26 25
 
... ... struct si_gfx_ib {
98 97 uint64_t dws_n; uint64_t dws_n;
99 98 }; };
100 99
101 /*----------------------------------------------------------------------------*/
102 /* valid only if pattern support was compiled in */
103 #define PATTERN_ID_DB_FB_FILL 1
104 #define PATTERN_ID_TRI 2
105 struct si_patterns {
106 uint8_t id;
107 union {
108 struct ptn_db_fb_fill {
109 uint64_t front_gpu_addr;
110 uint64_t back_gpu_addr;
111 uint32_t w;
112 uint32_t h;
113 uint8_t pixel_fmt;
114 } ptn_db_fb_fill;
115 struct ptn_tri {
116 uint64_t fb_gpu_addr;
117 uint32_t w;
118 uint32_t h;
119 uint8_t pixel_fmt;
120 } ptn_tri;
121 };
122 };
123 /*----------------------------------------------------------------------------*/
124
125 100 #ifndef __KERNEL__ #ifndef __KERNEL__
126 101 #define SI_GPU_PAGE_SZ 4096 #define SI_GPU_PAGE_SZ 4096
127 102 #endif #endif
File include/alga/amd/si/pkt.h copied from file drivers/gpu/alga/amd/si/gpu/cps.h (similarity 71%) (mode: 100644) (index 8108209..6807128)
1 #ifndef _GPU_CPS_H
2 #define _GPU_CPS_H
1 #ifndef ALGA_AMD_SI_PKT_H
2 #define ALGA_AMD_SI_PKT_H
3 3 /* /*
4 4 author Sylvain Bertrand <digital.ragnarok@gmail.com> author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 8
9 /* do get raw u32 value from a 32 bits float */
10 union f2u {
11 float f;
12 u32 u;
13 };
14 static inline u32 f2u(float f)
15 {
16 union f2u tmp;
9 /* XXX:meant to be used from userland too */
17 10
18 tmp.f = f;
19 return tmp.u;
20 }
21
22 #define CP_RING_LOG2_QWS 17
23 #define CP_RING_LOG2_DWS (CP_RING_LOG2_QWS + 1)
24 #define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1)
11 #ifndef __KERNEL__
12 #ifndef BIT
13 #define BIT(x) (1 << (x))
14 #endif
15 #endif
25 16
26 17 #define CP_RING_PFP_DWS 16 #define CP_RING_PFP_DWS 16
27 18 #define CP_RING_PFP_DW_MASK (CP_RING_PFP_DWS - 1) #define CP_RING_PFP_DW_MASK (CP_RING_PFP_DWS - 1)
 
... ... static inline u32 f2u(float f)
110 101 #define PKT3_SET_SH_REG_END 0x0000c000 #define PKT3_SET_SH_REG_END 0x0000c000
111 102 #define SH_REG_IDX(x) ((x - PKT3_SET_SH_REG_START) >> 2) #define SH_REG_IDX(x) ((x - PKT3_SET_SH_REG_START) >> 2)
112 103
113 struct cp
114 {
115 struct fence fence;
116 struct ring ring;
117 spinlock_t lock;
118 u32 wptr; /* dword index in ring buffer: accounted by CPU */
119 };
120
121 void cps_intr_ena(struct pci_dev *dev);
122 void cps_intr_reset(struct pci_dev *dev);
123 long cps_engines_ucode_load(struct pci_dev *dev);
124 void cps_engines_ucode_program(struct pci_dev *dev);
125 void cps_engines_stop(struct pci_dev *dev);
126 void cps_init_once(struct pci_dev *dev);
127 void cps_init(struct pci_dev *dev);
128 void cps_me_init(struct pci_dev *dev);
129 void cps_enable(struct pci_dev *dev);
130 void cps_ctx_clr(struct pci_dev *dev);
131 void gfx_wr(struct pci_dev *dev, u32 v);
132 void gfx_commit(struct pci_dev *dev);
133 void c0_wr(struct pci_dev *dev, u32 v);
134 void c0_commit(struct pci_dev *dev);
135 void c1_wr(struct pci_dev *dev, u32 v);
136 void c1_commit(struct pci_dev *dev);
137 104 #endif #endif
File include/alga/amd/si/regs_cfg.h renamed from drivers/gpu/alga/amd/si/gpu/regs_cfg.h (similarity 98%) (mode: 100644) (index 5ecf28c..25e1372)
1 #ifndef _GPU_REGS_CFG_H
2 #define _GPU_REGS_CFG_H
1 #ifndef ALGA_AMD_SI_REGS_CFG_H
2 #define ALGA_AMD_SI_REGS_CFG_H
3
4 /* XXX:meant to be used from userland too */
5
6 #ifndef __KERNEL__
7 #ifndef BIT
8 #define BIT(x) (1 << (x))
9 #endif
10 #endif
11
3 12 /* start of configuration register area: 0x8000-0xb000 */ /* start of configuration register area: 0x8000-0xb000 */
4 13 #define GRBM_CTL 0x8000 #define GRBM_CTL 0x8000
5 14 #define GC_RD_TIMEOUT 0xffffffff #define GC_RD_TIMEOUT 0xffffffff
File include/alga/amd/si/regs_ctx.h renamed from drivers/gpu/alga/amd/si/gpu/regs_ctx.h (similarity 99%) (mode: 100644) (index 5423750..ab6e94f)
1 #ifndef _GPU_REGS_CTX_H
2 #define _GPU_REGS_CTX_H
1 #ifndef ALGA_AMD_SI_REGS_CTX_H
2 #define ALGA_AMD_SI_REGS_CTX_H
3
4 /* XXX:meant to be used from userland too */
5
6 #ifndef __KERNEL__
7 #ifndef BIT
8 #define BIT(x) (1 << (x))
9 #endif
10 #endif
11
3 12 /* start of context register area: 0x28000-0x29000 */ /* start of context register area: 0x28000-0x29000 */
4 13 /* from there we must use indirect MMIO or a CP because above reg MMIO size */ /* from there we must use indirect MMIO or a CP because above reg MMIO size */
5 14 #define DB_RENDER_CTL 0x28000 #define DB_RENDER_CTL 0x28000
 
1405 1414 #define CB_7_COLOR_CLR_WORD_0 0x28e30 #define CB_7_COLOR_CLR_WORD_0 0x28e30
1406 1415 #define CB_7_COLOR_CLR_WORD_1 0x28e34 #define CB_7_COLOR_CLR_WORD_1 0x28e34
1407 1416 #endif #endif
1417
File include/alga/amd/si/regs_sh.h renamed from drivers/gpu/alga/amd/si/gpu/regs_sh.h (similarity 92%) (mode: 100644) (index 1bcf11e..5ef48ca)
1 #ifndef _GPU_REGS_SH_H
2 #define _GPU_REGS_SH_H
1 #ifndef ALGA_AMD_SI_REGS_SH_H
2 #define ALGA_AMD_SI_REGS_SH_H
3
4 /* XXX:meant to be used from userland too */
5
6 #ifndef __KERNEL__
7 #ifndef BIT
8 #define BIT(x) (1 << (x))
9 #endif
10 #endif
11
3 12 /* start of shader register area: 0xb000-0xc000 */ /* start of shader register area: 0xb000-0xc000 */
4 13 #define SPI_SH_USER_DATA_VS_0 0xb130 #define SPI_SH_USER_DATA_VS_0 0xb130
5 14 #define SPI_SH_USER_DATA_VS_1 0xb134 #define SPI_SH_USER_DATA_VS_1 0xb134
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/linux-gpu-amd-si

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main