sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
cosmestics ee91a7ee91132de107bef05de70a8ea28f89dddf Sylvain BERTRAND 2014-01-28 23:12:44
smc cac cfg tbl init and some cosmetics 823419aa67f2ad91afb08942112be28d59752435 Sylvain BERTRAND 2014-01-28 22:31:35
smc dte cfg tbl init f3689c3d9e04a3462acf5c3a3aaabbdbb5307580 Sylvain BERTRAND 2014-01-27 21:16:32
init the smc mc arb freq set e276bc781e0e1ec9f7550c9bc8ffdb8de253be8b Sylvain BERTRAND 2014-01-24 16:22:31
smc_eng_pll_tbl init 323df7359605e25ac08800ca960bd3eb2267bc87 Sylvain BERTRAND 2014-01-24 15:50:18
factor out enging pll params computation 0c99b244c1a699abca8493097a8b1f82299b6721 Sylvain BERTRAND 2014-01-24 14:25:57
missed one file 99e76ae1afc06031299b77b3b1d7fbe80b869bc0 Sylvain BERTRAND 2014-01-24 13:03:50
atombios:eng mem pll used only for eng from SI dcdbc070fe4d7a9380ba27bb33274484d2725746 Sylvain BERTRAND 2014-01-24 13:01:43
mc arb tbl init c2d2e29d33a70910eaa09618ecb53783e976bea7 Sylvain BERTRAND 2014-01-24 11:06:39
preliminary support for smc mc arb reg set 0b7c90e4ccb988596b95ffccea10a2359ba585cd Sylvain BERTRAND 2014-01-23 16:57:47
removal of mc reg tbl slot idx duplicates 2b500504c5a651ed8f24df1fc43150cd205d8985 Sylvain BERTRAND 2014-01-23 14:08:10
mc regs set init for the driver state 7a9c50e02784f93d3443720d063b93829b9a57a1 Sylvain BERTRAND 2014-01-23 12:17:25
mc reg tbl init for the ulv state 97d55c06f7eeb31dd6f6a95fb13b30ddd22be157 Sylvain BERTRAND 2014-01-23 11:29:32
mc reg tbl init for the emergency state 7cf2fffd8bf166af90b20301652d03400feba029 Sylvain BERTRAND 2014-01-23 10:55:52
move smc sw related to mc reg tbl cbdb219935cc25639e5dca06ba99db995f87bef9 Sylvain BERTRAND 2014-01-23 10:15:53
smc mc reg tbl init for the initial state 1aa130d818c0aca415c0b76c80ec4bdb1e030a3f Sylvain BERTRAND 2014-01-22 18:01:49
clean way to deal with state and lvls 362777b13abdfacbeb0612e59c301e04dd2a7d65 Sylvain BERTRAND 2014-01-22 14:01:45
mc reg tbl reg address init 156ba053088bafba7a99fc2f1c2c0e2ca11d7f97 Sylvain BERTRAND 2014-01-22 13:15:15
mc register value valid bit set 4fabfcbad702789b9dbfd36d5fcaae8d0f9424f4 Sylvain BERTRAND 2014-01-22 02:31:53
addition of mc special registers ee876d15d34a720ebf4c26c57481d467fecbf1d5 Sylvain BERTRAND 2014-01-22 01:52:24
Commit ee91a7ee91132de107bef05de70a8ea28f89dddf - cosmestics
Author: Sylvain BERTRAND
Author date (UTC): 2014-01-28 23:12
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-01-28 23:12
Parent(s): 823419aa67f2ad91afb08942112be28d59752435
Signer:
Signing key:
Signing status: N
Tree: f830f3164baaa017e4238d2c056335f517dad35c
File Lines added Lines deleted
drivers/gpu/alga/amd/ABBREVIATIONS 1 0
drivers/gpu/alga/amd/atombios/tables/cmd.h 1 1
drivers/gpu/alga/amd/atombios/tables/data.h 1 1
drivers/gpu/alga/amd/atombios/tables/pp.h 25 25
drivers/gpu/alga/amd/atombios/tables/volt_info.h 65 0
drivers/gpu/alga/amd/atombios/tables/voltage_info.h 0 68
drivers/gpu/alga/amd/atombios/vm.c 89 99
drivers/gpu/alga/amd/atombios/vm.h 1 1
drivers/gpu/alga/amd/dce6/dp_link_train.c 12 13
drivers/gpu/alga/amd/si/Makefile 1 1
drivers/gpu/alga/amd/si/drv.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/ctx.c 31 32
drivers/gpu/alga/amd/si/dyn_pm/ctx.h 13 13
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c 14 14
drivers/gpu/alga/amd/si/dyn_pm/emergency.c 11 12
drivers/gpu/alga/amd/si/dyn_pm/initial.c 9 9
drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c 10 10
drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c 20 20
drivers/gpu/alga/amd/si/dyn_pm/smc_sw_regs.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c 31 31
drivers/gpu/alga/amd/si/dyn_pm/smc_volt.h 21 0
drivers/gpu/alga/amd/si/dyn_pm/smc_voltage.h 0 21
drivers/gpu/alga/amd/si/regs.h 1 1
drivers/gpu/alga/amd/si/smc_tbls.h 16 16
include/alga/amd/atombios/pp.h 8 8
include/alga/amd/atombios/vm.h 13 13
include/alga/dp.h 17 17
File drivers/gpu/alga/amd/ABBREVIATIONS changed (mode: 100644) (index fea8108..0799377)
... ... vesa Video Electronics Standards Association
300 300 vga Video Graphic Array vga Video Graphic Array
301 301 vgt Vertex Grouper and Tessellator (silicium block) vgt Vertex Grouper and Tessellator (silicium block)
302 302 vgt Vertex Geometry Translator vgt Vertex Geometry Translator
303 volt(s) voltage(s)
303 304 vport viewport vport viewport
304 305 vpost video post vpost video post
305 306 vram video ram vram video ram
File drivers/gpu/alga/amd/atombios/tables/cmd.h changed (mode: 100644) (index 3b0039b..f46ca97)
... ... struct cmd_tbls_list
36 36 u16 unused8[2]; u16 unused8[2];
37 37 __le16 dyn_mem_settings; __le16 dyn_mem_settings;
38 38 u16 unused9[3]; u16 unused9[3];
39 __le16 voltage;
39 __le16 volt;
40 40 u16 unused10[2]; u16 unused10[2];
41 41 __le16 mem_pll_compute; __le16 mem_pll_compute;
42 42 u16 unused11[5]; u16 unused11[5];
File drivers/gpu/alga/amd/atombios/tables/data.h changed (mode: 100644) (index fe898bb..89654f9)
... ... struct data_tbls_list
37 37
38 38 u16 unused6[3]; u16 unused6[3];
39 39
40 u16 voltage_info;
40 u16 volt_info;
41 41
42 42 u16 unused7; u16 unused7;
43 43 } __packed; } __packed;
File drivers/gpu/alga/amd/atombios/tables/pp.h changed (mode: 100644) (index 541cfd7..0093dbb)
... ... struct pp_thermal_ctrler {
67 67 #define PP_PLATFORM_CAPS_HW_DC BIT(5) #define PP_PLATFORM_CAPS_HW_DC BIT(5)
68 68 #define PP_PLATFORM_CAPS_GEMINI_PRIMARY BIT(6) #define PP_PLATFORM_CAPS_GEMINI_PRIMARY BIT(6)
69 69 #define PP_PLATFORM_CAPS_STEP_VDDC BIT(7) #define PP_PLATFORM_CAPS_STEP_VDDC BIT(7)
70 /* XXX:should not be used, use voltage_info table */
71 #define PP_PLATFORM_CAPS_VOLTAGE_CTL BIT(8)
70 /* XXX:should not be used, use volt_info tbl */
71 #define PP_PLATFORM_CAPS_VOLT_CTL BIT(8)
72 72 #define PP_PLATFORM_CAPS_SIDEPORT_CTL BIT(9) #define PP_PLATFORM_CAPS_SIDEPORT_CTL BIT(9)
73 73 #define PP_PLATFORM_CAPS_TURNOFFPLL_ASPML1 BIT(10) #define PP_PLATFORM_CAPS_TURNOFFPLL_ASPML1 BIT(10)
74 74 #define PP_PLATFORM_CAPS_HTLINK_CTL BIT(11) #define PP_PLATFORM_CAPS_HTLINK_CTL BIT(11)
75 /* XXX:should not be used, use voltage_info table */
75 /* XXX:should not be used, use volt_info tbl */
76 76 #define PP_PLATFORM_CAPS_MVDD_CTL BIT(12) #define PP_PLATFORM_CAPS_MVDD_CTL BIT(12)
77 77 /* ho to boot state on alerts (e.g. on an AC->DC transition) */ /* ho to boot state on alerts (e.g. on an AC->DC transition) */
78 78 #define PP_PLATFORM_CAPS_GOTO_BOOT_ON_ALERT BIT(13) #define PP_PLATFORM_CAPS_GOTO_BOOT_ON_ALERT BIT(13)
 
... ... struct pp_thermal_ctrler {
80 80 #define _PP_PLATFORM_CAPS_DONT_WAIT_FOR_VBLANK_ON_ALERT BIT(14) #define _PP_PLATFORM_CAPS_DONT_WAIT_FOR_VBLANK_ON_ALERT BIT(14)
81 81 /* /*
82 82 * does the driver control vddci independently from vddc * does the driver control vddci independently from vddc
83 * XXX:should not be used, use voltage_info table
83 * XXX:should not be used, use volt_info tbl
84 84 */ */
85 85 #define PP_PLATFORM_CAPS_VDDCI_CTL BIT(15) #define PP_PLATFORM_CAPS_VDDCI_CTL BIT(15)
86 86 /* enable the 'regulator hot' feature */ /* enable the 'regulator hot' feature */
87 87 #define PP_PLATFORM_CAPS_REGULATOR_HOT BIT(16) #define PP_PLATFORM_CAPS_REGULATOR_HOT BIT(16)
88 88 /* does the driver supports baco state */ /* does the driver supports baco state */
89 89 #define PP_PLATFORM_CAPS_BACO BIT(17) #define PP_PLATFORM_CAPS_BACO BIT(17)
90 /* does the driver supports new cac voltage table */
91 #define PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE BIT(18)
90 /* does the driver supports new cac volt tbl */
91 #define PP_PLATFORM_CAPS_NEW_CAC_VOLT BIT(18)
92 92 /* does the driver supports revert gpio5 polarity */ /* does the driver supports revert gpio5 polarity */
93 93 #define PP_PLATFORM_CAPS_REVERT_GPIO5_POLARITY BIT(19) #define PP_PLATFORM_CAPS_REVERT_GPIO5_POLARITY BIT(19)
94 94 /* does the driver supports thermal2gpio17 */ /* does the driver supports thermal2gpio17 */
 
... ... struct pp0 {
114 114 __le16 desc_array_of; __le16 desc_array_of;
115 115
116 116 __le16 back_bias_time; /* microseconds */ __le16 back_bias_time; /* microseconds */
117 __le16 voltage_time; /* microseconds */
117 __le16 volt_time; /* microseconds */
118 118 __le16 tbl_sz; /* used to selection proper revision */ __le16 tbl_sz; /* used to selection proper revision */
119 119
120 120 __le32 platform_caps; __le32 platform_caps;
 
... ... struct pp2 {
138 138 } __packed; } __packed;
139 139
140 140 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
141 struct voltage_on_clk_dep_tbl_entry {
141 struct volt_on_clk_dep_tbl_entry {
142 142 __le16 clk_low; __le16 clk_low;
143 143 u8 clk_hi; u8 clk_hi;
144 __le16 voltage_id; /* mV units or lkge idx */
144 __le16 volt_id; /* mV units or lkge idx */
145 145 } __packed; } __packed;
146 146
147 struct voltage_on_clk_dep_tbl {
147 struct volt_on_clk_dep_tbl {
148 148 u8 entries_n; u8 entries_n;
149 struct voltage_on_clk_dep_tbl_entry entries[];
149 struct volt_on_clk_dep_tbl_entry entries[];
150 150 } __packed; } __packed;
151 151
152 152 struct vddc_phase_shed_limits_tbl_entry { struct vddc_phase_shed_limits_tbl_entry {
153 __le16 voltage_mv; /* mV units only */
153 __le16 volt_mv; /* mV units only */
154 154 __le16 sclk_low; __le16 sclk_low;
155 155 u8 sclk_hi; u8 sclk_hi;
156 156 __le16 mclk_low; __le16 mclk_low;
 
... ... struct pp3 {
168 168 __le16 vddc_dep_on_sclk_tbl_of; __le16 vddc_dep_on_sclk_tbl_of;
169 169 __le16 vddci_dep_on_mclk_tbl_of; __le16 vddci_dep_on_mclk_tbl_of;
170 170 __le16 vddc_dep_on_mclk_tbl_of; __le16 vddc_dep_on_mclk_tbl_of;
171 __le16 clk_voltage_max_on_dc_tbl_of;
171 __le16 clk_volt_max_on_dc_tbl_of;
172 172 __le16 vddc_phase_shed_limits_tbl_of; __le16 vddc_phase_shed_limits_tbl_of;
173 173 __le16 mvdd_dep_on_mclk_tbl_of; __le16 mvdd_dep_on_mclk_tbl_of;
174 174 } __packed; } __packed;
 
... ... struct cac_lkge_tbl_entry {
179 179 /* /*
180 180 * We use this field for the "fake" standardized vddc for * We use this field for the "fake" standardized vddc for
181 181 * power calculations. For ci and newer, we use this as the * power calculations. For ci and newer, we use this as the
182 * real vddc value. In CI we read it as std_voltage_hi_sidd.
182 * real vddc value. In CI we read it as std_volt_hi_sidd.
183 183 */ */
184 184 __le16 vddc_mv; __le16 vddc_mv;
185 185 /* /*
186 186 * For ci and newer we use this as the "fake" standardized * For ci and newer we use this as the "fake" standardized
187 * vddc value. In ci we read it as std_voltage_lo_sidd.
187 * vddc value. In ci we read it as std_volt_lo_sidd.
188 188 */ */
189 189 __le32 lkge; __le32 lkge;
190 190 } __packed; } __packed;
 
... ... struct pp_clk_array {
298 298 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
299 299
300 300 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
301 #define VOLTAGE_TYPE_VDDC 1
302 #define VOLTAGE_TYPE_MVDDC 2
303 #define VOLTAGE_TYPE_MVDDQ 3
304 #define VOLTAGE_TYPE_VDDCI 4
305
306 #define VOLTAGE_ACTION_SET 0
307 #define VOLTAGE_ACTION_INIT_REGULATOR 3
308 #define VOLTAGE_ACTION_SET_PHASE 4
309 #define VOLTAGE_ACTION_GET 6/* get from virtual voltage id */
310 struct voltage_params {
301 #define VOLT_TYPE_VDDC 1
302 #define VOLT_TYPE_MVDDC 2
303 #define VOLT_TYPE_MVDDQ 3
304 #define VOLT_TYPE_VDDCI 4
305
306 #define VOLT_ACTION_SET 0
307 #define VOLT_ACTION_INIT_REGULATOR 3
308 #define VOLT_ACTION_SET_PHASE 4
309 #define VOLT_ACTION_GET 6/* get from virtual volt id */
310 struct volt_params {
311 311 u8 type; u8 type;
312 312 u8 action; u8 action;
313 313 __le16 lvl; __le16 lvl;
File drivers/gpu/alga/amd/atombios/tables/volt_info.h added (mode: 100644) (index 0000000..71205a8)
1 #ifndef TABLES_VOLT_INFO_H
2 #define TABLES_VOLT_INFO_H
3 /*
4 * Copyright 2013 Sylvain Bertrand (digital.ragnarok@gmail.com)
5 * This fork is protected by the GNU affero GPLv3 with additionnal rights
6 * Original code from Advanced Micro Devices, Inc.
7 */
8
9 struct volt_info_obj_hdr {
10 /* volt src: vddc, mvddc, mvddq or mvddci */
11 u8 type;
12 /* volt ctl mode: init/set volt/lkge/set phase */
13 u8 mode;
14 /* size of object */
15 __le16 sz;
16 } __packed;
17
18 /*----------------------------------------------------------------------------*/
19 /* volt_info_obj_hdr.mode */
20
21 /* volt and gpio lut */
22 #define VOLT_OBJ_GPIO_LUT 0x00
23 /* volt regulator init sequence through i2c */
24 #define VOLT_OBJ_VR_I2C_INIT_SEQ 0x03
25 /* set vregulator phase lookup table */
26 #define VOLT_OBJ_GPIO_PHASE_SHED_LUT 0x04
27 /* volt ctl by SVID2 */
28 #define VOLT_OBJ_SVID2 0x07
29 /* pwrboost volt and lkge_id lut */
30 #define VOLT_OBJ_PWRBOOST_LKGE_LUT 0x10
31 /* high volt state volt and lkge_id lut */
32 #define VOLT_OBJ_HIGH_STATE_LKGE_LUT 0x11
33 /* high1 volt_state volt and lkge_id lut */
34 #define VOLT_OBJ_HIGH1_STATE_LKGE_LUT 0x12
35 /*----------------------------------------------------------------------------*/
36
37 struct volt_info_obj_gpio_lut_entry {
38 __le32 volt_id; /* for gpio programming */
39 __le16 volt_val; /* volt value, mV units */
40 } __packed;
41
42 struct volt_info_obj_gpio {
43 /* volt mode = VOLT_OBJ_GPIO_LUT or VOLT_OBJ_GPIO_PHASE_SHED_LUT */
44 struct volt_info_obj_hdr hdr;
45 /* default is 0 which indicate control through cg vid mode */
46 u8 volt_gpio_ctl_id;
47 /* the number of entries in votlage/gpio lookup table */
48 u8 lut_entries_n;
49 /* phase delay in us */
50 u8 phase_delay;
51 u8 rsvd;
52 __le32 gpio_mask;
53 struct volt_info_obj_gpio_lut_entry lut_entries[];
54 } __packed;
55
56 union volt_info_obj {
57 struct volt_info_obj_gpio gpio;
58 /* many other types of object possible, see volt_info_obj_hdr.mode */
59 } __packed;
60
61 struct volt_info {
62 struct common_tbl_hdr hdr;
63 union volt_info_obj objs[];
64 } __packed;
65 #endif
File drivers/gpu/alga/amd/atombios/tables/voltage_info.h deleted (index bd94a4f..0000000)
1 #ifndef TABLES_VOLTAGE_INFO_H
2 #define TABLES_VOLTAGE_INFO_H
3 /*
4 * Copyright 2013 Sylvain Bertrand (digital.ragnarok@gmail.com)
5 * This fork is protected by the GNU affero GPLv3 with additionnal rights
6 * Original code from Advanced Micro Devices, Inc.
7 */
8
9 struct voltage_info_obj_hdr {
10 /* voltage source: vddc, mvddc, mvddq or mvddci */
11 u8 type;
12 /* voltage control mode: init/set voltage /lkge/set phase */
13 u8 mode;
14 /* size of object */
15 __le16 sz;
16 } __packed;
17
18 /*----------------------------------------------------------------------------*/
19 /* voltage_info_obj_hdr.mode */
20
21 /* voltage and gpio lookup table */
22 #define VOLTAGE_OBJ_GPIO_LUT 0x00
23 /* voltage regulator init sequence through i2c */
24 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 0x03
25 /* set vregulator phase lookup table */
26 #define VOLTAGE_OBJ_GPIO_PHASE_SHED_LUT 0x04
27 /* voltage control by SVID2 */
28 #define VOLTAGE_OBJ_SVID2 0x07
29 /* powerboost voltage and lkge_id lookup tbl */
30 #define VOLTAGE_OBJ_PWRBOOST_LKGE_LUT 0x10
31 /* high voltage state voltage and lkge_id lookup tbl */
32 #define VOLTAGE_OBJ_HIGH_STATE_LKGE_LUT 0x11
33 /* high1 voltage state voltage and lkge_id lookup table */
34 #define VOLTAGE_OBJ_HIGH1_STATE_LKGE_LUT 0x12
35 /*----------------------------------------------------------------------------*/
36
37 struct voltage_info_obj_gpio_lut_entry {
38 __le32 voltage_id; /* for gpio programming */
39 __le16 voltage_val; /* voltage value, mV units */
40 } __packed;
41
42 struct voltage_info_obj_gpio {
43 /*
44 * voltage mode = VOLTAGE_OBJ_GPIO_LUT or
45 * VOLTAGE_OBJ_GPIO_PHASE_SHED_LUT
46 */
47 struct voltage_info_obj_hdr hdr;
48 /* default is 0 which indicate control through cg vid mode */
49 u8 voltage_gpio_ctl_id;
50 /* the number of entries in votlage/gpio lookup table */
51 u8 lut_entries_n;
52 /* phase delay in us */
53 u8 phase_delay;
54 u8 rsvd;
55 __le32 gpio_mask;
56 struct voltage_info_obj_gpio_lut_entry lut_entries[];
57 } __packed;
58
59 union voltage_info_obj {
60 struct voltage_info_obj_gpio gpio;
61 /* many other types of object possible, see voltage_info_obj_hdr.mode */
62 } __packed;
63
64 struct voltage_info {
65 struct common_tbl_hdr hdr;
66 union voltage_info_obj objs[];
67 } __packed;
68 #endif
File drivers/gpu/alga/amd/atombios/vm.c changed (mode: 100644) (index 8d4f24f..734f29e)
17 17 #include "tables/atb.h" #include "tables/atb.h"
18 18 #include "tables/cmd.h" #include "tables/cmd.h"
19 19 #include "tables/data.h" #include "tables/data.h"
20 #include "tables/voltage_info.h"
20 #include "tables/volt_info.h"
21 21 #include "tables/i2c.h" #include "tables/i2c.h"
22 22 #include "tables/pp.h" #include "tables/pp.h"
23 23
 
26 26
27 27 #define DONT_HAVE_X_CTL 0 #define DONT_HAVE_X_CTL 0
28 28 #define HAVE_X_CTL 1 #define HAVE_X_CTL 1
29 static long have_x_ctl(struct atombios *atb, u8 voltage_type, u8 voltage_mode)
29 static long have_x_ctl(struct atombios *atb, u8 volt_type, u8 volt_mode)
30 30 { {
31 31 u16 of; u16 of;
32 32 struct master_data_tbl *data_tbl; struct master_data_tbl *data_tbl;
33 struct voltage_info *info;
33 struct volt_info *info;
34 34 long r; long r;
35 35 u16 tbl_sz; u16 tbl_sz;
36 36 u8 *tbl_start; u8 *tbl_start;
 
... ... static long have_x_ctl(struct atombios *atb, u8 voltage_type, u8 voltage_mode)
40 40 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of); of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
41 41 data_tbl = atb->adev.rom + of; data_tbl = atb->adev.rom + of;
42 42
43 of = get_unaligned_le16(&data_tbl->list.voltage_info);
43 of = get_unaligned_le16(&data_tbl->list.volt_info);
44 44 info = atb->adev.rom + of; info = atb->adev.rom + of;
45 45
46 dev_info(atb->adev.dev, "atombios:voltage_info (0x%04x) revision "
47 "%u.%u\n", of, info->hdr.tbl_fmt_rev,
48 info->hdr.tbl_content_rev);
46 dev_info(atb->adev.dev, "atombios:volt_info (0x%04x) revision %u.%u\n",
47 of, info->hdr.tbl_fmt_rev, info->hdr.tbl_content_rev);
49 48 if (info->hdr.tbl_fmt_rev != 3 && info->hdr.tbl_content_rev != 1) { if (info->hdr.tbl_fmt_rev != 3 && info->hdr.tbl_content_rev != 1) {
50 dev_err(atb->adev.dev, "atombios:voltage_info revision not supported");
49 dev_err(atb->adev.dev, "atombios:volt_info revision not supported");
51 50 r = -ATB_ERR; r = -ATB_ERR;
52 51 goto unlock_mutex; goto unlock_mutex;
53 52 } }
54 53
55 54 /* /*
56 55 * We have vddc control, if there is a gpio to control vddc. We get this * We have vddc control, if there is a gpio to control vddc. We get this
57 * piece of information parsing the voltage info, looking for the
58 * definition of a gpio control voltage object for vddc.
56 * piece of information parsing the volt info, looking for the
57 * definition of a gpio control volt object for vddc.
59 58 */ */
60 59 tbl_start = (u8*)info; tbl_start = (u8*)info;
61 60 tbl_sz = get_unaligned_le16(&info->hdr.sz); tbl_sz = get_unaligned_le16(&info->hdr.sz);
62 of = offsetof(struct voltage_info, objs[0]);
61 of = offsetof(struct volt_info, objs[0]);
63 62
64 63 while (of < tbl_sz) { while (of < tbl_sz) {
65 struct voltage_info_obj_hdr *obj_hdr;
64 struct volt_info_obj_hdr *obj_hdr;
66 65
67 obj_hdr = (struct voltage_info_obj_hdr*)(tbl_start + of);
66 obj_hdr = (struct volt_info_obj_hdr*)(tbl_start + of);
68 67
69 if (obj_hdr->type == voltage_type
70 && obj_hdr->mode == voltage_mode) {
68 if (obj_hdr->type == volt_type
69 && obj_hdr->mode == volt_mode) {
71 70 r = HAVE_X_CTL; r = HAVE_X_CTL;
72 71 goto unlock_mutex; goto unlock_mutex;
73 72 } }
 
... ... long atb_have_vddc_ctl(struct atombios *atb)
86 85 { {
87 86 long r; long r;
88 87
89 r = have_x_ctl(atb, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT);
88 r = have_x_ctl(atb, VOLT_TYPE_VDDC, VOLT_OBJ_GPIO_LUT);
90 89 switch (r) { switch (r) {
91 90 case HAVE_X_CTL: case HAVE_X_CTL:
92 91 r = ATB_HAVE_VDDC_CTL; r = ATB_HAVE_VDDC_CTL;
 
... ... long atb_have_mvddc_ctl(struct atombios *atb)
103 102 { {
104 103 long r; long r;
105 104
106 r = have_x_ctl(atb, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
105 r = have_x_ctl(atb, VOLT_TYPE_MVDDC, VOLT_OBJ_GPIO_LUT);
107 106 switch (r) { switch (r) {
108 107 case HAVE_X_CTL: case HAVE_X_CTL:
109 108 r = ATB_HAVE_MVDDC_CTL; r = ATB_HAVE_MVDDC_CTL;
 
... ... long atb_have_vddci_ctl(struct atombios *atb)
120 119 { {
121 120 long r; long r;
122 121
123 r = have_x_ctl(atb, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
122 r = have_x_ctl(atb, VOLT_TYPE_VDDCI, VOLT_OBJ_GPIO_LUT);
124 123 switch (r) { switch (r) {
125 124 case HAVE_X_CTL: case HAVE_X_CTL:
126 125 r = ATB_HAVE_VDDCI_CTL; r = ATB_HAVE_VDDCI_CTL;
 
... ... long atb_have_vddc_phase_shed_ctl(struct atombios *atb)
137 136 { {
138 137 long r; long r;
139 138
140 r = have_x_ctl(atb, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_PHASE_SHED_LUT);
139 r = have_x_ctl(atb, VOLT_TYPE_VDDC, VOLT_OBJ_GPIO_PHASE_SHED_LUT);
141 140 switch (r) { switch (r) {
142 141 case HAVE_X_CTL: case HAVE_X_CTL:
143 142 r = ATB_HAVE_VDDC_PHASE_SHED_CTL; r = ATB_HAVE_VDDC_PHASE_SHED_CTL;
 
... ... long atb_have_vddc_phase_shed_ctl(struct atombios *atb)
150 149 } }
151 150 EXPORT_SYMBOL_GPL(atb_have_vddc_phase_shed_ctl); EXPORT_SYMBOL_GPL(atb_have_vddc_phase_shed_ctl);
152 151
153 static long voltage_info_obj_gpio_parse(struct atombios *atb,
154 struct voltage_info_obj_gpio *obj_gpio,
155 struct atb_voltage_tbl *tbl)
152 static long volt_info_obj_gpio_parse(struct atombios *atb,
153 struct volt_info_obj_gpio *obj_gpio,
154 struct atb_volt_tbl *tbl)
156 155 { {
157 156 u8 i; u8 i;
158 157
159 if (obj_gpio->lut_entries_n > ATB_VOLTAGE_TBL_ENTRIES_N_MAX) {
160 dev_err(atb->adev.dev, "atombios:voltage_info_obj_gpio has too many entries\n");
158 if (obj_gpio->lut_entries_n > ATB_VOLT_TBL_ENTRIES_N_MAX) {
159 dev_err(atb->adev.dev, "atombios:volt_info_obj_gpio has too many entries\n");
161 160 return -ATB_ERR; return -ATB_ERR;
162 161 } }
163 162
 
... ... static long voltage_info_obj_gpio_parse(struct atombios *atb,
166 165 tbl->mask_low = get_unaligned_le32(&obj_gpio->gpio_mask); tbl->mask_low = get_unaligned_le32(&obj_gpio->gpio_mask);
167 166
168 167 for (i = 0; i < obj_gpio->lut_entries_n; ++i) { for (i = 0; i < obj_gpio->lut_entries_n; ++i) {
169 struct voltage_info_obj_gpio_lut_entry *entry;
168 struct volt_info_obj_gpio_lut_entry *entry;
170 169
171 170 entry = &obj_gpio->lut_entries[i]; entry = &obj_gpio->lut_entries[i];
172 tbl->entries[i].val_mv = get_unaligned_le16(
173 &entry->voltage_val);
174 tbl->entries[i].smio_low = get_unaligned_le32(
175 &entry->voltage_id);
171 tbl->entries[i].val_mv = get_unaligned_le16(&entry->volt_val);
172 tbl->entries[i].smio_low = get_unaligned_le32(&entry->volt_id);
176 173 } }
177 174 return 0; return 0;
178 175 } }
179 176
180 static long x_gpio_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl,
181 u8 voltage_type, u8 voltage_mode)
177 static long x_gpio_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl,
178 u8 volt_type, u8 volt_mode)
182 179 { {
183 180 u16 of; u16 of;
184 181 struct master_data_tbl *data_tbl; struct master_data_tbl *data_tbl;
185 struct voltage_info *info;
182 struct volt_info *info;
186 183 long r; long r;
187 184 u16 tbl_sz; u16 tbl_sz;
188 185 u8 *tbl_start; u8 *tbl_start;
 
... ... static long x_gpio_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl,
192 189 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of); of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
193 190 data_tbl = atb->adev.rom + of; data_tbl = atb->adev.rom + of;
194 191
195 of = get_unaligned_le16(&data_tbl->list.voltage_info);
192 of = get_unaligned_le16(&data_tbl->list.volt_info);
196 193 info = atb->adev.rom + of; info = atb->adev.rom + of;
197 194
198 dev_info(atb->adev.dev, "atombios:voltage_info (0x%04x) revision "
199 "%u.%u\n", of, info->hdr.tbl_fmt_rev,
200 info->hdr.tbl_content_rev);
195 dev_info(atb->adev.dev, "atombios:volt_info (0x%04x) revision %u.%u\n",
196 of, info->hdr.tbl_fmt_rev, info->hdr.tbl_content_rev);
201 197 if (info->hdr.tbl_fmt_rev != 3 && info->hdr.tbl_content_rev != 1) { if (info->hdr.tbl_fmt_rev != 3 && info->hdr.tbl_content_rev != 1) {
202 dev_err(atb->adev.dev, "atombios:voltage_info revision not supported");
198 dev_err(atb->adev.dev, "atombios:volt_info revision not supported");
203 199 r = -ATB_ERR; r = -ATB_ERR;
204 200 goto unlock_mutex; goto unlock_mutex;
205 201 } }
206 202
207 203 /* /*
208 204 * We have vddc control, if there is a gpio to control vddc. We get this * We have vddc control, if there is a gpio to control vddc. We get this
209 * piece of information parsing the voltage info, looking for the
210 * definition of a gpio control voltage object for vddc.
205 * piece of information parsing the volt info, looking for the
206 * definition of a gpio control volt object for vddc.
211 207 */ */
212 208 tbl_start = (u8*)info; tbl_start = (u8*)info;
213 209 tbl_sz = get_unaligned_le16(&info->hdr.sz); tbl_sz = get_unaligned_le16(&info->hdr.sz);
214 of = offsetof(struct voltage_info, objs[0]);
210 of = offsetof(struct volt_info, objs[0]);
215 211
216 212 memset(tbl, 0, sizeof(*tbl)); memset(tbl, 0, sizeof(*tbl));
217 213 r = 0; r = 0;
218 214
219 215 while (of < tbl_sz) { while (of < tbl_sz) {
220 struct voltage_info_obj_hdr *obj_hdr;
216 struct volt_info_obj_hdr *obj_hdr;
221 217
222 obj_hdr = (struct voltage_info_obj_hdr*)(tbl_start + of);
218 obj_hdr = (struct volt_info_obj_hdr*)(tbl_start + of);
223 219
224 if (obj_hdr->type == voltage_type
225 && obj_hdr->mode == voltage_mode) {
226 struct voltage_info_obj_gpio *obj_gpio;
220 if (obj_hdr->type == volt_type
221 && obj_hdr->mode == volt_mode) {
222 struct volt_info_obj_gpio *obj_gpio;
227 223
228 obj_gpio = (struct voltage_info_obj_gpio*)obj_hdr;
229 r = voltage_info_obj_gpio_parse(atb, obj_gpio, tbl);
224 obj_gpio = (struct volt_info_obj_gpio*)obj_hdr;
225 r = volt_info_obj_gpio_parse(atb, obj_gpio, tbl);
230 226 goto unlock_mutex; goto unlock_mutex;
231 227 } }
232 228
 
... ... unlock_mutex:
238 234 return r; return r;
239 235 } }
240 236
241 long atb_vddc_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl)
237 long atb_vddc_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl)
242 238 { {
243 return x_gpio_tbl_get(atb, tbl, VOLTAGE_TYPE_VDDC,
244 VOLTAGE_OBJ_GPIO_LUT);
239 return x_gpio_tbl_get(atb, tbl, VOLT_TYPE_VDDC, VOLT_OBJ_GPIO_LUT);
245 240 } }
246 241 EXPORT_SYMBOL_GPL(atb_vddc_tbl_get); EXPORT_SYMBOL_GPL(atb_vddc_tbl_get);
247 242
248 long atb_vddci_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl)
243 long atb_vddci_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl)
249 244 { {
250 return x_gpio_tbl_get(atb, tbl, VOLTAGE_TYPE_VDDCI,
251 VOLTAGE_OBJ_GPIO_LUT);
245 return x_gpio_tbl_get(atb, tbl, VOLT_TYPE_VDDCI, VOLT_OBJ_GPIO_LUT);
252 246 } }
253 247 EXPORT_SYMBOL_GPL(atb_vddci_tbl_get); EXPORT_SYMBOL_GPL(atb_vddci_tbl_get);
254 248
255 long atb_mvddc_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl)
249 long atb_mvddc_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl)
256 250 { {
257 return x_gpio_tbl_get(atb, tbl, VOLTAGE_TYPE_MVDDC,
258 VOLTAGE_OBJ_GPIO_LUT);
251 return x_gpio_tbl_get(atb, tbl, VOLT_TYPE_MVDDC, VOLT_OBJ_GPIO_LUT);
259 252 } }
260 253 EXPORT_SYMBOL_GPL(atb_mvddc_tbl_get); EXPORT_SYMBOL_GPL(atb_mvddc_tbl_get);
261 254
262 long atb_vddc_phase_shed_tbl_get(struct atombios *atb,
263 struct atb_voltage_tbl *tbl)
255 long atb_vddc_phase_shed_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl)
264 256 { {
265 return x_gpio_tbl_get(atb, tbl, VOLTAGE_TYPE_VDDC,
266 VOLTAGE_OBJ_GPIO_PHASE_SHED_LUT);
257 return x_gpio_tbl_get(atb, tbl, VOLT_TYPE_VDDC,
258 VOLT_OBJ_GPIO_PHASE_SHED_LUT);
267 259 } }
268 260 EXPORT_SYMBOL_GPL(atb_vddc_phase_shed_tbl_get); EXPORT_SYMBOL_GPL(atb_vddc_phase_shed_tbl_get);
269 261
270 long voltage_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *mv)
262 long volt_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *mv)
271 263 { {
272 264 u16 of; u16 of;
273 265 struct master_cmd_tbl *cmd_tbl; struct master_cmd_tbl *cmd_tbl;
274 struct common_cmd_tbl_hdr *voltage;
275 struct voltage_params *ps;
266 struct common_cmd_tbl_hdr *volt;
267 struct volt_params *ps;
276 268 long r; long r;
277 269
278 270 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of); of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
279 271 cmd_tbl = atb->adev.rom + of; cmd_tbl = atb->adev.rom + of;
280 of = get_unaligned_le16(&cmd_tbl->list.voltage);
281
282 voltage = atb->adev.rom + of;
283 dev_info(atb->adev.dev, "atombios:voltage (0x%04x) revision %u.%u\n",
284 of, voltage->hdr.tbl_fmt_rev,voltage->hdr.tbl_content_rev);
285 if (voltage->hdr.tbl_fmt_rev != 1
286 || voltage->hdr.tbl_content_rev != 3) {
287 dev_err(atb->adev.dev, "atombios:voltage revision not supported");
272 of = get_unaligned_le16(&cmd_tbl->list.volt);
273
274 volt = atb->adev.rom + of;
275 dev_info(atb->adev.dev, "atombios:volt (0x%04x) revision %u.%u\n",
276 of, volt->hdr.tbl_fmt_rev,volt->hdr.tbl_content_rev);
277 if (volt->hdr.tbl_fmt_rev != 1 || volt->hdr.tbl_content_rev != 3) {
278 dev_err(atb->adev.dev, "atombios:volt revision not supported");
288 279 r = -ATB_ERR; r = -ATB_ERR;
289 280 goto exit; goto exit;
290 281 } }
 
... ... long voltage_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *mv)
296 287 r = -ATB_ERR; r = -ATB_ERR;
297 288 goto exit; goto exit;
298 289 } }
299 ps = (struct voltage_params *)atb->g_ctx.ps_top;
290 ps = (struct volt_params *)atb->g_ctx.ps_top;
300 291 ps->type = type; ps->type = type;
301 ps->action = VOLTAGE_ACTION_GET;
292 ps->action = VOLT_ACTION_GET;
302 293 put_unaligned_le16(lkge_idx, &ps->lvl); put_unaligned_le16(lkge_idx, &ps->lvl);
303 294
304 295 atb->g_ctx.fb_wnd = 0; atb->g_ctx.fb_wnd = 0;
 
... ... exit:
316 307 return r; return r;
317 308 } }
318 309
319 long atb_voltage_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *lvl)
310 long atb_volt_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *lvl)
320 311 { {
321 312 long r; long r;
322 313
323 314 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
324 315
325 r = voltage_get(atb, type, lkge_idx, lvl);
316 r = volt_get(atb, type, lkge_idx, lvl);
326 317
327 318 mutex_unlock(&atb->mutex); mutex_unlock(&atb->mutex);
328 319 return r; return r;
329 320 } }
330 EXPORT_SYMBOL_GPL(atb_voltage_get);
321 EXPORT_SYMBOL_GPL(atb_volt_get);
331 322
332 long atb_voltage_set(struct atombios *atb, u8 type, u16 lvl)
323 long atb_volt_set(struct atombios *atb, u8 type, u16 lvl)
333 324 { {
334 325 u16 of; u16 of;
335 326 struct master_cmd_tbl *cmd_tbl; struct master_cmd_tbl *cmd_tbl;
336 struct common_cmd_tbl_hdr *voltage;
337 struct voltage_params *ps;
327 struct common_cmd_tbl_hdr *volt;
328 struct volt_params *ps;
338 329 long r; long r;
339 330
340 331 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
341 332
342 333 of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of); of = get_unaligned_le16(&atb->hdr->master_cmd_tbl_of);
343 334 cmd_tbl = atb->adev.rom + of; cmd_tbl = atb->adev.rom + of;
344 of = get_unaligned_le16(&cmd_tbl->list.voltage);
345
346 voltage = atb->adev.rom + of;
347 dev_info(atb->adev.dev, "atombios:voltage (0x%04x) revision %u.%u\n",
348 of, voltage->hdr.tbl_fmt_rev,voltage->hdr.tbl_content_rev);
349 if (voltage->hdr.tbl_fmt_rev != 1
350 || voltage->hdr.tbl_content_rev != 3) {
351 dev_err(atb->adev.dev, "atombios:voltage revision not supported");
335 of = get_unaligned_le16(&cmd_tbl->list.volt);
336
337 volt = atb->adev.rom + of;
338 dev_info(atb->adev.dev, "atombios:volt (0x%04x) revision %u.%u\n",
339 of, volt->hdr.tbl_fmt_rev, volt->hdr.tbl_content_rev);
340 if (volt->hdr.tbl_fmt_rev != 1 || volt->hdr.tbl_content_rev != 3) {
341 dev_err(atb->adev.dev, "atombios:volt revision not supported");
352 342 r = -ATB_ERR; r = -ATB_ERR;
353 343 goto unlock_mutex; goto unlock_mutex;
354 344 } }
 
... ... long atb_voltage_set(struct atombios *atb, u8 type, u16 lvl)
360 350 r = -ATB_ERR; r = -ATB_ERR;
361 351 goto unlock_mutex; goto unlock_mutex;
362 352 } }
363 ps = (struct voltage_params *)atb->g_ctx.ps_top;
353 ps = (struct volt_params *)atb->g_ctx.ps_top;
364 354 ps->type = type; ps->type = type;
365 ps->action = VOLTAGE_ACTION_SET;
355 ps->action = VOLT_ACTION_SET;
366 356 put_unaligned_le16(lvl, &ps->lvl); put_unaligned_le16(lvl, &ps->lvl);
367 357
368 358 atb->g_ctx.fb_wnd = 0; atb->g_ctx.fb_wnd = 0;
 
... ... unlock_mutex:
376 366 mutex_unlock(&atb->mutex); mutex_unlock(&atb->mutex);
377 367 return r; return r;
378 368 } }
379 EXPORT_SYMBOL_GPL(atb_voltage_set);
369 EXPORT_SYMBOL_GPL(atb_volt_set);
380 370
381 static long voltage_on_clk_dep_tbl_parse(struct atombios *atb,
382 struct voltage_on_clk_dep_tbl *src,
383 struct atb_voltage_on_clk_dep_tbl *dst)
371 static long volt_on_clk_dep_tbl_parse(struct atombios *atb,
372 struct atb_volt_on_clk_dep_tbl *dst,
373 struct volt_on_clk_dep_tbl *src)
384 374 { {
385 375 u8 i; u8 i;
386 376
 
... ... static long voltage_on_clk_dep_tbl_parse(struct atombios *atb,
396 386 dst->entries[i].clk = dst->entries[i].clk =
397 387 get_unaligned_le16(&src->entries[i].clk_low) get_unaligned_le16(&src->entries[i].clk_low)
398 388 | (src->entries[i].clk_hi << 16); | (src->entries[i].clk_hi << 16);
399 dst->entries[i].voltage_id = get_unaligned_le16(
400 &src->entries[i].voltage_id);
389 dst->entries[i].volt_id = get_unaligned_le16(
390 &src->entries[i].volt_id);
401 391 } }
402 392 return 0; return 0;
403 393 } }
404 394
405 395 long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb, long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb,
406 struct atb_voltage_on_clk_dep_tbl *tbl)
396 struct atb_volt_on_clk_dep_tbl *tbl)
407 397 { {
408 398 u16 of; u16 of;
409 399 u16 pp_of; u16 pp_of;
 
... ... long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb,
412 402 long r; long r;
413 403 u16 tbl_sz; u16 tbl_sz;
414 404 u16 vddc_dep_on_sclk_tbl_of; u16 vddc_dep_on_sclk_tbl_of;
415 struct voltage_on_clk_dep_tbl *src_dep_tbl;
405 struct volt_on_clk_dep_tbl *src_dep_tbl;
416 406
417 407 mutex_lock(&atb->mutex); mutex_lock(&atb->mutex);
418 408
 
... ... long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb,
448 438 if (vddc_dep_on_sclk_tbl_of) { if (vddc_dep_on_sclk_tbl_of) {
449 439 src_dep_tbl = atb->adev.rom + pp_of + vddc_dep_on_sclk_tbl_of; src_dep_tbl = atb->adev.rom + pp_of + vddc_dep_on_sclk_tbl_of;
450 440
451 r = voltage_on_clk_dep_tbl_parse(atb, src_dep_tbl, tbl);
441 r = volt_on_clk_dep_tbl_parse(atb, tbl, src_dep_tbl);
452 442 } }
453 443
454 444 unlock_mutex: unlock_mutex:
 
... ... static long vddc_phase_shed_limits_tbl_parse(struct atombios *atb,
607 597
608 598 for (i = 0; i < dst->entries_n; ++i) { for (i = 0; i < dst->entries_n; ++i) {
609 599 dst->entries[i].vddc_mv = get_unaligned_le16( dst->entries[i].vddc_mv = get_unaligned_le16(
610 &src->entries[i].voltage_mv);
600 &src->entries[i].volt_mv);
611 601 dst->entries[i].sclk = dst->entries[i].sclk =
612 602 get_unaligned_le16(&src->entries[i].sclk_low) get_unaligned_le16(&src->entries[i].sclk_low)
613 603 | (src->entries[i].sclk_hi << 16); | (src->entries[i].sclk_hi << 16);
File drivers/gpu/alga/amd/atombios/vm.h changed (mode: 100644) (index 3c118fc..928c9b3)
5 5 * This fork is protected by the GNU affero GPLv3 with additionnal rights * This fork is protected by the GNU affero GPLv3 with additionnal rights
6 6 * Original code from Advanced Micro Devices, Inc. * Original code from Advanced Micro Devices, Inc.
7 7 */ */
8 long voltage_get(struct atombios *atb, u8 type, u16 id, u16 *mv);
8 long volt_get(struct atombios *atb, u8 type, u16 id, u16 *mv);
9 9 #endif #endif
File drivers/gpu/alga/amd/dce6/dp_link_train.c changed (mode: 100644) (index c7f62b9..69ce275)
26 26
27 27 static char *vs_names(u8 vs_pre_emph) static char *vs_names(u8 vs_pre_emph)
28 28 { {
29 vs_pre_emph &= DPCD_VOLTAGE_SWING_MASK;
29 vs_pre_emph &= DPCD_VOLT_SWING_MASK;
30 30
31 31 switch (vs_pre_emph) { switch (vs_pre_emph) {
32 case DPCD_VOLTAGE_SWING_400:
32 case DPCD_VOLT_SWING_400:
33 33 return "400 mV"; return "400 mV";
34 case DPCD_VOLTAGE_SWING_600:
34 case DPCD_VOLT_SWING_600:
35 35 return "600 mV"; return "600 mV";
36 case DPCD_VOLTAGE_SWING_800:
36 case DPCD_VOLT_SWING_800:
37 37 return "800 mV"; return "800 mV";
38 case DPCD_VOLTAGE_SWING_1200:
38 case DPCD_VOLT_SWING_1200:
39 39 return "1200 mV"; return "1200 mV";
40 40 default: default:
41 41 return "unregistered mV"; return "unregistered mV";
 
... ... static void lane_adjust_req_extract(u8 *link_status, u8 l, u8 *vs, u8 *pre_emph)
186 186 vs_pre_emph = link_status[DPCD_ADJUST_REQUEST_LANE0_1 vs_pre_emph = link_status[DPCD_ADJUST_REQUEST_LANE0_1
187 187 - DPCD_LANE0_1_STATUS + (l >> 1)]; - DPCD_LANE0_1_STATUS + (l >> 1)];
188 188 if (l & 1) if (l & 1)
189 vs_pre_emph = vs_pre_emph >>
190 DPCD_ADJUST_VOLTAGE_SWING_LANEY_SHIFT;
189 vs_pre_emph = vs_pre_emph >> DPCD_ADJUST_VOLT_SWING_LANEY_SHIFT;
191 190
192 *vs = vs_pre_emph & DPCD_ADJUST_VOLTAGE_SWING_LANEX_MASK;
191 *vs = vs_pre_emph & DPCD_ADJUST_VOLT_SWING_LANEX_MASK;
193 192 *pre_emph = vs_pre_emph & DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK; *pre_emph = vs_pre_emph & DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK;
194 193 } }
195 194
 
... ... static long drive_adjust(struct dce6 *dce, u8 i, u8 *vs_pre_emph,
227 226
228 227 pre_emph <<= 1; /* shift request bits for lane set register */ pre_emph <<= 1; /* shift request bits for lane set register */
229 228
230 current_vs = *vs_pre_emph & DPCD_VOLTAGE_SWING_MASK;
229 current_vs = *vs_pre_emph & DPCD_VOLT_SWING_MASK;
231 230 if (vs != current_vs) if (vs != current_vs)
232 231 r = VS_DIFFERENT; r = VS_DIFFERENT;
233 232
234 if (vs >= DPCD_VOLTAGE_SWING_1200)
235 vs |= DPCD_MAX_VOLTAGE_SWING_REACHED;
233 if (vs >= DPCD_VOLT_SWING_1200)
234 vs |= DPCD_MAX_VOLT_SWING_REACHED;
236 235 if (pre_emph >= DPCD_PRE_EMPHASIS_9_5) if (pre_emph >= DPCD_PRE_EMPHASIS_9_5)
237 236 pre_emph |= DPCD_MAX_PRE_EMPHASIS_REACHED; pre_emph |= DPCD_MAX_PRE_EMPHASIS_REACHED;
238 237
 
... ... static long clock_recovery(struct dce6 *dce, u8 i, u8 *vs_pre_emph)
272 271 if (clock_recovered(dce, i, link_status)) if (clock_recovered(dce, i, link_status))
273 272 break; break;
274 273
275 /* max voltage failed, downclock the link speed */
276 if ((*vs_pre_emph & DPCD_MAX_VOLTAGE_SWING_REACHED) != 0)
274 /* max volt failed, downclock the link speed */
275 if ((*vs_pre_emph & DPCD_MAX_VOLT_SWING_REACHED) != 0)
277 276 return CLOCK_RECOVERY_LINK_RATE_DOWNSHIFT_REQ; return CLOCK_RECOVERY_LINK_RATE_DOWNSHIFT_REQ;
278 277
279 278 r = drive_adjust(dce, i, vs_pre_emph, link_status); r = drive_adjust(dce, i, vs_pre_emph, link_status);
File drivers/gpu/alga/amd/si/Makefile changed (mode: 100644) (index 5c137ab..65a87c4)
... ... hdp.o bif.o golden.o dmas.o fence.o ring.o fops/fops.o fops/mmap.o fops/dma.o \
4 4 fops/dce.o rlc.o rlc_clearstate.o vm.o cm.o smc.o dyn_pm/dyn_pm.o dyn_pm/ctx.o \ fops/dce.o rlc.o rlc_clearstate.o vm.o cm.o smc.o dyn_pm/dyn_pm.o dyn_pm/ctx.o \
5 5 dyn_pm/initial.o dyn_pm/emergency.o dyn_pm/smc_state_tbl.o \ dyn_pm/initial.o dyn_pm/emergency.o dyn_pm/smc_state_tbl.o \
6 6 dyn_pm/smc_sw_regs.o dyn_pm/pwrtune.o dyn_pm/smc_mem_clk.o \ dyn_pm/smc_sw_regs.o dyn_pm/pwrtune.o dyn_pm/smc_mem_clk.o \
7 dyn_pm/smc_eng_clk.o dyn_pm/smc_voltage.o dyn_pm/smc_lvl.o dyn_pm/ulv.o \
7 dyn_pm/smc_eng_clk.o dyn_pm/smc_volt.o dyn_pm/smc_lvl.o dyn_pm/ulv.o \
8 8 dyn_pm/smc_mc_reg_tbl.o dyn_pm/driver.o dyn_pm/smc_mc_arb_tbl.o \ dyn_pm/smc_mc_reg_tbl.o dyn_pm/driver.o dyn_pm/smc_mc_arb_tbl.o \
9 9 dyn_pm/smc_eng_pll_tbl.o dyn_pm/smc_dte_cfg_tbl.o dyn_pm/smc_cac_cfg_tbl.o dyn_pm/smc_eng_pll_tbl.o dyn_pm/smc_dte_cfg_tbl.o dyn_pm/smc_cac_cfg_tbl.o
10 10 obj-$(CONFIG_ALGA_AMD_SI)+= si.o obj-$(CONFIG_ALGA_AMD_SI)+= si.o
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index faaaca4..02990fd)
... ... static int probe(struct pci_dev *dev, const struct pci_device_id *id)
552 552 } }
553 553 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
554 554
555 /* get defaults clocks and voltages */
555 /* get defaults clocks and volts */
556 556 r = atb_pp_defaults_get(dd->atb, &atb_pp_defaults); r = atb_pp_defaults_get(dd->atb, &atb_pp_defaults);
557 557 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
558 558 dev_err(&dev->dev, "atombios failed to get default clocks and voltages\n"); dev_err(&dev->dev, "atombios failed to get default clocks and voltages\n");
File drivers/gpu/alga/amd/si/dyn_pm/ctx.c changed (mode: 100644) (index 11ffca2..367206a)
39 39 #include "private.h" #include "private.h"
40 40
41 41 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
42 #include "smc_voltage.h"
42 #include "smc_volt.h"
43 43 static void atb_pp_state_dump(struct atb_pp_state *s, char *name) static void atb_pp_state_dump(struct atb_pp_state *s, char *name)
44 44 { {
45 45 u8 lvl_idx; u8 lvl_idx;
 
... ... static void atb_pp_state_dump(struct atb_pp_state *s, char *name)
59 59 } }
60 60 } }
61 61
62 static void atb_voltage_on_clk_dep_tbl_dump(
63 struct atb_voltage_on_clk_dep_tbl *tbl)
62 static void atb_volt_on_clk_dep_tbl_dump(struct atb_volt_on_clk_dep_tbl *tbl)
64 63 { {
65 64 u8 entry_idx; u8 entry_idx;
66 65 for (entry_idx = 0; entry_idx < tbl->entries_n; ++entry_idx) { for (entry_idx = 0; entry_idx < tbl->entries_n; ++entry_idx) {
67 struct atb_voltage_on_clk_dep *step;
66 struct atb_volt_on_clk_dep *step;
68 67
69 68 step = &tbl->entries[entry_idx]; step = &tbl->entries[entry_idx];
70 if (IS_VDDC_LKGE_IDX(step->voltage_id)) {
69 if (IS_VDDC_LKGE_IDX(step->volt_id)) {
71 70 LOG("vddc_dep_on_sclk[%u]:clk=%ukHz voltage=0x%04x(leakage index)", LOG("vddc_dep_on_sclk[%u]:clk=%ukHz voltage=0x%04x(leakage index)",
72 entry_idx, step->clk * 10, step->voltage_id);
71 entry_idx, step->clk * 10, step->volt_id);
73 72 } else { } else {
74 73 LOG("vddc_dep_on_sclk[%u]:clk=%ukHz voltage=%umV", LOG("vddc_dep_on_sclk[%u]:clk=%ukHz voltage=%umV",
75 entry_idx, step->clk * 10, step->voltage_id);
74 entry_idx, step->clk * 10, step->volt_id);
76 75 } }
77 76 } }
78 77 } }
 
... ... static void atb_vddc_phase_shed_limits_tbl_dump(
103 102 } }
104 103 } }
105 104
106 static void atb_voltage_tbl_dump(struct atb_voltage_tbl *tbl, char *name)
105 static void atb_volt_tbl_dump(struct atb_volt_tbl *tbl, char *name)
107 106 { {
108 107 u8 entry_idx; u8 entry_idx;
109 108
110 LOG("atb_voltage_%s:phase_delay=%u mask_low=0x%08x", name,
109 LOG("atb_volt_%s:phase_delay=%u mask_low=0x%08x", name,
111 110 tbl->phase_delay, tbl->mask_low); tbl->phase_delay, tbl->mask_low);
112 111 for (entry_idx = 0; entry_idx < tbl->entries_n; ++entry_idx) { for (entry_idx = 0; entry_idx < tbl->entries_n; ++entry_idx) {
113 struct atb_voltage_tbl_entry *entry;
112 struct atb_volt_tbl_entry *entry;
114 113
115 114 entry = &tbl->entries[entry_idx]; entry = &tbl->entries[entry_idx];
116 LOG("atb_voltage_%s[%u]:smio_low=0x%08x val_mv=%u",
115 LOG("atb_volt_%s[%u]:smio_low=0x%08x val_mv=%u",
117 116 name, entry_idx, entry->smio_low, entry->val_mv); name, entry_idx, entry->smio_low, entry->val_mv);
118 117 } }
119 118 } }
120 119 #else #else
121 120 static void atb_pp_state_dump(struct atb_pp_state *s, char *name){} static void atb_pp_state_dump(struct atb_pp_state *s, char *name){}
122 static void atb_voltage_on_clk_dep_tbl_dump(
123 struct atb_voltage_on_clk_dep_tbl *tbl){}
121 static void atb_volt_on_clk_dep_tbl_dump(
122 struct atb_volt_on_clk_dep_tbl *tbl){}
124 123 static void atb_cac_lkge_tbl_dump(struct atb_cac_lkge_tbl *tbl){} static void atb_cac_lkge_tbl_dump(struct atb_cac_lkge_tbl *tbl){}
125 124 static void atb_vddc_phase_shed_limits_tbl_dump( static void atb_vddc_phase_shed_limits_tbl_dump(
126 125 struct atb_vddc_phase_shed_limits_tbl *tbl){} struct atb_vddc_phase_shed_limits_tbl *tbl){}
127 static void atb_voltage_tbl_dump(struct atb_voltage_tbl *tbl, char *name){}
126 static void atb_volt_tbl_dump(struct atb_volt_tbl *tbl, char *name){}
128 127 #endif #endif
129 128
130 static long voltages_ctl_caps_get(struct ctx *ctx)
129 static long volts_ctl_caps_get(struct ctx *ctx)
131 130 { {
132 131 struct dev_drv_data *dd; struct dev_drv_data *dd;
133 132 long r; long r;
 
... ... static long voltages_ctl_caps_get(struct ctx *ctx)
141 140 return -SI_ERR; return -SI_ERR;
142 141 } else if (r == ATB_HAVE_VDDC_CTL) { } else if (r == ATB_HAVE_VDDC_CTL) {
143 142 LOG("vddc control supported"); LOG("vddc control supported");
144 ctx->voltage_caps |= VOLTAGE_CAPS_VDDC_CTL_ENA;
143 ctx->volt_caps |= VOLT_CAPS_VDDC_CTL_ENA;
145 144 } else if (r == ATB_DONT_HAVE_VDDC_CTL) { } else if (r == ATB_DONT_HAVE_VDDC_CTL) {
146 145 LOG("vddc control unsupported"); LOG("vddc control unsupported");
147 146 return 0; /* XXX:master switch */ return 0; /* XXX:master switch */
 
... ... static long voltages_ctl_caps_get(struct ctx *ctx)
155 154 return -SI_ERR; return -SI_ERR;
156 155 } else if (r == ATB_HAVE_MVDDC_CTL) { } else if (r == ATB_HAVE_MVDDC_CTL) {
157 156 LOG("mvdd control supported"); LOG("mvdd control supported");
158 ctx->voltage_caps |= VOLTAGE_CAPS_MVDD_CTL_ENA;
157 ctx->volt_caps |= VOLT_CAPS_MVDD_CTL_ENA;
159 158 } else if (r == ATB_DONT_HAVE_MVDDC_CTL) { } else if (r == ATB_DONT_HAVE_MVDDC_CTL) {
160 159 LOG("mvdd control unsupported"); LOG("mvdd control unsupported");
161 160 } }
 
... ... static long voltages_ctl_caps_get(struct ctx *ctx)
168 167 return -SI_ERR; return -SI_ERR;
169 168 } else if (r == ATB_HAVE_VDDCI_CTL) { } else if (r == ATB_HAVE_VDDCI_CTL) {
170 169 LOG("vddci control supported"); LOG("vddci control supported");
171 ctx->voltage_caps |= VOLTAGE_CAPS_VDDCI_CTL_ENA;
170 ctx->volt_caps |= VOLT_CAPS_VDDCI_CTL_ENA;
172 171 } else if (r == ATB_DONT_HAVE_VDDCI_CTL) { } else if (r == ATB_DONT_HAVE_VDDCI_CTL) {
173 172 LOG("vddci control unsupported"); LOG("vddci control unsupported");
174 173 } }
 
... ... static long voltages_ctl_caps_get(struct ctx *ctx)
181 180 return -SI_ERR; return -SI_ERR;
182 181 } else if (r == ATB_HAVE_VDDC_PHASE_SHED_CTL) { } else if (r == ATB_HAVE_VDDC_PHASE_SHED_CTL) {
183 182 LOG("vddc phase shedding supported"); LOG("vddc phase shedding supported");
184 ctx->voltage_caps |= VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA;
183 ctx->volt_caps |= VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA;
185 184 } else if (r == ATB_DONT_HAVE_VDDC_PHASE_SHED_CTL) { } else if (r == ATB_DONT_HAVE_VDDC_PHASE_SHED_CTL) {
186 185 LOG("vddc phase shedding unsupported"); LOG("vddc phase shedding unsupported");
187 186 } }
 
... ... long ctx_init(struct pci_dev *dev, struct ctx *ctx)
508 507 } }
509 508 LOG("powerplay platform capabilities is 0x%08x", ctx->platform_caps); LOG("powerplay platform capabilities is 0x%08x", ctx->platform_caps);
510 509
511 r = voltages_ctl_caps_get(ctx);
510 r = volts_ctl_caps_get(ctx);
512 511 if (r == -SI_ERR) if (r == -SI_ERR)
513 512 goto err; goto err;
514 513
 
... ... long ctx_init(struct pci_dev *dev, struct ctx *ctx)
544 543 ctx->misc_caps |= MISC_CAPS_VRAM_IS_GDDR5; ctx->misc_caps |= MISC_CAPS_VRAM_IS_GDDR5;
545 544 } }
546 545
547 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA) {
546 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
548 547 r = atb_vddc_tbl_get(dd->atb, &ctx->atb_vddc_tbl); r = atb_vddc_tbl_get(dd->atb, &ctx->atb_vddc_tbl);
549 548 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
550 549 dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc voltage table\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc voltage table\n");
551 550 goto err; goto err;
552 551 } }
553 atb_voltage_tbl_dump(&ctx->atb_vddc_tbl, "vddc");
552 atb_volt_tbl_dump(&ctx->atb_vddc_tbl, "vddc");
554 553 } }
555 554
556 if (ctx->voltage_caps & VOLTAGE_CAPS_MVDD_CTL_ENA) {
555 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA) {
557 556 r = atb_mvddc_tbl_get(dd->atb, &ctx->atb_mvddc_tbl); r = atb_mvddc_tbl_get(dd->atb, &ctx->atb_mvddc_tbl);
558 557 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
559 558 dev_err(&dev->dev, "dyn_pm:unable to fetch the mvddc voltage table\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the mvddc voltage table\n");
560 559 goto err; goto err;
561 560 } }
562 atb_voltage_tbl_dump(&ctx->atb_mvddc_tbl, "mvddc");
561 atb_volt_tbl_dump(&ctx->atb_mvddc_tbl, "mvddc");
563 562 } }
564 563
565 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDCI_CTL_ENA) {
564 if (ctx->volt_caps & VOLT_CAPS_VDDCI_CTL_ENA) {
566 565 r = atb_vddci_tbl_get(dd->atb, &ctx->atb_vddci_tbl); r = atb_vddci_tbl_get(dd->atb, &ctx->atb_vddci_tbl);
567 566 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
568 567 dev_err(&dev->dev, "dyn_pm:unable to fetch the vddci voltage table\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the vddci voltage table\n");
569 568 goto err; goto err;
570 569 } }
571 atb_voltage_tbl_dump(&ctx->atb_vddci_tbl, "vddci");
570 atb_volt_tbl_dump(&ctx->atb_vddci_tbl, "vddci");
572 571 } }
573 572
574 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
573 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
575 574 r = atb_vddc_phase_shed_tbl_get(dd->atb, &ctx->atb_vddc_phase_shed_tbl); r = atb_vddc_phase_shed_tbl_get(dd->atb, &ctx->atb_vddc_phase_shed_tbl);
576 575 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
577 576 dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc phase shedding table\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc phase shedding table\n");
578 577 goto err; goto err;
579 578 } }
580 atb_voltage_tbl_dump(&ctx->atb_vddc_phase_shed_tbl,
579 atb_volt_tbl_dump(&ctx->atb_vddc_phase_shed_tbl,
581 580 "vddc_phase_shed"); "vddc_phase_shed");
582 581
583 582 r = atb_vddc_phase_shed_limits_tbl_get(dd->atb, r = atb_vddc_phase_shed_limits_tbl_get(dd->atb,
 
... ... long ctx_init(struct pci_dev *dev, struct ctx *ctx)
591 590
592 591 } }
593 592
594 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE) {
593 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLT) {
595 594 r = atb_vddc_dep_on_sclk_tbl_get(dd->atb, r = atb_vddc_dep_on_sclk_tbl_get(dd->atb,
596 595 &ctx->atb_vddc_dep_on_sclk_tbl); &ctx->atb_vddc_dep_on_sclk_tbl);
597 596 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
598 597 dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc on sclk dependency table\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the vddc on sclk dependency table\n");
599 598 goto err_free_vddc_phase_shed_limits_tbl_entries; goto err_free_vddc_phase_shed_limits_tbl_entries;
600 599 } }
601 atb_voltage_on_clk_dep_tbl_dump(&ctx->atb_vddc_dep_on_sclk_tbl);
600 atb_volt_on_clk_dep_tbl_dump(&ctx->atb_vddc_dep_on_sclk_tbl);
602 601 } }
603 602
604 603 r = atb_cac_lkge_tbl_get(dd->atb, &ctx->atb_cac_lkge_tbl); r = atb_cac_lkge_tbl_get(dd->atb, &ctx->atb_cac_lkge_tbl);
 
... ... err_free_cac_lkge_tbl_entries:
662 661 if (ctx->atb_cac_lkge_tbl.entries_n) if (ctx->atb_cac_lkge_tbl.entries_n)
663 662 kfree(ctx->atb_cac_lkge_tbl.entries); kfree(ctx->atb_cac_lkge_tbl.entries);
664 663 err_free_vddc_dep_on_sclk_tbl_entries: err_free_vddc_dep_on_sclk_tbl_entries:
665 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE)
664 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLT)
666 665 if (ctx->atb_cac_lkge_tbl.entries_n) if (ctx->atb_cac_lkge_tbl.entries_n)
667 666 kfree(ctx->atb_cac_lkge_tbl.entries); kfree(ctx->atb_cac_lkge_tbl.entries);
668 667 err_free_vddc_phase_shed_limits_tbl_entries: err_free_vddc_phase_shed_limits_tbl_entries:
 
... ... void ctx_free(struct ctx *ctx)
676 675 { {
677 676 if (ctx->atb_cac_lkge_tbl.entries_n) if (ctx->atb_cac_lkge_tbl.entries_n)
678 677 kfree(ctx->atb_cac_lkge_tbl.entries); kfree(ctx->atb_cac_lkge_tbl.entries);
679 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE)
678 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLT)
680 679 if (ctx->atb_vddc_dep_on_sclk_tbl.entries_n) if (ctx->atb_vddc_dep_on_sclk_tbl.entries_n)
681 680 kfree(ctx->atb_vddc_dep_on_sclk_tbl.entries); kfree(ctx->atb_vddc_dep_on_sclk_tbl.entries);
682 681 if (ctx->atb_vddc_phase_shed_limits_tbl.entries_n) if (ctx->atb_vddc_phase_shed_limits_tbl.entries_n)
File drivers/gpu/alga/amd/si/dyn_pm/ctx.h changed (mode: 100644) (index 8d90099..bed26df)
7 7 */ */
8 8
9 9 /* used to track what was done */ /* used to track what was done */
10 #define STATE_VOLTAGE_PM_ENA BIT(0)
10 #define STATE_VOLT_PM_ENA BIT(0)
11 11 #define STATE_SS_ENA BIT(1) #define STATE_SS_ENA BIT(1)
12 12 #define STATE_THERMAL_PROTECTION_ENA BIT(2) #define STATE_THERMAL_PROTECTION_ENA BIT(2)
13 13
14 /* voltage caps */
15 #define VOLTAGE_CAPS_VDDC_CTL_ENA BIT(0)
16 #define VOLTAGE_CAPS_MVDD_CTL_ENA BIT(1)
17 #define VOLTAGE_CAPS_VDDCI_CTL_ENA BIT(2)
18 #define VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA BIT(3)
14 /* volt caps */
15 #define VOLT_CAPS_VDDC_CTL_ENA BIT(0)
16 #define VOLT_CAPS_MVDD_CTL_ENA BIT(1)
17 #define VOLT_CAPS_VDDCI_CTL_ENA BIT(2)
18 #define VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA BIT(3)
19 19
20 20 /* misc caps */ /* misc caps */
21 21 #define MISC_CAPS_ENG_CLK_SS_ENA BIT(0) #define MISC_CAPS_ENG_CLK_SS_ENA BIT(0)
 
... ... struct ctx {
32 32
33 33 u8 state; /* track what was enabled */ u8 state; /* track what was enabled */
34 34
35 u8 voltage_caps;
35 u8 volt_caps;
36 36 u32 platform_caps; /* from atombios pp */ u32 platform_caps; /* from atombios pp */
37 37 u8 misc_caps; u8 misc_caps;
38 38
39 struct atb_voltage_tbl atb_vddc_tbl;
40 struct atb_voltage_tbl atb_mvddc_tbl;
41 struct atb_voltage_tbl atb_vddci_tbl;
42 struct atb_voltage_tbl atb_vddc_phase_shed_tbl;
39 struct atb_volt_tbl atb_vddc_tbl;
40 struct atb_volt_tbl atb_mvddc_tbl;
41 struct atb_volt_tbl atb_vddci_tbl;
42 struct atb_volt_tbl atb_vddc_phase_shed_tbl;
43 43
44 struct atb_voltage_on_clk_dep_tbl atb_vddc_dep_on_sclk_tbl;
44 struct atb_volt_on_clk_dep_tbl atb_vddc_dep_on_sclk_tbl;
45 45 struct atb_cac_lkge_tbl atb_cac_lkge_tbl; struct atb_cac_lkge_tbl atb_cac_lkge_tbl;
46 46 struct atb_vddc_phase_shed_limits_tbl atb_vddc_phase_shed_limits_tbl; struct atb_vddc_phase_shed_limits_tbl atb_vddc_phase_shed_limits_tbl;
47 47
 
... ... struct ctx {
49 49 u16 atb_load_line_slope; u16 atb_load_line_slope;
50 50
51 51 /* /*
52 * We do do store the atb_boot, since the clks and voltages are wrong.
52 * We do do store the atb_boot, since the clks and volts are wrong.
53 53 * the initial state is a combination of data from the firmware info * the initial state is a combination of data from the firmware info
54 54 * tbl and the boot state! * tbl and the boot state!
55 55 */ */
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c changed (mode: 100644) (index cec23cf..4f9549d)
... ... static void mc_lp_regs_init(struct pci_dev *dev)
201 201 wr32(dev, rr32(dev, MC_SEQ_WR_CTL_2), MC_SEQ_WR_CTL_2_LP); wr32(dev, rr32(dev, MC_SEQ_WR_CTL_2), MC_SEQ_WR_CTL_2_LP);
202 202 } }
203 203
204 static void general_voltage_pm_ena(struct pci_dev *dev)
204 static void general_volt_pm_ena(struct pci_dev *dev)
205 205 { {
206 206 u32 general_pm; u32 general_pm;
207 207
208 208 general_pm = rr32(dev, GENERAL_PM); general_pm = rr32(dev, GENERAL_PM);
209 general_pm |= GP_VOLTAGE_PM_ENA;
209 general_pm |= GP_VOLT_PM_ENA;
210 210 wr32(dev, general_pm, GENERAL_PM); wr32(dev, general_pm, GENERAL_PM);
211 211
212 212 } }
213 213
214 static void general_voltage_pm_dis(struct pci_dev *dev)
214 static void general_volt_pm_dis(struct pci_dev *dev)
215 215 { {
216 216 u32 general_pm; u32 general_pm;
217 217
218 218 general_pm = rr32(dev, GENERAL_PM); general_pm = rr32(dev, GENERAL_PM);
219 general_pm &= ~GP_VOLTAGE_PM_ENA;
219 general_pm &= ~GP_VOLT_PM_ENA;
220 220 wr32(dev, general_pm, GENERAL_PM); wr32(dev, general_pm, GENERAL_PM);
221 221
222 222 } }
 
... ... long dyn_pm_ena(struct pci_dev *dev)
696 696 } }
697 697 LOG("smc is not running"); LOG("smc is not running");
698 698
699 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA) {
700 LOG("enabling voltage pm");
701 general_voltage_pm_ena(dev);
702 ctx->state |= STATE_VOLTAGE_PM_ENA;
699 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
700 LOG("enabling voltage power management");
701 general_volt_pm_ena(dev);
702 ctx->state |= STATE_VOLT_PM_ENA;
703 703 } else } else
704 LOG("voltage pm not enabled");
704 LOG("voltage power management not enabled");
705 705
706 706 mc_lp_regs_init(dev); mc_lp_regs_init(dev);
707 707
 
... ... err_clear_vc:
835 835 if (ctx->state & STATE_SS_ENA) if (ctx->state & STATE_SS_ENA)
836 836 general_ss_dis(dev); general_ss_dis(dev);
837 837
838 if (ctx->state & STATE_VOLTAGE_PM_ENA)
839 general_voltage_pm_dis(dev);
838 if (ctx->state & STATE_VOLT_PM_ENA)
839 general_volt_pm_dis(dev);
840 840
841 841 if (ctx->atb_emergency.lvls_n) if (ctx->atb_emergency.lvls_n)
842 842 emergency_dis(dev); emergency_dis(dev);
 
... ... void dyn_pm_dis(struct pci_dev *dev)
913 913 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
914 914 dev_err(&dev->dev, "dyn_pm:unable to look for vddc control\n"); dev_err(&dev->dev, "dyn_pm:unable to look for vddc control\n");
915 915 } else if (r == ATB_HAVE_VDDC_CTL) { } else if (r == ATB_HAVE_VDDC_CTL) {
916 LOG("disabling voltage pm");
917 general_voltage_pm_dis(dev);
916 LOG("disabling voltage power management");
917 general_volt_pm_dis(dev);
918 918 } else } else
919 LOG("voltage pm not disabled");
919 LOG("voltage power management not disabled");
920 920 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
921 921
922 922 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
File drivers/gpu/alga/amd/si/dyn_pm/emergency.c changed (mode: 100644) (index 31a017c..bfa4c46)
36 36
37 37 #include "ctx.h" #include "ctx.h"
38 38 #include "private.h" #include "private.h"
39 #include "smc_voltage.h"
39 #include "smc_volt.h"
40 40 #include "smc_mc_reg_tbl.h" #include "smc_mc_reg_tbl.h"
41 41
42 42 static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl) static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl)
 
... ... static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl)
47 47 atb_lvl = &ctx->atb_emergency.lvls[0]; atb_lvl = &ctx->atb_emergency.lvls[0];
48 48 smc_lvl = &tbl->emergency_lvl; smc_lvl = &tbl->emergency_lvl;
49 49
50 if ((ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA)
51 && atb_lvl->vddc_id) {
50 if ((ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) && atb_lvl->vddc_id) {
52 51 long r; long r;
53 52
54 r = smc_voltage_vddc_set_from_atb_id(ctx, &smc_lvl->vddc,
53 r = smc_volt_vddc_set_from_atb_id(ctx, &smc_lvl->vddc,
55 54 atb_lvl->vddc_id); atb_lvl->vddc_id);
56 55 if (r == -SI_ERR) { if (r == -SI_ERR) {
57 56 dev_err(&ctx->dev->dev, "dyn_pm:unable to patch emergency state vddc\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to patch emergency state vddc\n");
58 57 return -SI_ERR; return -SI_ERR;
59 58 } }
60 smc_voltage_std_vddc_compute(ctx, &smc_lvl->std_vddc,
59 smc_volt_std_vddc_compute(ctx, &smc_lvl->std_vddc,
61 60 &smc_lvl->vddc); &smc_lvl->vddc);
62 61 } }
63 62
64 if ((ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA)
63 if ((ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA)
65 64 && atb_lvl->vddc_id) { && atb_lvl->vddc_id) {
66 65 u8 i; u8 i;
67 66
68 67 /* /*
69 * the limit table range from low to high voltages, then locate
70 * a limit with enough power for the for the targetted vddc
68 * the limit tbl rng from low to high volts, then locate
69 * a limit with enough pwr for the for the targetted vddc
71 70 */ */
72 71 for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n; for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n;
73 72 ++i) { ++i) {
 
... ... static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl)
82 81 smc_lvl->vddc.phase_settings = i; smc_lvl->vddc.phase_settings = i;
83 82 } }
84 83
85 if ((ctx->voltage_caps & VOLTAGE_CAPS_VDDCI_CTL_ENA)
84 if ((ctx->volt_caps & VOLT_CAPS_VDDCI_CTL_ENA)
86 85 && atb_lvl->vddc_id && atb_lvl->vddci_mv) { && atb_lvl->vddc_id && atb_lvl->vddci_mv) {
87 86 long r; long r;
88 87
89 r = smc_voltage_vddci_set_from_atb_mv(ctx, &smc_lvl->vddci,
88 r = smc_volt_vddci_set_from_atb_mv(ctx, &smc_lvl->vddci,
90 89 atb_lvl->vddci_mv); atb_lvl->vddci_mv);
91 90 if (r == -SI_ERR) { if (r == -SI_ERR) {
92 91 dev_err(&ctx->dev->dev, "dyn_pm:unable to patch emergency state vddci\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to patch emergency state vddci\n");
 
... ... long smc_state_tbl_emergency_init(struct ctx *ctx, struct smc_state_tbl *tbl)
174 173 put_unaligned_be32(0, &lvl->eng_clk.clk); put_unaligned_be32(0, &lvl->eng_clk.clk);
175 174 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
176 175
177 if (ctx->voltage_caps & VOLTAGE_CAPS_MVDD_CTL_ENA)
178 smc_voltage_mvdd_set_from_atb_mem_clk(ctx, &lvl->mvdd, 0);
176 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA)
177 smc_volt_mvdd_set_from_atb_mem_clk(ctx, &lvl->mvdd, 0);
179 178
180 179 lvl->dpm_to_perf_lvl.max_ps = 0; lvl->dpm_to_perf_lvl.max_ps = 0;
181 180 lvl->dpm_to_perf_lvl.near_tdp_dec = 0; lvl->dpm_to_perf_lvl.near_tdp_dec = 0;
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index 0eb12f7..e79e77e)
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37 37 #include "smc_lvl.h" #include "smc_lvl.h"
38 #include "smc_voltage.h"
38 #include "smc_volt.h"
39 39 #include "smc_mc_reg_tbl.h" #include "smc_mc_reg_tbl.h"
40 40 #include "smc_mc_arb_tbl.h" #include "smc_mc_arb_tbl.h"
41 41
 
... ... long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
95 95 lvl->mc_arb_set_idx = MC_ARB_SET_IDX_INITIAL; lvl->mc_arb_set_idx = MC_ARB_SET_IDX_INITIAL;
96 96 lvl->mc_reg_set_idx = MC_REG_SET_IDX_INITIAL; lvl->mc_reg_set_idx = MC_REG_SET_IDX_INITIAL;
97 97
98 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA) {
99 r = smc_voltage_vddc_set_from_atb_mv(ctx, &lvl->vddc,
98 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
99 r = smc_volt_vddc_set_from_atb_mv(ctx, &lvl->vddc,
100 100 dd->pp.default_vddc); dd->pp.default_vddc);
101 101 if (r == -SI_ERR) { if (r == -SI_ERR) {
102 102 dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot vddc in smc initial state\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot vddc in smc initial state\n");
103 103 return -SI_ERR; return -SI_ERR;
104 104 } }
105 105
106 smc_voltage_std_vddc_compute(ctx, &lvl->std_vddc, &lvl->vddc);
106 smc_volt_std_vddc_compute(ctx, &lvl->std_vddc, &lvl->vddc);
107 107 } }
108 108
109 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDCI_CTL_ENA) {
110 r = smc_voltage_vddci_set_from_atb_mv(ctx, &lvl->vddci,
109 if (ctx->volt_caps & VOLT_CAPS_VDDCI_CTL_ENA) {
110 r = smc_volt_vddci_set_from_atb_mv(ctx, &lvl->vddci,
111 111 dd->pp.default_vddci); dd->pp.default_vddci);
112 112 if (r == -SI_ERR) { if (r == -SI_ERR) {
113 113 dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot vddci in smc initial state\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot vddci in smc initial state\n");
 
... ... long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
115 115 } }
116 116 } }
117 117
118 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
118 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
119 119 u8 i; u8 i;
120 120
121 121 for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n; for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n;
 
... ... long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
131 131 lvl->vddc.phase_settings = i; lvl->vddc.phase_settings = i;
132 132 } }
133 133
134 if (ctx->voltage_caps & VOLTAGE_CAPS_MVDD_CTL_ENA) {
135 r = smc_voltage_mvdd_set_from_atb_mv(ctx, &lvl->mvdd,
134 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA) {
135 r = smc_volt_mvdd_set_from_atb_mv(ctx, &lvl->mvdd,
136 136 dd->pp.default_mvddc); dd->pp.default_mvddc);
137 137 if (r == -SI_ERR) { if (r == -SI_ERR) {
138 138 dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot mvdd in smc initial state\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find and set default/boot mvdd in smc initial state\n");
File drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c changed (mode: 100644) (index 83895f3..e448336)
36 36 #include "private.h" #include "private.h"
37 37 #include "smc_eng_clk.h" #include "smc_eng_clk.h"
38 38 #include "smc_mem_clk.h" #include "smc_mem_clk.h"
39 #include "smc_voltage.h"
39 #include "smc_volt.h"
40 40
41 41 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
42 42 /* only for gddr5 */ /* only for gddr5 */
 
... ... long smc_lvl_from_atb(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
203 203 return -SI_ERR; return -SI_ERR;
204 204 } }
205 205
206 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA) {
207 r = smc_voltage_vddc_set_from_atb_id(ctx, &smc_lvl->vddc,
206 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
207 r = smc_volt_vddc_set_from_atb_id(ctx, &smc_lvl->vddc,
208 208 atb_lvl->vddc_id); atb_lvl->vddc_id);
209 209 if (r == -SI_ERR) { if (r == -SI_ERR) {
210 210 dev_err(&ctx->dev->dev, "dyn_pm:unable to find/set vddc_id\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find/set vddc_id\n");
211 211 return -SI_ERR; return -SI_ERR;
212 212 } }
213 smc_voltage_std_vddc_compute(ctx, &smc_lvl->std_vddc,
213 smc_volt_std_vddc_compute(ctx, &smc_lvl->std_vddc,
214 214 &smc_lvl->vddc); &smc_lvl->vddc);
215 215 } else } else
216 216 LOG("no vddc control enable for atombios powerplay level"); LOG("no vddc control enable for atombios powerplay level");
217 217
218 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
218 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
219 219 u8 i; u8 i;
220 220
221 221 /* /*
222 * the limit table range from low to high voltages, then locate
222 * the limit table range from low to high volts, then locate
223 223 * a limit with enough power for the for the targetted vddc * a limit with enough power for the for the targetted vddc
224 224 */ */
225 225 for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n; for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n;
 
... ... long smc_lvl_from_atb(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
238 238 } else } else
239 239 LOG("no vddc phase shedding control for atombios powerplay level"); LOG("no vddc phase shedding control for atombios powerplay level");
240 240
241 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDCI_CTL_ENA) {
242 r = smc_voltage_vddci_set_from_atb_mv(ctx, &smc_lvl->vddci,
241 if (ctx->volt_caps & VOLT_CAPS_VDDCI_CTL_ENA) {
242 r = smc_volt_vddci_set_from_atb_mv(ctx, &smc_lvl->vddci,
243 243 atb_lvl->vddci_mv); atb_lvl->vddci_mv);
244 244 if (r == -SI_ERR) { if (r == -SI_ERR) {
245 245 dev_err(&ctx->dev->dev, "dyn_pm:unable to find/set vddci\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find/set vddci\n");
 
... ... long smc_lvl_from_atb(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
248 248 } else } else
249 249 LOG("no vddci control for atombios powerplay level"); LOG("no vddci control for atombios powerplay level");
250 250
251 if (ctx->voltage_caps & VOLTAGE_CAPS_MVDD_CTL_ENA) {
252 smc_voltage_mvdd_set_from_atb_mem_clk(ctx, &smc_lvl->mvdd,
251 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA) {
252 smc_volt_mvdd_set_from_atb_mem_clk(ctx, &smc_lvl->mvdd,
253 253 atb_lvl->mem_clk); atb_lvl->mem_clk);
254 254 } else } else
255 255 LOG("no mvdd control for atombios powerplay level"); LOG("no mvdd control for atombios powerplay level");
File drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c changed (mode: 100644) (index 567c730..8f5773d)
... ... static void smc_vddc_tbl_init(struct ctx *ctx,
59 59 } }
60 60
61 61 put_unaligned_be32(ctx->atb_vddc_tbl.mask_low, put_unaligned_be32(ctx->atb_vddc_tbl.mask_low,
62 &smc_state_tbl->voltage_mask_tbl.mask_low[
63 SMC_VOLTAGE_MASK_VDDC]);
62 &smc_state_tbl->volt_mask_tbl.mask_low[
63 SMC_VOLT_MASK_VDDC]);
64 64
65 65 /* /*
66 66 * The smc needs to know which step has the highest vddc output. * The smc needs to know which step has the highest vddc output.
 
... ... static void smc_mvdd_tbl_init(struct ctx *ctx,
97 97 } }
98 98
99 99 put_unaligned_be32(ctx->atb_mvddc_tbl.mask_low, put_unaligned_be32(ctx->atb_mvddc_tbl.mask_low,
100 &smc_state_tbl->voltage_mask_tbl.mask_low[
101 SMC_VOLTAGE_MASK_MVDD]);
100 &smc_state_tbl->volt_mask_tbl.mask_low[
101 SMC_VOLT_MASK_MVDD]);
102 102 } }
103 103
104 104 static void smc_vddci_tbl_init(struct ctx *ctx, static void smc_vddci_tbl_init(struct ctx *ctx,
 
... ... static void smc_vddci_tbl_init(struct ctx *ctx,
120 120 } }
121 121
122 122 put_unaligned_be32(ctx->atb_vddci_tbl.mask_low, put_unaligned_be32(ctx->atb_vddci_tbl.mask_low,
123 &smc_state_tbl->voltage_mask_tbl.mask_low[
124 SMC_VOLTAGE_MASK_VDDCI]);
123 &smc_state_tbl->volt_mask_tbl.mask_low[
124 SMC_VOLT_MASK_VDDCI]);
125 125 } }
126 126
127 127 static void smc_vddc_phase_shed_tbl_init(struct ctx *ctx, static void smc_vddc_phase_shed_tbl_init(struct ctx *ctx,
 
... ... static void smc_vddc_phase_shed_tbl_init(struct ctx *ctx,
137 137 for (i = 0; i < ctx->atb_vddc_phase_shed_tbl.entries_n; ++i) { for (i = 0; i < ctx->atb_vddc_phase_shed_tbl.entries_n; ++i) {
138 138 u32 smio_low; u32 smio_low;
139 139
140 /* phase shedding params share smio_low with voltage levels */
140 /* phase shed params share smio_low with volt lvls */
141 141 smio_low = get_unaligned_be32(&smc_state_tbl->smio_low[i]); smio_low = get_unaligned_be32(&smc_state_tbl->smio_low[i]);
142 142 smio_low |= ctx->atb_vddc_phase_shed_tbl.entries[i].smio_low; smio_low |= ctx->atb_vddc_phase_shed_tbl.entries[i].smio_low;
143 143 put_unaligned_be32(smio_low, &smc_state_tbl->smio_low[i]); put_unaligned_be32(smio_low, &smc_state_tbl->smio_low[i]);
 
... ... static void smc_vddc_phase_shed_tbl_init(struct ctx *ctx,
145 145
146 146 put_unaligned_be32(ctx->atb_vddc_phase_shed_tbl.mask_low, put_unaligned_be32(ctx->atb_vddc_phase_shed_tbl.mask_low,
147 147 &smc_state_tbl->phase_mask_tbl.mask_low[ &smc_state_tbl->phase_mask_tbl.mask_low[
148 SMC_VOLTAGE_MASK_VDDC]);
148 SMC_VOLT_MASK_VDDC]);
149 149 } }
150 150
151 151 /* /*
152 * A voltage level step is a n-upplet of vddc/mvdd/vddci. Each voltage
153 * (vddc/mvdd/vddci) have a bit mask stored in voltage_mask_tbl. Then all gpio
154 * values needed to program a voltage level are stored in smio_low, and that
152 * A volt lvl step is a n-upplet of vddc/mvdd/vddci. Each volt
153 * (vddc/mvdd/vddci) have a bit mask stored in volt_mask_tbl. Then all gpio
154 * values needed to program a volt lvl are stored in smio_low, and that
155 155 * based on the previous mask. * based on the previous mask.
156 * Idem for phase shedding step, except the gpio mask is stored in
157 * phase_mask_tbl. smio_low masks are shared with the voltage levels, then
156 * Idem for phase shed step, except the gpio mask is stored in
157 * phase_mask_tbl. smio_low masks are shared with the volt lvls, then
158 158 * must work together. * must work together.
159 * The mV values are stored in smc level tables.
159 * The mV values are stored in smc lvl tbls.
160 160 */ */
161 static void smc_voltage_tbls_init(struct ctx *ctx,
161 static void smc_volt_tbls_init(struct ctx *ctx,
162 162 struct smc_state_tbl *smc_state_tbl) struct smc_state_tbl *smc_state_tbl)
163 163 { {
164 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_CTL_ENA)
164 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA)
165 165 smc_vddc_tbl_init(ctx, smc_state_tbl); smc_vddc_tbl_init(ctx, smc_state_tbl);
166 166
167 if (ctx->voltage_caps & VOLTAGE_CAPS_MVDD_CTL_ENA)
167 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA)
168 168 smc_mvdd_tbl_init(ctx, smc_state_tbl); smc_mvdd_tbl_init(ctx, smc_state_tbl);
169 169
170 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDCI_CTL_ENA)
170 if (ctx->volt_caps & VOLT_CAPS_VDDCI_CTL_ENA)
171 171 smc_vddci_tbl_init(ctx, smc_state_tbl); smc_vddci_tbl_init(ctx, smc_state_tbl);
172 172
173 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA)
173 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA)
174 174 smc_vddc_phase_shed_tbl_init(ctx, smc_state_tbl); smc_vddc_phase_shed_tbl_init(ctx, smc_state_tbl);
175 175 } }
176 176
 
... ... long smc_state_tbl_init(struct ctx *ctx, struct smc_state_tbl *tbl)
178 178 { {
179 179 long r; long r;
180 180
181 smc_voltage_tbls_init(ctx, tbl);
181 smc_volt_tbls_init(ctx, tbl);
182 182
183 183 if (ctx->state & STATE_THERMAL_PROTECTION_ENA) if (ctx->state & STATE_THERMAL_PROTECTION_ENA)
184 184 tbl->thermal_protection_type = tbl->thermal_protection_type =
File drivers/gpu/alga/amd/si/dyn_pm/smc_sw_regs.c changed (mode: 100644) (index b6723d8..36c0030)
... ... long smc_sw_regs_init(struct ctx *ctx)
45 45
46 46 dd = pci_get_drvdata(ctx->dev); dd = pci_get_drvdata(ctx->dev);
47 47
48 if (ctx->voltage_caps & VOLTAGE_CAPS_VDDC_PHASE_SHED_CTL_ENA)
48 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA)
49 49 smc_sw_wr32(ctx->dev, ctx->atb_vddc_phase_shed_tbl.phase_delay, smc_sw_wr32(ctx->dev, ctx->atb_vddc_phase_shed_tbl.phase_delay,
50 50 SMC_SW_PHASE_SHEDDING_DELAY); SMC_SW_PHASE_SHEDDING_DELAY);
51 51
File drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c renamed from drivers/gpu/alga/amd/si/dyn_pm/smc_voltage.c (similarity 77%) (mode: 100644) (index 6b42cc9..39f0498)
34 34
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37 #include "smc_voltage.h"
37 #include "smc_volt.h"
38 38
39 static long voltage_step_idx(struct atb_voltage_tbl *tbl, u16 val_mv)
39 static long volt_step_idx(struct atb_volt_tbl *tbl, u16 val_mv)
40 40 { {
41 41 u8 step; u8 step;
42 42
 
... ... static long voltage_step_idx(struct atb_voltage_tbl *tbl, u16 val_mv)
51 51 return 0; return 0;
52 52 } }
53 53
54 long smc_voltage_vddc_set_from_atb_id(struct ctx *ctx, struct smc_voltage *vddc,
54 long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc,
55 55 u32 vddc_id) u32 vddc_id)
56 56 { {
57 57 u16 vddc_mv; /* vddc in mV units, not lkge index */ u16 vddc_mv; /* vddc in mV units, not lkge index */
 
... ... long smc_voltage_vddc_set_from_atb_id(struct ctx *ctx, struct smc_voltage *vddc,
62 62
63 63 dd = pci_get_drvdata(ctx->dev); dd = pci_get_drvdata(ctx->dev);
64 64
65 r = atb_voltage_get(dd->atb, ATB_VOLTAGE_TYPE_VDDC, vddc_id,
65 r = atb_volt_get(dd->atb, ATB_VOLT_TYPE_VDDC, vddc_id,
66 66 &vddc_mv); &vddc_mv);
67 67 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
68 68 dev_err(&ctx->dev->dev, "dyn_pm:unable to find vddc mV value for leakage index 0x%04x\n", dev_err(&ctx->dev->dev, "dyn_pm:unable to find vddc mV value for leakage index 0x%04x\n",
 
... ... long smc_voltage_vddc_set_from_atb_id(struct ctx *ctx, struct smc_voltage *vddc,
73 73 } else } else
74 74 vddc_mv = vddc_id; vddc_mv = vddc_id;
75 75
76 r = voltage_step_idx(&ctx->atb_vddc_tbl, vddc_mv);
76 r = volt_step_idx(&ctx->atb_vddc_tbl, vddc_mv);
77 77 if (r == -SI_ERR) { if (r == -SI_ERR) {
78 78 dev_err(&ctx->dev->dev, "dyn_pm:unable to find powerfull enough vddc in atombios voltage table\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find powerfull enough vddc in atombios voltage table\n");
79 79 return -SI_ERR; return -SI_ERR;
 
... ... long smc_voltage_vddc_set_from_atb_id(struct ctx *ctx, struct smc_voltage *vddc,
84 84 return 0; return 0;
85 85 } }
86 86
87 static long mv_set_from_atb(struct ctx *ctx, struct smc_voltage *voltage,
88 struct atb_voltage_tbl *atb_voltage_tbl, u32 voltage_mv)
87 static long mv_set_from_atb(struct ctx *ctx, struct smc_volt *volt,
88 struct atb_volt_tbl *atb_volt_tbl, u32 volt_mv)
89 89 { {
90 90 long r; long r;
91 91
92 r = voltage_step_idx(atb_voltage_tbl, voltage_mv);
92 r = volt_step_idx(atb_volt_tbl, volt_mv);
93 93 if (r == -SI_ERR) { if (r == -SI_ERR) {
94 94 dev_err(&ctx->dev->dev, "dyn_pm:unable to find emergency powerfull enough voltage in atombios voltage table\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to find emergency powerfull enough voltage in atombios voltage table\n");
95 95 return -SI_ERR; return -SI_ERR;
96 96 } }
97 97
98 voltage->step_idx = (u8)r;
99 put_unaligned_be16(atb_voltage_tbl->entries[r].val_mv, &voltage->val);
98 volt->step_idx = (u8)r;
99 put_unaligned_be16(atb_volt_tbl->entries[r].val_mv, &volt->val);
100 100 return 0; return 0;
101 101 } }
102 102
103 long smc_voltage_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_voltage *vddc,
103 long smc_volt_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_volt *vddc,
104 104 u32 vddc_mv) u32 vddc_mv)
105 105 { {
106 106 return mv_set_from_atb(ctx, vddc, &ctx->atb_vddc_tbl, vddc_mv); return mv_set_from_atb(ctx, vddc, &ctx->atb_vddc_tbl, vddc_mv);
107 107 } }
108 108
109 long smc_voltage_vddci_set_from_atb_mv(struct ctx *ctx,
110 struct smc_voltage *vddci, u32 vddci_mv)
109 long smc_volt_vddci_set_from_atb_mv(struct ctx *ctx, struct smc_volt *vddci,
110 u32 vddci_mv)
111 111 { {
112 112 return mv_set_from_atb(ctx, vddci, &ctx->atb_vddci_tbl, vddci_mv); return mv_set_from_atb(ctx, vddci, &ctx->atb_vddci_tbl, vddci_mv);
113 113 } }
114 114
115 115 /* only used by the initial state */ /* only used by the initial state */
116 long smc_voltage_mvdd_set_from_atb_mv(struct ctx *ctx,
117 struct smc_voltage *mvdd, u32 mvdd_mv)
116 long smc_volt_mvdd_set_from_atb_mv(struct ctx *ctx, struct smc_volt *mvdd,
117 u32 mvdd_mv)
118 118 { {
119 119 return mv_set_from_atb(ctx, mvdd, &ctx->atb_mvddc_tbl, mvdd_mv); return mv_set_from_atb(ctx, mvdd, &ctx->atb_mvddc_tbl, mvdd_mv);
120 120 } }
121 121
122 122 #define MVDD_SPLIT_FREQ 30000 /* 10 kHz units */ #define MVDD_SPLIT_FREQ 30000 /* 10 kHz units */
123 void smc_voltage_mvdd_set_from_atb_mem_clk(struct ctx *ctx,
124 struct smc_voltage *mvdd, u32 mem_clk)
123 void smc_volt_mvdd_set_from_atb_mem_clk(struct ctx *ctx, struct smc_volt *mvdd,
124 u32 mem_clk)
125 125 { {
126 126 u8 idx; u8 idx;
127 127
128 128 if (mem_clk < MVDD_SPLIT_FREQ) if (mem_clk < MVDD_SPLIT_FREQ)
129 129 idx = 0; idx = 0;
130 130 else else
131 /* use the highest voltage in atb table */
131 /* use the highest volt in atb tbl */
132 132 idx = ctx->atb_mvddc_tbl.entries_n - 1; idx = ctx->atb_mvddc_tbl.entries_n - 1;
133 133
134 134 mvdd->step_idx = idx; mvdd->step_idx = idx;
 
... ... void smc_voltage_mvdd_set_from_atb_mem_clk(struct ctx *ctx,
136 136 } }
137 137
138 138 static void std_vddc_from_old_cac_lkge_tbl(struct ctx *ctx, static void std_vddc_from_old_cac_lkge_tbl(struct ctx *ctx,
139 struct smc_voltage *std_vddc, struct smc_voltage *vddc)
139 struct smc_volt *std_vddc, struct smc_volt *vddc)
140 140 { {
141 141 LOG("computing std_vddc from old cac table"); LOG("computing std_vddc from old cac table");
142 142
 
... ... static void std_vddc_from_old_cac_lkge_tbl(struct ctx *ctx,
152 152 } }
153 153
154 154 static void std_vddc_from_new_cac_lkge_entry(struct ctx *ctx, static void std_vddc_from_new_cac_lkge_entry(struct ctx *ctx,
155 struct smc_voltage *std_vddc, u8 vddc_step_idx, u8 dep_tbl_idx)
155 struct smc_volt *std_vddc, u8 vddc_step_idx, u8 dep_tbl_idx)
156 156 { {
157 157 if (dep_tbl_idx < ctx->atb_cac_lkge_tbl.entries_n) { if (dep_tbl_idx < ctx->atb_cac_lkge_tbl.entries_n) {
158 158 put_unaligned_be16( put_unaligned_be16(
 
... ... static void std_vddc_from_new_cac_lkge_entry(struct ctx *ctx,
175 175 } }
176 176
177 177 static void std_vddc_from_new_cac_lkge_tbl(struct ctx *ctx, static void std_vddc_from_new_cac_lkge_tbl(struct ctx *ctx,
178 struct smc_voltage *std_vddc, struct smc_voltage *vddc)
178 struct smc_volt *std_vddc, struct smc_volt *vddc)
179 179 { {
180 180 u8 dep_tbl_idx; u8 dep_tbl_idx;
181 181 long r; long r;
 
... ... static void std_vddc_from_new_cac_lkge_tbl(struct ctx *ctx,
195 195 u16 dep_vddc_mv; u16 dep_vddc_mv;
196 196
197 197 dep_vddc_id = ctx->atb_vddc_dep_on_sclk_tbl.entries[dep_tbl_idx] dep_vddc_id = ctx->atb_vddc_dep_on_sclk_tbl.entries[dep_tbl_idx]
198 .voltage_id;
198 .volt_id;
199 199
200 200 if (IS_VDDC_LKGE_IDX(dep_vddc_id)) { if (IS_VDDC_LKGE_IDX(dep_vddc_id)) {
201 201 struct dev_drv_data *dd; struct dev_drv_data *dd;
202 202
203 203 dd = pci_get_drvdata(ctx->dev); dd = pci_get_drvdata(ctx->dev);
204 204
205 r = atb_voltage_get(dd->atb, ATB_VOLTAGE_TYPE_VDDC,
205 r = atb_volt_get(dd->atb, ATB_VOLT_TYPE_VDDC,
206 206 dep_vddc_id, &dep_vddc_mv); dep_vddc_id, &dep_vddc_mv);
207 207 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
208 208 dev_err(&ctx->dev->dev, "dyn_pm:unable to convert a leakage index in vddc on engine clock dependency table\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to convert a leakage index in vddc on engine clock dependency table\n");
 
... ... static void std_vddc_from_new_cac_lkge_tbl(struct ctx *ctx,
221 221 } }
222 222
223 223 /* /*
224 * Will try to find an approximate match: The table is from low voltage
225 * to high voltage, then try to find a voltage step which will provide
226 * a bit more voltage than the targetted vddc.
224 * Will try to find an approximate match: The tbl is from low volt to
225 * high volt, then try to find a volt step which will provide a bit
226 * more volt than the targetted vddc.
227 227 */ */
228 228 for (dep_tbl_idx = 0; for (dep_tbl_idx = 0;
229 229 dep_tbl_idx < ctx->atb_vddc_dep_on_sclk_tbl.entries_n; dep_tbl_idx < ctx->atb_vddc_dep_on_sclk_tbl.entries_n;
 
... ... static void std_vddc_from_new_cac_lkge_tbl(struct ctx *ctx,
232 232 u16 dep_vddc_mv; u16 dep_vddc_mv;
233 233
234 234 dep_vddc_id = ctx->atb_vddc_dep_on_sclk_tbl.entries[dep_tbl_idx] dep_vddc_id = ctx->atb_vddc_dep_on_sclk_tbl.entries[dep_tbl_idx]
235 .voltage_id;
235 .volt_id;
236 236
237 237 if (IS_VDDC_LKGE_IDX(dep_vddc_id)) { if (IS_VDDC_LKGE_IDX(dep_vddc_id)) {
238 238 struct dev_drv_data *dd; struct dev_drv_data *dd;
239 239
240 240 dd = pci_get_drvdata(ctx->dev); dd = pci_get_drvdata(ctx->dev);
241 241
242 r = atb_voltage_get(dd->atb, ATB_VOLTAGE_TYPE_VDDC,
242 r = atb_volt_get(dd->atb, ATB_VOLT_TYPE_VDDC,
243 243 dep_vddc_id, &dep_vddc_mv); dep_vddc_id, &dep_vddc_mv);
244 244 if (r == -ATB_ERR) { if (r == -ATB_ERR) {
245 245 dev_err(&ctx->dev->dev, "dyn_pm:unable to convert a leakage index in vddc on engine clock dependency table\n"); dev_err(&ctx->dev->dev, "dyn_pm:unable to convert a leakage index in vddc on engine clock dependency table\n");
 
... ... exit_set_std_vddc_to_vddc:
267 267 } }
268 268
269 269 /* will put vddc in std_vddc if it encounters errors */ /* will put vddc in std_vddc if it encounters errors */
270 void smc_voltage_std_vddc_compute(struct ctx *ctx, struct smc_voltage *std_vddc,
271 struct smc_voltage *vddc)
270 void smc_volt_std_vddc_compute(struct ctx *ctx, struct smc_volt *std_vddc,
271 struct smc_volt *vddc)
272 272 { {
273 273 LOG("computing std_vddc"); LOG("computing std_vddc");
274 274
 
... ... void smc_voltage_std_vddc_compute(struct ctx *ctx, struct smc_voltage *std_vddc,
277 277 return; return;
278 278 } }
279 279
280 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE)
280 if (ctx->platform_caps & ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLT)
281 281 std_vddc_from_new_cac_lkge_tbl(ctx, std_vddc, vddc); std_vddc_from_new_cac_lkge_tbl(ctx, std_vddc, vddc);
282 282 else else
283 283 std_vddc_from_old_cac_lkge_tbl(ctx, std_vddc, vddc); std_vddc_from_old_cac_lkge_tbl(ctx, std_vddc, vddc);
File drivers/gpu/alga/amd/si/dyn_pm/smc_volt.h added (mode: 100644) (index 0000000..919a608)
1 #ifndef DYN_PM_SMC_VOLT_H
2 #define DYN_PM_SMC_VOLT_H
3 /*
4 author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 Protected by GNU Affero GPL v3 with some exceptions.
6 See README at root of alga tree.
7 */
8 #define IS_VDDC_LKGE_IDX(x) (((x) & 0xff00) == 0xff00)
9 long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc,
10 u32 vddc_id);
11 long smc_volt_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_volt *vddc,
12 u32 vddc_mv);
13 long smc_volt_vddci_set_from_atb_mv(struct ctx *ctx,
14 struct smc_volt *vddci, u32 vddci_mv);
15 long smc_volt_mvdd_set_from_atb_mv(struct ctx *ctx, struct smc_volt *mvdd,
16 u32 mvdd_mv);
17 void smc_volt_mvdd_set_from_atb_mem_clk(struct ctx *ctx, struct smc_volt *mvdd,
18 u32 mem_clk);
19 void smc_volt_std_vddc_compute(struct ctx *ctx, struct smc_volt *std_vddc,
20 struct smc_volt *vddc);
21 #endif
File drivers/gpu/alga/amd/si/dyn_pm/smc_voltage.h deleted (index 23e18bf..0000000)
1 #ifndef DYN_PM_SMC_VOLTAGE_H
2 #define DYN_PM_SMC_VOLTAGE_H
3 /*
4 author Sylvain Bertrand <digital.ragnarok@gmail.com>
5 Protected by GNU Affero GPL v3 with some exceptions.
6 See README at root of alga tree.
7 */
8 #define IS_VDDC_LKGE_IDX(x) (((x) & 0xff00) == 0xff00)
9 long smc_voltage_vddc_set_from_atb_id(struct ctx *ctx, struct smc_voltage *vddc,
10 u32 vddc_id);
11 long smc_voltage_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_voltage *vddc,
12 u32 vddc_mv);
13 long smc_voltage_vddci_set_from_atb_mv(struct ctx *ctx,
14 struct smc_voltage *vddci, u32 vddci_mv);
15 long smc_voltage_mvdd_set_from_atb_mv(struct ctx *ctx,
16 struct smc_voltage *mvdd, u32 mvdd_mv);
17 void smc_voltage_mvdd_set_from_atb_mem_clk(struct ctx *ctx,
18 struct smc_voltage *mvdd, u32 mem_clk);
19 void smc_voltage_std_vddc_compute(struct ctx *ctx,
20 struct smc_voltage *std_vddc, struct smc_voltage *vddc);
21 #endif
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 6c96d0d..43a427a)
... ... static inline u32 get(u32 mask, u32 v)
75 75 #define GP_THERMAL_PROTECTION_TYPE BIT(3) #define GP_THERMAL_PROTECTION_TYPE BIT(3)
76 76 /* XXX: only one bit? */ /* XXX: only one bit? */
77 77 #define GP_SW_SMIO_IDX BIT(6) #define GP_SW_SMIO_IDX BIT(6)
78 #define GP_VOLTAGE_PM_ENA BIT(10)
78 #define GP_VOLT_PM_ENA BIT(10)
79 79 #define GP_DYN_SPREAD_SPECTRUM_ENA BIT(23) #define GP_DYN_SPREAD_SPECTRUM_ENA BIT(23)
80 80 #define CG_TPC 0x784 #define CG_TPC 0x784
81 81 #define ENG_CLK_PM_CTL 0x788 #define ENG_CLK_PM_CTL 0x788
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index e209841..61ab000)
... ... struct smc_mem_clk {
66 66 __be32 clk; __be32 clk;
67 67 } __packed; } __packed;
68 68
69 struct smc_voltage {
69 struct smc_volt {
70 70 __be16 val; __be16 val;
71 71 u8 step_idx; u8 step_idx;
72 72 u8 phase_settings; u8 phase_settings;
 
... ... struct smc_lvl {
99 99 __be32 b_sp; __be32 b_sp;
100 100 struct smc_eng_clk eng_clk; struct smc_eng_clk eng_clk;
101 101 struct smc_mem_clk mem_clk; struct smc_mem_clk mem_clk;
102 struct smc_voltage vddc;
103 struct smc_voltage mvdd;
104 struct smc_voltage vddci;
105 struct smc_voltage std_vddc;
102 struct smc_volt vddc;
103 struct smc_volt mvdd;
104 struct smc_volt vddci;
105 struct smc_volt std_vddc;
106 106 u8 hysteresis_up; u8 hysteresis_up;
107 107 u8 hysteresis_down; u8 hysteresis_down;
108 108 u8 state_flgs; u8 state_flgs;
 
... ... struct smc_lvl {
110 110 __be32 sq_pwr_throttle_0; __be32 sq_pwr_throttle_0;
111 111 __be32 sq_pwr_throttle_1; __be32 sq_pwr_throttle_1;
112 112 __be32 cus_n_max; __be32 cus_n_max;
113 struct smc_voltage high_temp_vddc;
114 struct smc_voltage low_temp_vddc;
113 struct smc_volt high_temp_vddc;
114 struct smc_volt low_temp_vddc;
115 115 __be32 rsvd[2]; __be32 rsvd[2];
116 116 struct smc_pp_dpm_to_perf_lvl dpm_to_perf_lvl; struct smc_pp_dpm_to_perf_lvl dpm_to_perf_lvl;
117 117 } __packed; } __packed;
 
... ... struct smc_pp_dpm_to_params {
135 135 __be32 min_limit_delta; __be32 min_limit_delta;
136 136 } __packed; } __packed;
137 137
138 #define SMC_VOLTAGE_MASK_VDDC 0
139 #define SMC_VOLTAGE_MASK_MVDD 1
140 #define SMC_VOLTAGE_MASK_VDDCI 2
141 #define SMC_VOLTAGE_MASKS_N_MAX 4
138 #define SMC_VOLT_MASK_VDDC 0
139 #define SMC_VOLT_MASK_MVDD 1
140 #define SMC_VOLT_MASK_VDDCI 2
141 #define SMC_VOLT_MASKS_N_MAX 4
142 142
143 struct smc_voltage_mask_tbl {
144 __be32 mask_low[SMC_VOLTAGE_MASKS_N_MAX];
143 struct smc_volt_mask_tbl {
144 __be32 mask_low[SMC_VOLT_MASKS_N_MAX];
145 145 } __packed; } __packed;
146 146
147 147 #define SMC_PP_THERMAL_PROTECTION_TYPE_INTERNAL 0x00 #define SMC_PP_THERMAL_PROTECTION_TYPE_INTERNAL 0x00
 
... ... struct smc_voltage_mask_tbl {
163 163 #define SMC_PP_EXTRA_FLGS_ACTION_GOTO_INITIAL_STATE 0x01 #define SMC_PP_EXTRA_FLGS_ACTION_GOTO_INITIAL_STATE 0x01
164 164 #define SMC_PP_EXTRA_FLGS_GPIO5_POLARITY_HIGH 0x02 #define SMC_PP_EXTRA_FLGS_GPIO5_POLARITY_HIGH 0x02
165 165
166 /* a step is a set of voltage levels and phase shedding params */
166 /* a step is a set of volt levels and phase shedding params */
167 167 #define SMC_VREG_STEPS_N_MAX 32 #define SMC_VREG_STEPS_N_MAX 32
168 168 #define SMC_SW_STATE_LVLS_N_MAX 16 #define SMC_SW_STATE_LVLS_N_MAX 16
169 169 struct smc_state_tbl { struct smc_state_tbl {
 
... ... struct smc_state_tbl {
172 172 u8 max_vddc_idx; u8 max_vddc_idx;
173 173 u8 extra_flgs; u8 extra_flgs;
174 174 __be32 smio_low[SMC_VREG_STEPS_N_MAX]; __be32 smio_low[SMC_VREG_STEPS_N_MAX];
175 struct smc_voltage_mask_tbl voltage_mask_tbl;
176 struct smc_voltage_mask_tbl phase_mask_tbl;
175 struct smc_volt_mask_tbl volt_mask_tbl;
176 struct smc_volt_mask_tbl phase_mask_tbl;
177 177 struct smc_pp_dpm_to_params dpm_to_params; struct smc_pp_dpm_to_params dpm_to_params;
178 178
179 179 struct smc_sw_state initial; struct smc_sw_state initial;
File include/alga/amd/atombios/pp.h changed (mode: 100644) (index 7daad46..b6b8a9b)
... ... long atb_pp_emergency_state_get(struct atombios *atb,
33 33 long atb_pp_ulv_state_get(struct atombios *atb, struct atb_pp_state *ulv); long atb_pp_ulv_state_get(struct atombios *atb, struct atb_pp_state *ulv);
34 34 long atb_pp_performance_state_get(struct atombios *atb, long atb_pp_performance_state_get(struct atombios *atb,
35 35 struct atb_pp_state *performance); struct atb_pp_state *performance);
36 #define ATB_VOLTAGE_TYPE_VDDC 1
37 #define ATB_VOLTAGE_TYPE_MVDDC 2
38 #define ATB_VOLTAGE_TYPE_MVDDQ 3
39 #define ATB_VOLTAGE_TYPE_VDDCI 4
40 long atb_voltage_set(struct atombios *atb, u8 type, u16 lvl);
41 long atb_voltage_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *lvl);
36 #define ATB_VOLT_TYPE_VDDC 1
37 #define ATB_VOLT_TYPE_MVDDC 2
38 #define ATB_VOLT_TYPE_MVDDQ 3
39 #define ATB_VOLT_TYPE_VDDCI 4
40 long atb_volt_set(struct atombios *atb, u8 type, u16 lvl);
41 long atb_volt_get(struct atombios *atb, u8 type, u16 lkge_idx, u16 *lvl);
42 42 long atb_eng_clk_set(struct atombios *atb, u32 clk); long atb_eng_clk_set(struct atombios *atb, u32 clk);
43 43 long atb_mem_clk_set(struct atombios *atb, u32 clk); long atb_mem_clk_set(struct atombios *atb, u32 clk);
44 44
 
... ... long atb_have_thermal_protection(struct atombios *atb);
68 68 #define ATB_PP_PLATFORM_CAPS_REGULATOR_HOT BIT(16) #define ATB_PP_PLATFORM_CAPS_REGULATOR_HOT BIT(16)
69 69 /* does the driver supports baco state */ /* does the driver supports baco state */
70 70 #define ATB_PP_PLATFORM_CAPS_BACO BIT(17) #define ATB_PP_PLATFORM_CAPS_BACO BIT(17)
71 /* does the driver supports new cac voltage table */
72 #define ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLTAGE BIT(18)
71 /* does the driver supports new cac volt tbl */
72 #define ATB_PP_PLATFORM_CAPS_NEW_CAC_VOLT BIT(18)
73 73 /* does the driver supports revert gpio5 polarity */ /* does the driver supports revert gpio5 polarity */
74 74 #define ATB_PP_PLATFORM_CAPS_REVERT_GPIO5_POLARITY BIT(19) #define ATB_PP_PLATFORM_CAPS_REVERT_GPIO5_POLARITY BIT(19)
75 75 /* does the driver supports thermal2gpio17 */ /* does the driver supports thermal2gpio17 */
File include/alga/amd/atombios/vm.h changed (mode: 100644) (index 87485d5..de9bfb1)
... ... long atb_have_vddci_ctl(struct atombios *atb);
22 22 long atb_have_vddc_phase_shed_ctl(struct atombios *atb); long atb_have_vddc_phase_shed_ctl(struct atombios *atb);
23 23
24 24 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
25 struct atb_voltage_tbl_entry {
25 struct atb_volt_tbl_entry {
26 26 u32 smio_low; u32 smio_low;
27 27 u16 val_mv; /* XXX: mV units or phase shed thingy */ u16 val_mv; /* XXX: mV units or phase shed thingy */
28 28 }; };
29 29
30 #define ATB_VOLTAGE_TBL_ENTRIES_N_MAX 32
31 struct atb_voltage_tbl {
30 #define ATB_VOLT_TBL_ENTRIES_N_MAX 32
31 struct atb_volt_tbl {
32 32 u8 entries_n; u8 entries_n;
33 33 u8 phase_delay; u8 phase_delay;
34 34 u32 mask_low; u32 mask_low;
35 struct atb_voltage_tbl_entry entries[ATB_VOLTAGE_TBL_ENTRIES_N_MAX];
35 struct atb_volt_tbl_entry entries[ATB_VOLT_TBL_ENTRIES_N_MAX];
36 36 }; };
37 long atb_vddc_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl);
38 long atb_mvddc_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl);
39 long atb_vddci_tbl_get(struct atombios *atb, struct atb_voltage_tbl *tbl);
37 long atb_vddc_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl);
38 long atb_mvddc_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl);
39 long atb_vddci_tbl_get(struct atombios *atb, struct atb_volt_tbl *tbl);
40 40 long atb_vddc_phase_shed_tbl_get(struct atombios *atb, long atb_vddc_phase_shed_tbl_get(struct atombios *atb,
41 struct atb_voltage_tbl *tbl);
41 struct atb_volt_tbl *tbl);
42 42 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
43 43
44 44 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
45 struct atb_voltage_on_clk_dep {
45 struct atb_volt_on_clk_dep {
46 46 u32 clk; u32 clk;
47 u16 voltage_id; /* XXX: can be a lkge idx or mV units */
47 u16 volt_id; /* XXX: can be a lkge idx or mV units */
48 48 }; };
49 struct atb_voltage_on_clk_dep_tbl {
49 struct atb_volt_on_clk_dep_tbl {
50 50 u8 entries_n; u8 entries_n;
51 struct atb_voltage_on_clk_dep *entries;
51 struct atb_volt_on_clk_dep *entries;
52 52 }; };
53 53 long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb, long atb_vddc_dep_on_sclk_tbl_get(struct atombios *atb,
54 struct atb_voltage_on_clk_dep_tbl *tbl);
54 struct atb_volt_on_clk_dep_tbl *tbl);
55 55 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
56 56
57 57 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
File include/alga/dp.h changed (mode: 100644) (index 104cf88..89f4747)
58 58 #define DPCD_TRAINING_LANE1_SET 0x0104 #define DPCD_TRAINING_LANE1_SET 0x0104
59 59 #define DPCD_TRAINING_LANE2_SET 0x0105 #define DPCD_TRAINING_LANE2_SET 0x0105
60 60 #define DPCD_TRAINING_LANE3_SET 0x0106 #define DPCD_TRAINING_LANE3_SET 0x0106
61 #define DPCD_VOLTAGE_SWING_SHIFT 0
62 #define DPCD_VOLTAGE_SWING_MASK (0x3 << \
63 DPCD_VOLTAGE_SWING_SHIFT)
64 #define DPCD_MAX_VOLTAGE_SWING_REACHED BIT(2 + \
65 DPCD_VOLTAGE_SWING_SHIFT)
66 #define DPCD_VOLTAGE_SWING_400 (0 << \
67 DPCD_VOLTAGE_SWING_SHIFT)
68 #define DPCD_VOLTAGE_SWING_600 (1 << \
69 DPCD_VOLTAGE_SWING_SHIFT)
70 #define DPCD_VOLTAGE_SWING_800 (2 << \
71 DPCD_VOLTAGE_SWING_SHIFT)
72 #define DPCD_VOLTAGE_SWING_1200 (3 << \
73 DPCD_VOLTAGE_SWING_SHIFT)
61 #define DPCD_VOLT_SWING_SHIFT 0
62 #define DPCD_VOLT_SWING_MASK (0x3 << \
63 DPCD_VOLT_SWING_SHIFT)
64 #define DPCD_MAX_VOLT_SWING_REACHED BIT(2 + \
65 DPCD_VOLT_SWING_SHIFT)
66 #define DPCD_VOLT_SWING_400 (0 << \
67 DPCD_VOLT_SWING_SHIFT)
68 #define DPCD_VOLT_SWING_600 (1 << \
69 DPCD_VOLT_SWING_SHIFT)
70 #define DPCD_VOLT_SWING_800 (2 << \
71 DPCD_VOLT_SWING_SHIFT)
72 #define DPCD_VOLT_SWING_1200 (3 << \
73 DPCD_VOLT_SWING_SHIFT)
74 74
75 75 #define DPCD_PRE_EMPHASIS_SHIFT 3 #define DPCD_PRE_EMPHASIS_SHIFT 3
76 76 #define DPCD_PRE_EMPHASIS_MASK (0x3 << \ #define DPCD_PRE_EMPHASIS_MASK (0x3 << \
 
108 108
109 109 #define DPCD_ADJUST_REQUEST_LANE0_1 0x0206 #define DPCD_ADJUST_REQUEST_LANE0_1 0x0206
110 110 #define DPCD_ADJUST_REQUEST_LANE2_3 0x0207 #define DPCD_ADJUST_REQUEST_LANE2_3 0x0207
111 #define DPCD_ADJUST_VOLTAGE_SWING_LANEX_MASK 0x03
112 #define DPCD_ADJUST_VOLTAGE_SWING_LANEX_SHIFT 0
111 #define DPCD_ADJUST_VOLT_SWING_LANEX_MASK 0x03
112 #define DPCD_ADJUST_VOLT_SWING_LANEX_SHIFT 0
113 113 #define DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK 0x0c #define DPCD_ADJUST_PRE_EMPHASIS_LANEX_MASK 0x0c
114 114 #define DPCD_ADJUST_PRE_EMPHASIS_LANEX_SHIFT 2 #define DPCD_ADJUST_PRE_EMPHASIS_LANEX_SHIFT 2
115 #define DPCD_ADJUST_VOLTAGE_SWING_LANEY_MASK 0x30
116 #define DPCD_ADJUST_VOLTAGE_SWING_LANEY_SHIFT 4
115 #define DPCD_ADJUST_VOLT_SWING_LANEY_MASK 0x30
116 #define DPCD_ADJUST_VOLT_SWING_LANEY_SHIFT 4
117 117 #define DPCD_ADJUST_PRE_EMPHASIS_LANEY_MASK 0xc0 #define DPCD_ADJUST_PRE_EMPHASIS_LANEY_MASK 0xc0
118 118 #define DPCD_ADJUST_PRE_EMPHASIS_LANEY_SHIFT 6 #define DPCD_ADJUST_PRE_EMPHASIS_LANEY_SHIFT 6
119 119
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