sylware / nyanlinux (public) (License: AFFERO GPLv3) (since 2019-09-09) (hash sha1)
scripts for a lean, from scratch, amd hardware, linux distro
Clone URLs: https://rocketgit.com/user/sylware/nyanlinux ssh://rocketgit@ssh.rocketgit.com/user/sylware/nyanlinux git://git.rocketgit.com/user/sylware/nyanlinux
master
List of commits:
Subject Hash Author Date (UTC)
gfx stack update a3294175b467172d7f022c2e85133cf69a745326 Sylvain BERTRAND 2020-09-20 22:07:30
gfx stack update e77750988b70fd80025d2976b356610c29245112 Sylvain BERTRAND 2020-09-13 17:44:23
gfx stack update a3e78c179a9448d58de3c8570f8e481c1a3cb2a9 Sylvain BERTRAND 2020-09-06 19:11:59
x86:steam distributes the alsa-lib which breaks everything 49a7145777ae0033d8d203ab1afeec92e6ce64e1 Sylvain BERTRAND 2020-08-29 20:04:11
libxkbcommon with reasonable sdk 5a16c5350e09e0cc68fb4d842b9588994a04c944 Sylvain BERTRAND 2020-08-29 18:56:21
gfx stack update 76a10355fbb5a94dbe3f7b6fa2780cbe5ff9ec71 Sylvain BERTRAND 2020-08-24 21:43:41
gfx stack update caa9a0f9059e3c8140a10abe2b02d20faade28e7 Sylvain BERTRAND 2020-08-16 16:21:05
backup some wip 587cb6b5375b10533ebf92e4c151756f4541af7c Sylvain BERTRAND 2020-07-26 23:47:29
alsa-lib:wrong way to use a git snapshot here fb3c82ebddcd320bb7c435c80f88ac65b45401cf Sylvain BERTRAND 2020-07-26 23:35:30
gfx stack update 1a61af333cf6f4264679987cb53cb1258eca5b6f Sylvain BERTRAND 2020-07-26 22:15:23
update some c++ cr*p cf6270785e5ab1deaefdf3a09a5eb476f246bdda Sylvain BERTRAND 2020-07-19 21:43:11
gfx stack update 8a470044332a4ab0bb2f4247632d4ddc05591540 Sylvain BERTRAND 2020-07-19 21:42:01
gfx stack update 2c819ea9ca081c61a9e5f7961c188324e623b53d Sylvain BERTRAND 2020-07-12 17:50:40
gfx stack update bdc04d6f6e371752d5ff32737f1de0511cebe2b2 Sylvain BERTRAND 2020-07-05 18:03:47
gfx stack update 6bf84e0e956e8676945e47d8457f4b63857c912f Sylvain BERTRAND 2020-06-29 18:23:49
gfx stack update e5bc37ec0e4e5b33446eb377eb3c66f33ad79020 Sylvain BERTRAND 2020-06-15 02:43:05
add sample code for raw x11 cursor visibility 042be7d6259fd2ab4c759409fb0dceaf3043f4d9 Sylvain BERTRAND 2020-06-09 15:04:53
gfx stack update 7518a03d3592c7eefd8266d73545a803054fd807 Sylvain BERTRAND 2020-06-07 17:37:18
dwm: add npv to floating layout c270a17aeaee624528587328942ba20cd29a9e37 Sylvain BERTRAND 2020-06-05 22:19:55
st: update c4cdf6d812f06b0df6258fee5f798301c75744d7 Sylvain BERTRAND 2020-05-31 22:16:26
Commit a3294175b467172d7f022c2e85133cf69a745326 - gfx stack update
Author: Sylvain BERTRAND
Author date (UTC): 2020-09-20 22:07
Committer name: Sylvain BERTRAND
Committer date (UTC): 2020-09-20 22:07
Parent(s): e77750988b70fd80025d2976b356610c29245112
Signer:
Signing key:
Signing status: N
Tree: 7bce1b2e848871440f48c7e43978439db3a2c8d5
File Lines added Lines deleted
builders/dav1d-0/builder.sh 1 1
builders/ffmpeg-0/builder.sh 1 1
builders/llvm-0/builder.sh 1 1
builders/mesa-gl-0/builder.sh 1 1
builders/mesa-gl-0/contrib/gallium_auxiliary.sh 0 1
builders/mesa-vulkan-1/builder.sh 1 1
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/amd/r600/load.c 0 23
builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/load.c 8 2
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_alu.c 41 6
builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c 32 27
builders/mesa-vulkan-1/contrib/generators/nir/nir_intrinsics_c.c 1 0
builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh 6 0
builders/nyanmp-0/builder.sh 1 1
builders/xf86-video-amdgpu-1/builder.sh 1 1
builders/xf86-video-amdgpu/builder.sh 6 0
builders/xserver-0/builder.sh 1 1
builders/xserver/builder.sh 2 1
File builders/dav1d-0/builder.sh changed (mode: 100644) (index 43ec93a..6336e00)
1 git_commit=f57189e30080c6d5a0389533e722f6f2bac20272
1 git_commit=f90ada0d08e99ccfb676e59b8e3c497e77879915
2 2 slot=0 slot=0
3 3 major=5 major=5
4 4 minor=0 minor=0
File builders/ffmpeg-0/builder.sh changed (mode: 100644) (index e78b7ff..b8cb418)
1 git_commit=bc8662984261f422b49fdfff4cb273adde06917a
1 git_commit=9f7e592df27bd96bdffae173e3462d0438aea120
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/ffmpeg/builder.sh . $nyan_root/builders/ffmpeg/builder.sh
File builders/llvm-0/builder.sh changed (mode: 100644) (index 4b970db..24e2d6d)
1 git_commit=8c386c94749a78392fd763f8449ca3e55f030ffd
1 git_commit=91720ee561b2da4161df6abaddfd8a677aebb504
2 2 version=12.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt version=12.0.0git # do check at the top of llvm-project/llvm/CMakeLists.txt
3 3 slot=0 slot=0
4 4 . $nyan_root/builders/llvm/builder.sh . $nyan_root/builders/llvm/builder.sh
File builders/mesa-gl-0/builder.sh changed (mode: 100644) (index a60be53..87957f4)
1 git_commit=4868ce1451ffceb65a03ef230da01da639286c2c
1 git_commit=27516baa2aebe815dca011957d45e15f5b319fd6
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/mesa-gl/builder.sh . $nyan_root/builders/mesa-gl/builder.sh
File builders/mesa-gl-0/contrib/gallium_auxiliary.sh changed (mode: 100644) (index f41322b..56b542a)
... ... $src_dir/src/gallium/auxiliary/translate/translate_generic.c \
133 133 $src_dir/src/gallium/auxiliary/translate/translate_sse.c \ $src_dir/src/gallium/auxiliary/translate/translate_sse.c \
134 134 $src_dir/src/gallium/auxiliary/util/u_async_debug.c \ $src_dir/src/gallium/auxiliary/util/u_async_debug.c \
135 135 $src_dir/src/gallium/auxiliary/util/u_bitmask.c \ $src_dir/src/gallium/auxiliary/util/u_bitmask.c \
136 $src_dir/src/gallium/auxiliary/util/u_blit.c \
137 136 $src_dir/src/gallium/auxiliary/util/u_blitter.c \ $src_dir/src/gallium/auxiliary/util/u_blitter.c \
138 137 $src_dir/src/gallium/auxiliary/util/u_cache.c \ $src_dir/src/gallium/auxiliary/util/u_cache.c \
139 138 $src_dir/src/gallium/auxiliary/util/u_compute.c \ $src_dir/src/gallium/auxiliary/util/u_compute.c \
File builders/mesa-vulkan-1/builder.sh changed (mode: 100644) (index 37c281f..7697018)
1 git_commit=e8d55e6db366a1c93501cd208999820c002ddb82
1 git_commit=27516baa2aebe815dca011957d45e15f5b319fd6
2 2 slot=1 slot=1
3 3 . $nyan_root/builders/mesa-vulkan/builder.sh . $nyan_root/builders/mesa-vulkan/builder.sh
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/amd/r600/load.c deleted (index b563c36..0000000)
1 /*
2 * R600 specific instrincs
3 *
4 * R600 can only fetch 16 byte aligned data from an UBO, and the actual offset
5 * is given in vec4 units, so we have to fetch the a vec4 and get the component
6 * later
7 * src[] = { buffer_index, offset }.
8 */
9 struct nir_intrinsic nir_load_ubo_r600 = {
10 .name = "load_ubo_r600",
11 .srcs_n = 2,
12 .src_components_n = {
13 1,1
14 },
15 .has_dest = true,
16 .idxs_n = 3,
17 .idxs_map = {
18 [NIR_INTRINSIC_IDX_ACCESS] = 1,
19 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
20 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
21 },
22 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
23 };
File builders/mesa-vulkan-1/contrib/generators/nir/intrinsics/generic/load.c changed (mode: 100644) (index 90cdf0e..883b487)
11 11 * range (starting at base) of the data from which we are loading. If * range (starting at base) of the data from which we are loading. If
12 12 * range == 0, then the range is unknown. * range == 0, then the range is unknown.
13 13 * *
14 * UBO load operations have a nir_intrinsic_range_base() and
15 * nir_intrinsic_range() that specify the byte range [range_base,
16 * range_base+range] of the UBO that the src offset access must lie within.
17 *
14 18 * Some load operations such as UBO/SSBO load and per_vertex loads take an * Some load operations such as UBO/SSBO load and per_vertex loads take an
15 19 * additional source to specify which UBO/SSBO/vertex to load from. * additional source to specify which UBO/SSBO/vertex to load from.
16 20 * *
 
... ... struct nir_intrinsic nir_load_ubo = {
43 47 -1,1 -1,1
44 48 }, },
45 49 .has_dest = true, .has_dest = true,
46 .idxs_n = 3,
50 .idxs_n = 5,
47 51 .idxs_map = { .idxs_map = {
48 52 [NIR_INTRINSIC_IDX_ACCESS] = 1, [NIR_INTRINSIC_IDX_ACCESS] = 1,
49 53 [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2, [NIR_INTRINSIC_IDX_ALIGN_MUL] = 2,
50 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3
54 [NIR_INTRINSIC_IDX_ALIGN_OFFSET] = 3,
55 [NIR_INTRINSIC_IDX_RANGE_BASE] = 4,
56 [NIR_INTRINSIC_IDX_RANGE] = 5
51 57 }, },
52 58 .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER .flags = NIR_INTRINSIC_FLAGS_CAN_ELIMINATE | NIR_INTRINSIC_FLAGS_CAN_REORDER
53 59 }; };
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_alu.c changed (mode: 100644) (index 9f719b2..45eae97)
31 31 #define NIR_OP_INPUTS_N_MAX 16 #define NIR_OP_INPUTS_N_MAX 16
32 32 #define NIR_OP_ALGEBRAIC_PROPERTIES_2SRC_COMMUTATIVE 0x01 #define NIR_OP_ALGEBRAIC_PROPERTIES_2SRC_COMMUTATIVE 0x01
33 33 #define NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE 0x02 #define NIR_OP_ALGEBRAIC_PROPERTIES_ASSOCIATIVE 0x02
34 /* XXX: conversion field is used only by the intel driver for now */
34 35 struct nir_op { struct nir_op {
35 36 char *name; char *name;
36 37 u8 type; u8 type;
 
... ... static struct nir_op nir_f2fmp = {
323 324 NIR_TYPE_FLOAT16, NIR_TYPE_FLOAT16,
324 325 1, 1,
325 326 {0}, {0},
326 {NIR_TYPE_FLOAT},
327 {NIR_TYPE_FLOAT32},
327 328 0 0
328 329 }; };
329 330 static struct nir_op nir_i2imp = { static struct nir_op nir_i2imp = {
 
... ... static struct nir_op nir_i2imp = {
333 334 NIR_TYPE_INT16, NIR_TYPE_INT16,
334 335 1, 1,
335 336 {0}, {0},
336 {NIR_TYPE_INT},
337 {NIR_TYPE_INT32},
338 0
339 };
340 /* u2ump isn't defined, because the behavior is equal to i2imp */
341 static struct nir_op nir_f2imp = {
342 "f2imp",
343 NIR_OP_TYPE_ALU,
344 0,
345 NIR_TYPE_INT16,
346 1,
347 {0},
348 {NIR_TYPE_FLOAT32},
337 349 0 0
338 350 }; };
339 static struct nir_op nir_u2ump = {
340 "u2ump",
351 static struct nir_op nir_f2ump = {
352 "f2ump",
341 353 NIR_OP_TYPE_ALU, NIR_OP_TYPE_ALU,
342 354 0, 0,
343 355 NIR_TYPE_UINT16, NIR_TYPE_UINT16,
344 356 1, 1,
345 357 {0}, {0},
346 {NIR_TYPE_UINT},
358 {NIR_TYPE_FLOAT32},
359 0
360 };
361 static struct nir_op nir_i2fmp = {
362 "i2fmp",
363 NIR_OP_TYPE_ALU,
364 0,
365 NIR_TYPE_FLOAT16,
366 1,
367 {0},
368 {NIR_TYPE_INT32},
369 0
370 };
371 static struct nir_op nir_u2fmp = {
372 "u2fmp",
373 NIR_OP_TYPE_ALU,
374 0,
375 NIR_TYPE_FLOAT16,
376 1,
377 {0},
378 {NIR_TYPE_UINT32},
347 379 0 0
348 380 }; };
349 381 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
 
... ... static struct nir_op *nir_ops[] = {
2038 2070 &nir_unpack_32_4x8, &nir_unpack_32_4x8,
2039 2071 &nir_pack_32_4x8, &nir_pack_32_4x8,
2040 2072 &nir_i2imp, &nir_i2imp,
2041 &nir_u2ump,
2042 2073 &nir_fisnormal, &nir_fisnormal,
2043 2074 &nir_fisfinite, &nir_fisfinite,
2075 &nir_f2imp,
2076 &nir_f2ump,
2077 &nir_i2fmp,
2078 &nir_u2fmp,
2044 2079 }; };
File builders/mesa-vulkan-1/contrib/generators/nir/nir_database_intrinsic.c changed (mode: 100644) (index 18426fa..ebc1aca)
14 14 * not constant. * not constant.
15 15 */ */
16 16 #define NIR_INTRINSIC_IDX_RANGE 5 #define NIR_INTRINSIC_IDX_RANGE 5
17 /*
18 * The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative
19 * to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't
20 * have the implicit addition of a base to the offset.
21 */
22 #define NIR_INTRINSIC_IDX_RANGE_BASE 6
17 23 /* /*
18 24 * The vulkan descriptor set binding for vulkan_resource_index * The vulkan descriptor set binding for vulkan_resource_index
19 25 * intrinsic * intrinsic
20 26 */ */
21 #define NIR_INTRINSIC_IDX_DESC_SET 6
27 #define NIR_INTRINSIC_IDX_DESC_SET 7
22 28 /* /*
23 29 * The vulkan descriptor set binding for vulkan_resource_index * The vulkan descriptor set binding for vulkan_resource_index
24 30 * intrinsic * intrinsic
25 31 */ */
26 #define NIR_INTRINSIC_IDX_BINDING 7
32 #define NIR_INTRINSIC_IDX_BINDING 8
27 33 /* Component offset */ /* Component offset */
28 #define NIR_INTRINSIC_IDX_COMPONENT 8
34 #define NIR_INTRINSIC_IDX_COMPONENT 9
29 35 /* Interpolation mode (only meaningful for FS inputs) */ /* Interpolation mode (only meaningful for FS inputs) */
30 #define NIR_INTRINSIC_IDX_INTERP_MODE 9
36 #define NIR_INTRINSIC_IDX_INTERP_MODE 10
31 37 /* A binary nir_op to use when performing a reduction or scan operation */ /* A binary nir_op to use when performing a reduction or scan operation */
32 #define NIR_INTRINSIC_IDX_REDUCTION_OP 10
38 #define NIR_INTRINSIC_IDX_REDUCTION_OP 11
33 39 /* Cluster size for reduction operations */ /* Cluster size for reduction operations */
34 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 11
40 #define NIR_INTRINSIC_IDX_CLUSTER_SIZE 12
35 41 /* Parameter index for a load_param intrinsic */ /* Parameter index for a load_param intrinsic */
36 #define NIR_INTRINSIC_IDX_PARAM_IDX 12
42 #define NIR_INTRINSIC_IDX_PARAM_IDX 13
37 43 /* Image dimensionality for image intrinsics */ /* Image dimensionality for image intrinsics */
38 #define NIR_INTRINSIC_IDX_IMAGE_DIM 13
44 #define NIR_INTRINSIC_IDX_IMAGE_DIM 14
39 45 /* Non-zero if we are accessing an array image */ /* Non-zero if we are accessing an array image */
40 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 14
46 #define NIR_INTRINSIC_IDX_IMAGE_ARRAY 15
41 47 /* Image format for image intrinsics */ /* Image format for image intrinsics */
42 #define NIR_INTRINSIC_IDX_FORMAT 15
48 #define NIR_INTRINSIC_IDX_FORMAT 16
43 49 /* Access qualifiers for image and memory access intrinsics */ /* Access qualifiers for image and memory access intrinsics */
44 #define NIR_INTRINSIC_IDX_ACCESS 16
45 #define NIR_INTRINSIC_IDX_DST_ACCESS 17
46 #define NIR_INTRINSIC_IDX_SRC_ACCESS 18
50 #define NIR_INTRINSIC_IDX_ACCESS 17
51 #define NIR_INTRINSIC_IDX_DST_ACCESS 18
52 #define NIR_INTRINSIC_IDX_SRC_ACCESS 19
47 53 /* Offset or address alignment */ /* Offset or address alignment */
48 #define NIR_INTRINSIC_IDX_ALIGN_MUL 19
49 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 20
54 #define NIR_INTRINSIC_IDX_ALIGN_MUL 20
55 #define NIR_INTRINSIC_IDX_ALIGN_OFFSET 21
50 56 /* The vulkan descriptor type for vulkan_resource_index */ /* The vulkan descriptor type for vulkan_resource_index */
51 #define NIR_INTRINSIC_IDX_DESC_TYPE 21
57 #define NIR_INTRINSIC_IDX_DESC_TYPE 22
52 58 /* The nir_alu_type of a uniform/input/output */ /* The nir_alu_type of a uniform/input/output */
53 #define NIR_INTRINSIC_IDX_TYPE 22
59 #define NIR_INTRINSIC_IDX_TYPE 23
54 60 /* The swizzle mask for quad_swizzle_amd & masked_swizzle_amd */ /* The swizzle mask for quad_swizzle_amd & masked_swizzle_amd */
55 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 23
61 #define NIR_INTRINSIC_IDX_SWIZZLE_MASK 24
56 62 /* Driver location of attribute */ /* Driver location of attribute */
57 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 24
63 #define NIR_INTRINSIC_IDX_DRIVER_LOCATION 25
58 64 /* ordering and visibility of a memory operation */ /* ordering and visibility of a memory operation */
59 #define NIR_INTRINSIC_IDX_MEMORY_SEMANTICS 25
65 #define NIR_INTRINSIC_IDX_MEMORY_SEMANTICS 26
60 66 /* Modes affected by a memory operation */ /* Modes affected by a memory operation */
61 #define NIR_INTRINSIC_IDX_MEMORY_MODES 26
67 #define NIR_INTRINSIC_IDX_MEMORY_MODES 27
62 68 /* Scope of a memory operation */ /* Scope of a memory operation */
63 #define NIR_INTRINSIC_IDX_MEMORY_SCOPE 27
69 #define NIR_INTRINSIC_IDX_MEMORY_SCOPE 28
64 70 /* Scope of a control operation */ /* Scope of a control operation */
65 #define NIR_INTRINSIC_IDX_EXECUTION_SCOPE 28
66 #define NIR_INTRINSIC_IDX_IO_SEMANTICS 29
67 #define NIR_INTRINSIC_IDXS_N_MAX 30
71 #define NIR_INTRINSIC_IDX_EXECUTION_SCOPE 29
72 #define NIR_INTRINSIC_IDX_IO_SEMANTICS 30
73 #define NIR_INTRINSIC_IDXS_N_MAX 31
68 74
69 75 static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = { static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = {
70 76 "UNKNOWN_IDX", "UNKNOWN_IDX",
 
... ... static u8 *idxs_str[NIR_INTRINSIC_IDXS_N_MAX] = {
73 79 "nir_intrinsic_idx_stream_id", "nir_intrinsic_idx_stream_id",
74 80 "nir_intrinsic_idx_ucp_id", "nir_intrinsic_idx_ucp_id",
75 81 "nir_intrinsic_idx_range", "nir_intrinsic_idx_range",
82 "nir_intrinsic_idx_range_base",
76 83 "nir_intrinsic_idx_desc_set", "nir_intrinsic_idx_desc_set",
77 84 "nir_intrinsic_idx_binding", "nir_intrinsic_idx_binding",
78 85 "nir_intrinsic_idx_component", "nir_intrinsic_idx_component",
 
... ... struct nir_intrinsic {
131 138 #include "intrinsics/amd/system_values.c" #include "intrinsics/amd/system_values.c"
132 139 /* wtf ? */ /* wtf ? */
133 140 #include "intrinsics/amd/r600/r600.c" #include "intrinsics/amd/r600/r600.c"
134 #include "intrinsics/amd/r600/load.c"
135 141 #include "intrinsics/amd/r600/store.c" #include "intrinsics/amd/r600/store.c"
136 142 #include "intrinsics/amd/r600/system_values.c" #include "intrinsics/amd/r600/system_values.c"
137 143 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
 
... ... struct nir_intrinsic *nir_intrinsics[] = {
478 484 &nir_control_barrier, &nir_control_barrier,
479 485 &nir_memory_barrier_tcs_patch, &nir_memory_barrier_tcs_patch,
480 486 &nir_store_zs_output_pan, &nir_store_zs_output_pan,
481 &nir_load_ubo_r600,
482 487 &nir_load_ssbo_address, &nir_load_ssbo_address,
483 488 &nir_bindless_resource_ir3, &nir_bindless_resource_ir3,
484 489 &nir_load_tcs_in_param_base_r600, &nir_load_tcs_in_param_base_r600,
File builders/mesa-vulkan-1/contrib/generators/nir/nir_intrinsics_c.c changed (mode: 100644) (index 2251e96..dab7aab)
... ... static char *idx_str(u8 idx)
101 101 case NIR_INTRINSIC_IDX_STREAM_ID: return "NIR_INTRINSIC_STREAM_ID"; case NIR_INTRINSIC_IDX_STREAM_ID: return "NIR_INTRINSIC_STREAM_ID";
102 102 case NIR_INTRINSIC_IDX_UCP_ID: return "NIR_INTRINSIC_UCP_ID"; case NIR_INTRINSIC_IDX_UCP_ID: return "NIR_INTRINSIC_UCP_ID";
103 103 case NIR_INTRINSIC_IDX_RANGE: return "NIR_INTRINSIC_RANGE"; case NIR_INTRINSIC_IDX_RANGE: return "NIR_INTRINSIC_RANGE";
104 case NIR_INTRINSIC_IDX_RANGE_BASE: return "NIR_INTRINSIC_RANGE_BASE";
104 105 case NIR_INTRINSIC_IDX_DESC_SET: return "NIR_INTRINSIC_DESC_SET"; case NIR_INTRINSIC_IDX_DESC_SET: return "NIR_INTRINSIC_DESC_SET";
105 106 case NIR_INTRINSIC_IDX_BINDING: return "NIR_INTRINSIC_BINDING"; case NIR_INTRINSIC_IDX_BINDING: return "NIR_INTRINSIC_BINDING";
106 107 case NIR_INTRINSIC_IDX_COMPONENT: return "NIR_INTRINSIC_COMPONENT"; case NIR_INTRINSIC_IDX_COMPONENT: return "NIR_INTRINSIC_COMPONENT";
File builders/mesa-vulkan-1/contrib/x86_64_amdgpu_linux_gnu_vulkan_x11_drm_gcc.sh changed (mode: 100755) (index 96a4851..1f8f192)
... ... fi
147 147 # enable gcc attribute for atomic in src/util.c and thread emulation # enable gcc attribute for atomic in src/util.c and thread emulation
148 148 # HAVE_ENDIAN_H=1: # HAVE_ENDIAN_H=1:
149 149 # autoconf macro for the endian.h header used in src/util/u_endian.h # autoconf macro for the endian.h header used in src/util/u_endian.h
150 # HAVE_FLOCK=1:
151 # autoconf macro for src/util/disk_cache_os.c
150 152 # VK_USE_PLATFORM_XCB_KHR: # VK_USE_PLATFORM_XCB_KHR:
151 153 # vulkan macro enabling x11/xcb platform support, linked to # vulkan macro enabling x11/xcb platform support, linked to
152 154 # VK_USE_PLATFORM_XLIB_KHR in the code # VK_USE_PLATFORM_XLIB_KHR in the code
 
... ... linux_glibc_cppflags="\
237 239 -DHAVE_ENDIAN_H=1 \ -DHAVE_ENDIAN_H=1 \
238 240 -DHAVE_PROGRAM_INVOCATION_NAME=1 \ -DHAVE_PROGRAM_INVOCATION_NAME=1 \
239 241 -DHAVE_DLADDR=1 \ -DHAVE_DLADDR=1 \
242 -DHAVE_FLOCK=1 \
240 243 " "
241 244 mesa_cppflags="\ mesa_cppflags="\
242 245 -DNDEBUG \ -DNDEBUG \
 
... ... libaco_files="\
1239 1242 $src_dir/src/amd/compiler/aco_dead_code_analysis.cpp \ $src_dir/src/amd/compiler/aco_dead_code_analysis.cpp \
1240 1243 $src_dir/src/amd/compiler/aco_dominance.cpp \ $src_dir/src/amd/compiler/aco_dominance.cpp \
1241 1244 $src_dir/src/amd/compiler/aco_instruction_selection.cpp \ $src_dir/src/amd/compiler/aco_instruction_selection.cpp \
1245 $src_dir/src/amd/compiler/aco_instruction_selection_setup.cpp \
1242 1246 $src_dir/src/amd/compiler/aco_interface.cpp \ $src_dir/src/amd/compiler/aco_interface.cpp \
1243 1247 $src_dir/src/amd/compiler/aco_assembler.cpp \ $src_dir/src/amd/compiler/aco_assembler.cpp \
1244 1248 $src_dir/src/amd/compiler/aco_insert_exec_mask.cpp \ $src_dir/src/amd/compiler/aco_insert_exec_mask.cpp \
 
... ... $src_dir/src/util/crc32.c \
1329 1333 $src_dir/src/util/dag.c \ $src_dir/src/util/dag.c \
1330 1334 $src_dir/src/util/debug.c \ $src_dir/src/util/debug.c \
1331 1335 $src_dir/src/util/disk_cache.c \ $src_dir/src/util/disk_cache.c \
1336 $src_dir/src/util/disk_cache_os.c \
1332 1337 $src_dir/src/util/double.c \ $src_dir/src/util/double.c \
1333 1338 $src_dir/src/util/fast_idiv_by_const.c \ $src_dir/src/util/fast_idiv_by_const.c \
1334 1339 $src_dir/src/util/half_float.c \ $src_dir/src/util/half_float.c \
 
... ... $src_dir/src/util/format/u_format_s3tc.c \
1366 1371 $src_dir/src/util/format/u_format_tests.c \ $src_dir/src/util/format/u_format_tests.c \
1367 1372 $src_dir/src/util/format/u_format_yuv.c \ $src_dir/src/util/format/u_format_yuv.c \
1368 1373 $src_dir/src/util/format/u_format_zs.c \ $src_dir/src/util/format/u_format_zs.c \
1374 $src_dir/src/util/u_idalloc.c \
1369 1375 $src_dir/src/util/u_math.c \ $src_dir/src/util/u_math.c \
1370 1376 $src_dir/src/util/u_mm.c \ $src_dir/src/util/u_mm.c \
1371 1377 $src_dir/src/util/u_process.c \ $src_dir/src/util/u_process.c \
File builders/nyanmp-0/builder.sh changed (mode: 100644) (index 64301b0..a291ebe)
1 1 src_name=nyanmp src_name=nyanmp
2 git_commit=b319e79f4f1b79670f6eef754142cc65c891ad4b
2 git_commit=a9b52940ff2d567dc6c26b28d86eab54f5876819
3 3 git_url0=git://repo.or.cz/$src_name git_url0=git://repo.or.cz/$src_name
4 4
5 5 slot=0 slot=0
File builders/xf86-video-amdgpu-1/builder.sh changed (mode: 100644) (index bfec5b9..44c4732)
1 1 src_name=xf86-video-amdgpu src_name=xf86-video-amdgpu
2 git_commit=442efe73dd579dc36445a3b232937abbed9d2fbb
2 git_commit=6bd3dc6bd8af238868154f24a37ff13cc9aa2705
3 3 git_url0=git://anongit.freedesktop.org/xorg/driver/$pkg_name git_url0=git://anongit.freedesktop.org/xorg/driver/$pkg_name
4 4
5 5 src_dir=$src_dir_root/$src_name src_dir=$src_dir_root/$src_name
File builders/xf86-video-amdgpu/builder.sh changed (mode: 100644) (index 32367bf..3672d96)
... ... export "PKG_CONFIG_LIBDIR=\
46 46 /nyan/xserver/current/lib/pkgconfig:\ /nyan/xserver/current/lib/pkgconfig:\
47 47 /nyan/util-macro/current/share/pkgconfig" /nyan/util-macro/current/share/pkgconfig"
48 48
49 # configure want autoheader
50 export OLD_PATH=$PATH
51 export PATH=$sdk_audotconf_path:$PATH
52
49 53 # at link time, the only way to tell gnu ld where to look for shared lib dependencies is to pass the -rpath-link option # at link time, the only way to tell gnu ld where to look for shared lib dependencies is to pass the -rpath-link option
50 54 export "CC=gcc -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib -static-libgcc" export "CC=gcc -B/nyan/glibc/current/lib -L/nyan/glibc/current/lib -Wl,-rpath-link,/nyan/glibc/current/lib -static-libgcc"
51 55 export 'CFLAGS=-O2 -pipe -fPIC' export 'CFLAGS=-O2 -pipe -fPIC'
 
... ... unset CPPFLAGS
54 58 unset CFLAGS unset CFLAGS
55 59 unset CC unset CC
56 60
61 export OLD_PATH=$PATH
62
57 63 make -j $threads_n make -j $threads_n
58 64 make install make install
59 65
File builders/xserver-0/builder.sh changed (mode: 100644) (index 4cd1003..7537a63)
1 git_commit=727df0a74e75982f4352f0a3e574fcf6db3372f7
1 git_commit=add3df2001a2eadc41c47683f50fdc0fd8b14964
2 2 slot=0 slot=0
3 3 . $nyan_root/builders/xserver/builder.sh . $nyan_root/builders/xserver/builder.sh
File builders/xserver/builder.sh changed (mode: 100644) (index 3b632fd..4d463df)
... ... export "CC=gcc -static-libgcc -B/nyan/glibc/current/lib -L/nyan/glibc/current/li
91 91 /nyan/libpciaccess/current/lib:\ /nyan/libpciaccess/current/lib:\
92 92 /nyan/libepoxy/current/lib:\ /nyan/libepoxy/current/lib:\
93 93 /nyan/libfontenc/current/lib" /nyan/libfontenc/current/lib"
94 export 'CFLAGS=-O2 -pipe -fPIC'
94 # sdk bug:must force libdrm include
95 export 'CFLAGS=-O2 -pipe -fPIC -I/nyan/drm/current/include/libdrm'
95 96 # xserver is not using nettle pkgconfig # xserver is not using nettle pkgconfig
96 97 export "LDFLAGS=-L/nyan/nettle/current/lib" export "LDFLAGS=-L/nyan/nettle/current/lib"
97 98 $pkg_dir/configure \ $pkg_dir/configure \
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
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Clone this repository using git:
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This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main