sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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List of commits:
Subject Hash Author Date (UTC)
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
tidy mc reg tbl 4761bf039ff2caf87c7eb139cf54c0f2e1932b60 Sylvain BERTRAND 2014-01-30 18:23:10
cpy cpu mem to smc mem 1b2deae0c86f878c72a40b2c4d07cdf308c3be11 Sylvain BERTRAND 2014-01-30 16:56:51
init of smc sw regs for response times af87f39cda6b64d7c5367ea4fa77899a55a0b9e0 Sylvain BERTRAND 2014-01-30 15:39:37
smc state dyn pm params init 66b37051c3927dfecc92d6d630c53ddf927c7d79 Sylvain BERTRAND 2014-01-30 11:11:05
init of smc cac cfg regs add98b596c10e16693171e04a7f9168232a1f65d Sylvain BERTRAND 2014-01-29 19:38:59
cosmestics ee91a7ee91132de107bef05de70a8ea28f89dddf Sylvain BERTRAND 2014-01-28 23:12:44
smc cac cfg tbl init and some cosmetics 823419aa67f2ad91afb08942112be28d59752435 Sylvain BERTRAND 2014-01-28 22:31:35
smc dte cfg tbl init f3689c3d9e04a3462acf5c3a3aaabbdbb5307580 Sylvain BERTRAND 2014-01-27 21:16:32
init the smc mc arb freq set e276bc781e0e1ec9f7550c9bc8ffdb8de253be8b Sylvain BERTRAND 2014-01-24 16:22:31
smc_eng_pll_tbl init 323df7359605e25ac08800ca960bd3eb2267bc87 Sylvain BERTRAND 2014-01-24 15:50:18
factor out enging pll params computation 0c99b244c1a699abca8493097a8b1f82299b6721 Sylvain BERTRAND 2014-01-24 14:25:57
missed one file 99e76ae1afc06031299b77b3b1d7fbe80b869bc0 Sylvain BERTRAND 2014-01-24 13:03:50
atombios:eng mem pll used only for eng from SI dcdbc070fe4d7a9380ba27bb33274484d2725746 Sylvain BERTRAND 2014-01-24 13:01:43
mc arb tbl init c2d2e29d33a70910eaa09618ecb53783e976bea7 Sylvain BERTRAND 2014-01-24 11:06:39
preliminary support for smc mc arb reg set 0b7c90e4ccb988596b95ffccea10a2359ba585cd Sylvain BERTRAND 2014-01-23 16:57:47
removal of mc reg tbl slot idx duplicates 2b500504c5a651ed8f24df1fc43150cd205d8985 Sylvain BERTRAND 2014-01-23 14:08:10
mc regs set init for the driver state 7a9c50e02784f93d3443720d063b93829b9a57a1 Sylvain BERTRAND 2014-01-23 12:17:25
mc reg tbl init for the ulv state 97d55c06f7eeb31dd6f6a95fb13b30ddd22be157 Sylvain BERTRAND 2014-01-23 11:29:32
mc reg tbl init for the emergency state 7cf2fffd8bf166af90b20301652d03400feba029 Sylvain BERTRAND 2014-01-23 10:55:52
Commit 10c88c7898f027e114846f253262e6631a44f5eb - tidy mc reg tbl and mc arb reg tbl
Author: Sylvain BERTRAND
Author date (UTC): 2014-01-30 18:42
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-01-30 18:42
Parent(s): 4761bf039ff2caf87c7eb139cf54c0f2e1932b60
Signing key:
Tree: d477b2bb9ef3c150e9bc7adb8ad2db4eccbac329
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/driver.c 0 12
drivers/gpu/alga/amd/si/dyn_pm/driver.h 0 1
drivers/gpu/alga/amd/si/dyn_pm/initial.c 1 29
drivers/gpu/alga/amd/si/dyn_pm/private.h 4 4
drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.c 28 9
drivers/gpu/alga/amd/si/dyn_pm/smc_mc_reg_tbl.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/ulv.c 1 1
File drivers/gpu/alga/amd/si/dyn_pm/driver.c changed (mode: 100644) (index 0cddb2a..d1b1b53)
34 34
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37
38 /* the driver state mc regs are the initial/emergency ones for the init */
39 void smc_mc_reg_tbl_driver_init(struct smc_mc_reg_tbl *tbl)
40 {
41 struct smc_mc_reg_set *initial;
42 struct smc_mc_reg_set *driver;
43
44 initial = &tbl->sets[MC_REG_SET_IDX_INITIAL_EMERGENCY];
45 driver = &tbl->sets[MC_REG_SET_IDX_DRIVER];
46
47 memcpy(driver, initial, sizeof(*driver));
48 }
File drivers/gpu/alga/amd/si/dyn_pm/driver.h changed (mode: 100644) (index 7c0dbb2..5b3f66f)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 void smc_mc_reg_tbl_driver_init(struct smc_mc_reg_tbl *tbl);
9 8 #endif #endif
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index 85120e0..fc59fc0)
36 36 #include "private.h" #include "private.h"
37 37 #include "smc_lvl.h" #include "smc_lvl.h"
38 38 #include "smc_volt.h" #include "smc_volt.h"
39 #include "smc_mc_reg_tbl.h"
40 #include "smc_mc_arb_tbl.h"
41 39
42 40 long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl) long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
43 41 { {
 
... ... long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
92 90 put_unaligned_be32(dd->pp.default_eng_clk, &lvl->eng_clk.clk); put_unaligned_be32(dd->pp.default_eng_clk, &lvl->eng_clk.clk);
93 91 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
94 92
95 lvl->mc_arb_set_idx = MC_ARB_SET_IDX_INITIAL;
93 lvl->mc_arb_set_idx = MC_ARB_SET_IDX_INITIAL_EMERGENCY;
96 94 lvl->mc_reg_set_idx = MC_REG_SET_IDX_INITIAL_EMERGENCY; lvl->mc_reg_set_idx = MC_REG_SET_IDX_INITIAL_EMERGENCY;
97 95
98 96 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) { if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
 
... ... long smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
173 171 &lvl->sq_pwr_throttle_1); &lvl->sq_pwr_throttle_1);
174 172 return 0; return 0;
175 173 } }
176
177 long smc_mc_arb_tbl_initial_init(struct ctx *ctx,
178 struct smc_state_tbl *smc_state_tbl,
179 struct smc_mc_arb_tbl *smc_mc_arb_tbl)
180 {
181 u32 eng_clk;
182 u32 mem_clk;
183 struct smc_mc_arb_regs *initial_set;
184 long r;
185
186 /*
187 * we don't use the atombios pp boot state table, then we get the
188 * required information directly from the smc table
189 */
190 eng_clk = get_unaligned_be32(&smc_state_tbl->initial_lvl.eng_clk.clk);
191 mem_clk = get_unaligned_be32(&smc_state_tbl->initial_lvl.mem_clk.clk);
192
193 initial_set = &smc_mc_arb_tbl->sets[MC_ARB_SET_IDX_INITIAL];
194
195 r = smc_mc_arb_tbl_set_compute(ctx, initial_set, eng_clk, mem_clk);
196 if (r == -SI_ERR) {
197 dev_err(&ctx->dev->dev, "dyn_pm:unable to init the memory controller arb register set for the initial state\n");
198 return -SI_ERR;
199 }
200 return 0;
201 }
File drivers/gpu/alga/amd/si/dyn_pm/private.h changed (mode: 100644) (index cf86f5f..45a2cf7)
18 18 #define MEM_CLK_STUTTER_MODE_THRESHOLD MEM_CLK_STROBE_MODE_THRESHOLD #define MEM_CLK_STUTTER_MODE_THRESHOLD MEM_CLK_STROBE_MODE_THRESHOLD
19 19
20 20 /* this is our layout for the smc mc_arb_tbl */ /* this is our layout for the smc mc_arb_tbl */
21 #define MC_ARB_SET_IDX_INITIAL 0 /* only one lvl */
22 #define MC_ARB_SET_IDX_EMERGENCY 1 /* only one lvl */
23 #define MC_ARB_SET_IDX_ULV 2 /* only one lvl */
21 #define MC_ARB_SET_IDX_INITIAL_EMERGENCY 0
22 #define MC_ARB_SET_IDX_ULV 1
23 /* third slot is not used */
24 24 /* index of the set of the first current pwr state lvl */ /* index of the set of the first current pwr state lvl */
25 #define MC_ARB_SET_IDX_DRIVER 3
25 #define MC_ARB_SET_IDX_DRIVER 3
26 26
27 27 /* this is our layout for the smc mc_reg_tbl */ /* this is our layout for the smc mc_reg_tbl */
28 28 #define MC_REG_SET_IDX_INITIAL_EMERGENCY 0 #define MC_REG_SET_IDX_INITIAL_EMERGENCY 0
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_arb_tbl.c changed (mode: 100644) (index cd08a72..c8345d6)
... ... long smc_mc_arb_tbl_set_compute(struct ctx *ctx, struct smc_mc_arb_regs *set,
103 103 return 0; return 0;
104 104 } }
105 105
106 static long initial_emergency_init(struct ctx *ctx,
107 struct smc_state_tbl *smc_state_tbl,
108 struct smc_mc_arb_tbl *smc_mc_arb_tbl)
109 {
110 u32 eng_clk;
111 u32 mem_clk;
112 struct smc_mc_arb_regs *initial_set;
113 long r;
114
115 /*
116 * we don't use the atombios pp boot state table, then we get the
117 * required information directly from the smc table
118 */
119 eng_clk = get_unaligned_be32(&smc_state_tbl->initial_lvl.eng_clk.clk);
120 mem_clk = get_unaligned_be32(&smc_state_tbl->initial_lvl.mem_clk.clk);
121
122 initial_set = &smc_mc_arb_tbl->sets[MC_ARB_SET_IDX_INITIAL_EMERGENCY];
123
124 r = smc_mc_arb_tbl_set_compute(ctx, initial_set, eng_clk, mem_clk);
125 if (r == -SI_ERR) {
126 dev_err(&ctx->dev->dev, "dyn_pm:unable to init the memory controller arb register set for the initial state\n");
127 return -SI_ERR;
128 }
129 return 0;
130 }
131
106 132 long smc_mc_arb_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl, long smc_mc_arb_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
107 133 struct smc_mc_arb_tbl *smc_mc_arb_tbl) struct smc_mc_arb_tbl *smc_mc_arb_tbl)
108 134 { {
 
... ... long smc_mc_arb_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
110 136
111 137 LOG("smc memory controller arb table init"); LOG("smc memory controller arb table init");
112 138
113 r = smc_mc_arb_tbl_initial_init(ctx, smc_state_tbl, smc_mc_arb_tbl);
139 r = initial_emergency_init(ctx, smc_state_tbl, smc_mc_arb_tbl);
114 140 if (r == -SI_ERR) if (r == -SI_ERR)
115 141 return -SI_ERR; return -SI_ERR;
116 /*
117 * XXX:the emergency state is using the same mc arb reg set than the
118 * initial state, then in the table the mc arb reg set index is 0
119 */
120 142 r = smc_mc_arb_tbl_ulv_init(ctx, smc_mc_arb_tbl); r = smc_mc_arb_tbl_ulv_init(ctx, smc_mc_arb_tbl);
121 143 if (r == -SI_ERR) if (r == -SI_ERR)
122 144 return -SI_ERR; return -SI_ERR;
123 /*
124 * XXX:the driver state is using the same mc arb reg set than the
125 * initial state, then in the table the mc arb reg set index is 0
126 */
145 /* XXX:in initing phase, the driver state is the initial state */
127 146
128 147 /* set the hw register set to use for the mc arb */ /* set the hw register set to use for the mc arb */
129 148 smc_mc_arb_tbl->arb_freq_fx_current = MAC_MC_CG_ARB_FREQ_F1; smc_mc_arb_tbl->arb_freq_fx_current = MAC_MC_CG_ARB_FREQ_F1;
File drivers/gpu/alga/amd/si/dyn_pm/smc_mc_reg_tbl.c changed (mode: 100644) (index b344461..2d02863)
... ... long smc_mc_reg_tbl_init(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
228 228
229 229 initial_emergency_init(ctx, smc_state_tbl, smc_mc_reg_tbl); initial_emergency_init(ctx, smc_state_tbl, smc_mc_reg_tbl);
230 230 smc_mc_reg_tbl_ulv_init(ctx, smc_mc_reg_tbl); smc_mc_reg_tbl_ulv_init(ctx, smc_mc_reg_tbl);
231 smc_mc_reg_tbl_driver_init(smc_mc_reg_tbl);
231 /* XXX:in initing phase, the driver state is the initial state */
232 232 return 0; return 0;
233 233 } }
234 234
File drivers/gpu/alga/amd/si/dyn_pm/ulv.c changed (mode: 100644) (index e763d7a..93fe6a2)
... ... void smc_mc_reg_tbl_ulv_init(struct ctx *ctx,
120 120 * namely the first set, since the table is sorted from lowest mem clk * namely the first set, since the table is sorted from lowest mem clk
121 121 * to highest. Yes, the mem clk from the atombios pwr lvl is ignored. * to highest. Yes, the mem clk from the atombios pwr lvl is ignored.
122 122 */ */
123 set = &smc_mc_reg_tbl->sets[MC_REG_SET_IDX_INITIAL_EMERGENCY];
123 set = &smc_mc_reg_tbl->sets[MC_REG_SET_IDX_ULV];
124 124 smc_mc_reg_set_load(ctx, 0, set); smc_mc_reg_set_load(ctx, 0, set);
125 125 } }
126 126
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