sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
mainly bug fixing 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf Sylvain BERTRAND 2014-02-18 12:46:40
dump smc sw regs 5b42263039c858624ff411d94318f6ef5171a864 Sylvain BERTRAND 2014-02-17 12:22:26
disable switch to low power when no display 69f94e04ea89c1fe9ccaef153da5f5ade232c2a1 Sylvain BERTRAND 2014-02-17 09:59:28
finish smc switch to driver power state 6f99d0a01491dd671174919d842a771ac4a81a4b Sylvain BERTRAND 2014-02-17 09:47:02
pcie things and follow upstream for dyn pm init f4fb120597276a3badc08eec30783b10d111f756 Sylvain BERTRAND 2014-02-17 09:00:00
dump performance state tbls 06a22756b504ecf4523c86f657104e0b970195de Sylvain BERTRAND 2014-02-14 17:02:23
smc_mc_arb_tbl init for the driver state 5d1868e75b11164dbb97caaddbc7992b252ab973 Sylvain BERTRAND 2014-02-14 13:01:26
smc_mc_reg tbl init for the driver state e8aa12b1c87571031098c4427822733a74133afc Sylvain BERTRAND 2014-02-14 11:32:04
installation of the perf pwr state continued 535c853e7d0a0ab04fbff3b0d5613ef9a34d525c Sylvain BERTRAND 2014-02-13 19:16:33
installation of the perf pwr state continued b229eef2798acbe053aa09e47c213e23749638dd Sylvain BERTRAND 2014-02-13 10:48:02
dyn pm second part continuation 95dd7b4754476a014d8f84854e5b2ce5c81d23b4 Sylvain BERTRAND 2014-02-12 20:15:03
beginning of dyn pm second part c32c19d884dbf1f440480bbea42140e9c5ed8cd3 Sylvain BERTRAND 2014-02-12 14:44:04
uvd does only mpeg, then switch off 7e36b98bcab47e9986a63093dbeed98ab290f85f Sylvain BERTRAND 2014-02-12 10:55:54
bug fixing, end of dyn pm first part 533a4bd6731205f71704886e5fa099063be985ea Sylvain BERTRAND 2014-02-11 13:49:27
bug fixing c3fc0d7b807c98d20c13f53dcfc09713309ad2fa Sylvain BERTRAND 2014-02-11 11:16:00
static bios tbls *must* be ok e050fa94c2f1e846bb051748347332e234a6b93a Sylvain BERTRAND 2014-02-10 10:17:33
bug fixing 7baa7069aa89a98d831d7def358766155771e9ca Sylvain BERTRAND 2014-02-07 15:08:53
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
tbls fixes 4795a3090a17bc486056301bc6bef509b9c5e339 Sylvain BERTRAND 2014-02-05 15:09:41
log more accurately the smc tbls 3d88d2a589a89e9a34f4046242f4a72a76069ddb Sylvain BERTRAND 2014-02-05 10:51:39
Commit 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf - mainly bug fixing
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-18 12:46
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-18 12:46
Parent(s): 5b42263039c858624ff411d94318f6ef5171a864
Signing key:
Tree: 52ae58d8ebee99d4010b5103ff4387fe22e93c55
File Lines added Lines deleted
drivers/gpu/alga/amd/si/cm.c 53 1
drivers/gpu/alga/amd/si/dyn_pm/driver.c 20 5
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c 3 2
drivers/gpu/alga/amd/si/dyn_pm/emergency.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/initial.c 1 1
drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.c 2 0
drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c 3 4
drivers/gpu/alga/amd/si/regs.h 18 0
drivers/gpu/alga/amd/si/smc_regs.h 7 0
drivers/gpu/alga/amd/si/smc_tbls.h 5 5
drivers/gpu/alga/amd/si/vm.c 3 6
File drivers/gpu/alga/amd/si/cm.c changed (mode: 100644) (index 50abf1d..072c482)
37 37
38 38 #include "hdp.h" #include "hdp.h"
39 39 #include "bif.h" #include "bif.h"
40 #include "smc.h"
40 41
41 42 #include "regs.h" #include "regs.h"
42 43
 
... ... static __maybe_unused void gfx_cgcg_ena(struct pci_dev *dev)
92 93 if (cur != want) if (cur != want)
93 94 wr32(dev, want, RLC_CGCG_CGLS_CTL); wr32(dev, want, RLC_CGCG_CGLS_CTL);
94 95 } }
95
96
97 static u32 uvd_r32(struct pci_dev *dev, u32 addr)
98 {
99 wr32(dev, addr, UVD_IDX);
100 return rr32(dev, UVD_DATA);
101 }
102
103 static void uvd_w32(struct pci_dev *dev, u32 val, u32 addr)
104 {
105 wr32(dev, addr, UVD_IDX);
106 wr32(dev, val, UVD_DATA);
107 }
108
109 static void uvd_internal_cg_ena(struct pci_dev *dev)
110 {
111 u32 uvd_cgc_ctl_0;
112
113 uvd_cgc_ctl_0 = rr32(dev, UVD_CGC_CTL_0);
114 uvd_cgc_ctl_0 &= ~(UCC0_CG_DT | UCC0_CLK_OD);
115 uvd_cgc_ctl_0 |= UCC0_DCM | set(UCC0_CG_DT, 1) | set(UCC0_CLK_OD, 4);
116
117 uvd_cgc_ctl_0 |= 0x7ffff800;
118
119 wr32(dev, uvd_cgc_ctl_0, UVD_CGC_CTL_0);
120 uvd_w32(dev, 0, UVD_CGC_CTL_1);
121 }
122
123 static void uvd_mgcg_ena(struct pci_dev *dev)
124 {
125 u32 uvd_cgc_mem_ctl;
126 u32 cur;
127 u32 want;
128
129 /* uvd indirect access */
130 uvd_cgc_mem_ctl = uvd_r32(dev, UVD_CGC_MEM_CTL);
131 uvd_cgc_mem_ctl |= 0x3fff;
132 uvd_w32(dev, uvd_cgc_mem_ctl, UVD_CGC_MEM_CTL);
133
134 /* uvd direct access */
135 cur = rr32(dev, UVD_CGC_CTL_0);
136 want = cur | UCC0_DCM;
137 if (cur != want)
138 wr32(dev, want, UVD_CGC_CTL_0);
139
140 smc_w32(dev, 0, SMC_CG_IND_START + SMC_CG_CGTT_LOCAL_0);
141 smc_w32(dev, 0, SMC_CG_IND_START + SMC_CG_CGTT_LOCAL_1);
142 }
143
96 144 void cg_ena(struct pci_dev *dev) void cg_ena(struct pci_dev *dev)
97 145 { {
98 146 gpu_3d_ring_intr_idle_dis(dev);/* XXX: may be managed above */ gpu_3d_ring_intr_idle_dis(dev);/* XXX: may be managed above */
 
... ... void cg_ena(struct pci_dev *dev)
114 162
115 163 hdp_mgcg_ena(dev); hdp_mgcg_ena(dev);
116 164 hdp_ls_ena(dev); hdp_ls_ena(dev);
165
166 /* we do enable it, even if the block is not used */
167 uvd_mgcg_ena(dev);
168 uvd_internal_cg_ena(dev);
117 169 } }
118 170
119 171 void cg_dis(struct pci_dev *dev) void cg_dis(struct pci_dev *dev)
File drivers/gpu/alga/amd/si/dyn_pm/driver.c changed (mode: 100644) (index 98b8f4d..df25f2b)
... ... static long smc_pp_dpm_to_perf_lvl_init(struct ctx *ctx, u8 lvl_idx,
85 85 u16 pwr_efficiency_ratio; u16 pwr_efficiency_ratio;
86 86
87 87 if (lvl_idx == 0) { if (lvl_idx == 0) {
88 dpm_to_perf_lvl->max_ps = 0;
88 dpm_to_perf_lvl->max_pulse_skip = 0;
89 89 dpm_to_perf_lvl->near_tdp_dec = 0; dpm_to_perf_lvl->near_tdp_dec = 0;
90 90 dpm_to_perf_lvl->above_safe_inc = 0; dpm_to_perf_lvl->above_safe_inc = 0;
91 91 dpm_to_perf_lvl->below_safe_inc = 0; dpm_to_perf_lvl->below_safe_inc = 0;
 
... ... static long smc_pp_dpm_to_perf_lvl_init(struct ctx *ctx, u8 lvl_idx,
97 97
98 98 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
99 99
100 dpm_to_perf_lvl->max_ps = 0; /* because no uvd */
100 dpm_to_perf_lvl->max_pulse_skip = 0; /* because no uvd */
101 101 dpm_to_perf_lvl->near_tdp_dec = NEAR_TDP_DEC ; dpm_to_perf_lvl->near_tdp_dec = NEAR_TDP_DEC ;
102 102 dpm_to_perf_lvl->above_safe_inc = ABOVE_SAFE_INC; dpm_to_perf_lvl->above_safe_inc = ABOVE_SAFE_INC;
103 103 dpm_to_perf_lvl->below_safe_inc = BELOW_SAFE_INC; dpm_to_perf_lvl->below_safe_inc = BELOW_SAFE_INC;
 
... ... static void sq_ramping_threshold_init(struct ctx *ctx, u8 lvl_idx,
140 140 u32 sq_pwr_throttle_0; u32 sq_pwr_throttle_0;
141 141 u32 sq_pwr_throttle_1; u32 sq_pwr_throttle_1;
142 142
143 #if 0
144 It seems sq ramping threshold is disabled for good on SI. Told upstream, waiting
145 for feedback. Because of SQ_RAMPING_LTI_RATIO and SPT1_LTI_RATIO mask values on
146 SI.
143 147 if (ctx->atb_performance.lvls[lvl_idx].eng_clk >= if (ctx->atb_performance.lvls[lvl_idx].eng_clk >=
144 148 ctx->atb_sq_ramping_threshold) { ctx->atb_sq_ramping_threshold) {
145 149 sq_pwr_throttle_0 = set(SPT0_PWR_MAX, SQ_RAMPING_PWR_MAX); sq_pwr_throttle_0 = set(SPT0_PWR_MAX, SQ_RAMPING_PWR_MAX);
 
... ... static void sq_ramping_threshold_init(struct ctx *ctx, u8 lvl_idx,
154 158 sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ
155 159 | SPT1_LTI_RATIO; | SPT1_LTI_RATIO;
156 160 } }
161 #else
162 sq_pwr_throttle_0 = SPT0_PWR_MIN | SPT0_PWR_MAX;
163 sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ | SPT1_LTI_RATIO;
164 #endif
157 165
158 166 put_unaligned_be32(sq_pwr_throttle_0, &lvl->sq_pwr_throttle_0); put_unaligned_be32(sq_pwr_throttle_0, &lvl->sq_pwr_throttle_0);
159 167 put_unaligned_be32(sq_pwr_throttle_1, &lvl->sq_pwr_throttle_1); put_unaligned_be32(sq_pwr_throttle_1, &lvl->sq_pwr_throttle_1);
 
... ... static void tbls_cpy(struct ctx *ctx,
453 461
454 462 smc_ram_tbl_of = smc_major_tbl_of + offsetof(struct smc_mc_arb_tbl, smc_ram_tbl_of = smc_major_tbl_of + offsetof(struct smc_mc_arb_tbl,
455 463 sets); sets);
456 smc_ram_tbl_of += MC_ARB_SET_IDX_DRIVER * sizeof(*smc_mc_arb_tbl);
464 smc_ram_tbl_of += MC_ARB_SET_IDX_DRIVER * sizeof(*smc_mc_arb_reg_sets);
457 465 LOG("DRIVER SMC_MC_ARB_REG_SET OFFSET=0x%08x", smc_ram_tbl_of); LOG("DRIVER SMC_MC_ARB_REG_SET OFFSET=0x%08x", smc_ram_tbl_of);
458 466
459 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_arb_tbl,
460 sizeof(*smc_mc_arb_tbl));
467 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_arb_reg_sets,
468 sizeof(*smc_mc_arb_reg_sets) * ctx->atb_performance.lvls_n);
461 469
462 470 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
463 471 if (smc_mc_arb_tbl) { if (smc_mc_arb_tbl) {
 
... ... long driver_set_performance(struct ctx *ctx)
675 683 dev_err(&ctx->dev->dev, "dyn_pm:init:smc:failed to enable the ultra low voltage state\n"); dev_err(&ctx->dev->dev, "dyn_pm:init:smc:failed to enable the ultra low voltage state\n");
676 684 return -SI_ERR; return -SI_ERR;
677 685 } }
686 } else {
687 LOG("smc:disable ultra low voltage state");
688 r = smc_msg(ctx->dev, SMC_MSG_ULV_DIS);
689 if (r == -SI_ERR) {
690 dev_err(&ctx->dev->dev, "dyn_pm:init:smc:failed to disable the ultra low voltage state\n");
691 return -SI_ERR;
692 }
678 693 } }
679 694
680 695 LOG("smc:switching on the long term average calculation accumulator"); LOG("smc:switching on the long term average calculation accumulator");
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c changed (mode: 100644) (index 09c1303..804a7d6)
... ... long dyn_pm_ena(struct pci_dev *dev)
879 879
880 880 /* TODO: check the pcie link is retrained to max speed by the smc */ /* TODO: check the pcie link is retrained to max speed by the smc */
881 881
882 ctx_free(ctx);
883
884 882 LOG("switching off the universal video decoder (because mpeg)"); LOG("switching off the universal video decoder (because mpeg)");
885 883 r = smc_msg(ctx->dev, SMC_MSG_UVD_PWR_OFF); r = smc_msg(ctx->dev, SMC_MSG_UVD_PWR_OFF);
886 884 if (r == -SI_ERR) if (r == -SI_ERR)
887 885 dev_warn(&ctx->dev->dev, "dyn_pm:init:smc:unable to switch off the universal video decoder block (it does only mpeg)\n"); dev_warn(&ctx->dev->dev, "dyn_pm:init:smc:unable to switch off the universal video decoder block (it does only mpeg)\n");
886
887 ctx_free(ctx);
888
888 889 return 0; return 0;
889 890
890 891 err_free_ctx: err_free_ctx:
File drivers/gpu/alga/amd/si/dyn_pm/emergency.c changed (mode: 100644) (index dc3306a..a105ffe)
... ... long smc_state_tbl_emergency_init(struct ctx *ctx, struct smc_state_tbl *tbl)
224 224 if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA) if (ctx->volt_caps & VOLT_CAPS_MVDD_CTL_ENA)
225 225 smc_volt_mvdd_set_from_atb_mem_clk(ctx, &lvl->mvdd, 0); smc_volt_mvdd_set_from_atb_mem_clk(ctx, &lvl->mvdd, 0);
226 226
227 lvl->dpm_to_perf_lvl.max_ps = 0;
227 lvl->dpm_to_perf_lvl.max_pulse_skip = 0;
228 228 lvl->dpm_to_perf_lvl.near_tdp_dec = 0; lvl->dpm_to_perf_lvl.near_tdp_dec = 0;
229 229 lvl->dpm_to_perf_lvl.above_safe_inc = 0; lvl->dpm_to_perf_lvl.above_safe_inc = 0;
230 230 lvl->dpm_to_perf_lvl.below_safe_inc = 0; lvl->dpm_to_perf_lvl.below_safe_inc = 0;
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index 229d921..3b53103)
... ... void smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
141 141 tbl->initial.lvls_n = 1; tbl->initial.lvls_n = 1;
142 142 tbl->initial.flgs |= SMC_SW_STATE_FLGS_DC; tbl->initial.flgs |= SMC_SW_STATE_FLGS_DC;
143 143
144 lvl->dpm_to_perf_lvl.max_ps = 0;
144 lvl->dpm_to_perf_lvl.max_pulse_skip = 0;
145 145 lvl->dpm_to_perf_lvl.near_tdp_dec = 0; lvl->dpm_to_perf_lvl.near_tdp_dec = 0;
146 146 lvl->dpm_to_perf_lvl.above_safe_inc = 0; lvl->dpm_to_perf_lvl.above_safe_inc = 0;
147 147 lvl->dpm_to_perf_lvl.below_safe_inc = 0; lvl->dpm_to_perf_lvl.below_safe_inc = 0;
File drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.c changed (mode: 100644) (index d5a8908..266c773)
... ... long smc_eng_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
88 88 &smc_eng_clk->cg_eng_pll_func_ctl_1); &smc_eng_clk->cg_eng_pll_func_ctl_1);
89 89 put_unaligned_be32(eng_pll.cg_eng_pll_func_ctl_2, put_unaligned_be32(eng_pll.cg_eng_pll_func_ctl_2,
90 90 &smc_eng_clk->cg_eng_pll_func_ctl_2); &smc_eng_clk->cg_eng_pll_func_ctl_2);
91 put_unaligned_be32(eng_pll.cg_eng_pll_func_ctl_3,
92 &smc_eng_clk->cg_eng_pll_func_ctl_3);
91 93
92 94 put_unaligned_be32(eng_pll.cg_eng_pll_ss_0, put_unaligned_be32(eng_pll.cg_eng_pll_ss_0,
93 95 &smc_eng_clk->cg_eng_pll_ss_0); &smc_eng_clk->cg_eng_pll_ss_0);
File drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c changed (mode: 100644) (index 7b107c5..25daad2)
... ... static void dpm_to_perf_lvl_dump(struct smc_pp_dpm_to_perf_lvl *tbl)
46 46 u8 i; u8 i;
47 47
48 48 L("SMC_PP_DPM_TO_PERF_LVL START"); L("SMC_PP_DPM_TO_PERF_LVL START");
49 L("max_ps=0x%02x",tbl->max_ps);
49 L("max_pulse_skip=0x%02x",tbl->max_pulse_skip);
50 50 L("tgt_act=0x%02x",tbl->tgt_act); L("tgt_act=0x%02x",tbl->tgt_act);
51 L("max_ps_step_inc=0x%02x",tbl->max_ps_step_inc);
52 L("max_ps_step_dec=0x%02x",tbl->max_ps_step_dec);
51 L("max_pulse_skip_step_inc=0x%02x",tbl->max_pulse_skip_step_inc);
52 L("max_pulse_skip_step_dec=0x%02x",tbl->max_pulse_skip_step_dec);
53 53 L("ps_sampling_time=0x%02x",tbl->ps_sampling_time); L("ps_sampling_time=0x%02x",tbl->ps_sampling_time);
54 54 L("near_tdp_dec=0x%02x",tbl->near_tdp_dec); L("near_tdp_dec=0x%02x",tbl->near_tdp_dec);
55 55 L("above_safe_inc=0x%02x",tbl->above_safe_inc); L("above_safe_inc=0x%02x",tbl->above_safe_inc);
 
... ... static u8 gddr5_dll_state_compute(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
209 209 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
210 210
211 211 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
212 /* this should be never called as this driver is meant for discret gpus */
213 212 static u8 ddr3_mem_clk_freq_ratio_compute(u32 mem_clk) static u8 ddr3_mem_clk_freq_ratio_compute(u32 mem_clk)
214 213 { {
215 214 u8 mc_para_idx; u8 mc_para_idx;
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index ca0bd83..4af1944)
... ... static inline u32 get(u32 mask, u32 v)
597 597 #define SPT1_LTI_RATIO 0x78000000 #define SPT1_LTI_RATIO 0x78000000
598 598 /* end of configuration register area: 0x8000-0xb000--------------------------*/ /* end of configuration register area: 0x8000-0xb000--------------------------*/
599 599
600 /*----------------------------------------------------------------------------*/
601 #define UVD_IDX 0xf4a0
602 #define UI_ADDR 0x000001ff
603 #define UVD_DATA 0xf4a4
604
605 #define UVD_CGC_CTL_0 0xf4b0
606 #define UCC0_DCM BIT(0)
607 #define UCC0_CG_DT 0x0000003c
608 #define UCC0_CLK_OD 0x000007c0
609
610 /* uvd indirect register space */
611 #define UVD_CGC_MEM_CTL 0xc0
612 #define UVD_CGC_CTL_1 0xc1
613 #define UCC_DYN_OR_ENA BIT(0)
614 #define UCC_DYN_RR_ENA BIT(1)
615 #define UCC_G_DIV_ID 0x0000008c
616 /*----------------------------------------------------------------------------*/
617
600 618 #include "rlc_regs.h" #include "rlc_regs.h"
601 619 #include "dmas_regs.h" #include "dmas_regs.h"
602 620 #include "hdp_regs.h" #include "hdp_regs.h"
File drivers/gpu/alga/amd/si/smc_regs.h changed (mode: 100644) (index aadc133..3260fe3)
34 34 */ */
35 35 #define SMC_CG_IND_START 0xc0030000 #define SMC_CG_IND_START 0xc0030000
36 36 #define SMC_CG_IND_END 0xc0040000 #define SMC_CG_IND_END 0xc0040000
37
38 /*
39 * the following regs are in the above indirect smc space, probably not a
40 * xrbm feedback, but uvd
41 */
42 #define SMC_CG_CGTT_LOCAL_0 0x400
43 #define SMC_CG_CGTT_LOCAL_1 0x401
37 44 /* end of SMC register area---------------------------------------------------*/ /* end of SMC register area---------------------------------------------------*/
38 45
39 46 /* start of software SMC register area----------------------------------------*/ /* start of software SMC register area----------------------------------------*/
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index f6fd27d..b0c6316)
29 29 /* offset in smc address space SMC_FW_HDR_STATE_TBL */ /* offset in smc address space SMC_FW_HDR_STATE_TBL */
30 30 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
31 31 struct smc_pp_dpm_to_perf_lvl { struct smc_pp_dpm_to_perf_lvl {
32 u8 max_ps;
32 u8 max_pulse_skip;
33 33 u8 tgt_act; u8 tgt_act;
34 u8 max_ps_step_inc;
35 u8 max_ps_step_dec;
34 u8 max_pulse_skip_step_inc;
35 u8 max_pulse_skip_step_dec;
36 36 u8 ps_sampling_time; u8 ps_sampling_time;
37 37 u8 near_tdp_dec; u8 near_tdp_dec;
38 38 u8 above_safe_inc; u8 above_safe_inc;
 
... ... struct smc_volt {
86 86
87 87 #define SMC_STATE_FLGS_AUTO_PULSE_SKIP BIT(0) #define SMC_STATE_FLGS_AUTO_PULSE_SKIP BIT(0)
88 88 #define SMC_STATE_FLGS_PWR_BOOST BIT(1) #define SMC_STATE_FLGS_PWR_BOOST BIT(1)
89 #define SMC_STATE_FLGS_DEEPSLEEP_THROTTLE BIT(9)
90 #define SMC_STATE_FLGS_DEEPSLEEP_BYPASS BIT(10)
89 #define SMC_STATE_FLGS_DEEPSLEEP_THROTTLE BIT(5)
90 #define SMC_STATE_FLGS_DEEPSLEEP_BYPASS BIT(6)
91 91
92 92 struct smc_lvl { struct smc_lvl {
93 93 u8 mc_reg_set_idx; u8 mc_reg_set_idx;
File drivers/gpu/alga/amd/si/vm.c changed (mode: 100644) (index 2d5da22..180df2a)
... ... void vg_ena(struct pci_dev *dev)
43 43 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
44 44
45 45 /* /*
46 * XXX: the refactored upstream code path does not enable pg code
47 * path
46 * XXX: only verde chips have volt/pw gating, and the only block stable
47 * enough to be enabled is the one of the dma discret engines.
48 48 */ */
49 49
50 50 wr32(dev, dd->rlc.save_restore >> 8, RLC_SAVE_RESTORE_BASE); wr32(dev, dd->rlc.save_restore >> 8, RLC_SAVE_RESTORE_BASE);
 
... ... void vg_ena(struct pci_dev *dev)
53 53
54 54 void vg_dis(struct pci_dev *dev) void vg_dis(struct pci_dev *dev)
55 55 { {
56 /*
57 * XXX: the refactored upstream code path does not enable pg code
58 * path
59 */
56 /* XXX: see note above */
60 57 } }
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