sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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List of commits:
Subject Hash Author Date (UTC)
log more accurately the smc tbls 3d88d2a589a89e9a34f4046242f4a72a76069ddb Sylvain BERTRAND 2014-02-05 10:51:39
log more 5018f3c130cb9ce53e1834fcc586f00614a3ed86 Sylvain BERTRAND 2014-02-04 21:46:05
smc sw regs dump code 46acefa1d42984757cb1ba48a32130f2f9674687 Sylvain BERTRAND 2014-02-04 20:44:26
do dump the tbls c79209766b71e2d3231cf25673684762bf46dd8c Sylvain BERTRAND 2014-02-04 20:20:33
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
mc_mc_reg_tbl dump code af3826d3878248194a46cf3fda7dc2c503f8948b Sylvain BERTRAND 2014-02-04 19:40:11
mc_cac_cfg_tbl dump code 5b2ab4803a9053f36cf378a64c27f237c2c2bf0b Sylvain BERTRAND 2014-02-04 19:25:10
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
comestics and first fixes 784ed88cc10c159c57c923853bc8bd29238cc2c6 Sylvain BERTRAND 2014-02-04 17:01:06
tidy a bit a386d7d732466b07022622e8c763ebc608b9ab92 Sylvain BERTRAND 2014-02-03 17:40:52
cpy smc tbls to smc ram bc0860a37eec9cdf5962d4b9f9bb0c6981023587 Sylvain BERTRAND 2014-02-03 13:44:45
thermal regs programming 9a9ed598a7e8d9109a9ab23e90f3a94cb5c02e37 Sylvain BERTRAND 2014-01-31 14:22:12
eng clk pm and global pm switch to on a50fed4758305b9032d313cdf0021ec6a612d344 Sylvain BERTRAND 2014-01-31 12:54:41
send nodisplay msg to smc 91808e6c48d9d37da87f08da253825252122e4d9 Sylvain BERTRAND 2014-01-31 12:33:21
smc start 6c09abb37b34599c132f324359ce38d11888091f Sylvain BERTRAND 2014-01-31 12:03:10
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
tidy mc reg tbl 4761bf039ff2caf87c7eb139cf54c0f2e1932b60 Sylvain BERTRAND 2014-01-30 18:23:10
cpy cpu mem to smc mem 1b2deae0c86f878c72a40b2c4d07cdf308c3be11 Sylvain BERTRAND 2014-01-30 16:56:51
Commit 3d88d2a589a89e9a34f4046242f4a72a76069ddb - log more accurately the smc tbls
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-05 10:51
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-05 10:51
Parent(s): 5018f3c130cb9ce53e1834fcc586f00614a3ed86
Signing key:
Tree: 708a707cd6f16e5d9792ab7373ea79a7e417bfa0
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/smc_tbls.c 24 6
drivers/gpu/alga/amd/si/smc.c 46 2
drivers/gpu/alga/amd/si/smc.h 2 1
File drivers/gpu/alga/amd/si/dyn_pm/smc_tbls.c changed (mode: 100644) (index fc92238..8de94b2)
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
62 62
63 63 LOG("SMC_FW_HDR_STATE_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_STATE_TBL=0x%08x", smc_ram_tbl_of);
64 64
65 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_state_tbl,
65 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_state_tbl,
66 66 sizeof(*smc_state_tbl)); sizeof(*smc_state_tbl));
67 67 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
68 memset(smc_state_tbl, 0, sizeof(*smc_state_tbl));
69 smc_memcpy_from(ctx->dev, (u8*)smc_state_tbl, smc_ram_tbl_of,
70 sizeof(*smc_state_tbl));
68 71 smc_state_tbl_dump(smc_state_tbl); smc_state_tbl_dump(smc_state_tbl);
69 72 #endif #endif
70 73
 
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
75 78
76 79 LOG("SMC_FW_HDR_CAC_CFG_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_CAC_CFG_TBL=0x%08x", smc_ram_tbl_of);
77 80
78 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_cac_cfg_tbl,
81 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_cac_cfg_tbl,
79 82 sizeof(*smc_cac_cfg_tbl)); sizeof(*smc_cac_cfg_tbl));
80 83
81 84 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
85 memset(smc_cac_cfg_tbl, 0, sizeof(*smc_cac_cfg_tbl));
86 smc_memcpy_from(ctx->dev, (u8*)smc_cac_cfg_tbl, smc_ram_tbl_of,
87 sizeof(*smc_cac_cfg_tbl));
82 88 smc_cac_cfg_tbl_dump(smc_cac_cfg_tbl); smc_cac_cfg_tbl_dump(smc_cac_cfg_tbl);
83 89 #endif #endif
84 90
 
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
89 95
90 96 LOG("SMC_FW_HDR_MC_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_MC_TBL=0x%08x", smc_ram_tbl_of);
91 97
92 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_reg_tbl,
98 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_reg_tbl,
93 99 sizeof(*smc_mc_reg_tbl)); sizeof(*smc_mc_reg_tbl));
94 100 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
101 memset(smc_mc_reg_tbl, 0, sizeof(*smc_mc_reg_tbl));
102 smc_memcpy_from(ctx->dev, (u8*)smc_mc_reg_tbl, smc_ram_tbl_of,
103 sizeof(*smc_mc_reg_tbl));
95 104 smc_mc_reg_tbl_dump(smc_mc_reg_tbl); smc_mc_reg_tbl_dump(smc_mc_reg_tbl);
96 105 #endif #endif
97 106
 
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
102 111
103 112 LOG("SMC_FW_HDR_MC_ARB_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_MC_ARB_TBL=0x%08x", smc_ram_tbl_of);
104 113
105 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_arb_tbl,
114 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_mc_arb_tbl,
106 115 sizeof(*smc_mc_arb_tbl)); sizeof(*smc_mc_arb_tbl));
107 116
108 117 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
118 memset(smc_mc_arb_tbl, 0, sizeof(*smc_mc_arb_tbl));
119 smc_memcpy_from(ctx->dev, (u8*)smc_mc_arb_tbl, smc_ram_tbl_of,
120 sizeof(*smc_mc_reg_tbl));
109 121 smc_mc_arb_tbl_dump(smc_mc_arb_tbl); smc_mc_arb_tbl_dump(smc_mc_arb_tbl);
110 122 #endif #endif
111 123
 
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
116 128
117 129 LOG("SMC_FW_HDR_ENG_PLL_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_ENG_PLL_TBL=0x%08x", smc_ram_tbl_of);
118 130
119 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_eng_pll_tbl,
131 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_eng_pll_tbl,
120 132 sizeof(*smc_eng_pll_tbl)); sizeof(*smc_eng_pll_tbl));
121 133
122 134 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
135 memset(smc_eng_pll_tbl, 0, sizeof(*smc_eng_pll_tbl));
136 smc_memcpy_from(ctx->dev, (u8*)smc_eng_pll_tbl, smc_ram_tbl_of,
137 sizeof(*smc_eng_pll_tbl));
123 138 smc_eng_pll_tbl_dump(smc_eng_pll_tbl); smc_eng_pll_tbl_dump(smc_eng_pll_tbl);
124 139 #endif #endif
125 140
 
... ... static void tbls_cpy(struct ctx *ctx, struct smc_state_tbl *smc_state_tbl,
130 145
131 146 LOG("SMC_FW_HDR_DTE_CFG_TBL=0x%08x", smc_ram_tbl_of); LOG("SMC_FW_HDR_DTE_CFG_TBL=0x%08x", smc_ram_tbl_of);
132 147
133 smc_memcpy(ctx->dev, smc_ram_tbl_of, (u8*)smc_dte_cfg_tbl,
148 smc_memcpy_to(ctx->dev, smc_ram_tbl_of, (u8*)smc_dte_cfg_tbl,
134 149 sizeof(*smc_dte_cfg_tbl)); sizeof(*smc_dte_cfg_tbl));
135 150 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
151 memset(smc_dte_cfg_tbl, 0, sizeof(*smc_dte_cfg_tbl));
152 smc_memcpy_from(ctx->dev, (u8*)smc_dte_cfg_tbl, smc_ram_tbl_of,
153 sizeof(*smc_dte_cfg_tbl));
136 154 smc_dte_cfg_tbl_dump(smc_dte_cfg_tbl); smc_dte_cfg_tbl_dump(smc_dte_cfg_tbl);
137 155 #endif #endif
138 156
File drivers/gpu/alga/amd/si/smc.c changed (mode: 100644) (index d9d589c..be425ee)
... ... u32 smc_sw_r32(struct pci_dev *dev, u16 of)
207 207 return smc_r32(dev, reg_addr); return smc_r32(dev, reg_addr);
208 208 } }
209 209
210 void smc_memcpy(struct pci_dev *dev, u32 dest, u8 *src, u32 bytes_n)
210 void smc_memcpy_to(struct pci_dev *dev, u32 dest, u8 *src, u32 bytes_n)
211 211 { {
212 212 while (bytes_n >= 4) { while (bytes_n >= 4) {
213 213 /* /*
 
... ... void smc_memcpy(struct pci_dev *dev, u32 dest, u8 *src, u32 bytes_n)
250 250 } }
251 251 } }
252 252
253 void smc_memcpy_from(struct pci_dev *dev, u8 *dest, u32 src, u32 bytes_n)
254 {
255 while (bytes_n >= 4) {
256 __be32 be32;
257 u8 *be32p;
258
259 /* the xRBM will read that value as be32 from smc memory */
260 wr32(dev, src, SMC_IDX);
261 be32 = (__be32)rr32(dev, SMC_DATA);
262 be32p = (u8*)&be32;
263
264 dest[0] = be32p[3];
265 dest[1] = be32p[2];
266 dest[2] = be32p[1];
267 dest[3] = be32p[0];
268
269 src += 4;
270 bytes_n -= 4;
271 dest += 4;
272 }
273
274 /* the final dw */
275 if (bytes_n > 0) {
276 __be32 be32_last;
277 u8 *be32_lastp;
278 u8 dest_byte_idx;
279 u8 src_byte_idx;
280
281 wr32(dev, src, SMC_IDX);
282 be32_last = (__be32)rr32(dev, SMC_DATA);
283
284 be32_lastp = (u8*)&be32_last;
285
286 dest_byte_idx = 0;
287 src_byte_idx = 3;
288 while (bytes_n > 0) {
289 dest[dest_byte_idx] = be32_lastp[src_byte_idx];
290 ++dest_byte_idx;
291 src_byte_idx--;
292 bytes_n--;
293 }
294 }
295 }
296
253 297 void smc_initial_jmp_setup(struct pci_dev *dev) void smc_initial_jmp_setup(struct pci_dev *dev)
254 298 { {
255 299 static u8 jmp_instr[] = { 0x0e, 0x00, 0x40, 0x40 }; static u8 jmp_instr[] = { 0x0e, 0x00, 0x40, 0x40 };
256 300
257 smc_memcpy(dev, 0x0, &jmp_instr[0], sizeof(jmp_instr));
301 smc_memcpy_to(dev, 0x0, &jmp_instr[0], sizeof(jmp_instr));
258 302 } }
259 303
260 304 void smc_start(struct pci_dev *dev) void smc_start(struct pci_dev *dev)
File drivers/gpu/alga/amd/si/smc.h changed (mode: 100644) (index 175de48..04eb2f8)
... ... u32 smc_sw_r32(struct pci_dev *dev, u16 of);
20 20 void smc_sw_wr32(struct pci_dev *dev, u16 of, u32 val); void smc_sw_wr32(struct pci_dev *dev, u16 of, u32 val);
21 21 void smc_auto_increment_ena(struct pci_dev *dev); void smc_auto_increment_ena(struct pci_dev *dev);
22 22 void smc_auto_increment_dis(struct pci_dev *dev); void smc_auto_increment_dis(struct pci_dev *dev);
23 void smc_memcpy(struct pci_dev *dev, u32 dest, u8 *src, u32 bytes_n);
23 void smc_memcpy_to(struct pci_dev *dev, u32 dest, u8 *src, u32 bytes_n);
24 void smc_memcpy_from(struct pci_dev *dev, u8 *dest, u32 src, u32 bytes_n);
24 25
25 26 #define SMG_MSG_NODISPLAY 0x005d #define SMG_MSG_NODISPLAY 0x005d
26 27 long smc_msg(struct pci_dev *dev, u16 msg); long smc_msg(struct pci_dev *dev, u16 msg);
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