sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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master
List of commits:
Subject Hash Author Date (UTC)
installation of the perf pwr state continued b229eef2798acbe053aa09e47c213e23749638dd Sylvain BERTRAND 2014-02-13 10:48:02
dyn pm second part continuation 95dd7b4754476a014d8f84854e5b2ce5c81d23b4 Sylvain BERTRAND 2014-02-12 20:15:03
beginning of dyn pm second part c32c19d884dbf1f440480bbea42140e9c5ed8cd3 Sylvain BERTRAND 2014-02-12 14:44:04
uvd does only mpeg, then switch off 7e36b98bcab47e9986a63093dbeed98ab290f85f Sylvain BERTRAND 2014-02-12 10:55:54
bug fixing, end of dyn pm first part 533a4bd6731205f71704886e5fa099063be985ea Sylvain BERTRAND 2014-02-11 13:49:27
bug fixing c3fc0d7b807c98d20c13f53dcfc09713309ad2fa Sylvain BERTRAND 2014-02-11 11:16:00
static bios tbls *must* be ok e050fa94c2f1e846bb051748347332e234a6b93a Sylvain BERTRAND 2014-02-10 10:17:33
bug fixing 7baa7069aa89a98d831d7def358766155771e9ca Sylvain BERTRAND 2014-02-07 15:08:53
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
tbls fixes 4795a3090a17bc486056301bc6bef509b9c5e339 Sylvain BERTRAND 2014-02-05 15:09:41
log more accurately the smc tbls 3d88d2a589a89e9a34f4046242f4a72a76069ddb Sylvain BERTRAND 2014-02-05 10:51:39
log more 5018f3c130cb9ce53e1834fcc586f00614a3ed86 Sylvain BERTRAND 2014-02-04 21:46:05
smc sw regs dump code 46acefa1d42984757cb1ba48a32130f2f9674687 Sylvain BERTRAND 2014-02-04 20:44:26
do dump the tbls c79209766b71e2d3231cf25673684762bf46dd8c Sylvain BERTRAND 2014-02-04 20:20:33
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
mc_mc_reg_tbl dump code af3826d3878248194a46cf3fda7dc2c503f8948b Sylvain BERTRAND 2014-02-04 19:40:11
mc_cac_cfg_tbl dump code 5b2ab4803a9053f36cf378a64c27f237c2c2bf0b Sylvain BERTRAND 2014-02-04 19:25:10
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
Commit b229eef2798acbe053aa09e47c213e23749638dd - installation of the perf pwr state continued
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-13 10:48
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-13 10:48
Parent(s): 95dd7b4754476a014d8f84854e5b2ce5c81d23b4
Signer:
Signing key:
Signing status: N
Tree: d28f13d02b8a5540b5f3741342cffa7f2546377b
File Lines added Lines deleted
drivers/gpu/alga/amd/atombios/pp.c 46 0
drivers/gpu/alga/amd/atombios/tables/pp.h 4 4
drivers/gpu/alga/amd/si/dyn_pm/ctx.c 7 0
drivers/gpu/alga/amd/si/dyn_pm/ctx.h 2 0
drivers/gpu/alga/amd/si/dyn_pm/driver.c 47 2
drivers/gpu/alga/amd/si/dyn_pm/emergency.c 2 2
drivers/gpu/alga/amd/si/dyn_pm/initial.c 2 2
drivers/gpu/alga/amd/si/regs.h 3 3
include/alga/amd/atombios/pp.h 2 0
File drivers/gpu/alga/amd/atombios/pp.c changed (mode: 100644) (index e386e85..05e3a0d)
... ... unlock_mutex:
498 498 return r; return r;
499 499 } }
500 500 EXPORT_SYMBOL_GPL(atb_pp_tdp_limits_get); EXPORT_SYMBOL_GPL(atb_pp_tdp_limits_get);
501
502 long atb_pp_sq_ramping_threshold_get(struct atombios *atb,
503 u32 *sq_ramping_threshold)
504 {
505 u16 of;
506 struct master_data_tbl *data_tbl;
507 union pp *pp;
508 u16 tbl_sz;
509 long r;
510
511 mutex_lock(&atb->mutex);
512
513 of = get_unaligned_le16(&atb->hdr->master_data_tbl_of);
514 data_tbl = atb->adev.rom + of;
515
516 of = get_unaligned_le16(&data_tbl->list.pp_info);
517 pp = atb->adev.rom + of;
518
519 dev_info(atb->adev.dev, "atombios:pp_info (0x%04x) revision %u.%u\n",
520 of, pp->pp0.hdr.tbl_fmt_rev, pp->pp0.hdr.tbl_content_rev);
521
522 if (pp->pp0.hdr.tbl_fmt_rev != 6 && pp->pp0.hdr.tbl_content_rev != 1) {
523 dev_err(atb->adev.dev, "atombios:pp_info (0x%04x) revision %u.%u not supported\n",
524 of, pp->pp0.hdr.tbl_fmt_rev,
525 pp->pp0.hdr.tbl_content_rev);
526 r = -ATB_ERR;
527 goto unlock_mutex;
528 }
529
530 tbl_sz = get_unaligned_le16(&pp->pp0.tbl_sz);
531 if (tbl_sz < sizeof(struct pp4)) {
532 dev_err(atb->adev.dev, "atombios:missing powerplay 4 table\n");
533 r = -ATB_ERR;
534 goto unlock_mutex;
535 }
536
537 *sq_ramping_threshold = get_unaligned_le32(
538 &pp->pp4.sq_ramping_threshold);
539
540 r = 0;
541
542 unlock_mutex:
543 mutex_unlock(&atb->mutex);
544 return r;
545 }
546 EXPORT_SYMBOL_GPL(atb_pp_sq_ramping_threshold_get);
File drivers/gpu/alga/amd/atombios/tables/pp.h changed (mode: 100644) (index 13bee9a..f224d4b)
... ... struct pp4 {
198 198 struct pp3 pp3; struct pp3 pp3;
199 199 __le32 tdp_limit; __le32 tdp_limit;
200 200 __le32 near_tdp_limit; __le32 near_tdp_limit;
201 __le32 unused0;
201 __le32 sq_ramping_threshold; /* units of 10 kHz */
202 202 __le16 cac_lkge_tbl_of; __le16 cac_lkge_tbl_of;
203 __le32 cac_lkge; /* for driver calculated cac lkge tbl */
204 __le16 unused1;
205 __le16 load_line_slope; /* mOhms * 100 */
203 __le32 cac_lkge; /* for driver calculated cac lkge tbl */
204 __le16 unused0;
205 __le16 load_line_slope; /* mOhms * 100 */
206 206 } __packed; } __packed;
207 207 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
208 208
File drivers/gpu/alga/amd/si/dyn_pm/ctx.c changed (mode: 100644) (index 8931550..fac74ea)
... ... long ctx_init(struct pci_dev *dev, struct ctx *ctx)
677 677 dev_err(&dev->dev, "dyn_pm:unable to fetch the voltage time\n"); dev_err(&dev->dev, "dyn_pm:unable to fetch the voltage time\n");
678 678 goto err_free_cac_lkge_tbl_entries; goto err_free_cac_lkge_tbl_entries;
679 679 } }
680
681 r = atb_pp_sq_ramping_threshold_get(dd->atb,
682 &ctx->atb_sq_ramping_threshold);
683 if (r == -ATB_ERR) {
684 dev_err(&dev->dev, "dyn_pm:unable to fetch the sequencer block ramping threshold\n");
685 goto err_free_cac_lkge_tbl_entries;
686 }
680 687 return 0; return 0;
681 688
682 689 err_free_cac_lkge_tbl_entries: err_free_cac_lkge_tbl_entries:
File drivers/gpu/alga/amd/si/dyn_pm/ctx.h changed (mode: 100644) (index ee0efaf..0e9f836)
... ... struct ctx {
83 83
84 84 u16 atb_back_bias_time; u16 atb_back_bias_time;
85 85 u16 atb_volt_time; u16 atb_volt_time;
86
87 u32 atb_sq_ramping_threshold;
86 88 }; };
87 89
88 90 long ctx_init(struct pci_dev *dev, struct ctx *ctx); long ctx_init(struct pci_dev *dev, struct ctx *ctx);
File drivers/gpu/alga/amd/si/dyn_pm/driver.c changed (mode: 100644) (index 6d19e77..1721e29)
... ... static void smc_sw_state_init(struct ctx *ctx, struct smc_sw_state *state)
44 44 state->lvls_n = ctx->atb_performance.lvls_n; state->lvls_n = ctx->atb_performance.lvls_n;
45 45 } }
46 46
47 #define PWR_EFFICIENCY_RATIO_MARGIN 10
47 48 static u16 pwr_efficiency_ratio_compute(struct ctx *ctx, static u16 pwr_efficiency_ratio_compute(struct ctx *ctx,
48 49 struct smc_volt *prev_std_vddc, struct smc_volt *cur_std_vddc) struct smc_volt *prev_std_vddc, struct smc_volt *cur_std_vddc)
49 50 { {
50 //TODO
51 return 0;
51 u64 prev_std_vddc_mv;
52 u64 cur_std_vddc_mv;
53 u64 n;
54 u64 d;
55 u64 pwr_efficiency_ratio;
56
57 prev_std_vddc_mv = (u64)get_unaligned_be16(&prev_std_vddc->val);
58 cur_std_vddc_mv = (u64)get_unaligned_be16(&cur_std_vddc->val);
59
60 n = div64_u64(1024 * cur_std_vddc_mv * cur_std_vddc_mv
61 * (1000 + PWR_EFFICIENCY_RATIO_MARGIN), 1000);
62 d = prev_std_vddc_mv * prev_std_vddc_mv;
63
64 pwr_efficiency_ratio = div64_u64(n, d);
65 return (u16)pwr_efficiency_ratio;
52 66 } }
53 67
54 68 #define NEAR_TDP_DEC 10 #define NEAR_TDP_DEC 10
 
... ... static long smc_pp_dpm_to_perf_lvl_init(struct ctx *ctx, u8 lvl_idx,
111 125 return 0; return 0;
112 126 } }
113 127
128 #define SQ_RAMPING_PWR_MAX 0x3fff
129 #define SQ_RAMPING_PWR_MIN 0x12
130 #define SQ_RAMPING_PWR_DELTA_MAX 0x15
131 #define SQ_RAMPING_STI_SZ 0x1e
132 #define SQ_RAMPING_LTI_RATIO 0xf
133 static void sq_ramping_threshold_init(struct ctx *ctx, u8 lvl_idx,
134 struct smc_lvl *lvl)
135 {
136 u32 sq_pwr_throttle_0;
137 u32 sq_pwr_throttle_1;
138
139 if (ctx->atb_performance.lvls[lvl_idx].eng_clk >=
140 ctx->atb_sq_ramping_threshold) {
141 sq_pwr_throttle_0 = set(SPT0_PWR_MAX, SQ_RAMPING_PWR_MAX);
142 sq_pwr_throttle_0 |= set(SPT0_PWR_MIN, SQ_RAMPING_PWR_MIN);
143
144 sq_pwr_throttle_1 = set(SPT1_PWR_DELTA_MAX,
145 SQ_RAMPING_PWR_DELTA_MAX);
146 sq_pwr_throttle_1 |= set(SPT1_STI_SZ, SQ_RAMPING_STI_SZ);
147 sq_pwr_throttle_1 |= set(SPT1_LTI_RATIO, SQ_RAMPING_LTI_RATIO);
148 } else {
149 sq_pwr_throttle_0 = SPT0_PWR_MIN | SPT0_PWR_MAX;
150 sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ
151 | SPT1_LTI_RATIO;
152 }
153
154 put_unaligned_be32(sq_pwr_throttle_0, &lvl->sq_pwr_throttle_0);
155 put_unaligned_be32(sq_pwr_throttle_1, &lvl->sq_pwr_throttle_1);
156 }
157
114 158 static long smc_lvls_init(struct ctx *ctx, struct smc_lvl *lvls) static long smc_lvls_init(struct ctx *ctx, struct smc_lvl *lvls)
115 159 { {
116 160 u8 lvl_idx; u8 lvl_idx;
 
... ... static long smc_lvls_init(struct ctx *ctx, struct smc_lvl *lvls)
149 193
150 194 smc_pp_dpm_to_perf_lvl_init(ctx, lvl_idx, smc_pp_dpm_to_perf_lvl_init(ctx, lvl_idx,
151 195 &lvl->dpm_to_perf_lvl); &lvl->dpm_to_perf_lvl);
196 sq_ramping_threshold_init(ctx, lvl_idx, lvl);
152 197 //TODO //TODO
153 198 } }
154 199 return 0; return 0;
File drivers/gpu/alga/amd/si/dyn_pm/emergency.c changed (mode: 100644) (index e651a0f..dc3306a)
... ... long smc_state_tbl_emergency_init(struct ctx *ctx, struct smc_state_tbl *tbl)
231 231 lvl->dpm_to_perf_lvl.pwr_efficiency_ratio = 0; lvl->dpm_to_perf_lvl.pwr_efficiency_ratio = 0;
232 232
233 233 /* set everything to the max value, namely all bits to 1 */ /* set everything to the max value, namely all bits to 1 */
234 put_unaligned_be32(SPT0_MIN_PWR | SPT0_MAX_PWR,
234 put_unaligned_be32(SPT0_PWR_MIN | SPT0_PWR_MAX,
235 235 &lvl->sq_pwr_throttle_0); &lvl->sq_pwr_throttle_0);
236 236
237 put_unaligned_be32(SPT1_MAX_PWR_DELTA | SPT1_STI_SZ | SPT1_LTI_RATIO,
237 put_unaligned_be32(SPT1_PWR_DELTA_MAX | SPT1_STI_SZ | SPT1_LTI_RATIO,
238 238 &lvl->sq_pwr_throttle_1); &lvl->sq_pwr_throttle_1);
239 239 return 0; return 0;
240 240 } }
File drivers/gpu/alga/amd/si/dyn_pm/initial.c changed (mode: 100644) (index 291f8ab..229d921)
... ... void smc_state_tbl_initial_init(struct ctx *ctx, struct smc_state_tbl *tbl)
148 148 lvl->dpm_to_perf_lvl.pwr_efficiency_ratio = 0; lvl->dpm_to_perf_lvl.pwr_efficiency_ratio = 0;
149 149
150 150 /* set everything to the max value, namely all bits to 1 */ /* set everything to the max value, namely all bits to 1 */
151 put_unaligned_be32(SPT0_MIN_PWR | SPT0_MAX_PWR,
151 put_unaligned_be32(SPT0_PWR_MIN | SPT0_PWR_MAX,
152 152 &lvl->sq_pwr_throttle_0); &lvl->sq_pwr_throttle_0);
153 153
154 put_unaligned_be32(SPT1_MAX_PWR_DELTA | SPT1_STI_SZ | SPT1_LTI_RATIO,
154 put_unaligned_be32(SPT1_PWR_DELTA_MAX | SPT1_STI_SZ | SPT1_LTI_RATIO,
155 155 &lvl->sq_pwr_throttle_1); &lvl->sq_pwr_throttle_1);
156 156 } }
File drivers/gpu/alga/amd/si/regs.h changed (mode: 100644) (index 1e59658..e2ee383)
... ... static inline u32 get(u32 mask, u32 v)
589 589 #define SCRATCH_ADDR 0x8544 #define SCRATCH_ADDR 0x8544
590 590
591 591 #define SQ_PWR_THROTTLE_0 0x8e58 #define SQ_PWR_THROTTLE_0 0x8e58
592 #define SPT0_MIN_PWR 0x00003fff
593 #define SPT0_MAX_PWR 0x3fff0000
592 #define SPT0_PWR_MIN 0x00003fff
593 #define SPT0_PWR_MAX 0x3fff0000
594 594 #define SQ_PWR_THROTTLE_1 0x8e5c #define SQ_PWR_THROTTLE_1 0x8e5c
595 #define SPT1_MAX_PWR_DELTA 0x00003fff
595 #define SPT1_PWR_DELTA_MAX 0x00003fff
596 596 #define SPT1_STI_SZ 0x03ff0000 #define SPT1_STI_SZ 0x03ff0000
597 597 #define SPT1_LTI_RATIO 0x78000000 #define SPT1_LTI_RATIO 0x78000000
598 598 /* end of configuration register area: 0x8000-0xb000--------------------------*/ /* end of configuration register area: 0x8000-0xb000--------------------------*/
File include/alga/amd/atombios/pp.h changed (mode: 100644) (index b6b8a9b..b986d39)
... ... long atb_pp_back_bias_time_get(struct atombios *atb, u16 *back_bias_time);
85 85
86 86 long atb_pp_tdp_limits_get(struct atombios *atb, u32 *tdp_limit, long atb_pp_tdp_limits_get(struct atombios *atb, u32 *tdp_limit,
87 87 u32 *near_tdp_limit); u32 *near_tdp_limit);
88 long atb_pp_sq_ramping_threshold_get(struct atombios *atb,
89 u32 *sq_ramping_threshold);
88 90 #endif #endif
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