sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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master
List of commits:
Subject Hash Author Date (UTC)
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
tbls fixes 4795a3090a17bc486056301bc6bef509b9c5e339 Sylvain BERTRAND 2014-02-05 15:09:41
log more accurately the smc tbls 3d88d2a589a89e9a34f4046242f4a72a76069ddb Sylvain BERTRAND 2014-02-05 10:51:39
log more 5018f3c130cb9ce53e1834fcc586f00614a3ed86 Sylvain BERTRAND 2014-02-04 21:46:05
smc sw regs dump code 46acefa1d42984757cb1ba48a32130f2f9674687 Sylvain BERTRAND 2014-02-04 20:44:26
do dump the tbls c79209766b71e2d3231cf25673684762bf46dd8c Sylvain BERTRAND 2014-02-04 20:20:33
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
mc_mc_reg_tbl dump code af3826d3878248194a46cf3fda7dc2c503f8948b Sylvain BERTRAND 2014-02-04 19:40:11
mc_cac_cfg_tbl dump code 5b2ab4803a9053f36cf378a64c27f237c2c2bf0b Sylvain BERTRAND 2014-02-04 19:25:10
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
comestics and first fixes 784ed88cc10c159c57c923853bc8bd29238cc2c6 Sylvain BERTRAND 2014-02-04 17:01:06
tidy a bit a386d7d732466b07022622e8c763ebc608b9ab92 Sylvain BERTRAND 2014-02-03 17:40:52
cpy smc tbls to smc ram bc0860a37eec9cdf5962d4b9f9bb0c6981023587 Sylvain BERTRAND 2014-02-03 13:44:45
thermal regs programming 9a9ed598a7e8d9109a9ab23e90f3a94cb5c02e37 Sylvain BERTRAND 2014-01-31 14:22:12
eng clk pm and global pm switch to on a50fed4758305b9032d313cdf0021ec6a612d344 Sylvain BERTRAND 2014-01-31 12:54:41
send nodisplay msg to smc 91808e6c48d9d37da87f08da253825252122e4d9 Sylvain BERTRAND 2014-01-31 12:33:21
smc start 6c09abb37b34599c132f324359ce38d11888091f Sylvain BERTRAND 2014-01-31 12:03:10
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
Commit d4a1ef00d163bc42e277c83d0a763fa11476af56 - bug fixing
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-06 20:14
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-06 20:14
Parent(s): 4795a3090a17bc486056301bc6bef509b9c5e339
Signer:
Signing key:
Signing status: N
Tree: 3e237250f1bb240e53b23dcdebeeb2844441eb40
File Lines added Lines deleted
drivers/gpu/alga/amd/atombios/cm.c 2 2
drivers/gpu/alga/amd/atombios/tables/pp.h 1 1
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c 3 1
drivers/gpu/alga/amd/si/dyn_pm/emergency.c 60 5
drivers/gpu/alga/amd/si/dyn_pm/private.h 1 0
drivers/gpu/alga/amd/si/dyn_pm/smc_cac_cfg_tbl.c 3 3
drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c 3 5
drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c 1 1
drivers/gpu/alga/amd/si/smc_tbls.h 5 5
File drivers/gpu/alga/amd/atombios/cm.c changed (mode: 100644) (index ffa8f89..90515d5)
... ... long atb_eng_pll_compute(struct atombios *atb, u32 eng_clk,
547 547 DEV_INFOC(atb->adev.dev, "eng_pll_compute(0x%04x) revision %u.%u", DEV_INFOC(atb->adev.dev, "eng_pll_compute(0x%04x) revision %u.%u",
548 548 of,eng_pll_compute->hdr.tbl_fmt_rev, of,eng_pll_compute->hdr.tbl_fmt_rev,
549 549 eng_pll_compute->hdr.tbl_content_rev); eng_pll_compute->hdr.tbl_content_rev);
550 //FIXME: lock the info->hdr.tbl_fmt_rev
551 if (eng_pll_compute->hdr.tbl_content_rev != 5) {
550 if (eng_pll_compute->hdr.tbl_fmt_rev != 1
551 && eng_pll_compute->hdr.tbl_content_rev != 5) {
552 552 dev_err(atb->adev.dev, "atombios:eng_pll_compute revision not supported"); dev_err(atb->adev.dev, "atombios:eng_pll_compute revision not supported");
553 553 r = -ATB_ERR; r = -ATB_ERR;
554 554 goto unlock_mutex; goto unlock_mutex;
File drivers/gpu/alga/amd/atombios/tables/pp.h changed (mode: 100644) (index 0093dbb..13bee9a)
... ... struct volt_params {
317 317
318 318 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
319 319 #define MEM_ENG_SET_CLK 0x00ffffff #define MEM_ENG_SET_CLK 0x00ffffff
320 #define MEM_ENG_COMPUTE_OP 0x0300000
320 #define MEM_ENG_COMPUTE_OP 0x03000000
321 321 #define COMPUTE_MEMORY_PLL 1 #define COMPUTE_MEMORY_PLL 1
322 322 #define COMPUTE_ENGINE_PLL 2 #define COMPUTE_ENGINE_PLL 2
323 323 #define ADJUST_MC_SETTING 3 #define ADJUST_MC_SETTING 3
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c changed (mode: 100644) (index 37a7430..4970037)
... ... long eng_pll_compute(struct ctx *ctx, u32 eng_clk, struct eng_pll *eng_pll)
91 91 eng_pll->cg_eng_pll_func_ctl_2 |= set(CEPFC2_FB_DIV, fb_div); eng_pll->cg_eng_pll_func_ctl_2 |= set(CEPFC2_FB_DIV, fb_div);
92 92 eng_pll->cg_eng_pll_func_ctl_2 |= CEPFC2_DITH_ENA; eng_pll->cg_eng_pll_func_ctl_2 |= CEPFC2_DITH_ENA;
93 93
94 eng_pll->cg_eng_pll_func_ctl_3 = dd->pp.clks_regs.cg_eng_pll_func_ctl_3;
95
94 96 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
95 97 /* related to spread spectrum */ /* related to spread spectrum */
96 98 /*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
 
... ... static void clks_regs_save(struct pci_dev *dev)
603 605 CG_ENG_PLL_FUNC_CTL_1); CG_ENG_PLL_FUNC_CTL_1);
604 606 dd->pp.clks_regs.cg_eng_pll_func_ctl_2 = rr32(dev, dd->pp.clks_regs.cg_eng_pll_func_ctl_2 = rr32(dev,
605 607 CG_ENG_PLL_FUNC_CTL_2); CG_ENG_PLL_FUNC_CTL_2);
606 dd->pp.clks_regs.cg_eng_pll_func_ctl_2 = rr32(dev,
608 dd->pp.clks_regs.cg_eng_pll_func_ctl_3 = rr32(dev,
607 609 CG_ENG_PLL_FUNC_CTL_3); CG_ENG_PLL_FUNC_CTL_3);
608 610 dd->pp.clks_regs.cg_eng_pll_ss_0 = rr32(dev, CG_ENG_PLL_SS_0); dd->pp.clks_regs.cg_eng_pll_ss_0 = rr32(dev, CG_ENG_PLL_SS_0);
609 611 dd->pp.clks_regs.cg_eng_pll_ss_1 = rr32(dev, CG_ENG_PLL_SS_1); dd->pp.clks_regs.cg_eng_pll_ss_1 = rr32(dev, CG_ENG_PLL_SS_1);
File drivers/gpu/alga/amd/si/dyn_pm/emergency.c changed (mode: 100644) (index 4416510..f16fd45)
39 39 #include "smc_volt.h" #include "smc_volt.h"
40 40 #include "smc_mc_reg_tbl.h" #include "smc_mc_reg_tbl.h"
41 41
42 static void patch(struct ctx *ctx, struct smc_state_tbl *tbl)
43 {
44 struct atb_pp_lvl *atb_lvl;
45 struct smc_lvl *smc_lvl;
46
47 atb_lvl = &ctx->atb_emergency.lvls[0];
48 smc_lvl = &tbl->emergency_lvl;
49
50 if (ctx->volt_caps & VOLT_CAPS_VDDC_CTL_ENA) {
51 /*
52 * We cheat here: We are supposed to use a kind of lowest
53 * vddc in atb pp state tbls. Here we use the lowest value
54 * in the atb volt tbl, namely with idx 0.
55 */
56 smc_lvl->vddc.step_idx = 0;
57 put_unaligned_be16(ctx->atb_vddc_tbl.entries[0].val_mv,
58 &smc_lvl->vddc.val);
59
60 smc_volt_std_vddc_compute(ctx, &smc_lvl->std_vddc,
61 &smc_lvl->vddc);
62 }
63
64 if (ctx->volt_caps & VOLT_CAPS_VDDC_PHASE_SHED_CTL_ENA) {
65 u8 i;
66
67 /*
68 * the limit tbl rng from low to high volts, then locate
69 * a limit with enough pwr for the for the targetted vddc
70 */
71 for (i = 0; i < ctx->atb_vddc_phase_shed_limits_tbl.entries_n;
72 ++i) {
73 struct atb_vddc_phase_shed_limits *limit;
74
75 limit = &ctx->atb_vddc_phase_shed_limits_tbl.entries[i];
76 /* don't use the atb_lvl to avoid a lkge index */
77 if (limit->vddc_mv
78 >= get_unaligned_be16(&smc_lvl->vddc.val))
79 break;
80 }
81 smc_lvl->vddc.phase_settings = i;
82 }
83
84 /* do not patch vddci from the initial state */
85
86 smc_lvl->pcie_gen = pcie_speed_cap(ctx, BIF_PCIE_GEN_1);
87 }
88
42 89 static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl) static long patch_from_atb(struct ctx *ctx, struct smc_state_tbl *tbl)
43 90 { {
44 91 struct atb_pp_lvl *atb_lvl; struct atb_pp_lvl *atb_lvl;
 
... ... long smc_state_tbl_emergency_init(struct ctx *ctx, struct smc_state_tbl *tbl)
109 156
110 157 LOG("emergency smc table init"); LOG("emergency smc table init");
111 158
112 /* the emergency state is a patched version of the initial state */
159 /*
160 * The emergency state is a patched version of the initial state. If
161 * the atombios has an emergency table, do patch further the state
162 * with the data provided.
163 */
113 164 tbl->emergency = tbl->initial; tbl->emergency = tbl->initial;
114 165 tbl->emergency_lvl = tbl->initial_lvl; tbl->emergency_lvl = tbl->initial_lvl;
115 166 tbl->emergency.flgs &= ~SMC_SW_STATE_FLGS_DC; tbl->emergency.flgs &= ~SMC_SW_STATE_FLGS_DC;
167 lvl = &tbl->emergency_lvl;
116 168
117 r = patch_from_atb(ctx, tbl);
118 if (r == -SI_ERR)
119 return -SI_ERR;
169 if (ctx->atb_emergency.lvls_n) {
170 r = patch_from_atb(ctx, tbl);
171 if (r == -SI_ERR)
172 return -SI_ERR;
173 } else {
174 patch(ctx, tbl);
175 }
120 176
121 lvl = &tbl->emergency_lvl;
122 177 dd = pci_get_drvdata(ctx->dev); dd = pci_get_drvdata(ctx->dev);
123 178
124 179 /* patch some clock registers */ /* patch some clock registers */
File drivers/gpu/alga/amd/si/dyn_pm/private.h changed (mode: 100644) (index 45a2cf7..5a67f67)
... ... struct eng_pll {
36 36 u32 cg_eng_pll_func_ctl_0; u32 cg_eng_pll_func_ctl_0;
37 37 u32 cg_eng_pll_func_ctl_1; u32 cg_eng_pll_func_ctl_1;
38 38 u32 cg_eng_pll_func_ctl_2; u32 cg_eng_pll_func_ctl_2;
39 u32 cg_eng_pll_func_ctl_3;
39 40 u32 cg_eng_pll_ss_0; u32 cg_eng_pll_ss_0;
40 41 u32 cg_eng_pll_ss_1; u32 cg_eng_pll_ss_1;
41 42 }; };
File drivers/gpu/alga/amd/si/dyn_pm/smc_cac_cfg_tbl.c changed (mode: 100644) (index 81a71f9..d7666c9)
... ... static void lkge_lut_init(struct ctx *ctx, struct smc_cac_cfg_tbl *tbl,
207 207
208 208 static u32 wnd_time_compute(struct ctx *ctx) static u32 wnd_time_compute(struct ctx *ctx)
209 209 { {
210 u32 cg_cac_ctl;
211 210 u32 cac_wnd; u32 cac_wnd;
212 211 u32 cac_wnd_sz; u32 cac_wnd_sz;
212 struct pwrtune *pwrtune;
213 213
214 cg_cac_ctl = rr32(ctx->dev, CG_CAC_CTL);
215 cac_wnd = get(CCC_CAC_WND, cg_cac_ctl);
214 pwrtune = pwrtune_get(ctx->dev);
215 cac_wnd = get(CCC_CAC_WND, pwrtune->cac_wnd);
216 216
217 217 cac_wnd_sz = ((cac_wnd & 0xffff0000) >> 16) * (cac_wnd & 0x0000ffff); cac_wnd_sz = ((cac_wnd & 0xffff0000) >> 16) * (cac_wnd & 0x0000ffff);
218 218
File drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c changed (mode: 100644) (index 925c8ea..0f56199)
... ... long smc_state_tbl_init(struct ctx *ctx, struct smc_state_tbl *tbl)
321 321 if (r == -SI_ERR) if (r == -SI_ERR)
322 322 return -SI_ERR; return -SI_ERR;
323 323
324 if (ctx->atb_emergency.lvls_n) {
325 r = smc_state_tbl_emergency_init(ctx, tbl);
326 if (r == -SI_ERR)
327 return -SI_ERR;
328 }
324 r = smc_state_tbl_emergency_init(ctx, tbl);
325 if (r == -SI_ERR)
326 return -SI_ERR;
329 327
330 328 if (ctx->atb_ulv.lvls_n) { if (ctx->atb_ulv.lvls_n) {
331 329 r = smc_state_tbl_ulv_init(ctx, tbl); r = smc_state_tbl_ulv_init(ctx, tbl);
File drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c changed (mode: 100644) (index 2e92109..10c0763)
... ... static long volt_step_idx(struct atb_volt_tbl *tbl, u16 val_mv)
62 62
63 63 if (step == tbl->entries_n) if (step == tbl->entries_n)
64 64 return -SI_ERR; return -SI_ERR;
65 return 0;
65 return step;
66 66 } }
67 67
68 68 long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc, long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc,
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index bb6819c..a8bf396)
... ... struct smc_volt_mask_tbl {
151 151
152 152 #define SMC_PP_SYSTEM_FLGS_GPIO_DC BIT(0) #define SMC_PP_SYSTEM_FLGS_GPIO_DC BIT(0)
153 153 #define SMC_PP_SYSTEM_FLGS_STEP_VDDC BIT(1) #define SMC_PP_SYSTEM_FLGS_STEP_VDDC BIT(1)
154 #define SMC_PP_SYSTEM_FLGS_GDDR5 BIT(3)
155 #define SMC_PP_SYSTEM_FLGS_DIS_BABYSTEP BIT(4)
156 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT BIT(5)
157 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT_ANALOG BIT(6)
158 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT_PROG_GPIO BIT(7)
154 #define SMC_PP_SYSTEM_FLGS_GDDR5 BIT(2)
155 #define SMC_PP_SYSTEM_FLGS_DIS_BABYSTEP BIT(3)
156 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT BIT(4)
157 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT_ANALOG BIT(5)
158 #define SMC_PP_SYSTEM_FLGS_REGULATOR_HOT_PROG_GPIO BIT(6)
159 159
160 160 /* which action to perform when going from ac to dc */ /* which action to perform when going from ac to dc */
161 161 #define SMC_PP_EXTRA_FLGS_DONT_WAIT_FOR_VBLANK 0x08 #define SMC_PP_EXTRA_FLGS_DONT_WAIT_FOR_VBLANK 0x08
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