sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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List of commits:
Subject Hash Author Date (UTC)
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
mc_mc_reg_tbl dump code af3826d3878248194a46cf3fda7dc2c503f8948b Sylvain BERTRAND 2014-02-04 19:40:11
mc_cac_cfg_tbl dump code 5b2ab4803a9053f36cf378a64c27f237c2c2bf0b Sylvain BERTRAND 2014-02-04 19:25:10
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
comestics and first fixes 784ed88cc10c159c57c923853bc8bd29238cc2c6 Sylvain BERTRAND 2014-02-04 17:01:06
tidy a bit a386d7d732466b07022622e8c763ebc608b9ab92 Sylvain BERTRAND 2014-02-03 17:40:52
cpy smc tbls to smc ram bc0860a37eec9cdf5962d4b9f9bb0c6981023587 Sylvain BERTRAND 2014-02-03 13:44:45
thermal regs programming 9a9ed598a7e8d9109a9ab23e90f3a94cb5c02e37 Sylvain BERTRAND 2014-01-31 14:22:12
eng clk pm and global pm switch to on a50fed4758305b9032d313cdf0021ec6a612d344 Sylvain BERTRAND 2014-01-31 12:54:41
send nodisplay msg to smc 91808e6c48d9d37da87f08da253825252122e4d9 Sylvain BERTRAND 2014-01-31 12:33:21
smc start 6c09abb37b34599c132f324359ce38d11888091f Sylvain BERTRAND 2014-01-31 12:03:10
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
tidy mc reg tbl 4761bf039ff2caf87c7eb139cf54c0f2e1932b60 Sylvain BERTRAND 2014-01-30 18:23:10
cpy cpu mem to smc mem 1b2deae0c86f878c72a40b2c4d07cdf308c3be11 Sylvain BERTRAND 2014-01-30 16:56:51
init of smc sw regs for response times af87f39cda6b64d7c5367ea4fa77899a55a0b9e0 Sylvain BERTRAND 2014-01-30 15:39:37
smc state dyn pm params init 66b37051c3927dfecc92d6d630c53ddf927c7d79 Sylvain BERTRAND 2014-01-30 11:11:05
init of smc cac cfg regs add98b596c10e16693171e04a7f9168232a1f65d Sylvain BERTRAND 2014-01-29 19:38:59
cosmestics ee91a7ee91132de107bef05de70a8ea28f89dddf Sylvain BERTRAND 2014-01-28 23:12:44
Commit 46dcab9ac217dbf29a1295622587e083f161b677 - mc_dte_cfg_tbl dump code
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-04 20:11
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-04 20:11
Parent(s): 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7
Signer:
Signing key:
Signing status: N
Tree: 74428339637a2d437c896cb189fb804c9903d770
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/smc_dte_cfg_tbl.c 54 1
drivers/gpu/alga/amd/si/dyn_pm/smc_dte_cfg_tbl.h 4 0
drivers/gpu/alga/amd/si/smc_tbls.h 2 2
File drivers/gpu/alga/amd/si/dyn_pm/smc_dte_cfg_tbl.c changed (mode: 100644) (index df65deb..759e13c)
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37 37
38 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
39 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
40 void smc_dte_cfg_tbl_dump(struct smc_dte_cfg_tbl *tbl)
41 {
42 u32 tmp;
43 u8 i;
44
45 L("SMC_DTE_CFG_TBL START");
46
47 for (i = 0; i < SMC_DTE_CFG_TBL_FILTER_STAGES_N_MAX; ++i) {
48 tmp = get_unaligned_be32(&tbl->tau[i]);
49 L("tau[%u]=0x%08x",i,tmp);
50 }
51
52 for (i = 0; i < SMC_DTE_CFG_TBL_FILTER_STAGES_N_MAX; ++i) {
53 tmp = get_unaligned_be32(&tbl->r[i]);
54 L("r[%u]=0x%08x",i,tmp);
55 }
56
57 tmp = get_unaligned_be32(&tbl->k);
58 L("k=0x%08x",tmp);
59
60 tmp = get_unaligned_be32(&tbl->t0);
61 L("t0=0x%08x",tmp);
62
63 tmp = get_unaligned_be32(&tbl->max_t);
64 L("max_t=0x%08x",tmp);
65
66 L("wnd_sz=0x%02x",tbl->wnd_sz);
67 L("temp_select=0x%02x",tbl->temp_select);
68 L("dte_mode=0x%02x",tbl->dte_mode);
69 L("tdep_cnt=0x%02x",tbl->tdep_cnt);
70
71 for (i = 0; i < SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX; ++i)
72 L("t_limits[%u]=0x%02x",i,tbl->t_limits[i]);
73
74 for (i = 0; i < SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX; ++i) {
75 tmp = get_unaligned_be32(&tbl->tdep_tau[i]);
76 L("tdep_tau[%u]=0x%08x",i,tmp);
77 }
78
79 for (i = 0; i <SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX; ++i) {
80 tmp = get_unaligned_be32(&tbl->tdep_r[i]);
81 L("tdep_r[%u]=0x%08x",i,tmp);
82 }
83
84 tmp = get_unaligned_be32(&tbl->t_threshold);
85 L("t_threshold=0x%08x",tmp);
86
87 L("SMC_DTE_CFG_TBL END");
88 }
89 #endif
90
38 91 static struct smc_dte_cfg_tbl tahiti = { static struct smc_dte_cfg_tbl tahiti = {
39 92 { {
40 93 1159409, 1159409,
 
... ... static void patch_from_pl2(struct ctx *ctx, struct smc_dte_cfg_tbl *dte)
1020 1073 return; return;
1021 1074 } }
1022 1075
1023 dte->tdep_count = 3;
1076 dte->tdep_cnt = 3;
1024 1077
1025 1078 for (i = 0; i < k; ++i) for (i = 0; i < k; ++i)
1026 1079 put_unaligned_be32((t_split[i] * (t_max - t_0/(u32)1000) put_unaligned_be32((t_split[i] * (t_max - t_0/(u32)1000)
File drivers/gpu/alga/amd/si/dyn_pm/smc_dte_cfg_tbl.h changed (mode: 100644) (index 933dfb4..cdd590b)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
9 void smc_dte_cfg_tbl_dump(struct smc_dte_cfg_tbl *tbl);
10 #endif
11
8 12 void smc_dte_cfg_tbl_init(struct ctx *ctx, struct smc_dte_cfg_tbl *dte); void smc_dte_cfg_tbl_init(struct ctx *ctx, struct smc_dte_cfg_tbl *dte);
9 13 #endif #endif
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index cc4bbea..0f2f653)
... ... struct smc_dte_cfg_tbl {
297 297 __be32 k; __be32 k;
298 298 __be32 t0; __be32 t0;
299 299 __be32 max_t; __be32 max_t;
300 u8 window_size;
300 u8 wnd_sz;
301 301 u8 temp_select; u8 temp_select;
302 302 u8 dte_mode; u8 dte_mode;
303 u8 tdep_count;
303 u8 tdep_cnt;
304 304 u8 t_limits[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX]; u8 t_limits[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX];
305 305 __be32 tdep_tau[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX]; __be32 tdep_tau[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX];
306 306 __be32 tdep_r[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX]; __be32 tdep_r[SMC_DTE_CFG_TBL_MAX_TEMP_DEPENDENT_ENTRIES_N_MAX];
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