sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
comestics and first fixes 784ed88cc10c159c57c923853bc8bd29238cc2c6 Sylvain BERTRAND 2014-02-04 17:01:06
tidy a bit a386d7d732466b07022622e8c763ebc608b9ab92 Sylvain BERTRAND 2014-02-03 17:40:52
cpy smc tbls to smc ram bc0860a37eec9cdf5962d4b9f9bb0c6981023587 Sylvain BERTRAND 2014-02-03 13:44:45
thermal regs programming 9a9ed598a7e8d9109a9ab23e90f3a94cb5c02e37 Sylvain BERTRAND 2014-01-31 14:22:12
eng clk pm and global pm switch to on a50fed4758305b9032d313cdf0021ec6a612d344 Sylvain BERTRAND 2014-01-31 12:54:41
send nodisplay msg to smc 91808e6c48d9d37da87f08da253825252122e4d9 Sylvain BERTRAND 2014-01-31 12:33:21
smc start 6c09abb37b34599c132f324359ce38d11888091f Sylvain BERTRAND 2014-01-31 12:03:10
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
tidy mc reg tbl 4761bf039ff2caf87c7eb139cf54c0f2e1932b60 Sylvain BERTRAND 2014-01-30 18:23:10
cpy cpu mem to smc mem 1b2deae0c86f878c72a40b2c4d07cdf308c3be11 Sylvain BERTRAND 2014-01-30 16:56:51
init of smc sw regs for response times af87f39cda6b64d7c5367ea4fa77899a55a0b9e0 Sylvain BERTRAND 2014-01-30 15:39:37
smc state dyn pm params init 66b37051c3927dfecc92d6d630c53ddf927c7d79 Sylvain BERTRAND 2014-01-30 11:11:05
init of smc cac cfg regs add98b596c10e16693171e04a7f9168232a1f65d Sylvain BERTRAND 2014-01-29 19:38:59
cosmestics ee91a7ee91132de107bef05de70a8ea28f89dddf Sylvain BERTRAND 2014-01-28 23:12:44
smc cac cfg tbl init and some cosmetics 823419aa67f2ad91afb08942112be28d59752435 Sylvain BERTRAND 2014-01-28 22:31:35
smc dte cfg tbl init f3689c3d9e04a3462acf5c3a3aaabbdbb5307580 Sylvain BERTRAND 2014-01-27 21:16:32
init the smc mc arb freq set e276bc781e0e1ec9f7550c9bc8ffdb8de253be8b Sylvain BERTRAND 2014-01-24 16:22:31
smc_eng_pll_tbl init 323df7359605e25ac08800ca960bd3eb2267bc87 Sylvain BERTRAND 2014-01-24 15:50:18
factor out enging pll params computation 0c99b244c1a699abca8493097a8b1f82299b6721 Sylvain BERTRAND 2014-01-24 14:25:57
Commit d5c198da094e7204b24d9879c5b0873dd36ee872 - smc_state_tbl dump code
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-04 19:12
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-04 19:12
Parent(s): 784ed88cc10c159c57c923853bc8bd29238cc2c6
Signing key:
Tree: e3c6df3d36babc04deedbfae4c50de7c21c6c263
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.c 33 0
drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.h 3 0
drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c 96 0
drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.h 3 0
drivers/gpu/alga/amd/si/dyn_pm/smc_mem_clk.c 44 0
drivers/gpu/alga/amd/si/dyn_pm/smc_mem_clk.h 4 0
drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c 89 0
drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c 14 0
drivers/gpu/alga/amd/si/dyn_pm/smc_volt.h 5 0
drivers/gpu/alga/amd/si/smc_tbls.h 4 4
File drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.c changed (mode: 100644) (index 6a68f45..d5a8908)
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37 37
38 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
39 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
40 void smc_eng_clk_dump(struct smc_eng_clk *tbl)
41 {
42 u32 tmp;
43
44 L("SMC_ENG_CLK START");
45
46 tmp = get_unaligned_be32(&tbl->cg_eng_pll_func_ctl_0);
47 L("cg_eng_pll_func_ctl_0=0x%08x",tmp);
48
49 tmp = get_unaligned_be32(&tbl->cg_eng_pll_func_ctl_1);
50 L("cg_eng_pll_func_ctl_1=0x%08x",tmp);
51
52 tmp = get_unaligned_be32(&tbl->cg_eng_pll_func_ctl_2);
53 L("cg_eng_pll_func_ctl_2=0x%08x",tmp);
54
55 tmp = get_unaligned_be32(&tbl->cg_eng_pll_func_ctl_3);
56 L("cg_eng_pll_func_ctl_3=0x%08x",tmp);
57
58 tmp = get_unaligned_be32(&tbl->cg_eng_pll_ss_0);
59 L("cg_eng_pll_ss_0=0x%08x",tmp);
60
61 tmp = get_unaligned_be32(&tbl->cg_eng_pll_ss_1);
62 L("cg_eng_pll_ss_1=0x%08x",tmp);
63
64 tmp = get_unaligned_be32(&tbl->clk);
65 L("clk=0x%08x",tmp);
66
67 L("SMC_ENG_CLK END");
68 }
69 #endif
70
38 71 long smc_eng_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl, long smc_eng_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
39 72 struct smc_lvl *smc_lvl) struct smc_lvl *smc_lvl)
40 73 { {
File drivers/gpu/alga/amd/si/dyn_pm/smc_eng_clk.h changed (mode: 100644) (index 359ae64..3aa74b9)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
9 void smc_eng_clk_dump(struct smc_eng_clk *tbl);
10 #endif
8 11 long smc_eng_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl, long smc_eng_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
9 12 struct smc_lvl *smc_lvl); struct smc_lvl *smc_lvl);
10 13 #endif #endif
File drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.c changed (mode: 100644) (index e448336..24fd721)
38 38 #include "smc_mem_clk.h" #include "smc_mem_clk.h"
39 39 #include "smc_volt.h" #include "smc_volt.h"
40 40
41 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
42 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
43 static void dpm_to_perf_lvl_dump(struct smc_pp_dpm_to_perf_lvl *tbl)
44 {
45 u16 tmp;
46 u8 i;
47
48 L("SMC_PP_DPM_TO_PERF_LVL START");
49 L("max_ps=0x%02x",tbl->max_ps);
50 L("tgt_act=0x%02x",tbl->tgt_act);
51 L("max_ps_step_inc=0x%02x",tbl->max_ps_step_inc);
52 L("max_ps_step_dec=0x%02x",tbl->max_ps_step_dec);
53 L("ps_sampling_time=0x%02x",tbl->near_tdp_dec);
54 L("above_safe_inc=0x%02x",tbl->above_safe_inc);
55 L("below_safe_inc=0x%02x",tbl->below_safe_inc);
56 L("ps_delta_limit=0x%02x",tbl->ps_delta_limit);
57 L("ps_delta_win=0x%02x",tbl->ps_delta_win);
58
59 tmp = get_unaligned_be16(&tbl->pwr_efficiency_ratio);
60 L("pwr_efficiency_ratio=0x%04x",tmp);
61
62 for (i = 0; i < 4; ++i)
63 L("rsvd[%u]=0x%02x",i,tbl->rsvd[i]);
64
65 L("SMC_PP_DPM_TO_PERF_LVL END");
66 }
67
68 void smc_lvl_dump(struct smc_lvl *lvl)
69 {
70 u32 tmp;
71
72 L("mc_reg_set_idx=0x%02x",lvl->mc_reg_set_idx);
73 L("disp_watermark=0x%02x",lvl->disp_watermark);
74 L("pcie_gen=0x%02x",lvl->pcie_gen);
75 L("uvd_watermark=0x%02x",lvl->uvd_watermark);
76 L("vce_watermark=0x%02x",lvl->vce_watermark);
77 L("strobe_mode=0x%02x",lvl->mc_flgs);
78 L("pad=0x%02x",lvl->pad);
79
80 tmp = get_unaligned_be32(&lvl->a_t);
81 L("a_t=0x%08x",tmp);
82
83 tmp = get_unaligned_be32(&lvl->b_sp);
84 L("b_sp=0x%08x",tmp);
85
86 smc_eng_clk_dump(&lvl->eng_clk);
87 smc_mem_clk_dump(&lvl->mem_clk);
88
89 L("SMC_VOLT VDDC START");
90 smc_volt_dump(&lvl->vddc);
91 L("SMC_VOLT VDDC END");
92
93 L("SMC_VOLT MVDD START");
94 smc_volt_dump(&lvl->mvdd);
95 L("SMC_VOLT MVDDC END");
96
97 L("SMC_VOLT VDDCI START");
98 smc_volt_dump(&lvl->vddci);
99 L("SMC_VOLT VDDCI END");
100
101 L("SMC_VOLT STD_VDDC START");
102 smc_volt_dump(&lvl->std_vddc);
103 L("SMC_VOLT STD_VDDC END");
104
105 L("hysteresis_up=0x%02x",lvl->hysteresis_up);
106 L("hysteresis_down=0x%02x",lvl->hysteresis_down);
107 L("state_flgs=0x%02x",lvl->state_flgs);
108 L("mc_arb_set_idx=0x%02x",lvl->mc_arb_set_idx);
109
110 tmp = get_unaligned_be32(&lvl->sq_pwr_throttle_0);
111 L("sq_pwr_throttle_0=0x%08x",tmp);
112
113 tmp = get_unaligned_be32(&lvl->sq_pwr_throttle_1);
114 L("sq_pwr_throttle_1=0x%08x",tmp);
115
116 tmp = get_unaligned_be32(&lvl->cus_n_max);
117 L("cus_n_max=0x%08x",tmp);
118
119 L("SMC_VOLT HIGH_TEMP_VDDC START");
120 smc_volt_dump(&lvl->high_temp_vddc);
121 L("SMC_VOLT HIGH_TEMP_VDDC END");
122
123 L("SMC_VOLT LOW_TEMP_VDDC START");
124 smc_volt_dump(&lvl->low_temp_vddc);
125 L("SMC_VOLT LOW_TEMP_VDDC END");
126
127 tmp = get_unaligned_be32(&lvl->rsvd[0]);
128 L("rsvd[0]=0x%08x",tmp);
129
130 tmp = get_unaligned_be32(&lvl->rsvd[1]);
131 L("rsvd[1]=0x%08x",tmp);
132
133 dpm_to_perf_lvl_dump(&lvl->dpm_to_perf_lvl);
134 }
135 #endif
136
41 137 /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
42 138 /* only for gddr5 */ /* only for gddr5 */
43 139 static u8 gddr5_mem_clk_freq_ratio_compute(u32 mem_clk, u8 strobe_mode) static u8 gddr5_mem_clk_freq_ratio_compute(u32 mem_clk, u8 strobe_mode)
File drivers/gpu/alga/amd/si/dyn_pm/smc_lvl.h changed (mode: 100644) (index 5a7b0aa..6ff301f)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
9 void smc_lvl_dump(struct smc_lvl *lvl);
10 #endif
8 11 u8 gddr5_strobe_mode_compute(struct ctx *ctx, u32 mem_clk); u8 gddr5_strobe_mode_compute(struct ctx *ctx, u32 mem_clk);
9 12 long smc_lvl_from_atb(struct ctx *ctx, struct atb_pp_lvl *atb_lvl, long smc_lvl_from_atb(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
10 13 struct smc_lvl *smc_lvl); struct smc_lvl *smc_lvl);
File drivers/gpu/alga/amd/si/dyn_pm/smc_mem_clk.c changed (mode: 100644) (index 1294ace..8baa264)
35 35 #include "ctx.h" #include "ctx.h"
36 36 #include "private.h" #include "private.h"
37 37
38 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
39 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
40 void smc_mem_clk_dump(struct smc_mem_clk *tbl)
41 {
42 u32 tmp;
43
44 L("SMC_MEM_CLK START");
45
46 tmp = get_unaligned_be32(&tbl->mem_pll_func_ctl_0);
47 L("mem_pll_func_ctl_0=0x%08x",tmp);
48
49 tmp = get_unaligned_be32(&tbl->mem_pll_func_ctl_1);
50 L("mem_pll_func_ctl_1=0x%08x",tmp);
51
52 tmp = get_unaligned_be32(&tbl->mem_pll_func_ctl_2);
53 L("mem_pll_func_ctl_2=0x%08x",tmp);
54
55 tmp = get_unaligned_be32(&tbl->mem_pll_ad_func_ctl);
56 L("mem_pll_ad_func_ctl=0x%08x",tmp);
57
58 tmp = get_unaligned_be32(&tbl->mem_pll_dq_func_ctl);
59 L("mem_pll_dq_func_ctl=0x%08x",tmp);
60
61 tmp = get_unaligned_be32(&tbl->mem_clk_pm_ctl);
62 L("mem_clk_pm_ctl=0x%08x",tmp);
63
64 tmp = get_unaligned_be32(&tbl->dll_ctl);
65 L("dll_ctl=0x%08x",tmp);
66
67 tmp = get_unaligned_be32(&tbl->mem_pll_ss_0);
68 L("mem_pll_ss_0=0x%08x",tmp);
69
70 tmp = get_unaligned_be32(&tbl->mem_pll_ss_1);
71 L("mem_pll_ss_1=0x%08x",tmp);
72
73 tmp = get_unaligned_be32(&tbl->clk);
74 L("clk=0x%08x",tmp);
75
76 L("cg_eng_pll_func_ctl_0=0x%08x",tmp);
77
78 L("SMC_MEM_CLK END");
79 }
80 #endif
81
38 82 #define STUTER_DISPLAYS_N_MAX 2 #define STUTER_DISPLAYS_N_MAX 2
39 83 void smc_mem_clk_displays_adjust(struct ctx *ctx, struct smc_lvl *smc_lvl, void smc_mem_clk_displays_adjust(struct ctx *ctx, struct smc_lvl *smc_lvl,
40 84 u8 displays_n) u8 displays_n)
File drivers/gpu/alga/amd/si/dyn_pm/smc_mem_clk.h changed (mode: 100644) (index e768ffa..3d4e325)
5 5 Protected by GNU Affero GPL v3 with some exceptions. Protected by GNU Affero GPL v3 with some exceptions.
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
9 void smc_mem_clk_dump(struct smc_mem_clk *tbl);
10 #endif
11
8 12 void smc_mem_clk_displays_adjust(struct ctx *ctx, struct smc_lvl *smc_lvl, void smc_mem_clk_displays_adjust(struct ctx *ctx, struct smc_lvl *smc_lvl,
9 13 u8 displays_n); u8 displays_n);
10 14 long smc_mem_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl, long smc_mem_clk_from_atb_pp(struct ctx *ctx, struct atb_pp_lvl *atb_lvl,
File drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c changed (mode: 100644) (index 1aede83..eb331ed)
38 38 #include "emergency.h" #include "emergency.h"
39 39 #include "ulv.h" #include "ulv.h"
40 40
41 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
42 #include "smc_lvl.h"
43 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
44 static void smc_sw_state_dump(struct smc_sw_state *state)
45 {
46 L("flgs=0x%02x",state->flgs);
47 L("lvls_n=0x%02x",state->lvls_n);
48 L("pad2=0x%02x",state->pad2);
49 L("pad3=0x%02x",state->pad3);
50 }
51
52 void smc_state_tbl_dump(struct smc_state_tbl *tbl)
53 {
54 u32 i;
55 u32 tmp;
56
57 L("SMC_STATE_TBL START");
58 L("thermal_protection_type=0x%02x",tbl->thermal_protection_type);
59 L("system_flgs=0x%02x",tbl->system_flgs);
60 L("max_vddc_idx=0x%02x",tbl->max_vddc_idx);
61 L("extra_flgs=0x%02x",tbl->extra_flgs);
62
63 for (i = 0; i < SMC_VREG_STEPS_N_MAX; ++i) {
64 u32 smio_low;
65 smio_low = get_unaligned_be32(&tbl->smio_low[i]);
66 L("smio_low[%u]=0x%08x",i,smio_low);
67 }
68
69 for (i = 0; i < SMC_VOLT_MASKS_N_MAX; ++i) {
70 u32 mask_low;
71 mask_low = get_unaligned_be32(&tbl->volt_mask_tbl.mask_low[i]);
72 L("volt_mask_tbl.mask_low[%u]=0x%08x",i,mask_low);
73 }
74
75 for (i = 0; i < SMC_VOLT_MASKS_N_MAX; ++i) {
76 u32 mask_low;
77 mask_low = get_unaligned_be32(&tbl->phase_mask_tbl.mask_low[i]);
78 L("phase_mask_tbl.mask_low[%u]=0x%08x",i,mask_low);
79 }
80
81 tmp = get_unaligned_be32(&tbl->dyn_pm_params.tdp_limit);
82 L("dyn_pm_params.tdp_limit=0x%08x\n",tmp);
83 tmp = get_unaligned_be32(&tbl->dyn_pm_params.near_tdp_limit);
84 L("dyn_pm_params.near_tdp_limit=0x%08x\n",tmp);
85 tmp = get_unaligned_be32(&tbl->dyn_pm_params.safe_pwr_limit);
86 L("dyn_pm_params.safe_pwr_limit=0x%08x\n",tmp);
87 tmp = get_unaligned_be32(&tbl->dyn_pm_params.pwrboost_limit);
88 L("dyn_pm_params.pwrboost_limit=0x%08x\n",tmp);
89 tmp = get_unaligned_be32(&tbl->dyn_pm_params.min_limit_delta);
90 L("dyn_pm_params.min_limit_delta=0x%08x\n",tmp);
91
92 L("SMC_SW_STATE INITIAL START");
93 smc_sw_state_dump(&tbl->initial);
94 L("SMC_SW_STATE INITIAL END");
95
96 L("SMC_LVL[0] INITIAL START");
97 smc_lvl_dump(&tbl->initial_lvl);
98 L("SMC_LVL[0] INITIAL END");
99
100 L("SMC_SW_STATE EMERGENCY START");
101 smc_sw_state_dump(&tbl->emergency);
102 L("SMC_SW_STATE EMERGENCY END");
103
104 L("SMC_LVL[0] EMERGENCY START");
105 smc_lvl_dump(&tbl->emergency_lvl);
106 L("SMC_LVL[0] EMERGENCY END");
107
108 L("SMC_SW_STATE ULV START");
109 smc_sw_state_dump(&tbl->ulv);
110 L("SMC_SW_STATE ULV END");
111
112 L("SMC_LVL[0] ULV START");
113 smc_lvl_dump(&tbl->ulv_lvl);
114 L("SMC_LVL[0] ULV END");
115
116 L("SMC_SW_STATE DRIVER START");
117 smc_sw_state_dump(&tbl->driver);
118 L("SMC_SW_STATE DRIVER END");
119
120 for (i = 0; i < tbl->driver.lvls_n; ++i) {
121 L("SMC_LVL[%u] DRIVER START", i);
122 smc_lvl_dump(&tbl->driver_lvls[i]);
123 L("SMC_LVL[%u] DRIVER END", i);
124 }
125
126 L("SMC_STATE_TBL END");
127 }
128 #endif
129
41 130 static void smc_vddc_tbl_init(struct ctx *ctx, static void smc_vddc_tbl_init(struct ctx *ctx,
42 131 struct smc_state_tbl *smc_state_tbl) struct smc_state_tbl *smc_state_tbl)
43 132 { {
File drivers/gpu/alga/amd/si/dyn_pm/smc_volt.c changed (mode: 100644) (index 39f0498..2e92109)
36 36 #include "private.h" #include "private.h"
37 37 #include "smc_volt.h" #include "smc_volt.h"
38 38
39 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
40 #define L(fmt,...) printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
41 void smc_volt_dump(struct smc_volt *tbl)
42 {
43 u16 tmp;
44
45 tmp = get_unaligned_be16(&tbl->val);
46 L("val=0x%04x",tmp);
47
48 L("step_idx=0x%02x",tbl->step_idx);
49 L("phase_settings=0x%02x",tbl->phase_settings);
50 }
51 #endif
52
39 53 static long volt_step_idx(struct atb_volt_tbl *tbl, u16 val_mv) static long volt_step_idx(struct atb_volt_tbl *tbl, u16 val_mv)
40 54 { {
41 55 u8 step; u8 step;
File drivers/gpu/alga/amd/si/dyn_pm/smc_volt.h changed (mode: 100644) (index 919a608..76ba293)
6 6 See README at root of alga tree. See README at root of alga tree.
7 7 */ */
8 8 #define IS_VDDC_LKGE_IDX(x) (((x) & 0xff00) == 0xff00) #define IS_VDDC_LKGE_IDX(x) (((x) & 0xff00) == 0xff00)
9
10 #ifdef CONFIG_ALGA_AMD_SI_DYN_PM_LOG
11 void smc_volt_dump(struct smc_volt *tbl);
12 #endif
13
9 14 long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc, long smc_volt_vddc_set_from_atb_id(struct ctx *ctx, struct smc_volt *vddc,
10 15 u32 vddc_id); u32 vddc_id);
11 16 long smc_volt_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_volt *vddc, long smc_volt_vddc_set_from_atb_mv(struct ctx *ctx, struct smc_volt *vddc,
File drivers/gpu/alga/amd/si/smc_tbls.h changed (mode: 100644) (index 893b64b..cc4bbea)
... ... struct smc_volt_mask_tbl {
168 168 #define SMC_VREG_STEPS_N_MAX 32 #define SMC_VREG_STEPS_N_MAX 32
169 169 #define SMC_SW_STATE_LVLS_N_MAX 16 #define SMC_SW_STATE_LVLS_N_MAX 16
170 170 struct smc_state_tbl { struct smc_state_tbl {
171 u8 thermal_protection_type;
172 u8 system_flgs;
173 u8 max_vddc_idx;
174 u8 extra_flgs;
171 u8 thermal_protection_type;
172 u8 system_flgs;
173 u8 max_vddc_idx;
174 u8 extra_flgs;
175 175 __be32 smio_low[SMC_VREG_STEPS_N_MAX]; __be32 smio_low[SMC_VREG_STEPS_N_MAX];
176 176 struct smc_volt_mask_tbl volt_mask_tbl; struct smc_volt_mask_tbl volt_mask_tbl;
177 177 struct smc_volt_mask_tbl phase_mask_tbl; struct smc_volt_mask_tbl phase_mask_tbl;
Hints:
Before first commit, do not forget to setup your git environment:
git config --global user.name "your_name_here"
git config --global user.email "your@email_here"

Clone this repository using HTTP(S):
git clone https://rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using ssh (do not forget to upload a key first):
git clone ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si

Clone this repository using git:
git clone git://git.rocketgit.com/user/sylware/linux-gpu-amd-si

You are allowed to anonymously push to this repository.
This means that your pushed commits will automatically be transformed into a merge request:
... clone the repository ...
... make some changes and some commits ...
git push origin main