sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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master
List of commits:
Subject Hash Author Date (UTC)
log more 5018f3c130cb9ce53e1834fcc586f00614a3ed86 Sylvain BERTRAND 2014-02-04 21:46:05
smc sw regs dump code 46acefa1d42984757cb1ba48a32130f2f9674687 Sylvain BERTRAND 2014-02-04 20:44:26
do dump the tbls c79209766b71e2d3231cf25673684762bf46dd8c Sylvain BERTRAND 2014-02-04 20:20:33
mc_dte_cfg_tbl dump code 46dcab9ac217dbf29a1295622587e083f161b677 Sylvain BERTRAND 2014-02-04 20:11:45
mc_eng_pll_tbl dump code 7906ec9bfacb86dd4a11bbbb2a71d33e4f3f85e7 Sylvain BERTRAND 2014-02-04 19:57:40
mc_mc_arb_tbl dump code 50faaa9b589277e1707ea2d3964731a400932654 Sylvain BERTRAND 2014-02-04 19:51:01
mc_mc_reg_tbl dump code af3826d3878248194a46cf3fda7dc2c503f8948b Sylvain BERTRAND 2014-02-04 19:40:11
mc_cac_cfg_tbl dump code 5b2ab4803a9053f36cf378a64c27f237c2c2bf0b Sylvain BERTRAND 2014-02-04 19:25:10
smc_state_tbl dump code d5c198da094e7204b24d9879c5b0873dd36ee872 Sylvain BERTRAND 2014-02-04 19:12:13
comestics and first fixes 784ed88cc10c159c57c923853bc8bd29238cc2c6 Sylvain BERTRAND 2014-02-04 17:01:06
tidy a bit a386d7d732466b07022622e8c763ebc608b9ab92 Sylvain BERTRAND 2014-02-03 17:40:52
cpy smc tbls to smc ram bc0860a37eec9cdf5962d4b9f9bb0c6981023587 Sylvain BERTRAND 2014-02-03 13:44:45
thermal regs programming 9a9ed598a7e8d9109a9ab23e90f3a94cb5c02e37 Sylvain BERTRAND 2014-01-31 14:22:12
eng clk pm and global pm switch to on a50fed4758305b9032d313cdf0021ec6a612d344 Sylvain BERTRAND 2014-01-31 12:54:41
send nodisplay msg to smc 91808e6c48d9d37da87f08da253825252122e4d9 Sylvain BERTRAND 2014-01-31 12:33:21
smc start 6c09abb37b34599c132f324359ce38d11888091f Sylvain BERTRAND 2014-01-31 12:03:10
tidy mc reg tbl and mc arb reg tbl 10c88c7898f027e114846f253262e6631a44f5eb Sylvain BERTRAND 2014-01-30 18:42:13
tidy mc reg tbl 4761bf039ff2caf87c7eb139cf54c0f2e1932b60 Sylvain BERTRAND 2014-01-30 18:23:10
cpy cpu mem to smc mem 1b2deae0c86f878c72a40b2c4d07cdf308c3be11 Sylvain BERTRAND 2014-01-30 16:56:51
init of smc sw regs for response times af87f39cda6b64d7c5367ea4fa77899a55a0b9e0 Sylvain BERTRAND 2014-01-30 15:39:37
Commit 5018f3c130cb9ce53e1834fcc586f00614a3ed86 - log more
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-04 21:46
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-04 21:46
Parent(s): 46acefa1d42984757cb1ba48a32130f2f9674687
Signer:
Signing key:
Signing status: N
Tree: 1e2a875a5c7e89fc88f925ada6f173455d911f0b
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c 17 10
drivers/gpu/alga/amd/si/dyn_pm/smc_cac_cfg_regs.c 6 0
drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c 5 5
File drivers/gpu/alga/amd/si/dyn_pm/dyn_pm.c changed (mode: 100644) (index d786721..37a7430)
... ... static void general_thermal_protection_dis(struct pci_dev *dev)
256 256
257 257 static void b_sp_program(struct ctx *ctx) static void b_sp_program(struct ctx *ctx)
258 258 { {
259 LOG("b_sp programming");
259 LOG("b_sp programming, CG_B_SP=0x%08x", ctx->d_sp);
260 260
261 261 wr32(ctx->dev, ctx->d_sp, CG_B_SP); wr32(ctx->dev, ctx->d_sp, CG_B_SP);
262 262 } }
 
... ... static void git_program(struct pci_dev *dev)
266 266 { {
267 267 u32 cg_git; u32 cg_git;
268 268
269 LOG("git programming");
270
271 269 cg_git = rr32(dev, CG_GIT); cg_git = rr32(dev, CG_GIT);
272 270 cg_git &= ~CG_GICST; cg_git &= ~CG_GICST;
273 271 cg_git |= set(CG_GICST, GICST_DEFAULT); cg_git |= set(CG_GICST, GICST_DEFAULT);
272
273 LOG("git programming CG_GIT=0x%08x", cg_git);
274 274 wr32(dev, cg_git, CG_GIT); wr32(dev, cg_git, CG_GIT);
275 275 } }
276 276
 
... ... static void tp_program(struct pci_dev *dev)
366 366 if (td == TD_AUTO) { if (td == TD_AUTO) {
367 367 eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL); eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL);
368 368 eng_clk_pm_ctl &= ~ECPC_FIR_FORCE_TREND_SEL; eng_clk_pm_ctl &= ~ECPC_FIR_FORCE_TREND_SEL;
369 LOG("TD_AUTO, ENG_CLK_PM_CTL=0x%08x",eng_clk_pm_ctl);
369 370 wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL); wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL);
370 371 } else { } else {
371 372 eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL); eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL);
372 373 eng_clk_pm_ctl |= ECPC_FIR_FORCE_TREND_SEL; eng_clk_pm_ctl |= ECPC_FIR_FORCE_TREND_SEL;
374 LOG("!TD_AUTO, ENG_CLK_PM_CTL=0x%08x",eng_clk_pm_ctl);
373 375 wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL); wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL);
374 376 } }
375 377
376 378 if (td == TD_UP) { if (td == TD_UP) {
377 379 eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL); eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL);
378 380 eng_clk_pm_ctl &= ~ECPC_FIR_TREND_MODE; eng_clk_pm_ctl &= ~ECPC_FIR_TREND_MODE;
381 LOG("TD_UP,=0x%08x",eng_clk_pm_ctl);
379 382 wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL); wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL);
380 383 } else if (td == TD_DOWN) { } else if (td == TD_DOWN) {
381 384 eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL); eng_clk_pm_ctl = rr32(dev, ENG_CLK_PM_CTL);
382 385 eng_clk_pm_ctl |= ECPC_FIR_TREND_MODE; eng_clk_pm_ctl |= ECPC_FIR_TREND_MODE;
386 LOG("!TD_UP,=0x%08x",eng_clk_pm_ctl);
383 387 wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL); wr32(dev, eng_clk_pm_ctl, ENG_CLK_PM_CTL);
384 388 } }
385 389 } }
 
... ... static void tp_program(struct pci_dev *dev)
388 392 #define TPC_DEFAULT 0x200 #define TPC_DEFAULT 0x200
389 393 static void tpp_program(struct pci_dev *dev) static void tpp_program(struct pci_dev *dev)
390 394 { {
391 LOG("tpp programming");
395 LOG("tpp programming CG_TPC=0x%08x",TPC_DEFAULT);
392 396
393 397 wr32(dev, TPC_DEFAULT, CG_TPC); wr32(dev, TPC_DEFAULT, CG_TPC);
394 398 } }
 
... ... static void tpp_program(struct pci_dev *dev)
397 401 #define SSTP_SST_DEFAULT 0x00c8 #define SSTP_SST_DEFAULT 0x00c8
398 402 static void sstp_program(struct pci_dev *dev) static void sstp_program(struct pci_dev *dev)
399 403 { {
400 LOG("sstp programming");
404 LOG("sstp programming CG_SSP=0x%08x", set(CS_SSTU, SSTP_SSTU_DEFAULT)
405 | set(CS_SST, SSTP_SST_DEFAULT));
401 406
402 407 wr32(dev, set(CS_SSTU, SSTP_SSTU_DEFAULT) wr32(dev, set(CS_SSTU, SSTP_SSTU_DEFAULT)
403 408 | set(CS_SST, SSTP_SST_DEFAULT), CG_SSP); | set(CS_SST, SSTP_SST_DEFAULT), CG_SSP);
 
... ... static void display_gap_ena(struct pci_dev *dev)
411 416 { {
412 417 u32 cg_disp_gap_ctl; u32 cg_disp_gap_ctl;
413 418
414 LOG("display gap programming");
415
416 419 cg_disp_gap_ctl = rr32(dev, CG_DISP_GAP_CTL); cg_disp_gap_ctl = rr32(dev, CG_DISP_GAP_CTL);
417 420
418 421 cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP | CDGC_DISP2_GAP); cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP | CDGC_DISP2_GAP);
 
... ... static void display_gap_ena(struct pci_dev *dev)
422 425 cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP_MCHG | CDGC_DISP2_GAP_MCHG); cg_disp_gap_ctl &= ~(CDGC_DISP1_GAP_MCHG | CDGC_DISP2_GAP_MCHG);
423 426 cg_disp_gap_ctl |= set(CDGC_DISP1_GAP_MCHG, DISP_GAP_VBLANK) cg_disp_gap_ctl |= set(CDGC_DISP1_GAP_MCHG, DISP_GAP_VBLANK)
424 427 | set(CDGC_DISP2_GAP_MCHG, DISP_GAP_IGNORE); | set(CDGC_DISP2_GAP_MCHG, DISP_GAP_IGNORE);
428 LOG("display gap programming CG_DISP_GAP_CTL=0x%08x",cg_disp_gap_ctl);
425 429 wr32(dev, cg_disp_gap_ctl, CG_DISP_GAP_CTL); wr32(dev, cg_disp_gap_ctl, CG_DISP_GAP_CTL);
426 430 } }
427 431
428 432 #define VRC_DEFAULT 0xc000b3 #define VRC_DEFAULT 0xc000b3
429 433 static void vc_program(struct pci_dev *dev) static void vc_program(struct pci_dev *dev)
430 434 { {
431 LOG("vc programming");
435 LOG("vc programming CG_FTV=0x%08x",VRC_DEFAULT);
432 436
433 437 wr32(dev, VRC_DEFAULT, CG_FTV); wr32(dev, VRC_DEFAULT, CG_FTV);
434 438 } }
 
... ... static void cac_wnd_set(struct pci_dev *dev)
558 562 u32 cg_cac_ctl; u32 cg_cac_ctl;
559 563 struct pwrtune *pwrtune; struct pwrtune *pwrtune;
560 564
561 LOG("setting calculation accumulator window");
562
563 565 cg_cac_ctl = rr32(dev, CG_CAC_CTL); cg_cac_ctl = rr32(dev, CG_CAC_CTL);
564 566 cg_cac_ctl &= ~CCC_CAC_WND; cg_cac_ctl &= ~CCC_CAC_WND;
565 567 pwrtune = pwrtune_get(dev); pwrtune = pwrtune_get(dev);
 
... ... static void ds_ena(struct pci_dev *dev)
578 580 misc_clk_ctl = rr32(dev, MISC_CLK_CTL); misc_clk_ctl = rr32(dev, MISC_CLK_CTL);
579 581 misc_clk_ctl &= ~MCC_DEEP_SLEEP_CLK_SEL; misc_clk_ctl &= ~MCC_DEEP_SLEEP_CLK_SEL;
580 582 misc_clk_ctl |= set(MCC_DEEP_SLEEP_CLK_SEL, 1); misc_clk_ctl |= set(MCC_DEEP_SLEEP_CLK_SEL, 1);
583 LOG("MISC_CLK_CTL=0x%08x",misc_clk_ctl);
581 584 wr32(dev, misc_clk_ctl, MISC_CLK_CTL); wr32(dev, misc_clk_ctl, MISC_CLK_CTL);
582 585
583 586 cg_eng_pll_autoscale_ctl = rr32(dev, CG_ENG_PLL_AUTOSCALE_CTL); cg_eng_pll_autoscale_ctl = rr32(dev, CG_ENG_PLL_AUTOSCALE_CTL);
584 587 cg_eng_pll_autoscale_ctl |= CEPAC_AUTOSCALE_ON_SS_CLR; cg_eng_pll_autoscale_ctl |= CEPAC_AUTOSCALE_ON_SS_CLR;
588 LOG("CG_ENG_PLL_AUTOSCALE_CTL=0x%08x",cg_eng_pll_autoscale_ctl);
585 589 wr32(dev, cg_eng_pll_autoscale_ctl, CG_ENG_PLL_AUTOSCALE_CTL); wr32(dev, cg_eng_pll_autoscale_ctl, CG_ENG_PLL_AUTOSCALE_CTL);
586 590 } }
587 591
 
... ... static void thermal_evt_src_set_digital(struct pci_dev *dev)
674 678 cg_thermal_ctl = rr32(dev, CG_THERMAL_CTL); cg_thermal_ctl = rr32(dev, CG_THERMAL_CTL);
675 679 cg_thermal_ctl &= ~CTC_DYN_PM_EVT_SRC; cg_thermal_ctl &= ~CTC_DYN_PM_EVT_SRC;
676 680 cg_thermal_ctl |= set(CTC_DYN_PM_EVT_SRC, CTC_EVT_SRC_DIGITAL); cg_thermal_ctl |= set(CTC_DYN_PM_EVT_SRC, CTC_EVT_SRC_DIGITAL);
681 LOG("CG_THERMAL_CTL=0x%08x",cg_thermal_ctl);
677 682 wr32(dev, cg_thermal_ctl, CG_THERMAL_CTL); wr32(dev, cg_thermal_ctl, CG_THERMAL_CTL);
678 683 } }
679 684
 
... ... static void thermal_temp_rng_set(struct pci_dev *dev)
690 695 cg_thermal_int &= ~(CTI_TEMP_LOW | CTI_TEMP_HIGH); cg_thermal_int &= ~(CTI_TEMP_LOW | CTI_TEMP_HIGH);
691 696 cg_thermal_int |= set(CTI_TEMP_LOW, TEMP_LOW); cg_thermal_int |= set(CTI_TEMP_LOW, TEMP_LOW);
692 697 cg_thermal_int |= set(CTI_TEMP_HIGH, TEMP_HIGH); cg_thermal_int |= set(CTI_TEMP_HIGH, TEMP_HIGH);
698 LOG("CG_THERMAL_INT=0x%08x",cg_thermal_int);
693 699 wr32(dev, cg_thermal_int, CG_THERMAL_INT); wr32(dev, cg_thermal_int, CG_THERMAL_INT);
694 700
695 701 cg_thermal_ctl = rr32(dev, CG_THERMAL_CTL); cg_thermal_ctl = rr32(dev, CG_THERMAL_CTL);
696 702 cg_thermal_ctl &= ~CTC_DYN_PM_DIGITAL_TEMP_HIGH; cg_thermal_ctl &= ~CTC_DYN_PM_DIGITAL_TEMP_HIGH;
697 703 cg_thermal_ctl |= set(CTC_DYN_PM_DIGITAL_TEMP_HIGH, TEMP_HIGH); cg_thermal_ctl |= set(CTC_DYN_PM_DIGITAL_TEMP_HIGH, TEMP_HIGH);
704 LOG("CG_THERMAL_CTL=0x%08x",cg_thermal_ctl);
698 705 wr32(dev, cg_thermal_ctl, CG_THERMAL_CTL); wr32(dev, cg_thermal_ctl, CG_THERMAL_CTL);
699 706 } }
700 707
File drivers/gpu/alga/amd/si/dyn_pm/smc_cac_cfg_regs.c changed (mode: 100644) (index 6956e6a..c419f49)
... ... void regs_wr(struct pci_dev *dev, struct reg *r)
1234 1234 val &= ~r->mask; val &= ~r->mask;
1235 1235 val |= ((r->val << r->shift) & r->mask); val |= ((r->val << r->shift) & r->mask);
1236 1236
1237 LOG("of=0x%08x val=0x%08x",r_of,val);
1237 1238 smc_w32(dev, r_of, val); smc_w32(dev, r_of, val);
1238 1239 ++r; ++r;
1239 1240 } }
 
... ... void smc_cac_cfg_regs_init(struct pci_dev *dev)
1249 1250 lcac = lcac_get(dev); lcac = lcac_get(dev);
1250 1251 cac_weights = cac_weights_get(dev); cac_weights = cac_weights_get(dev);
1251 1252
1253 LOG("LCAC REGS START");
1252 1254 regs_wr(dev, lcac); regs_wr(dev, lcac);
1255 LOG("LCAC REGS END");
1256
1257 LOG("CAC_WEIGHTS REGS START");
1253 1258 regs_wr(dev, cac_weights); regs_wr(dev, cac_weights);
1259 LOG("CAC_WEIGHTS REGS END");
1254 1260 } }
File drivers/gpu/alga/amd/si/dyn_pm/smc_state_tbl.c changed (mode: 100644) (index eb331ed..925c8ea)
... ... void smc_state_tbl_dump(struct smc_state_tbl *tbl)
79 79 } }
80 80
81 81 tmp = get_unaligned_be32(&tbl->dyn_pm_params.tdp_limit); tmp = get_unaligned_be32(&tbl->dyn_pm_params.tdp_limit);
82 L("dyn_pm_params.tdp_limit=0x%08x\n",tmp);
82 L("dyn_pm_params.tdp_limit=0x%08x",tmp);
83 83 tmp = get_unaligned_be32(&tbl->dyn_pm_params.near_tdp_limit); tmp = get_unaligned_be32(&tbl->dyn_pm_params.near_tdp_limit);
84 L("dyn_pm_params.near_tdp_limit=0x%08x\n",tmp);
84 L("dyn_pm_params.near_tdp_limit=0x%08x",tmp);
85 85 tmp = get_unaligned_be32(&tbl->dyn_pm_params.safe_pwr_limit); tmp = get_unaligned_be32(&tbl->dyn_pm_params.safe_pwr_limit);
86 L("dyn_pm_params.safe_pwr_limit=0x%08x\n",tmp);
86 L("dyn_pm_params.safe_pwr_limit=0x%08x",tmp);
87 87 tmp = get_unaligned_be32(&tbl->dyn_pm_params.pwrboost_limit); tmp = get_unaligned_be32(&tbl->dyn_pm_params.pwrboost_limit);
88 L("dyn_pm_params.pwrboost_limit=0x%08x\n",tmp);
88 L("dyn_pm_params.pwrboost_limit=0x%08x",tmp);
89 89 tmp = get_unaligned_be32(&tbl->dyn_pm_params.min_limit_delta); tmp = get_unaligned_be32(&tbl->dyn_pm_params.min_limit_delta);
90 L("dyn_pm_params.min_limit_delta=0x%08x\n",tmp);
90 L("dyn_pm_params.min_limit_delta=0x%08x",tmp);
91 91
92 92 L("SMC_SW_STATE INITIAL START"); L("SMC_SW_STATE INITIAL START");
93 93 smc_sw_state_dump(&tbl->initial); smc_sw_state_dump(&tbl->initial);
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