sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
upstream confirm bug, fixed e2142c3fdfc01d51e7fec7687ec4d02f548ce763 Sylvain BERTRAND 2014-02-18 16:10:14
mainly bug fixing 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf Sylvain BERTRAND 2014-02-18 12:46:40
dump smc sw regs 5b42263039c858624ff411d94318f6ef5171a864 Sylvain BERTRAND 2014-02-17 12:22:26
disable switch to low power when no display 69f94e04ea89c1fe9ccaef153da5f5ade232c2a1 Sylvain BERTRAND 2014-02-17 09:59:28
finish smc switch to driver power state 6f99d0a01491dd671174919d842a771ac4a81a4b Sylvain BERTRAND 2014-02-17 09:47:02
pcie things and follow upstream for dyn pm init f4fb120597276a3badc08eec30783b10d111f756 Sylvain BERTRAND 2014-02-17 09:00:00
dump performance state tbls 06a22756b504ecf4523c86f657104e0b970195de Sylvain BERTRAND 2014-02-14 17:02:23
smc_mc_arb_tbl init for the driver state 5d1868e75b11164dbb97caaddbc7992b252ab973 Sylvain BERTRAND 2014-02-14 13:01:26
smc_mc_reg tbl init for the driver state e8aa12b1c87571031098c4427822733a74133afc Sylvain BERTRAND 2014-02-14 11:32:04
installation of the perf pwr state continued 535c853e7d0a0ab04fbff3b0d5613ef9a34d525c Sylvain BERTRAND 2014-02-13 19:16:33
installation of the perf pwr state continued b229eef2798acbe053aa09e47c213e23749638dd Sylvain BERTRAND 2014-02-13 10:48:02
dyn pm second part continuation 95dd7b4754476a014d8f84854e5b2ce5c81d23b4 Sylvain BERTRAND 2014-02-12 20:15:03
beginning of dyn pm second part c32c19d884dbf1f440480bbea42140e9c5ed8cd3 Sylvain BERTRAND 2014-02-12 14:44:04
uvd does only mpeg, then switch off 7e36b98bcab47e9986a63093dbeed98ab290f85f Sylvain BERTRAND 2014-02-12 10:55:54
bug fixing, end of dyn pm first part 533a4bd6731205f71704886e5fa099063be985ea Sylvain BERTRAND 2014-02-11 13:49:27
bug fixing c3fc0d7b807c98d20c13f53dcfc09713309ad2fa Sylvain BERTRAND 2014-02-11 11:16:00
static bios tbls *must* be ok e050fa94c2f1e846bb051748347332e234a6b93a Sylvain BERTRAND 2014-02-10 10:17:33
bug fixing 7baa7069aa89a98d831d7def358766155771e9ca Sylvain BERTRAND 2014-02-07 15:08:53
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
tbls fixes 4795a3090a17bc486056301bc6bef509b9c5e339 Sylvain BERTRAND 2014-02-05 15:09:41
Commit e2142c3fdfc01d51e7fec7687ec4d02f548ce763 - upstream confirm bug, fixed
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-18 16:10
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-18 16:10
Parent(s): 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf
Signing key:
Tree: 8efc8f052b43e47a5b17e96e839f0882a396dcb9
File Lines added Lines deleted
drivers/gpu/alga/amd/si/dyn_pm/driver.c 0 8
File drivers/gpu/alga/amd/si/dyn_pm/driver.c changed (mode: 100644) (index df25f2b..c99a9dc)
... ... static void sq_ramping_threshold_init(struct ctx *ctx, u8 lvl_idx,
140 140 u32 sq_pwr_throttle_0; u32 sq_pwr_throttle_0;
141 141 u32 sq_pwr_throttle_1; u32 sq_pwr_throttle_1;
142 142
143 #if 0
144 It seems sq ramping threshold is disabled for good on SI. Told upstream, waiting
145 for feedback. Because of SQ_RAMPING_LTI_RATIO and SPT1_LTI_RATIO mask values on
146 SI.
147 143 if (ctx->atb_performance.lvls[lvl_idx].eng_clk >= if (ctx->atb_performance.lvls[lvl_idx].eng_clk >=
148 144 ctx->atb_sq_ramping_threshold) { ctx->atb_sq_ramping_threshold) {
149 145 sq_pwr_throttle_0 = set(SPT0_PWR_MAX, SQ_RAMPING_PWR_MAX); sq_pwr_throttle_0 = set(SPT0_PWR_MAX, SQ_RAMPING_PWR_MAX);
 
... ... SI.
158 154 sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ
159 155 | SPT1_LTI_RATIO; | SPT1_LTI_RATIO;
160 156 } }
161 #else
162 sq_pwr_throttle_0 = SPT0_PWR_MIN | SPT0_PWR_MAX;
163 sq_pwr_throttle_1 = SPT1_PWR_DELTA_MAX | SPT1_STI_SZ | SPT1_LTI_RATIO;
164 #endif
165 157
166 158 put_unaligned_be32(sq_pwr_throttle_0, &lvl->sq_pwr_throttle_0); put_unaligned_be32(sq_pwr_throttle_0, &lvl->sq_pwr_throttle_0);
167 159 put_unaligned_be32(sq_pwr_throttle_1, &lvl->sq_pwr_throttle_1); put_unaligned_be32(sq_pwr_throttle_1, &lvl->sq_pwr_throttle_1);
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