sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
Clone URLs: https://rocketgit.com/user/sylware/linux-gpu-amd-si ssh://rocketgit@ssh.rocketgit.com/user/sylware/linux-gpu-amd-si git://git.rocketgit.com/user/sylware/linux-gpu-amd-si
master
List of commits:
Subject Hash Author Date (UTC)
add no_dpm option because radeon dpm is a shame 003cb84f01f60e99b138d0694ddf58bebf724fd6 Sylvain BERTRAND 2014-09-01 08:41:24
page flip fix e51d9d4b1788c17633b0cdffd7a50309d51f8d0f Sylvain BERTRAND 2014-08-30 14:08:35
ack-ing the DCE irqs at the right time a12ec7f4781872de8d155e4e1d90b07df3e44c34 Sylvain BERTRAND 2014-08-28 15:23:29
normal programs use normal syscalls then ioctl 37589b6856d941efdc763eed41b237f4f62cb960 Sylvain BERTRAND 2014-07-08 19:01:52
new firware breaks the 3D pipeline 13db71ba4522d7266d68a21f43f25ee3781d0b92 Sylvain BERTRAND 2014-07-03 22:54:30
closed src or gnu gpl *not* v2 drivers are illegal dc1de426b639ffee863b0a211e9cf0e349f855f0 Sylvain BERTRAND 2014-07-03 17:59:46
compiling with 3.16 rc2 new mc fw code e00afdaeef8513da35c82cc82dcfee0745aa9129 Sylvain BERTRAND 2014-06-29 01:54:40
untested handling of new mc fw eb89a71b0af7781d1fc9ee226c1269b6d5183749 Sylvain BERTRAND 2014-06-29 01:26:15
become legal ef922b67f25aaf0c4f8cff5be572e53fb53bdfe5 Sylvain BERTRAND 2014-06-28 23:33:40
use usleep_range and fix a dp 1.1 time out d4183ce73e6ec7d7f3baf9d710dd2ba015b4a6a9 Sylvain BERTRAND 2014-02-19 20:09:44
fix dac a864ba601253674b679b07e4b1ddc00fb83a8cb6 Sylvain BERTRAND 2014-02-19 19:17:08
clear atombias dpm state and warn for instability 28b598d81f6a873f90d1a9325e3e1002743487a5 Sylvain BERTRAND 2014-02-19 19:10:43
CFG_MEM_SZ upper 16bits may have garbage f08f2e3471989e448d6d76ba02565fd9efc3293f Sylvain BERTRAND 2014-02-19 17:55:38
fix ena rbs mask performance critical bug 289497449dd0f2acb09e03f65988e22e45948fb6 Sylvain BERTRAND 2014-02-19 17:15:18
upstream confirm bug, fixed e2142c3fdfc01d51e7fec7687ec4d02f548ce763 Sylvain BERTRAND 2014-02-18 16:10:14
mainly bug fixing 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf Sylvain BERTRAND 2014-02-18 12:46:40
dump smc sw regs 5b42263039c858624ff411d94318f6ef5171a864 Sylvain BERTRAND 2014-02-17 12:22:26
disable switch to low power when no display 69f94e04ea89c1fe9ccaef153da5f5ade232c2a1 Sylvain BERTRAND 2014-02-17 09:59:28
finish smc switch to driver power state 6f99d0a01491dd671174919d842a771ac4a81a4b Sylvain BERTRAND 2014-02-17 09:47:02
pcie things and follow upstream for dyn pm init f4fb120597276a3badc08eec30783b10d111f756 Sylvain BERTRAND 2014-02-17 09:00:00
Commit 003cb84f01f60e99b138d0694ddf58bebf724fd6 - add no_dpm option because radeon dpm is a shame
Author: Sylvain BERTRAND
Author date (UTC): 2014-09-01 08:41
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-09-01 08:41
Parent(s): e51d9d4b1788c17633b0cdffd7a50309d51f8d0f
Signer:
Signing key:
Signing status: N
Tree: 6e1b60b59e9dca604aa52aebad27896ca36136ea
File Lines added Lines deleted
drivers/gpu/alga/amd/si/drv.c 30 16
File drivers/gpu/alga/amd/si/drv.c changed (mode: 100644) (index ba36e3c..4efeeae)
49 49 #include "regs.h" #include "regs.h"
50 50
51 51 bool fw_mc2 = 0; bool fw_mc2 = 0;
52 bool no_dpm = 0;
52 53 module_param(fw_mc2, bool, 0); module_param(fw_mc2, bool, 0);
53 54 MODULE_PARM_DESC(fw_mc2, "enable the new memory controller firmware (breaks the 3D pipeline)"); MODULE_PARM_DESC(fw_mc2, "enable the new memory controller firmware (breaks the 3D pipeline)");
55 module_param(no_dpm, bool, 0);
56 MODULE_PARM_DESC(no_dpm, "disable dynamic power management (end in power boot state which is not the highest)");
54 57
55 58 #define GPUS_MAX 256 #define GPUS_MAX 256
56 59 static DEFINE_IDA(ida); static DEFINE_IDA(ida);
 
... ... static void asic_deinit(struct pci_dev *dev)
288 291 struct dev_drv_data *dd; struct dev_drv_data *dd;
289 292
290 293 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
291
292 dyn_pm_dis(dev);
294
295 if (!no_dpm)
296 dyn_pm_dis(dev);
293 297 dmas_stop(dev); dmas_stop(dev);
294 298 cps_engines_stop(dev); cps_engines_stop(dev);
295 vg_dis(dev);
296 cg_dis(dev);
299 if (!no_dpm) {
300 vg_dis(dev);
301 cg_dis(dev);
302 }
297 303 ih_dis(dev); ih_dis(dev);
298 304 ih_reset(dev); ih_reset(dev);
299 305 mdelay(1); mdelay(1);
 
... ... static long asic_init(struct pci_dev *dev)
335 341 dev_info(&dev->dev, "vram size is %uMB\n", rr32(dev, CFG_MEM_SZ) dev_info(&dev->dev, "vram size is %uMB\n", rr32(dev, CFG_MEM_SZ)
336 342 & 0xffff); & 0xffff);
337 343
338 r = dyn_pm_ena(dev);
339 if (r == -SI_ERR)
340 goto err;
344 if (!no_dpm) {
345 r = dyn_pm_ena(dev);
346 if (r == -SI_ERR)
347 goto err;
348 }
341 349
342 350 /* claim back the 256k vga memory at vram beginning */ /* claim back the 256k vga memory at vram beginning */
343 351 dce6_vga_off(dd->dce); dce6_vga_off(dd->dce);
 
... ... static long asic_init(struct pci_dev *dev)
411 419 gpu_3d_ring_intr_idle_dis(dev); gpu_3d_ring_intr_idle_dis(dev);
412 420 rlc_serdes_wait(dev); rlc_serdes_wait(dev);
413 421 rlc_reset(dev); rlc_reset(dev);
414 vg_ena(dev);/* currently empty */
415 cg_ena(dev);
422 if (!no_dpm) {
423 vg_ena(dev);/* currently empty */
424 cg_ena(dev);
425 }
416 426 rlc_ucode_program(dev); rlc_ucode_program(dev);
417 if (mc_lb_pwr_supported(dev)) {
418 rlc_lb_pw_ena(dev);
419 } else {
420 rlc_lb_pw_dis(dev);
421 gpu_lb_pw_dis(dev);
427 if (!no_dpm) {
428 if (mc_lb_pwr_supported(dev)) {
429 rlc_lb_pw_ena(dev);
430 } else {
431 rlc_lb_pw_dis(dev);
432 gpu_lb_pw_dis(dev);
433 }
422 434 } }
423 435 rlc_ena(dev); rlc_ena(dev);
424 436 gpu_3d_ring_intr_idle_ena(dev); gpu_3d_ring_intr_idle_ena(dev);
 
... ... err_stop_dmas:
449 461 dmas_stop(dev); dmas_stop(dev);
450 462
451 463 cps_engines_stop(dev); cps_engines_stop(dev);
452 vg_dis(dev);
453 cg_dis(dev);
464 if (!no_dpm) {
465 vg_dis(dev);
466 cg_dis(dev);
467 }
454 468 ih_dis(dev); ih_dis(dev);
455 469 ih_reset(dev); ih_reset(dev);
456 470 mdelay(1); mdelay(1);
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