sylware / linux-gpu-amd-si (public) (License: GPLv2+) (since 2019-09-09) (hash sha1)
my old AMD Southern Islands GPU linux driver
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master
List of commits:
Subject Hash Author Date (UTC)
fix ena rbs mask performance critical bug 289497449dd0f2acb09e03f65988e22e45948fb6 Sylvain BERTRAND 2014-02-19 17:15:18
upstream confirm bug, fixed e2142c3fdfc01d51e7fec7687ec4d02f548ce763 Sylvain BERTRAND 2014-02-18 16:10:14
mainly bug fixing 1650d6a6e13bd81a4df9bfaa84a5daef2989ccdf Sylvain BERTRAND 2014-02-18 12:46:40
dump smc sw regs 5b42263039c858624ff411d94318f6ef5171a864 Sylvain BERTRAND 2014-02-17 12:22:26
disable switch to low power when no display 69f94e04ea89c1fe9ccaef153da5f5ade232c2a1 Sylvain BERTRAND 2014-02-17 09:59:28
finish smc switch to driver power state 6f99d0a01491dd671174919d842a771ac4a81a4b Sylvain BERTRAND 2014-02-17 09:47:02
pcie things and follow upstream for dyn pm init f4fb120597276a3badc08eec30783b10d111f756 Sylvain BERTRAND 2014-02-17 09:00:00
dump performance state tbls 06a22756b504ecf4523c86f657104e0b970195de Sylvain BERTRAND 2014-02-14 17:02:23
smc_mc_arb_tbl init for the driver state 5d1868e75b11164dbb97caaddbc7992b252ab973 Sylvain BERTRAND 2014-02-14 13:01:26
smc_mc_reg tbl init for the driver state e8aa12b1c87571031098c4427822733a74133afc Sylvain BERTRAND 2014-02-14 11:32:04
installation of the perf pwr state continued 535c853e7d0a0ab04fbff3b0d5613ef9a34d525c Sylvain BERTRAND 2014-02-13 19:16:33
installation of the perf pwr state continued b229eef2798acbe053aa09e47c213e23749638dd Sylvain BERTRAND 2014-02-13 10:48:02
dyn pm second part continuation 95dd7b4754476a014d8f84854e5b2ce5c81d23b4 Sylvain BERTRAND 2014-02-12 20:15:03
beginning of dyn pm second part c32c19d884dbf1f440480bbea42140e9c5ed8cd3 Sylvain BERTRAND 2014-02-12 14:44:04
uvd does only mpeg, then switch off 7e36b98bcab47e9986a63093dbeed98ab290f85f Sylvain BERTRAND 2014-02-12 10:55:54
bug fixing, end of dyn pm first part 533a4bd6731205f71704886e5fa099063be985ea Sylvain BERTRAND 2014-02-11 13:49:27
bug fixing c3fc0d7b807c98d20c13f53dcfc09713309ad2fa Sylvain BERTRAND 2014-02-11 11:16:00
static bios tbls *must* be ok e050fa94c2f1e846bb051748347332e234a6b93a Sylvain BERTRAND 2014-02-10 10:17:33
bug fixing 7baa7069aa89a98d831d7def358766155771e9ca Sylvain BERTRAND 2014-02-07 15:08:53
bug fixing d4a1ef00d163bc42e277c83d0a763fa11476af56 Sylvain BERTRAND 2014-02-06 20:14:33
Commit 289497449dd0f2acb09e03f65988e22e45948fb6 - fix ena rbs mask performance critical bug
Author: Sylvain BERTRAND
Author date (UTC): 2014-02-19 17:15
Committer name: Sylvain BERTRAND
Committer date (UTC): 2014-02-19 17:15
Parent(s): e2142c3fdfc01d51e7fec7687ec4d02f548ce763
Signing key:
Tree: bdcd89a6472384ad68dd5fef8167c4109101c84c
File Lines added Lines deleted
drivers/gpu/alga/amd/si/gpu.c 31 29
File drivers/gpu/alga/amd/si/gpu.c changed (mode: 100644) (index 1347b62..e9dccaf)
... ... static u32 sh_rbs_dis_get(struct pci_dev *dev)
177 177 rbs_dis = 0; rbs_dis = 0;
178 178 rbs_dis |= rr32(dev, GC_USER_RB_BACKEND_DIS); rbs_dis |= rr32(dev, GC_USER_RB_BACKEND_DIS);
179 179
180 /* don't use get(), since we may have major bits on top */
180 181 backend_dis_shift = ffs(CRBD_BACKEND_DIS); backend_dis_shift = ffs(CRBD_BACKEND_DIS);
181 182 rbs_dis >>= backend_dis_shift; rbs_dis >>= backend_dis_shift;
182 183
183 184 /* get a bit mask for the rbs which are disabled for this sh */ /* get a bit mask for the rbs which are disabled for this sh */
184 mask = bitmask_create(dd->cfg.gpu.se_rbs_n / dd->cfg.gpu.ses_n
185 / dd->cfg.gpu.se_shs_n);
185 mask = bitmask_create(dd->cfg.gpu.se_rbs_n / dd->cfg.gpu.se_shs_n);
186 186 return rbs_dis & mask; return rbs_dis & mask;
187 187 } }
188 188
 
... ... static u32 cus_ena_get(struct pci_dev *dev)
214 214 static void spi_setup(struct pci_dev *dev) static void spi_setup(struct pci_dev *dev)
215 215 { {
216 216 struct dev_drv_data *dd; struct dev_drv_data *dd;
217 u32 i;
218 u32 j;
219 u32 k;
217 u32 se;
218 u32 sh;
219 u32 cu;
220 220 u32 spi_static_thd_mgmt_2; u32 spi_static_thd_mgmt_2;
221 221 u32 cus_ena; u32 cus_ena;
222 222 u32 mask; u32 mask;
223 223
224 224 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
225 225
226 for (i = 0; i < dd->cfg.gpu.ses_n; ++i) {
227 for (j = 0; j < dd->cfg.gpu.se_shs_n; ++j) {
228 se_sh_select(dev, i, j);
226 for (se = 0; se < dd->cfg.gpu.ses_n; ++se) {
227 for (sh = 0; sh < dd->cfg.gpu.se_shs_n; ++sh) {
228 se_sh_select(dev, se, sh);
229 229 spi_static_thd_mgmt_2 = rr32(dev, spi_static_thd_mgmt_2 = rr32(dev,
230 230 SPI_STATIC_THD_MGMT_2); SPI_STATIC_THD_MGMT_2);
231 231 cus_ena = cus_ena_get(dev); cus_ena = cus_ena_get(dev);
232 232
233 233 mask = 1; mask = 1;
234 for (k = 0; k < CGSAC_SH_CUS_N_MAX; ++k) {
235 mask <<= k;
234 for (cu = 0; cu < CGSAC_SH_CUS_N_MAX; ++cu) {
235 mask <<= cu;
236 236 if (cus_ena & mask) { if (cus_ena & mask) {
237 237 spi_static_thd_mgmt_2 &= ~mask; spi_static_thd_mgmt_2 &= ~mask;
238 238 wr32(dev, spi_static_thd_mgmt_2, wr32(dev, spi_static_thd_mgmt_2,
 
... ... static void spi_setup(struct pci_dev *dev)
250 250 static void rbs_setup(struct pci_dev *dev) static void rbs_setup(struct pci_dev *dev)
251 251 { {
252 252 struct dev_drv_data *dd; struct dev_drv_data *dd;
253 u32 i;
254 u32 j;
253 u32 se;
254 u32 sh;
255 255 u32 sh_rbs_dis; u32 sh_rbs_dis;
256 256 u32 rbs_dis; u32 rbs_dis;
257 257 u32 mask; u32 mask;
 
... ... static void rbs_setup(struct pci_dev *dev)
260 260
261 261 dd = pci_get_drvdata(dev); dd = pci_get_drvdata(dev);
262 262
263 /* build the mask of disabled rbs from registers*/
263 /* build the mask of dis rbs from regs */
264 264 rbs_dis = 0; rbs_dis = 0;
265 for (i = 0; i < dd->cfg.gpu.ses_n; ++i) {
266 for (j = 0; j < dd->cfg.gpu.se_shs_n; ++j) {
267 se_sh_select(dev, i, j);
265 for (se = 0; se < dd->cfg.gpu.ses_n; ++se) {
266 for (sh = 0; sh < dd->cfg.gpu.se_shs_n; ++sh) {
267 se_sh_select(dev, se, sh);
268 268 sh_rbs_dis = sh_rbs_dis_get(dev); sh_rbs_dis = sh_rbs_dis_get(dev);
269 rbs_dis |= sh_rbs_dis << ((i * dd->cfg.gpu.se_shs_n + j)
270 * CRBD_TAHITI_RB_BITMAP_W_PER_SH);
269 rbs_dis |= sh_rbs_dis << ((se * dd->cfg.gpu.se_shs_n
270 + sh) * CRBD_TAHITI_RB_BITMAP_W_PER_SH);
271 271 } }
272 272 } }
273 273
274 274 se_sh_select(dev, 0xffffffff, 0xffffffff); se_sh_select(dev, 0xffffffff, 0xffffffff);
275 275
276 /* build the mask of enabled rbs from the mask of disabled rbs */
276 /* build the mask of ena rbs from the mask of dis rbs */
277 277 rbs_ena = 0; rbs_ena = 0;
278 278 mask = 1; mask = 1;
279 for (i = 0; i < dd->cfg.gpu.se_rbs_n; ++i) {
279 for (se = 0; se < dd->cfg.gpu.se_rbs_n * dd->cfg.gpu.ses_n; ++se) {
280 280 if(!(rbs_dis & mask)) if(!(rbs_dis & mask))
281 281 rbs_ena |= mask; rbs_ena |= mask;
282 282 mask <<= 1; mask <<= 1;
283 283 } }
284 284
285 /* configure the raster block for each sh */
286 for (i = 0; i < dd->cfg.gpu.ses_n; ++i) {
285 /* configure the raster blk for each sh */
286 for (se = 0; se < dd->cfg.gpu.ses_n; ++se) {
287 287 pa_sc_raster_cfg = 0; pa_sc_raster_cfg = 0;
288 for (j = 0; j < dd->cfg.gpu.se_shs_n; ++j) {
288 for (sh = 0; sh < dd->cfg.gpu.se_shs_n; ++sh) {
289 289 switch (rbs_ena & 3) { switch (rbs_ena & 3) {
290 290 case 1: case 1:
291 291 pa_sc_raster_cfg |= (PSRC_RB_MAP_0 pa_sc_raster_cfg |= (PSRC_RB_MAP_0
292 << (i * dd->cfg.gpu.se_shs_n + j) * 2);
292 << (se * dd->cfg.gpu.se_shs_n
293 + sh) * 2);
293 294 break; break;
294 295 case 2: case 2:
295 296 pa_sc_raster_cfg |= (PSRC_RB_MAP_3 pa_sc_raster_cfg |= (PSRC_RB_MAP_3
296 << (i * dd->cfg.gpu.se_shs_n + j) * 2);
297 << (se * dd->cfg.gpu.se_shs_n
298 + sh) * 2);
297 299 break; break;
298 300 case 3: case 3:
299 301 default: default:
300 302 pa_sc_raster_cfg |= (PSRC_RB_MAP_2 pa_sc_raster_cfg |= (PSRC_RB_MAP_2
301 << (i * dd->cfg.gpu.se_shs_n + j) * 2);
303 << (se * dd->cfg.gpu.se_shs_n + sh) * 2);
302 304 break; break;
303 305 } }
304 rbs_ena >>= 2;/* enabled rbs of next sh */
306 rbs_ena >>= 2;/* ena rbs of next sh */
305 307 } }
306 se_sh_select(dev, i, 0xffffffff);
307 dev_info(&dev->dev, "se_sh=%u pa_sc_raster_cfg=0x%08x\n", i,
308 se_sh_select(dev, se, 0xffffffff);
309 dev_info(&dev->dev, "se=%u pa_sc_raster_cfg=0x%08x\n", se,
308 310 pa_sc_raster_cfg); pa_sc_raster_cfg);
309 311 wr32(dev, pa_sc_raster_cfg, PA_SC_RASTER_CFG); wr32(dev, pa_sc_raster_cfg, PA_SC_RASTER_CFG);
310 312 } }
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